Refs #125.
- Added ST Nucleo-F303K8 demo bootloader and user program. - Added port for the STM32F3xx microcontroller family with ARM Cortex-M4 core. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@177 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
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|
@ -0,0 +1,175 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Boot\blt_conf.h
|
||||
* \brief Bootloader configuration header file.
|
||||
* \ingroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BLT_CONF_H
|
||||
#define BLT_CONF_H
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* To properly initialize the baudrate clocks of the communication interface, typically
|
||||
* the speed of the crystal oscillator and/or the speed at which the system runs is
|
||||
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
|
||||
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
|
||||
* not dependent on the targets architecture, the byte ordering needs to be known.
|
||||
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
|
||||
* little endian mode.
|
||||
*
|
||||
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
|
||||
* called the moment the user program is about to be started. This could be used to
|
||||
* de-initialize application specific parts, for example to stop blinking an LED, etc.
|
||||
*/
|
||||
/** \brief Frequency of the external crystal oscillator. */
|
||||
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
|
||||
/** \brief Desired system speed. */
|
||||
#define BOOT_CPU_SYSTEM_SPEED_KHZ (64000)
|
||||
/** \brief Motorola or Intel style byte ordering. */
|
||||
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
|
||||
/** \brief Enable/disable hook function call right before user program start. */
|
||||
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
|
||||
* in bits/second. Two CAN messages are reserved for communication with the host. The
|
||||
* message identifier for sending data from the target to the host is configured with
|
||||
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
|
||||
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
|
||||
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
|
||||
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
|
||||
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
|
||||
* CAN controller channel.
|
||||
*
|
||||
*/
|
||||
/** \brief Enable/disable CAN transport layer. */
|
||||
#define BOOT_COM_CAN_ENABLE (1)
|
||||
/** \brief Configure the desired CAN baudrate. */
|
||||
#define BOOT_COM_CAN_BAUDRATE (500000)
|
||||
/** \brief Configure CAN message ID target->host. */
|
||||
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
|
||||
/** \brief Configure number of bytes in the target->host CAN message. */
|
||||
#define BOOT_COM_CAN_TX_MAX_DATA (8)
|
||||
/** \brief Configure CAN message ID host->target. */
|
||||
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
|
||||
/** \brief Configure number of bytes in the host->target CAN message. */
|
||||
#define BOOT_COM_CAN_RX_MAX_DATA (8)
|
||||
/** \brief Select the desired CAN peripheral as a zero based index. */
|
||||
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
|
||||
|
||||
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
|
||||
* in bits/second. The maximum amount of data bytes in a message for data transmission
|
||||
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
|
||||
* respectively. It is common for a microcontroller to have more than 1 UART interface
|
||||
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
|
||||
*
|
||||
*/
|
||||
/** \brief Enable/disable UART transport layer. */
|
||||
#define BOOT_COM_UART_ENABLE (1)
|
||||
/** \brief Configure the desired communication speed. */
|
||||
#define BOOT_COM_UART_BAUDRATE (57600)
|
||||
/** \brief Configure number of bytes in the target->host data packet. */
|
||||
#define BOOT_COM_UART_TX_MAX_DATA (64)
|
||||
/** \brief Configure number of bytes in the host->target data packet. */
|
||||
#define BOOT_COM_UART_RX_MAX_DATA (64)
|
||||
/** \brief Select the desired UART peripheral as a zero based index. */
|
||||
#define BOOT_COM_UART_CHANNEL_INDEX (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* It is possible to implement an application specific method to force the bootloader to
|
||||
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
|
||||
* situations where the user program does not run properly and therefore cannot
|
||||
* reactivate the bootloader. By enabling these hook functions, the application can
|
||||
* implement the backdoor, which overrides the default backdoor entry that is programmed
|
||||
* into the bootloader. When desired for security purposes, these hook functions can
|
||||
* also be implemented in a way that disables the backdoor entry altogether.
|
||||
*/
|
||||
/** \brief Enable/disable the backdoor override hook functions. */
|
||||
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The NVM driver typically supports erase and program operations of the internal memory
|
||||
* present on the microcontroller. Through these hook functions the NVM driver can be
|
||||
* extended to support additional memory types such as external flash memory and serial
|
||||
* eeproms. The size of the internal memory in kilobytes is specified with configurable
|
||||
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
|
||||
* be overridden with a application specific method by enabling configuration switch
|
||||
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
|
||||
*/
|
||||
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
|
||||
#define BOOT_NVM_HOOKS_ENABLE (0)
|
||||
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
|
||||
#define BOOT_NVM_SIZE_KB (64)
|
||||
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
|
||||
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The COP driver cannot be configured internally in the bootloader, because its use
|
||||
* and configuration is application specific. The bootloader does need to service the
|
||||
* watchdog in case it is used. When the application requires the use of a watchdog,
|
||||
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
|
||||
* hook functions.
|
||||
*/
|
||||
/** \brief Enable/disable the hook functions for controlling the watchdog. */
|
||||
#define BOOT_COP_HOOKS_ENABLE (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
|
||||
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
|
||||
* operations can be performed, access to this resource need to be unlocked.
|
||||
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
|
||||
* implements the unlocking algorithm. The demo programs are configured for the (simple)
|
||||
* algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be
|
||||
* customized to your needs.
|
||||
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
|
||||
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
|
||||
* a key, which is also a byte array, and sends this back to the bootloader. The
|
||||
* bootloader then verifies this key to determine if programming and erase operations are
|
||||
* permitted.
|
||||
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
|
||||
* are called by the bootloader to obtain the seed and to verify the key, respectively.
|
||||
*/
|
||||
#define BOOT_XCP_SEED_KEY_ENABLE (0)
|
||||
|
||||
|
||||
#endif /* BLT_CONF_H */
|
||||
/*********************************** end of blt_conf.h *********************************/
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/**
|
||||
\defgroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC Bootloader
|
||||
\brief Bootloader.
|
||||
\ingroup ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
*/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,295 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Boot\hooks.c
|
||||
* \brief Bootloader callback source file.
|
||||
* \ingroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "led.h" /* LED driver header */
|
||||
#include "stm32f30x.h" /* STM32 registers and drivers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the backdoor entry option.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BackDoorInitHook(void)
|
||||
{
|
||||
} /*** end of BackDoorInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Checks if a backdoor entry is requested.
|
||||
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool BackDoorEntryHook(void)
|
||||
{
|
||||
/* default implementation always activates the bootloader after a reset */
|
||||
return BLT_TRUE;
|
||||
} /*** end of BackDoorEntryHook ***/
|
||||
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called when the bootloader is about to exit and
|
||||
** hand over control to the user program. This is the last moment that
|
||||
** some final checking can be performed and if necessary prevent the
|
||||
** bootloader from activiting the user program.
|
||||
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
|
||||
** keep the bootloader active.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool CpuUserProgramStartHook(void)
|
||||
{
|
||||
/* clean up the LED driver */
|
||||
LedBlinkExit();
|
||||
|
||||
/* additional and optional backdoor entry through the D1 digital input on the board. to
|
||||
* force the bootloader to stay active after reset, connect D1 to ground.
|
||||
*/
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)
|
||||
{
|
||||
/* pushbutton pressed, so do not start the user program and keep the
|
||||
* bootloader active instead.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* okay to start the user program.*/
|
||||
return BLT_TRUE;
|
||||
} /*** end of CpuUserProgramStartHook ***/
|
||||
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** initialization routine. It can be used to configure and enable the
|
||||
** watchdog.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopInitHook(void)
|
||||
{
|
||||
/* this function is called upon initialization. might as well use it to initialize
|
||||
* the LED driver. It is kind of a visual watchdog anyways.
|
||||
*/
|
||||
LedBlinkInit(100);
|
||||
} /*** end of CopInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** service routine. This gets called upon initialization and during
|
||||
** potential long lasting loops and routine. It can be used to service
|
||||
** the watchdog to prevent a watchdog reset.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopServiceHook(void)
|
||||
{
|
||||
/* run the LED blink task. this is a better place to do it than in the main() program
|
||||
* loop. certain operations such as flash erase can take a long time, which would cause
|
||||
* a blink interval to be skipped. this function is also called during such operations,
|
||||
* so no blink intervals will be skipped when calling the LED blink task here.
|
||||
*/
|
||||
LedBlinkTask();
|
||||
} /*** end of CopServiceHook ***/
|
||||
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the internal NVM driver
|
||||
** initialization routine.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInitHook(void)
|
||||
{
|
||||
} /*** end of NvmInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver write
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||
** been written yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \param data Pointer to the data buffer.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the write
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmWriteHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver erase
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
||||
** hasn't been erased yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the erase
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmEraseHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the NVM programming session.
|
||||
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDoneHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmDoneHook ***/
|
||||
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmVerifyChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if a valid user programming is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmWriteChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Provides a seed to the XCP master that will be used for the key
|
||||
** generation when the master attempts to unlock the specified resource.
|
||||
** Called by the GET_SEED command.
|
||||
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
|
||||
** \param seed Pointer to byte buffer wher the seed will be stored.
|
||||
** \return Length of the seed in bytes.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
|
||||
{
|
||||
/* request seed for unlocking ProGraMming resource */
|
||||
if ((resource & XCP_RES_PGM) != 0)
|
||||
{
|
||||
seed[0] = 0x55;
|
||||
}
|
||||
|
||||
/* return seed length */
|
||||
return 1;
|
||||
} /*** end of XcpGetSeedHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Called by the UNLOCK command and checks if the key to unlock the
|
||||
** specified resource was correct. If so, then the resource protection
|
||||
** will be removed.
|
||||
** \param resource resource to unlock (XCP_RES_XXX).
|
||||
** \param key pointer to the byte buffer holding the key.
|
||||
** \param len length of the key in bytes.
|
||||
** \return 1 if the key was correct, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
|
||||
{
|
||||
/* suppress compiler warning for unused parameter */
|
||||
len = len;
|
||||
|
||||
/* the example key algorithm in "FeaserKey.dll" works as follows:
|
||||
* - PGM will be unlocked if key = seed - 1
|
||||
*/
|
||||
|
||||
/* check key for unlocking ProGraMming resource */
|
||||
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
|
||||
{
|
||||
/* correct key received for unlocking PGM resource */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* still here so key incorrect */
|
||||
return 0;
|
||||
} /*** end of XcpVerifyKeyHook ***/
|
||||
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of hooks.c ************************************/
|
||||
|
|
@ -0,0 +1,632 @@
|
|||
# depslib dependency file v1.0
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_adc.c
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_adc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436355286 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\stm32f30x.h
|
||||
"core_cm4.h"
|
||||
"system_stm32f30x.h"
|
||||
<stdint.h>
|
||||
"stm32f30x_conf.h"
|
||||
|
||||
1436355025 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cm4.h
|
||||
<stdint.h>
|
||||
<core_cmInstr.h>
|
||||
<core_cmFunc.h>
|
||||
<core_cmSimd.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cminstr.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cmfunc.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cmsimd.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355286 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\system_stm32f30x.h
|
||||
|
||||
1439555739 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\stm32f30x_conf.h
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_crc.h"
|
||||
"stm32f30x_comp.h"
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_dbgmcu.h"
|
||||
"stm32f30x_dma.h"
|
||||
"stm32f30x_exti.h"
|
||||
"stm32f30x_flash.h"
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_hrtim.h"
|
||||
"stm32f30x_syscfg.h"
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_iwdg.h"
|
||||
"stm32f30x_opamp.h"
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_can.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_crc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_comp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dac.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dbgmcu.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dma.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_exti.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_flash.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_fmc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_gpio.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_hrtim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_syscfg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_i2c.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_iwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_opamp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_pwr.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_rcc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_rtc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_spi.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_tim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_usart.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_wwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_misc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_can.c
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_comp.c
|
||||
"stm32f30x_comp.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_crc.c
|
||||
"stm32f30x_crc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dac.c
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dbgmcu.c
|
||||
"stm32f30x_dbgmcu.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dma.c
|
||||
"stm32f30x_dma.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_exti.c
|
||||
"stm32f30x_exti.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_flash.c
|
||||
"stm32f30x_flash.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_fmc.c
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_gpio.c
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_hrtim.c
|
||||
"stm32f30x_hrtim.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_i2c.c
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_iwdg.c
|
||||
"stm32f30x_iwdg.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_misc.c
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_opamp.c
|
||||
"stm32f30x_opamp.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_pwr.c
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_rcc.c
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_rtc.c
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_spi.c
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_syscfg.c
|
||||
"stm32f30x_syscfg.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_tim.c
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_usart.c
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_wwdg.c
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1471084291 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\main.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1471084169 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\startup_stm32f30x.s
|
||||
|
||||
1471086847 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\system_stm32f30x.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1452185562 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\assert.c
|
||||
"header.h"
|
||||
|
||||
1461838668 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\header.h
|
||||
<stdint.h>
|
||||
<stdlib.h>
|
||||
"os.h"
|
||||
"hw.h"
|
||||
"app.h"
|
||||
|
||||
1452185952 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\os\os.h
|
||||
|
||||
1471085506 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\hw.h
|
||||
"stm32f30x.h"
|
||||
"led.h"
|
||||
|
||||
1452186099 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\led.h
|
||||
|
||||
1452185785 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\app.h
|
||||
"assert.h"
|
||||
|
||||
1452185438 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\assert.h
|
||||
|
||||
1471086902 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\hw.c
|
||||
"header.h"
|
||||
|
||||
1471086227 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\led.c
|
||||
"header.h"
|
||||
|
||||
1471086926 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\app.c
|
||||
"header.h"
|
||||
|
||||
1452185952 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\os\os.c
|
||||
"os.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_adc.c
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_adc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\stm32f30x.h
|
||||
"core_cm4.h"
|
||||
"system_stm32f30x.h"
|
||||
<stdint.h>
|
||||
"stm32f30x_conf.h"
|
||||
|
||||
1436351425 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cm4.h
|
||||
<stdint.h>
|
||||
<core_cmInstr.h>
|
||||
<core_cmFunc.h>
|
||||
<core_cmSimd.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cminstr.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cmfunc.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cmsimd.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\system_stm32f30x.h
|
||||
|
||||
1439552139 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\stm32f30x_conf.h
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_crc.h"
|
||||
"stm32f30x_comp.h"
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_dbgmcu.h"
|
||||
"stm32f30x_dma.h"
|
||||
"stm32f30x_exti.h"
|
||||
"stm32f30x_flash.h"
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_hrtim.h"
|
||||
"stm32f30x_syscfg.h"
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_iwdg.h"
|
||||
"stm32f30x_opamp.h"
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_can.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_crc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_comp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dac.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dbgmcu.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dma.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_exti.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_flash.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_fmc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_gpio.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_hrtim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_syscfg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_i2c.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_iwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_opamp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_pwr.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_rcc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_rtc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_spi.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_tim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_usart.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_wwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_misc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_can.c
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_comp.c
|
||||
"stm32f30x_comp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_crc.c
|
||||
"stm32f30x_crc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dac.c
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dbgmcu.c
|
||||
"stm32f30x_dbgmcu.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dma.c
|
||||
"stm32f30x_dma.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_exti.c
|
||||
"stm32f30x_exti.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_flash.c
|
||||
"stm32f30x_flash.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_fmc.c
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_gpio.c
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_hrtim.c
|
||||
"stm32f30x_hrtim.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_i2c.c
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_iwdg.c
|
||||
"stm32f30x_iwdg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_misc.c
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_opamp.c
|
||||
"stm32f30x_opamp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_pwr.c
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_rcc.c
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_rtc.c
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_spi.c
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_syscfg.c
|
||||
"stm32f30x_syscfg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_tim.c
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_usart.c
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_wwdg.c
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1471083247 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\system_stm32f30x.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1478878702 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\app.c
|
||||
"header.h"
|
||||
|
||||
1461835068 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\header.h
|
||||
<stdint.h>
|
||||
<stdlib.h>
|
||||
"os.h"
|
||||
"hw.h"
|
||||
"app.h"
|
||||
|
||||
1452182352 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\os\os.h
|
||||
|
||||
1471081906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\hw.h
|
||||
"stm32f30x.h"
|
||||
"led.h"
|
||||
|
||||
1452182499 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\led.h
|
||||
|
||||
1452182185 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\app.h
|
||||
"assert.h"
|
||||
|
||||
1452181838 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\assert.h
|
||||
|
||||
1452181962 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\assert.c
|
||||
"header.h"
|
||||
|
||||
1471083302 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\hw.c
|
||||
"header.h"
|
||||
|
||||
1471082627 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\led.c
|
||||
"header.h"
|
||||
|
||||
1471080569 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\startup_stm32f30x.s
|
||||
|
||||
1452182352 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\os\os.c
|
||||
"os.h"
|
||||
|
||||
1479139223 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\hooks.c
|
||||
"boot.h"
|
||||
"led.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1477216154 c:\work\software\openblt\target\source\boot.h
|
||||
"types.h"
|
||||
"assert.h"
|
||||
"blt_conf.h"
|
||||
"plausibility.h"
|
||||
"cpu.h"
|
||||
"cop.h"
|
||||
"nvm.h"
|
||||
"timer.h"
|
||||
"backdoor.h"
|
||||
"file.h"
|
||||
"com.h"
|
||||
|
||||
1478879101 c:\work\software\openblt\target\source\armcm4_stm32f3\types.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\assert.h
|
||||
|
||||
1479125255 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\blt_conf.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\plausibility.h
|
||||
|
||||
1476728168 c:\work\software\openblt\target\source\cpu.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\cop.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\nvm.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\timer.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\backdoor.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\file.h
|
||||
"ff.h"
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\com.h
|
||||
"xcp.h"
|
||||
|
||||
1476783465 c:\work\software\openblt\target\source\xcp.h
|
||||
|
||||
1478880688 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\led.h
|
||||
|
||||
1479124451 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\led.c
|
||||
"boot.h"
|
||||
"led.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1479139223 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\main.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1479124422 source:c:\work\software\openblt\target\source\armcm4_stm32f3\can.c
|
||||
"boot.h"
|
||||
|
||||
1478878920 source:c:\work\software\openblt\target\source\armcm4_stm32f3\cpu.c
|
||||
"boot.h"
|
||||
|
||||
1479121922 source:c:\work\software\openblt\target\source\armcm4_stm32f3\flash.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
"flash_layout.c"
|
||||
|
||||
1478879160 source:c:\work\software\openblt\target\source\armcm4_stm32f3\gcc\cpu_comp.c
|
||||
"boot.h"
|
||||
|
||||
1478879348 source:c:\work\software\openblt\target\source\armcm4_stm32f3\gcc\cstart.s
|
||||
|
||||
1478879055 source:c:\work\software\openblt\target\source\armcm4_stm32f3\nvm.c
|
||||
"boot.h"
|
||||
"flash.h"
|
||||
|
||||
1478879042 c:\work\software\openblt\target\source\armcm4_stm32f3\flash.h
|
||||
|
||||
1478879086 source:c:\work\software\openblt\target\source\armcm4_stm32f3\timer.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1479116679 source:c:\work\software\openblt\target\source\armcm4_stm32f3\uart.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1477295250 source:c:\work\software\openblt\target\source\assert.c
|
||||
"boot.h"
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\backdoor.c
|
||||
"boot.h"
|
||||
|
||||
1476728156 source:c:\work\software\openblt\target\source\boot.c
|
||||
"boot.h"
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\com.c
|
||||
"boot.h"
|
||||
"can.h"
|
||||
"uart.h"
|
||||
"usb.h"
|
||||
"net.h"
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\can.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\uart.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\usb.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\net.h
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\cop.c
|
||||
"boot.h"
|
||||
|
||||
1469281006 source:c:\work\software\openblt\target\source\file.c
|
||||
"boot.h"
|
||||
<string.h>
|
||||
<ctype.h>
|
||||
|
||||
1469431757 source:c:\work\software\openblt\target\source\net.c
|
||||
"boot.h"
|
||||
"netdev.h"
|
||||
"uip.h"
|
||||
"uip_arp.h"
|
||||
|
||||
1476783463 source:c:\work\software\openblt\target\source\xcp.c
|
||||
"boot.h"
|
||||
|
||||
|
|
@ -0,0 +1,421 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<EmBitz_project_file>
|
||||
<EmBitzVersion release="1.00" revision="0" />
|
||||
<FileVersion major="1" minor="0" />
|
||||
<Project>
|
||||
<Option title="stm32f303" />
|
||||
<Option pch_mode="2" />
|
||||
<Option compiler="armgcc_eb" />
|
||||
<Option virtualFolders="Libs\;Libs\cmsis\;Libs\SPL\;Srcs\;Srcs\Core\;Srcs\Core\ARMCM4_STM32F3\;Srcs\Core\ARMCM4_STM32F3\GCC\;" />
|
||||
<Build>
|
||||
<Target title="Debug">
|
||||
<Option output="..\bin\openblt_stm32f303.elf" />
|
||||
<Option object_output="..\obj\" />
|
||||
<Option type="0" />
|
||||
<Option compiler="armgcc_eb" />
|
||||
<Option projectDeviceOptionsRelation="0" />
|
||||
<Compiler>
|
||||
<Add option="-Wall" />
|
||||
<Add option="-fdata-sections" />
|
||||
<Add option="-ffunction-sections" />
|
||||
<Add option="-O0" />
|
||||
<Add option="-g3" />
|
||||
<Add option="-Og" />
|
||||
</Compiler>
|
||||
<Assembler>
|
||||
<Add option="-Wa,--gdwarf-2" />
|
||||
</Assembler>
|
||||
<Linker>
|
||||
<Add option="-Wl,--gc-sections" />
|
||||
</Linker>
|
||||
</Target>
|
||||
</Build>
|
||||
<Device>
|
||||
<Add option="$device=cortex-m4" />
|
||||
<Add option="$lscript=./../../../../Source/ARMCM4_STM32F3/GCC/memory.x" />
|
||||
<Add option="$stack=0x0100" />
|
||||
<Add option="$heap=0x0000" />
|
||||
</Device>
|
||||
<Compiler>
|
||||
<Add option="-mfloat-abi=soft" />
|
||||
<Add option="-fno-strict-aliasing" />
|
||||
<Add symbol="STM32F303K8" />
|
||||
<Add symbol="STM32F334x8" />
|
||||
<Add symbol="USE_STDPERIPH_DRIVER" />
|
||||
<Add directory="..\src" />
|
||||
<Add directory="..\src\app" />
|
||||
<Add directory="..\src\hw" />
|
||||
<Add directory="..\src\os" />
|
||||
<Add directory="..\lib" />
|
||||
<Add directory="..\lib\cmsis" />
|
||||
<Add directory="..\lib\SPL\inc" />
|
||||
</Compiler>
|
||||
<Linker>
|
||||
<Add option="-eb_lib=n" />
|
||||
<Add option="-eb_start_files" />
|
||||
</Linker>
|
||||
<ExtraCommands>
|
||||
<Add after="arm-none-eabi-objcopy -O srec $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).elf $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).srec" />
|
||||
<Mode before="0" />
|
||||
<Mode after="1" />
|
||||
</ExtraCommands>
|
||||
<Unit filename="..\blt_conf.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\hooks.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\led.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\led.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_common_tables.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_const_structs.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_math.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cm4.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmFunc.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmInstr.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmSimd.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_adc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_can.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_comp.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_crc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dac.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dbgmcu.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dma.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_exti.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_flash.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_fmc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_gpio.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_hrtim.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_i2c.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_iwdg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_misc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_opamp.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_pwr.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_rcc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_rtc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_spi.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_syscfg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_tim.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_usart.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_wwdg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_adc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_can.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_comp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_crc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dac.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dbgmcu.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dma.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_exti.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_flash.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_fmc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_gpio.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_hrtim.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_i2c.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_iwdg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_misc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_opamp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_pwr.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_rcc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_rtc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_spi.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_syscfg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_tim.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_usart.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_wwdg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\stm32f30x.h">
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\stm32f30x_conf.h">
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\system_stm32f30x.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\system_stm32f30x.h">
|
||||
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|
||||
</Unit>
|
||||
<Unit filename="..\main.c">
|
||||
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|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\can.c">
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\flash.c">
|
||||
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|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\flash.h">
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\GCC\cpu_comp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\GCC\" />
|
||||
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|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\GCC\cstart.S">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\GCC\" />
|
||||
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|
||||
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|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\timer.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\types.h">
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\ARMCM4_STM32F3\uart.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\ARMCM4_STM32F3\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\assert.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\assert.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\backdoor.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\backdoor.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\boot.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\boot.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\can.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\com.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\com.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\cop.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\cop.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\cpu.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\file.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\file.h">
|
||||
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|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\net.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\net.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\nvm.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\plausibility.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\timer.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\uart.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\usb.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\xcp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Unit filename="..\..\..\..\Source\xcp.h">
|
||||
<Option virtualFolder="Srcs\Core\" />
|
||||
</Unit>
|
||||
<Extensions>
|
||||
<code_completion />
|
||||
<debugger>
|
||||
<target_debugging_settings target="Debug" active_interface="ST-link">
|
||||
<debug_interface interface_id="ST-link" ip_address="localhost" ip_port="4242" path="${EMBITZ}\share\contrib" executable="STLinkGDB.exe" description="..\cfg\STM32F303x.svd" dont_start_server="false" backoff_time="1000" options="2" reg_filter="0" active_family="STMicroelectronics" gdb_before_conn="" gdb_after_conn="">
|
||||
<family_options family_id="STMicroelectronics">
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<option opt_id="ID_VEC_TABLE" opt_value="1" />
|
||||
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|
||||
<option opt_id="ID_ALL_MODE_DEBUG" opt_value="0" />
|
||||
<option opt_id="ID_DEV_ADDR" opt_value="" />
|
||||
<option opt_id="ID_VERBOSE_LEVEL" opt_value="3" />
|
||||
</family_options>
|
||||
</debug_interface>
|
||||
</target_debugging_settings>
|
||||
</debugger>
|
||||
<envvars />
|
||||
</Extensions>
|
||||
</Project>
|
||||
</EmBitz_project_file>
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<EmBitz_layout_file>
|
||||
<ActiveTarget name="Debug" />
|
||||
<File name="..\blt_conf.h" open="1" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="4294" topLine="52" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\hooks.c" open="0" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="4414" topLine="57" />
|
||||
</Cursor>
|
||||
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|
||||
<File name="..\led.c" open="0" top="0" tabpos="4" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
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|
||||
<Cursor1 position="3709" topLine="40" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_can.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="1655" topLine="19" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_flash.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="12443" topLine="261" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_gpio.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="10201" topLine="250" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_rcc.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="31070" topLine="671" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\src\stm32f30x_can.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
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|
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<Cursor1 position="11735" topLine="291" />
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|
||||
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|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Boot\led.c
|
||||
* \brief LED driver source file.
|
||||
* \ingroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "led.h" /* module header */
|
||||
#include "stm32f30x.h" /* STM32 registers and drivers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Holds the desired LED blink interval time. */
|
||||
static blt_int16u ledBlinkIntervalMs;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the LED blink driver.
|
||||
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkInit(blt_int16u interval_ms)
|
||||
{
|
||||
/* store the interval time between LED toggles */
|
||||
ledBlinkIntervalMs = interval_ms;
|
||||
} /*** end of LedBlinkInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Task function for blinking the LED as a fixed timer interval.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkTask(void)
|
||||
{
|
||||
static blt_bool ledOn = BLT_FALSE;
|
||||
static blt_int32u nextBlinkEvent = 0;
|
||||
|
||||
/* check for blink event */
|
||||
if (TimerGet() >= nextBlinkEvent)
|
||||
{
|
||||
/* toggle the LED state */
|
||||
if (ledOn == BLT_FALSE)
|
||||
{
|
||||
ledOn = BLT_TRUE;
|
||||
GPIO_SetBits(GPIOB, GPIO_Pin_3);
|
||||
}
|
||||
else
|
||||
{
|
||||
ledOn = BLT_FALSE;
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_3);
|
||||
}
|
||||
/* schedule the next blink event */
|
||||
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
|
||||
}
|
||||
} /*** end of LedBlinkTask ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Cleans up the LED blink driver. This is intended to be used upon program
|
||||
** exit.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkExit(void)
|
||||
{
|
||||
/* turn the LED off */
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_3);
|
||||
} /*** end of LedBlinkExit ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Boot\led.h
|
||||
* \brief LED driver header file.
|
||||
* \ingroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedBlinkInit(blt_int16u interval_ms);
|
||||
void LedBlinkTask(void);
|
||||
void LedBlinkExit(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,820 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_ADC_H
|
||||
#define __STM32F30x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_resolution */
|
||||
uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
|
||||
regular group conversion.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of injected channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_Injected_channels_conversion */
|
||||
uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for injected channel group.
|
||||
This parameter must range from 1 to 4. */
|
||||
uint32_t ADC_InjecSequence1;
|
||||
uint32_t ADC_InjecSequence2;
|
||||
uint32_t ADC_InjecSequence3;
|
||||
uint32_t ADC_InjecSequence4;
|
||||
}ADC_InjectedInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
|
||||
independent or multi mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
|
||||
and slave ADCs.
|
||||
This parameter can be a value of @ref ADC_Clock */
|
||||
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of
|
||||
@ref ADC_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
|
||||
This parameter can be a value of @ref ADC_DMA_Mode_definition */
|
||||
uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value between 0x0 and 0xF */
|
||||
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
/** @defgroup ADC_ContinuousConvMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
|
||||
#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
|
||||
#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
|
||||
((MODE) == ADC_ContinuousConvMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_OverunMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
|
||||
#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
|
||||
#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
|
||||
((MODE) == ADC_OverrunMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_AutoInjecMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
|
||||
#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
|
||||
#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
|
||||
((MODE) == ADC_AutoInjec_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
|
||||
#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
|
||||
#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
|
||||
#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
|
||||
|
||||
#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
|
||||
|
||||
#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
|
||||
#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
|
||||
#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
|
||||
#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
|
||||
#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
|
||||
#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
|
||||
#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
|
||||
#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
|
||||
#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
|
||||
#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
|
||||
#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
|
||||
#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
|
||||
#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
|
||||
#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
|
||||
#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
|
||||
#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
|
||||
#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
|
||||
#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
|
||||
#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
|
||||
#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
|
||||
#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
|
||||
#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
|
||||
#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
|
||||
#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
|
||||
#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
|
||||
#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
|
||||
#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
|
||||
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || \
|
||||
((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || \
|
||||
((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18))
|
||||
#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
|
||||
#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
|
||||
#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
|
||||
#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
|
||||
#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
|
||||
#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
|
||||
#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
|
||||
((MODE) == ADC_Mode_InjSimul) || \
|
||||
((MODE) == ADC_Mode_RegSimul) || \
|
||||
((MODE) == ADC_Mode_Interleave) || \
|
||||
((MODE) == ADC_Mode_AltTrig))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Clock
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
|
||||
#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
|
||||
#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
|
||||
#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
|
||||
#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
|
||||
#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
|
||||
#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
|
||||
((MODE) == ADC_DMAAccessMode_1) || \
|
||||
((MODE) == ADC_DMAAccessMode_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
|
||||
#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
|
||||
#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
|
||||
#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
|
||||
#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
|
||||
#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
|
||||
#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_2Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_4Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_19Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_61Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_181Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_601Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
|
||||
#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
|
||||
#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
|
||||
#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
|
||||
#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
|
||||
#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
|
||||
#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
|
||||
#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
|
||||
#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
|
||||
#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
|
||||
#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
|
||||
#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
|
||||
#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
|
||||
#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
|
||||
#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
|
||||
#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
|
||||
#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
|
||||
#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
|
||||
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_5) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_6) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_7) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_8) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_9) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_10) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_11) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_12) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_13) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_14) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_15) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_16) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_17) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Sequence_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
|
||||
#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
|
||||
#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
|
||||
#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
|
||||
#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_2) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_3) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Calibration_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
|
||||
#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
|
||||
|
||||
#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_DMA_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
|
||||
#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
|
||||
|
||||
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
|
||||
#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
|
||||
#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
|
||||
#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
|
||||
#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
|
||||
#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
|
||||
#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
|
||||
#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
|
||||
#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
|
||||
#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
|
||||
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
|
||||
((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
|
||||
((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
|
||||
((IT) == ADC_IT_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
|
||||
#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
|
||||
#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
|
||||
#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
|
||||
#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
|
||||
((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
|
||||
((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
|
||||
((FLAG) == ADC_FLAG_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Common_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
|
||||
#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
|
||||
#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
|
||||
#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
|
||||
#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
|
||||
|
||||
#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
|
||||
#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
|
||||
#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
|
||||
#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
|
||||
#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
|
||||
#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
|
||||
((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
|
||||
((FLAG) == ADC_FLAG_MSTJQOVF) || \
|
||||
((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
|
||||
((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
|
||||
((FLAG) == ADC_FLAG_SLVJQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_two_sampling_delay_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
|
||||
void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
|
||||
void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DisableCmd(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
|
||||
void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor, Vrefint and Vbat management function */
|
||||
void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
|
||||
void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
|
||||
|
||||
void ADC_StartConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
|
||||
void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
|
||||
void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* ADC Dual Modes Configuration functions *************************************/
|
||||
FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,643 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CAN_H
|
||||
#define __STM32F30x_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode_status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
|
||||
an empty mailbox */
|
||||
/* Legacy defines */
|
||||
#define CANTXFAILED CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* CAN Frames Transmission functions ******************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* CAN Frames Reception functions *********************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* CAN Bus Error management functions *****************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CAN_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_COMP_H
|
||||
#define __STM32F30x_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
|
||||
uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_NonInvertingInput */
|
||||
|
||||
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMP_Output */
|
||||
|
||||
uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPoloarity */
|
||||
|
||||
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
|
||||
and allows to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMP_Mode */
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
|
||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
|
||||
#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
|
||||
#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
|
||||
#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
|
||||
#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
|
||||
#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2) || \
|
||||
((PERIPH) == COMP_Selection_COMP3) || \
|
||||
((PERIPH) == COMP_Selection_COMP4) || \
|
||||
((PERIPH) == COMP_Selection_COMP5) || \
|
||||
((PERIPH) == COMP_Selection_COMP6) || \
|
||||
((PERIPH) == COMP_Selection_COMP7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
|
||||
|
||||
#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
|
||||
PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
|
||||
PC0 for COMP7) connected to comparator inverting input */
|
||||
|
||||
#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
|
||||
PB15 for COMP6) connected to comparator inverting input.
|
||||
It is valid only for STM32F303xC devices */
|
||||
|
||||
#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
|
||||
((INPUT) == COMP_InvertingInput_IO1) || \
|
||||
((INPUT) == COMP_InvertingInput_IO2) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC2OUT1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
|
||||
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
|
||||
PA0 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
|
||||
PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
|
||||
((INPUT) == COMP_NonInvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
|
||||
|
||||
/* Output Redirection common for all comparators COMP1...COMP7 */
|
||||
#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
|
||||
#define COMP_Output_TIM20BKIN ((uint32_t)0x00003000) /*!< COMP output connected to TIM20 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM20BKIN2 ((uint32_t)0x00003400) /*!< COMP output connected to TIM20 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input2 */
|
||||
|
||||
/* Output Redirection common for COMP1 and COMP2 */
|
||||
#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
|
||||
#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
|
||||
#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
|
||||
#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
|
||||
#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP2 */
|
||||
#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
|
||||
#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
|
||||
#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
|
||||
#define COMP_Output_TIM20OCREFCLR ((uint32_t)0x00003C00) /*!< COMP output connected to TIM20 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP3 */
|
||||
#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
|
||||
#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
|
||||
#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
|
||||
#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP4 */
|
||||
#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
|
||||
#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
|
||||
#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
|
||||
#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
|
||||
#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
|
||||
|
||||
#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
|
||||
#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
|
||||
#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
|
||||
|
||||
/* Output Redirection specific to COMP5 */
|
||||
#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
|
||||
#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
|
||||
#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP6 */
|
||||
#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
|
||||
#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
|
||||
|
||||
#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
|
||||
#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
|
||||
#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
|
||||
|
||||
/* Output Redirection specific to COMP7 */
|
||||
#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
|
||||
#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
|
||||
#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM16BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM16IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM17BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE8_2) || \
|
||||
((OUTPUT) == COMP_Output_TIM20BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM20BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2)|| \
|
||||
((OUTPUT) == COMP_Output_TIM20OCREFCLR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* No blanking source can be selected for all comparators */
|
||||
#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1 and COMP2 */
|
||||
#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2 and COMP5 */
|
||||
#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP3 and COMP6 */
|
||||
#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source for COMP4 */
|
||||
#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
|
||||
#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
|
||||
|
||||
#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPoloarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
|
||||
|
||||
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
|
||||
((POL) == COMP_OutputPol_Inverted))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the hysteresis level */
|
||||
#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
|
||||
#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
|
||||
#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
|
||||
#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
|
||||
|
||||
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Low) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Mode
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the power consumption values */
|
||||
#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
|
||||
#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
|
||||
#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
|
||||
#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
|
||||
|
||||
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
|
||||
((MODE) == COMP_Mode_LowPower) || \
|
||||
((MODE) == COMP_Mode_MediumSpeed) || \
|
||||
((MODE) == COMP_Mode_HighSpeed))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_WindowMode
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
|
||||
((WINDOW) == COMP_Selection_COMP4) || \
|
||||
((WINDOW) == COMP_Selection_COMP6))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the COMP configuration to the default reset state ****/
|
||||
void COMP_DeInit(uint32_t COMP_Selection);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
||||
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
|
||||
/* COMP configuration locking function ****************************************/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CRC_H
|
||||
#define __STM32F30x_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_ReverseInputData
|
||||
* @{
|
||||
*/
|
||||
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
|
||||
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
|
||||
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
|
||||
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
|
||||
|
||||
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
|
||||
((DATA) == CRC_ReverseInputData_8bits) || \
|
||||
((DATA) == CRC_ReverseInputData_16bits) || \
|
||||
((DATA) == CRC_ReverseInputData_32bits))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_PolynomialSize
|
||||
* @{
|
||||
*/
|
||||
#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
|
||||
|
||||
#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
|
||||
((SIZE) == CRC_PolSize_8) || \
|
||||
((SIZE) == CRC_PolSize_16) || \
|
||||
((SIZE) == CRC_PolSize_32))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Configuration of the CRC computation unit **********************************/
|
||||
void CRC_DeInit(void);
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue);
|
||||
void CRC_SetPolynomial(uint32_t CRC_Pol);
|
||||
|
||||
/* CRC computation ************************************************************/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
|
||||
/* Independent register (IDR) access (write/read) *****************************/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DAC_H
|
||||
#define __STM32F30x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
|
||||
the DAC channel output switch is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_buffer_switch */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
|
||||
((PERIPH) == DAC2))
|
||||
|
||||
#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_buffer_switch
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
|
||||
#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
|
||||
((STATE) == DAC_BufferSwitch_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(DAC_TypeDef* DACx);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DBGMCU_H
|
||||
#define __STM32F30x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
|
||||
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xBD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM20_STOP ((uint32_t)0x00000020)
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFC0) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Device and Revision ID management functions ********************************/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
|
||||
/* Peripherals Configuration functions ****************************************/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,436 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DMA_H
|
||||
#define __STM32F30x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_PeripheralDST DMA_CCR_DIR
|
||||
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
|
||||
((DIR) == DMA_DIR_PeripheralDST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralInc_Enable DMA_CCR_PINC
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
|
||||
((STATE) == DMA_PeripheralInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryInc_Enable DMA_CCR_MINC
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
|
||||
((STATE) == DMA_MemoryInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
|
||||
#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
|
||||
#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular DMA_CCR_CIRC
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh DMA_CCR_PL
|
||||
#define DMA_Priority_High DMA_CCR_PL_1
|
||||
#define DMA_Priority_Medium DMA_CCR_PL_0
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_M2M_Enable DMA_CCR_MEM2MEM
|
||||
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state ******/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
|
||||
/* Data Counter functions******************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the EXTI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_EXTI_H
|
||||
#define __STM32F30x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
|
||||
Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
|
||||
Connected to the RTC Alarm
|
||||
event */
|
||||
#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
|
||||
Connected to the USB Device
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
|
||||
Connected to the RTC Tamper
|
||||
and Time Stamp events */
|
||||
#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
|
||||
Connected to the RTC wakeup
|
||||
event */
|
||||
#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
|
||||
Connected to the Comparator 1
|
||||
event */
|
||||
#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
|
||||
Connected to the Comparator 2
|
||||
event */
|
||||
#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
|
||||
Connected to the I2C1 wakeup
|
||||
event */
|
||||
#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
|
||||
Connected to the I2C2 wakeup
|
||||
event */
|
||||
#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
|
||||
Connected to the USART1 wakeup
|
||||
event */
|
||||
#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
|
||||
Connected to the USART2 wakeup
|
||||
event */
|
||||
#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
|
||||
reserved */
|
||||
#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
|
||||
Connected to the USART3 wakeup
|
||||
event */
|
||||
#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
|
||||
Connected to the Comparator 3
|
||||
event */
|
||||
#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
|
||||
Connected to the Comparator 4
|
||||
event */
|
||||
#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
|
||||
Connected to the Comparator 5
|
||||
event */
|
||||
#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
|
||||
Connected to the Comparator 6
|
||||
event */
|
||||
#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
|
||||
Connected to the Comparator 7
|
||||
event */
|
||||
#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
|
||||
Connected to the USART4 wakeup
|
||||
event */
|
||||
#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
|
||||
Connected to the USART5 wakeup
|
||||
event */
|
||||
|
||||
#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
|
||||
#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
|
||||
((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
|
||||
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
|
||||
((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
|
||||
((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_FLASH_H
|
||||
#define __STM32F30x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_DATA_ADDRESS
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
|
||||
#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
|
||||
|
||||
#ifdef STM32F303xE
|
||||
#define OB_WRP_Pages62to263 ((uint32_t)0x80000000) /* Write protection of page 62 to 263 */
|
||||
#else
|
||||
#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F303xE */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Protection Level
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_BOOT1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Timeout_definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_Launch(void);
|
||||
FLASH_Status FLASH_OB_Erase(void);
|
||||
FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
|
||||
FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
|
||||
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
|
||||
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,722 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_fmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the FMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_FMC_H
|
||||
#define __STM32F30x_FMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 1 and 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 1 and 255.
|
||||
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 15.
|
||||
@note This parameter is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 2 and 16.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 2 and 17 in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FMC_Access_Mode */
|
||||
}FMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FMC_Memory_Type */
|
||||
|
||||
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
|
||||
|
||||
uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wrap_Mode */
|
||||
|
||||
uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Timing */
|
||||
|
||||
uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
|
||||
This parameter can be a value of @ref FMC_Write_Operation */
|
||||
|
||||
uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Signal */
|
||||
|
||||
uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FMC_Extended_Mode */
|
||||
|
||||
uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FMC_AsynchronousWait */
|
||||
|
||||
uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FMC_Write_Burst */
|
||||
|
||||
|
||||
FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
|
||||
|
||||
FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
|
||||
}FMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FMC NAND and PCCARD Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 255.*/
|
||||
|
||||
uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command de-assertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
}FMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NAND Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FMC_NAND_Bank */
|
||||
|
||||
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FMC_Wait_feature */
|
||||
|
||||
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FMC_NAND_Data_Width */
|
||||
|
||||
uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FMC_ECC */
|
||||
|
||||
uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 255. */
|
||||
|
||||
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
|
||||
}FMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FMC_Wait_feature */
|
||||
|
||||
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 255. */
|
||||
|
||||
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
|
||||
}FMC_PCCARDInitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
|
||||
#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FMC_NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FMC_DataAddressMux_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FMC_MemoryType_NOR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NORSRAM_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
|
||||
#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FMC_AsynchronousWait_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
|
||||
#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FMC_WaitSignalPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
|
||||
#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
|
||||
((MODE) == FMC_WrapMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
|
||||
#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FMC_WriteOperation_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
|
||||
#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FMC_ExtendedMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
|
||||
((BURST) == FMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Continous_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
|
||||
#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
|
||||
|
||||
#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
|
||||
((CCLOCK) == FMC_CClock_SyncAsync))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
|
||||
#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
|
||||
((MODE) == FMC_AccessMode_B) || \
|
||||
((MODE) == FMC_AccessMode_C) || \
|
||||
((MODE) == FMC_AccessMode_D))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FMC_Waitfeature_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_Data_Width
|
||||
* @{
|
||||
*/
|
||||
#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_ECC
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
|
||||
((STATE) == FMC_ECC_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
|
||||
#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_8192Bytes))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
|
||||
#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
|
||||
((IT) == FMC_IT_Level) || \
|
||||
((IT) == FMC_IT_FallingEdge))
|
||||
|
||||
#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND) || \
|
||||
((BANK) == FMC_Bank4_PCCARD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FMC_FLAG_Level) || \
|
||||
((FLAG) == FMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND) || \
|
||||
((BANK) == FMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* NOR/SRAM Controller functions **********************************************/
|
||||
void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
|
||||
void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
|
||||
void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
|
||||
void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
|
||||
/* NAND Controller functions **************************************************/
|
||||
void FMC_NANDDeInit(uint32_t FMC_Bank);
|
||||
void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
|
||||
void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
|
||||
void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
uint32_t FMC_GetECC(uint32_t FMC_Bank);
|
||||
|
||||
/* PCCARD Controller functions ************************************************/
|
||||
void FMC_PCCARDDeInit(void);
|
||||
void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
|
||||
void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
|
||||
void FMC_PCCARDCmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
|
||||
FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
|
||||
void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
|
||||
ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
|
||||
void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_FMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_GPIO_H
|
||||
#define __STM32F30x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH))
|
||||
|
||||
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC)|| \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOF))
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
|
||||
GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
|
||||
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
|
||||
((SPEED) == GPIO_Speed_Level_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
|
||||
MCO, NJTRST, TRACED, TRACECK */
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
|
||||
USART1, USART2, USART3 */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
|
||||
COMP5_OUT, COMP6_OUT */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
|
||||
((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
|
||||
((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
|
||||
((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
|
||||
((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
|
||||
((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
|
||||
((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
|
||||
((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Speed_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
|
||||
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the GPIO configuration to the default reset state *****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,477 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_I2C_H
|
||||
#define __STM32F30x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual*/
|
||||
|
||||
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_Analog_Filter */
|
||||
|
||||
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between 0x00 and 0x0F */
|
||||
|
||||
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter can be a 7-bit or 10-bit address */
|
||||
|
||||
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
|
||||
/** @defgroup I2C_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
|
||||
((FILTER) == I2C_AnalogFilter_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint32_t)0x00000000)
|
||||
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
|
||||
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
|
||||
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_Ack_Disable I2C_CR2_NACK
|
||||
|
||||
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
|
||||
((ACK) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
|
||||
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
|
||||
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
|
||||
#define I2C_Direction_Receiver ((uint16_t)0x0400)
|
||||
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
|
||||
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
|
||||
|
||||
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_slave_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_own_address2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NoMask ((uint8_t)0x00)
|
||||
#define I2C_OA2_Mask01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_Mask02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_Mask03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_Mask04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_Mask05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_Mask06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_Mask07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
|
||||
((MASK) == I2C_OA2_Mask01) || \
|
||||
((MASK) == I2C_OA2_Mask02) || \
|
||||
((MASK) == I2C_OA2_Mask03) || \
|
||||
((MASK) == I2C_OA2_Mask04) || \
|
||||
((MASK) == I2C_OA2_Mask05) || \
|
||||
((MASK) == I2C_OA2_Mask06) || \
|
||||
((MASK) == I2C_OA2_Mask07))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_TIMINGR ((uint8_t)0x10)
|
||||
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
|
||||
#define I2C_Register_ISR ((uint8_t)0x18)
|
||||
#define I2C_Register_ICR ((uint8_t)0x1C)
|
||||
#define I2C_Register_PECR ((uint8_t)0x20)
|
||||
#define I2C_Register_RXDR ((uint8_t)0x24)
|
||||
#define I2C_Register_TXDR ((uint8_t)0x28)
|
||||
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_TIMINGR) || \
|
||||
((REGISTER) == I2C_Register_TIMEOUTR) || \
|
||||
((REGISTER) == I2C_Register_ISR) || \
|
||||
((REGISTER) == I2C_Register_ICR) || \
|
||||
((REGISTER) == I2C_Register_PECR) || \
|
||||
((REGISTER) == I2C_Register_RXDR) || \
|
||||
((REGISTER) == I2C_Register_TXDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_NACKF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
|
||||
((FLAG) == I2C_FLAG_BUSY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_TXIS I2C_ISR_TXIS
|
||||
#define I2C_IT_RXNE I2C_ISR_RXNE
|
||||
#define I2C_IT_ADDR I2C_ISR_ADDR
|
||||
#define I2C_IT_NACKF I2C_ISR_NACKF
|
||||
#define I2C_IT_STOPF I2C_ISR_STOPF
|
||||
#define I2C_IT_TC I2C_ISR_TC
|
||||
#define I2C_IT_TCR I2C_ISR_TCR
|
||||
#define I2C_IT_BERR I2C_ISR_BERR
|
||||
#define I2C_IT_ARLO I2C_ISR_ARLO
|
||||
#define I2C_IT_OVR I2C_ISR_OVR
|
||||
#define I2C_IT_PECERR I2C_ISR_PECERR
|
||||
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_IT_ALERT I2C_ISR_ALERT
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
|
||||
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
|
||||
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
|
||||
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Reload_Mode I2C_CR2_RELOAD
|
||||
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
|
||||
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
|
||||
|
||||
|
||||
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
|
||||
((MODE) == I2C_AutoEnd_Mode) || \
|
||||
((MODE) == I2C_SoftEnd_Mode))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_No_StartStop ((uint32_t)0x00000000)
|
||||
#define I2C_Generate_Stop I2C_CR2_STOP
|
||||
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_Generate_Start_Write I2C_CR2_START
|
||||
|
||||
|
||||
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
|
||||
((MODE) == I2C_Generate_Start_Read) || \
|
||||
((MODE) == I2C_Generate_Start_Write) || \
|
||||
((MODE) == I2C_No_StartStop))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
|
||||
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Communications handling functions ******************************************/
|
||||
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
|
||||
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
|
||||
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
|
||||
|
||||
/* SMBUS management functions ************************************************/
|
||||
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* I2C registers management functions *****************************************/
|
||||
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
|
||||
/* Data transfers management functions ****************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_IWDG_H
|
||||
#define __STM32F30x_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IWDG_FLAG_WVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
|
||||
((FLAG) == IWDG_FLAG_WVU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Reload_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_CounterWindow_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_MISC_H
|
||||
#define __STM32F30x_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type (For
|
||||
the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32f30x.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15.
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15.
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the operational
|
||||
* amplifiers (OPAMP) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_OPAMP_H
|
||||
#define __STM32F30x_OPAMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief OPAMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
|
||||
This parameter can be a value of @ref OPAMP_InvertingInput */
|
||||
|
||||
uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
|
||||
This parameter can be a value of @ref OPAMP_NonInvertingInput */
|
||||
|
||||
}OPAMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
|
||||
#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
|
||||
#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
|
||||
#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
|
||||
|
||||
#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP2) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP3) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
|
||||
#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
|
||||
|
||||
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
|
||||
((INPUT) == OPAMP_InvertingInput_IO2) || \
|
||||
((INPUT) == OPAMP_InvertingInput_PGA) || \
|
||||
((INPUT) == OPAMP_InvertingInput_Vout))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
|
||||
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO2) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO3) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PGAGain_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
|
||||
#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
|
||||
#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
|
||||
#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
|
||||
|
||||
#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PGAConnect_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
|
||||
#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
|
||||
#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
|
||||
|
||||
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
|
||||
((CONNECT) == OPAMP_PGAConnect_IO1) || \
|
||||
((CONNECT) == OPAMP_PGAConnect_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_SecondaryInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
|
||||
((INVINPUT) == OPAMP_InvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Input
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
|
||||
#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
|
||||
|
||||
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
|
||||
((INPUT) == OPAMP_Input_NonInverting))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Vref
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
|
||||
#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
|
||||
#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
|
||||
#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
|
||||
|
||||
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
|
||||
((VREF) == OPAMP_Vref_10VDDA) || \
|
||||
((VREF) == OPAMP_Vref_50VDDA) || \
|
||||
((VREF) == OPAMP_Vref_90VDDA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Trimming
|
||||
*/
|
||||
|
||||
#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
|
||||
#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
|
||||
|
||||
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
|
||||
((TRIMMING) == OPAMP_Trimming_User))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_TrimValue
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
|
||||
#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the OPAMP configuration to the default reset state ***/
|
||||
void OPAMP_DeInit(uint32_t OPAMP_Selection);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
|
||||
void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
|
||||
void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
|
||||
|
||||
/* Calibration functions ******************************************************/
|
||||
void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
|
||||
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
|
||||
void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
|
||||
/* OPAMP configuration locking function ***************************************/
|
||||
void OPAMP_LockConfig(uint32_t OPAMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_OPAMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_PWR_H
|
||||
#define __STM32F30x_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
|
||||
#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
|
||||
#define PWR_WakeUpPin_3 PWR_CSR_EWUP3
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
|
||||
((PIN) == PWR_WakeUpPin_2) || \
|
||||
((PIN) == PWR_WakeUpPin_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower PWR_CR_LPSDSR
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* Backup Domain Access function **********************************************/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Flags management functions *************************************************/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,731 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the RCC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_RCC_H
|
||||
#define __STM32F30x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency;
|
||||
uint32_t HCLK_Frequency;
|
||||
uint32_t PCLK1_Frequency;
|
||||
uint32_t PCLK2_Frequency;
|
||||
uint32_t ADC12CLK_Frequency;
|
||||
uint32_t ADC34CLK_Frequency;
|
||||
uint32_t I2C1CLK_Frequency;
|
||||
uint32_t I2C2CLK_Frequency;
|
||||
uint32_t I2C3CLK_Frequency;
|
||||
uint32_t TIM1CLK_Frequency;
|
||||
uint32_t HRTIM1CLK_Frequency;
|
||||
uint32_t TIM8CLK_Frequency;
|
||||
uint32_t TIM2CLK_Frequency;
|
||||
uint32_t TIM3CLK_Frequency;
|
||||
uint32_t USART1CLK_Frequency;
|
||||
uint32_t USART2CLK_Frequency;
|
||||
uint32_t USART3CLK_Frequency;
|
||||
uint32_t UART4CLK_Frequency;
|
||||
uint32_t UART5CLK_Frequency;
|
||||
uint32_t TIM15CLK_Frequency;
|
||||
uint32_t TIM16CLK_Frequency;
|
||||
uint32_t TIM17CLK_Frequency;
|
||||
uint32_t TIM20CLK_Frequency;
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F303xE devices */
|
||||
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
|
||||
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
|
||||
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_PREDIV1)|| \
|
||||
((SOURCE) == RCC_PLLSource_HSI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Multiplication_Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
|
||||
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
|
||||
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
|
||||
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
|
||||
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
|
||||
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
|
||||
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
|
||||
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
|
||||
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
|
||||
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
|
||||
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
|
||||
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
|
||||
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
|
||||
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
|
||||
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||
((MUL) == RCC_PLLMul_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PREDIV1_division_factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
|
||||
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
|
||||
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
|
||||
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
|
||||
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
|
||||
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
|
||||
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
|
||||
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
|
||||
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
|
||||
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
|
||||
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
|
||||
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
|
||||
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
|
||||
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
|
||||
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
|
||||
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
|
||||
|
||||
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
|
||||
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
|
||||
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
|
||||
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
|
||||
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
|
||||
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
|
||||
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
|
||||
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
|
||||
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
|
||||
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ADC1 & ADC2 */
|
||||
#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
|
||||
#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
|
||||
#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
|
||||
#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
|
||||
#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
|
||||
#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
|
||||
#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
|
||||
#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
|
||||
#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
|
||||
#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
|
||||
#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
|
||||
#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
|
||||
|
||||
/* ADC3 & ADC4 */
|
||||
#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
|
||||
#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
|
||||
#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
|
||||
#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
|
||||
#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
|
||||
#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
|
||||
#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
|
||||
#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
|
||||
#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
|
||||
#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
|
||||
#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
|
||||
#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
|
||||
#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
|
||||
|
||||
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_TIM_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_TIM1CLK_PCLK ((uint32_t)0x00000000)
|
||||
#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
|
||||
|
||||
#define RCC_TIM8CLK_PCLK ((uint32_t)0x10000000)
|
||||
#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
|
||||
|
||||
#define RCC_TIM15CLK_PCLK ((uint32_t)0x20000000)
|
||||
#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
|
||||
|
||||
#define RCC_TIM16CLK_PCLK ((uint32_t)0x30000000)
|
||||
#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
|
||||
|
||||
#define RCC_TIM17CLK_PCLK ((uint32_t)0x40000000)
|
||||
#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
|
||||
|
||||
#define RCC_TIM20CLK_PCLK ((uint32_t)0x50000000)
|
||||
#define RCC_TIM20CLK_PLLCLK ((uint32_t)0x50008000)
|
||||
|
||||
#define RCC_TIM2CLK_PCLK ((uint32_t)0x60000000)
|
||||
#define RCC_TIM2CLK_PLLCLK ((uint32_t)0x61000000)
|
||||
|
||||
#define RCC_TIM3TIM4CLK_PCLK ((uint32_t)0x70000000)
|
||||
#define RCC_TIM3TIM4CLK_PLLCLK ((uint32_t)0x72000000)
|
||||
|
||||
#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_PCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
|
||||
((TIMCLK) == RCC_TIM8CLK_PCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
|
||||
((TIMCLK) == RCC_TIM15CLK_PCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
|
||||
((TIMCLK) == RCC_TIM16CLK_PCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
|
||||
((TIMCLK) == RCC_TIM17CLK_PCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK)|| \
|
||||
((TIMCLK) == RCC_TIM20CLK_PCLK) || ((TIMCLK) == RCC_TIM20CLK_PLLCLK)|| \
|
||||
((TIMCLK) == RCC_TIM2CLK_PCLK) || ((TIMCLK) == RCC_TIM2CLK_PLLCLK)|| \
|
||||
((TIMCLK) == RCC_TIM3TIM4CLK_PCLK) || ((TIMCLK) == RCC_TIM3TIM4CLK_PLLCLK))
|
||||
/* legacy RCC_TIM_clock_source*/
|
||||
#define RCC_TIM1CLK_HCLK RCC_TIM1CLK_PCLK
|
||||
#define RCC_TIM8CLK_HCLK RCC_TIM8CLK_PCLK
|
||||
#define RCC_TIM15CLK_HCLK RCC_TIM15CLK_PCLK
|
||||
#define RCC_TIM16CLK_HCLK RCC_TIM16CLK_PCLK
|
||||
#define RCC_TIM17CLK_HCLK RCC_TIM17CLK_PCLK
|
||||
#define RCC_TIM20CLK_HCLK RCC_TIM20CLK_PCLK
|
||||
#define RCC_TIM2CLK_HCLK RCC_TIM2CLK_PCLK
|
||||
#define RCC_TIM3CLK_HCLK RCC_TIM3TIM4CLK_PCLK
|
||||
#define RCC_TIM3CLK_PLLCLK RCC_TIM3TIM4CLK_PLLCLK
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HRTIM_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
|
||||
#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
|
||||
|
||||
#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2C_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
|
||||
|
||||
#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
|
||||
#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
|
||||
|
||||
#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
|
||||
#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
|
||||
|
||||
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
|
||||
((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
|
||||
((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_USART_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
|
||||
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
|
||||
#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
|
||||
#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
|
||||
|
||||
#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
|
||||
#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
|
||||
#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
|
||||
#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
|
||||
|
||||
#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
|
||||
#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
|
||||
#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
|
||||
#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
|
||||
|
||||
#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
|
||||
#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
|
||||
#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
|
||||
#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
|
||||
|
||||
#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
|
||||
#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
|
||||
#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
|
||||
#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
|
||||
|
||||
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
|
||||
((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
|
||||
((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
|
||||
((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
|
||||
((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
|
||||
|
||||
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_LSE_ON RCC_BDCR_LSEON
|
||||
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
|
||||
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
|
||||
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
|
||||
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
|
||||
/** @defgroup RCC_LSE_Drive_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
|
||||
#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
|
||||
#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
|
||||
#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
|
||||
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
|
||||
((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
|
||||
#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
|
||||
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
|
||||
#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
|
||||
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
|
||||
#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
|
||||
#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
|
||||
#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
|
||||
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
|
||||
#define RCC_AHBPeriph_FMC RCC_AHBENR_FMCEN
|
||||
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
|
||||
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
|
||||
#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
|
||||
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FF88) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FFDF) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
|
||||
#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
|
||||
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
|
||||
#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
|
||||
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
|
||||
#define RCC_APB2Periph_SPI4 RCC_APB2ENR_SPI4EN
|
||||
#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
|
||||
#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
|
||||
#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
|
||||
#define RCC_APB2Periph_TIM20 RCC_APB2ENR_TIM20EN
|
||||
#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFE807FE) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
|
||||
#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
|
||||
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
|
||||
#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
|
||||
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
|
||||
#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
|
||||
#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
|
||||
#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
|
||||
#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
|
||||
#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
|
||||
#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
|
||||
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
|
||||
#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
|
||||
#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
|
||||
#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
|
||||
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
|
||||
#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
|
||||
#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
|
||||
#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
|
||||
#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
|
||||
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCOSource_LSI ((uint8_t)0x02)
|
||||
#define RCC_MCOSource_LSE ((uint8_t)0x03)
|
||||
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCOSource_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCOSource_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
#define RCC_MCOSource_PLLCLK ((uint8_t)0x87)
|
||||
|
||||
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
|
||||
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
|
||||
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
|
||||
((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| ((SOURCE) == RCC_MCOSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCOPrescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
|
||||
#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
|
||||
#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
|
||||
#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
|
||||
#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
|
||||
#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
|
||||
#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
|
||||
#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
|
||||
|
||||
#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_2) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_4) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_8) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_16) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_32) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_64) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_USB_Device_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||||
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x11)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
|
||||
#define RCC_FLAG_MCOF ((uint8_t)0x9C)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_MCOF))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint32_t RCC_LSE);
|
||||
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
#ifdef STM32F303xC
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource);
|
||||
#else
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
|
||||
#endif /* STM32F303xC */
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
|
||||
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
|
||||
void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
|
||||
void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,852 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_RTC_H
|
||||
#define __STM32F30x_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x1FFF */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_HourFormat_12 is selected or 0-23 range if
|
||||
the RTC_HourFormat_24 is selected. */
|
||||
|
||||
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t RTC_Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter
|
||||
must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this
|
||||
parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_H12_AM ((uint8_t)0x00)
|
||||
#define RTC_H12_PM ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_Month_January ((uint8_t)0x01)
|
||||
#define RTC_Month_February ((uint8_t)0x02)
|
||||
#define RTC_Month_March ((uint8_t)0x03)
|
||||
#define RTC_Month_April ((uint8_t)0x04)
|
||||
#define RTC_Month_May ((uint8_t)0x05)
|
||||
#define RTC_Month_June ((uint8_t)0x06)
|
||||
#define RTC_Month_July ((uint8_t)0x07)
|
||||
#define RTC_Month_August ((uint8_t)0x08)
|
||||
#define RTC_Month_September ((uint8_t)0x09)
|
||||
#define RTC_Month_October ((uint8_t)0x10)
|
||||
#define RTC_Month_November ((uint8_t)0x11)
|
||||
#define RTC_Month_December ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_Weekday_Monday ((uint8_t)0x01)
|
||||
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
|
||||
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
|
||||
#define RTC_Weekday_Thursday ((uint8_t)0x04)
|
||||
#define RTC_Weekday_Friday ((uint8_t)0x05)
|
||||
#define RTC_Weekday_Saturday ((uint8_t)0x06)
|
||||
#define RTC_Weekday_Sunday ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
|
||||
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
|
||||
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
|
||||
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
|
||||
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
|
||||
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Alarm_A ((uint32_t)0x00000100)
|
||||
#define RTC_Alarm_B ((uint32_t)0x00000200)
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
|
||||
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
|
||||
#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
|
||||
#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
|
||||
((EDGE) == RTC_TimeStampEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Output_Disable ((uint32_t)0x00000000)
|
||||
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
|
||||
#define RTC_Output_AlarmB ((uint32_t)0x00400000)
|
||||
#define RTC_Output_WakeUp ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
|
||||
((OUTPUT) == RTC_Output_AlarmA) || \
|
||||
((OUTPUT) == RTC_Output_AlarmB) || \
|
||||
((OUTPUT) == RTC_Output_WakeUp))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
|
||||
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Digital_Calibration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
|
||||
#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
|
||||
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
|
||||
((SIGN) == RTC_CalibSign_Negative))
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
|
||||
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
|
||||
((OUTPUT) == RTC_CalibOutput_1Hz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVE) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
|
||||
((OPERATION) == RTC_StoreOperation_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
|
||||
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_HighLevel))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active leve. */
|
||||
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
|
||||
((FILTER) == RTC_TamperFilter_2Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_4Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_8Sample))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
|
||||
input tamper 1 */
|
||||
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
|
||||
input tamper 2 */
|
||||
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
|
||||
input tamper 3 */
|
||||
|
||||
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
|
||||
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
|
||||
((TYPE) == RTC_OutputType_PushPull))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
|
||||
((SEL) == RTC_ShiftAdd1S_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4) || \
|
||||
((BKP) == RTC_BKP_DR5) || \
|
||||
((BKP) == RTC_BKP_DR6) || \
|
||||
((BKP) == RTC_BKP_DR7) || \
|
||||
((BKP) == RTC_BKP_DR8) || \
|
||||
((BKP) == RTC_BKP_DR9) || \
|
||||
((BKP) == RTC_BKP_DR10) || \
|
||||
((BKP) == RTC_BKP_DR11) || \
|
||||
((BKP) == RTC_BKP_DR12) || \
|
||||
((BKP) == RTC_BKP_DR13) || \
|
||||
((BKP) == RTC_BKP_DR14) || \
|
||||
((BKP) == RTC_BKP_DR15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Format_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_Format_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
|
||||
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
|
||||
((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
|
||||
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
|
||||
((IT) == RTC_IT_TAMP3))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
|
||||
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
|
||||
uint32_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Digital Calibration configuration functions ********************************/
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
|
||||
RTC_DateTypeDef* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
|
||||
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
|
||||
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
|
||||
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
|
||||
void RTC_TamperPullUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Backup Data Registers configuration functions ******************************/
|
||||
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
|
||||
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
|
||||
|
||||
/* Output Type Config configuration functions *********************************/
|
||||
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint32_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,608 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_SPI_H
|
||||
#define __STM32F30x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == SPI4))
|
||||
|
||||
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == SPI4) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_4b ((uint16_t)0x0300)
|
||||
#define SPI_DataSize_5b ((uint16_t)0x0400)
|
||||
#define SPI_DataSize_6b ((uint16_t)0x0500)
|
||||
#define SPI_DataSize_7b ((uint16_t)0x0600)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0700)
|
||||
#define SPI_DataSize_9b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_10b ((uint16_t)0x0900)
|
||||
#define SPI_DataSize_11b ((uint16_t)0x0A00)
|
||||
#define SPI_DataSize_12b ((uint16_t)0x0B00)
|
||||
#define SPI_DataSize_13b ((uint16_t)0x0C00)
|
||||
#define SPI_DataSize_14b ((uint16_t)0x0D00)
|
||||
#define SPI_DataSize_15b ((uint16_t)0x0E00)
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0F00)
|
||||
#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
|
||||
((SIZE) == SPI_DataSize_5b) || \
|
||||
((SIZE) == SPI_DataSize_6b) || \
|
||||
((SIZE) == SPI_DataSize_7b) || \
|
||||
((SIZE) == SPI_DataSize_8b) || \
|
||||
((SIZE) == SPI_DataSize_9b) || \
|
||||
((SIZE) == SPI_DataSize_10b) || \
|
||||
((SIZE) == SPI_DataSize_11b) || \
|
||||
((SIZE) == SPI_DataSize_12b) || \
|
||||
((SIZE) == SPI_DataSize_13b) || \
|
||||
((SIZE) == SPI_DataSize_14b) || \
|
||||
((SIZE) == SPI_DataSize_15b) || \
|
||||
((SIZE) == SPI_DataSize_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRCLength_8b ((uint16_t)0x0000)
|
||||
#define SPI_CRCLength_16b ((uint16_t)0x0800)
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
|
||||
((LENGTH) == SPI_CRCLength_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
|
||||
#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
|
||||
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
|
||||
((THRESHOLD) == SPI_RxFIFOThreshold_QF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_last_DMA_transfers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
|
||||
#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
|
||||
#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
|
||||
#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
|
||||
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
|
||||
#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
|
||||
#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
|
||||
#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
|
||||
#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
|
||||
|
||||
|
||||
|
||||
#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
|
||||
((FLAG) == I2S_FLAG_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SPI configuration to the default reset state*******/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
|
||||
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,427 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*!< Define to prevent recursive inclusion -----------------------------------*/
|
||||
#ifndef __STM32F30x_SYSCFG_H
|
||||
#define __STM32F30x_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
|
||||
#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOF)|| \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOG)|| \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Memory_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x04)
|
||||
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_FMC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_DMA_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
|
||||
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
|
||||
#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */
|
||||
|
||||
#define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */
|
||||
#define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */
|
||||
#define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */
|
||||
|
||||
#define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */
|
||||
#define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */
|
||||
#define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */
|
||||
|
||||
#define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */
|
||||
#define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */
|
||||
#define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */
|
||||
|
||||
#define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */
|
||||
#define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */
|
||||
#define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */
|
||||
|
||||
#define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */
|
||||
#define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */
|
||||
#define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */
|
||||
|
||||
#define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */
|
||||
#define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */
|
||||
|
||||
/* SYSCFG_DMA_Remap_Legacy */
|
||||
#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */
|
||||
#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */
|
||||
|
||||
#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM16) || \
|
||||
((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
|
||||
((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \
|
||||
((REMAP) == SYSCFG_DMARemapCh2_ADC2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Trigger_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */
|
||||
#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
|
||||
#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */
|
||||
#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */
|
||||
|
||||
#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
|
||||
((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
|
||||
((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
|
||||
((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EncoderRemap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
|
||||
#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
|
||||
#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_I2C_FastModePlus_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#define SYSCFG_I2CFastModePlus_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
|
||||
#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_I2C2)|| \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_I2C3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FPU_Interrupt_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
|
||||
#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
|
||||
#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
|
||||
#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
|
||||
#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
|
||||
#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
|
||||
|
||||
#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Lock_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
|
||||
#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
|
||||
#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
|
||||
|
||||
#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
|
||||
((CONFIG) == SYSCFG_Break_SRAMParity) || \
|
||||
((CONFIG) == SYSCFG_Break_Lockup))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Trigger_Remapping
|
||||
* @{
|
||||
*/
|
||||
#define REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
|
||||
0: No remap (TIM1_CC3)
|
||||
1: Remap (TIM20_TRGO) */
|
||||
#define REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
|
||||
0: No remap (TIM2_CC2)
|
||||
1: Remap (TIM20_TRGO2) */
|
||||
#define REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
|
||||
0: No remap (TIM4_CC4)
|
||||
1: Remap (TIM20_CC1) */
|
||||
#define REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
|
||||
0: No remap (TIM6_TRGO)
|
||||
1: Remap (TIM20_CC2) */
|
||||
#define REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
|
||||
0: No remap (TIM3_CC4)
|
||||
1: Remap (TIM20_CC3) */
|
||||
#define REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
|
||||
0: No remap (TIM2_CC1)
|
||||
1: Remap (TIM20_TRGO) */
|
||||
#define REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
|
||||
0: No remap (EXTI line 15)
|
||||
1: Remap (TIM20_TRGO2) */
|
||||
#define REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
|
||||
0: No remap (TIM3_CC1)
|
||||
1: Remap (TIM20_CC4) */
|
||||
#define REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
|
||||
0: No remap (EXTI line 2)
|
||||
1: Remap (TIM20_TRGO) */
|
||||
#define REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
|
||||
0: No remap (TIM4_CC1)
|
||||
1: Remap (TIM20_TRGO2) */
|
||||
#define REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
|
||||
0: No remap (TIM2_CC1)
|
||||
1: Remap (TIM20_CC1) */
|
||||
#define REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
|
||||
0: No remap (TIM4_CC3)
|
||||
1: Remap (TIM20_TRGO) */
|
||||
#define REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
|
||||
0: No remap (TIM1_CC3)
|
||||
1: Remap (TIM20_TRGO2) */
|
||||
#define REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
|
||||
0: No remap (TIM7_TRGO)
|
||||
1: Remap (TIM20_CC2) */
|
||||
|
||||
#define IS_SYSCFG_ADC_TRIGGER_REMAP(RMP) (((RMP) == REMAPADCTRIGGER_ADC12_EXT2) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_EXT3) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_EXT5) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_EXT13) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_EXT15) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_JEXT3) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_JEXT6) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC12_JEXT13) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_EXT5) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_EXT6) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_EXT15) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_JEXT5) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_JEXT11) || \
|
||||
((RMP) == REMAPADCTRIGGER_ADC34_JEXT14))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAMWRP_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
|
||||
#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
|
||||
#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
|
||||
#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
|
||||
#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
|
||||
#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
|
||||
#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
|
||||
#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
|
||||
#define SYSCFG_SRAMWRP_Page8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
|
||||
#define SYSCFG_SRAMWRP_Page9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
|
||||
#define SYSCFG_SRAMWRP_Page10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
|
||||
#define SYSCFG_SRAMWRP_Page11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
|
||||
#define SYSCFG_SRAMWRP_Page12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
|
||||
#define SYSCFG_SRAMWRP_Page13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
|
||||
#define SYSCFG_SRAMWRP_Page14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
|
||||
#define SYSCFG_SRAMWRP_Page15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
|
||||
|
||||
#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFF0000) == 0x00000000) && ((PAGE) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
|
||||
|
||||
#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SYSCFG configuration to the default reset state **/
|
||||
void SYSCFG_DeInit(void);
|
||||
|
||||
/* SYSCFG configuration functions *********************************************/
|
||||
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
|
||||
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
|
||||
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
|
||||
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
|
||||
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
|
||||
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
|
||||
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
|
||||
void SYSCFG_BypassParityCheckDisable(void);
|
||||
void SYSCFG_ADCTriggerRemapConfig(uint32_t SYSCFG_ADCTriggerRemap, FunctionalState NewState);
|
||||
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
|
||||
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
|
||||
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,607 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_USART_H
|
||||
#define __STM32F30x_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t USART_HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3))
|
||||
|
||||
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4))
|
||||
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint32_t)0x00000000)
|
||||
#define USART_WordLength_9b USART_CR1_M
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint32_t)0x00000000)
|
||||
#define USART_StopBits_2 USART_CR2_STOP_1
|
||||
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint32_t)0x00000000)
|
||||
#define USART_Parity_Even USART_CR1_PCE
|
||||
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx USART_CR1_RE
|
||||
#define USART_Mode_Tx USART_CR1_TE
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
|
||||
((MODE) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
|
||||
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
|
||||
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
|
||||
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Clock_Disable ((uint32_t)0x00000000)
|
||||
#define USART_Clock_Enable USART_CR2_CLKEN
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint32_t)0x00000000)
|
||||
#define USART_CPOL_High USART_CR2_CPOL
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
|
||||
#define USART_CPHA_2Edge USART_CR2_CPHA
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint32_t)0x00000000)
|
||||
#define USART_LastBit_Enable USART_CR2_LBCL
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx USART_CR3_DMAT
|
||||
#define USART_DMAReq_Rx USART_CR3_DMAR
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
|
||||
((DMAREQ) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Recception_Error
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
|
||||
#define USART_DMAOnError_Disable USART_CR3_DDRE
|
||||
#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
|
||||
((DMAERROR) == USART_DMAOnError_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_MuteMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
|
||||
#define USART_WakeUp_AddressMark USART_CR1_WAKE
|
||||
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Address_Detection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AddressLength_4b ((uint32_t)0x00000000)
|
||||
#define USART_AddressLength_7b USART_CR2_ADDM7
|
||||
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
|
||||
((ADDRESS) == USART_AddressLength_7b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_StopMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
|
||||
#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
|
||||
#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
|
||||
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
|
||||
((SOURCE) == USART_WakeUpSource_StartBit) || \
|
||||
((SOURCE) == USART_WakeUpSource_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
|
||||
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower USART_CR3_IRLP
|
||||
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DE_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DEPolarity_High ((uint32_t)0x00000000)
|
||||
#define USART_DEPolarity_Low USART_CR3_DEP
|
||||
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
|
||||
((POLARITY) == USART_DEPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Inversion_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_InvPin_Tx USART_CR2_TXINV
|
||||
#define USART_InvPin_Rx USART_CR2_RXINV
|
||||
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
|
||||
((PIN) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_AutoBaudRate_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
|
||||
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
|
||||
#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
|
||||
#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
|
||||
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
|
||||
((MODE) == USART_AutoBaudRate_FallingEdge) || \
|
||||
((MODE) == USART_AutoBaudRate_0x7FFrame) || \
|
||||
((MODE) == USART_AutoBaudRate_0x55Frame))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_OVR_DETECTION
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
|
||||
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
|
||||
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
|
||||
((OVR) == USART_OVRDetection_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USART_Request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Request_ABRRQ USART_RQR_ABRRQ
|
||||
#define USART_Request_SBKRQ USART_RQR_SBKRQ
|
||||
#define USART_Request_MMRQ USART_RQR_MMRQ
|
||||
#define USART_Request_RXFRQ USART_RQR_RXFRQ
|
||||
#define USART_Request_TXFRQ USART_RQR_TXFRQ
|
||||
|
||||
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
|
||||
((REQUEST) == USART_Request_RXFRQ) || \
|
||||
((REQUEST) == USART_Request_MMRQ) || \
|
||||
((REQUEST) == USART_Request_SBKRQ) || \
|
||||
((REQUEST) == USART_Request_ABRRQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK USART_ISR_REACK
|
||||
#define USART_FLAG_TEACK USART_ISR_TEACK
|
||||
#define USART_FLAG_WU USART_ISR_WUF
|
||||
#define USART_FLAG_RWU USART_ISR_RWU
|
||||
#define USART_FLAG_SBK USART_ISR_SBKF
|
||||
#define USART_FLAG_CM USART_ISR_CMF
|
||||
#define USART_FLAG_BUSY USART_ISR_BUSY
|
||||
#define USART_FLAG_ABRF USART_ISR_ABRF
|
||||
#define USART_FLAG_ABRE USART_ISR_ABRE
|
||||
#define USART_FLAG_EOB USART_ISR_EOBF
|
||||
#define USART_FLAG_RTO USART_ISR_RTOF
|
||||
#define USART_FLAG_nCTSS USART_ISR_CTS
|
||||
#define USART_FLAG_CTS USART_ISR_CTSIF
|
||||
#define USART_FLAG_LBD USART_ISR_LBD
|
||||
#define USART_FLAG_TXE USART_ISR_TXE
|
||||
#define USART_FLAG_TC USART_ISR_TC
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE
|
||||
#define USART_FLAG_IDLE USART_ISR_IDLE
|
||||
#define USART_FLAG_ORE USART_ISR_ORE
|
||||
#define USART_FLAG_NE USART_ISR_NE
|
||||
#define USART_FLAG_FE USART_ISR_FE
|
||||
#define USART_FLAG_PE USART_ISR_PE
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
|
||||
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
|
||||
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
|
||||
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
|
||||
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
|
||||
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @brief USART Interrupt definition
|
||||
* USART_IT possible values
|
||||
* Elements values convention: 0xZZZZYYXX
|
||||
* XX: Position of the corresponding Interrupt
|
||||
* YY: Register index
|
||||
* ZZZZ: Flag position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_WU ((uint32_t)0x00140316)
|
||||
#define USART_IT_CM ((uint32_t)0x0011010E)
|
||||
#define USART_IT_EOB ((uint32_t)0x000C011B)
|
||||
#define USART_IT_RTO ((uint32_t)0x000B011A)
|
||||
#define USART_IT_PE ((uint32_t)0x00000108)
|
||||
#define USART_IT_TXE ((uint32_t)0x00070107)
|
||||
#define USART_IT_TC ((uint32_t)0x00060106)
|
||||
#define USART_IT_RXNE ((uint32_t)0x00050105)
|
||||
#define USART_IT_IDLE ((uint32_t)0x00040104)
|
||||
#define USART_IT_LBD ((uint32_t)0x00080206)
|
||||
#define USART_IT_CTS ((uint32_t)0x0009030A)
|
||||
#define USART_IT_ERR ((uint32_t)0x00000300)
|
||||
#define USART_IT_ORE ((uint32_t)0x00030300)
|
||||
#define USART_IT_NE ((uint32_t)0x00020300)
|
||||
#define USART_IT_FE ((uint32_t)0x00010300)
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
|
||||
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
|
||||
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Global_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
|
||||
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
|
||||
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
|
||||
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
|
||||
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
|
||||
|
||||
/* STOP Mode functions ********************************************************/
|
||||
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
|
||||
|
||||
/* AutoBaudRate functions *****************************************************/
|
||||
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
|
||||
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
|
||||
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* RS485 mode functions *******************************************************/
|
||||
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
|
||||
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
|
||||
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
|
||||
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
|
||||
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the WWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_WWDG_H
|
||||
#define __STM32F30x_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation functions **************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,507 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral:
|
||||
* + Comparators configuration
|
||||
* + Window mode control
|
||||
*
|
||||
@verbatim
|
||||
|
||||
==============================================================================
|
||||
##### COMP Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The device integrates 7 analog comparators COMP1, COMP2...COMP7:
|
||||
(#) The non inverting input and inverting input can be set to GPIO pins
|
||||
as shown in table1. COMP Inputs below.
|
||||
|
||||
(#) The COMP output is internally is available using COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
|
||||
|
||||
(#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
|
||||
Refer to table 3. COMP Outputs redirection to embedded timers below.
|
||||
|
||||
(#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
|
||||
mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
|
||||
|
||||
(#) The seven comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
(++) COMP3 is internally connected to EXTI Line 29
|
||||
(++) COMP4 is internally connected to EXTI Line 30
|
||||
(++) COMP5 is internally connected to EXTI Line 31
|
||||
(++) COMP6 is internally connected to EXTI Line 32
|
||||
(++) COMP7 is internally connected to EXTI Line 33
|
||||
|
||||
[..] Table 1. COMP Inputs
|
||||
+------------------------------------------------------------------------------------------+
|
||||
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-----------------|----------------|---------------|---------------------------------------|
|
||||
| | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC1 OUT1(PA4) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC1 OUT2(PA5) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
|
||||
| | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
|
||||
| | DAC2 OUT1(PA6) | --- | OK | --- | OK | --- | OK | --- |
|
||||
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
|
||||
| Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
|
||||
| Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
|
||||
+------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 2. COMP Outputs
|
||||
+-------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-------|-------|-------|-------|-------|-------|-------|
|
||||
| PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
|
||||
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
|
||||
| PA6 | PA12 | --- | --- | --- | --- | --- |
|
||||
| PA11 | PB9 | --- | --- | --- | --- | --- |
|
||||
| PB8 | --- | --- | --- | --- | --- | --- |
|
||||
+-------------------------------------------------------+
|
||||
|
||||
[..] Table 3. COMP Outputs redirection to embedded timers
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| + | + | + | + | + | + | + |
|
||||
| TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
|
||||
| | | | | | | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
|
||||
| | | | | | | |
|
||||
| TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
|
||||
| | | | | | | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 4. COMP Outputs blanking sources
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
|
||||
| | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators
|
||||
of all STM32F30x devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Enable the SYSCFG APB clock to get write access to comparator
|
||||
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
(#) Configure the comparator input in analog mode using GPIO_Init()
|
||||
|
||||
(#) Configure the comparator output in alternate function mode
|
||||
using GPIO_Init() and use GPIO_PinAFConfig() function to map the
|
||||
comparator output to the GPIO pin
|
||||
|
||||
(#) Configure the comparator using COMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the non-inverting input
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
|
||||
(#) Enable the comparator using COMP_Cmd() function
|
||||
|
||||
(#) If required enable the COMP interrupt by configuring and enabling
|
||||
EXTI line in Interrupt mode and selecting the desired sensitivity
|
||||
level using EXTI_Init() function. After that enable the comparator
|
||||
interrupt vector using NVIC_Init() function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_comp.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CSR register Mask */
|
||||
#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes COMP peripheral registers to their default reset values.
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_DeInit(uint32_t COMP_Selection)
|
||||
{
|
||||
/*!< Set COMP_CSR register to reset value */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP peripheral according to the specified parameters
|
||||
* in COMP_InitStruct
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @note By default, PA1 is selected as COMP1 non inverting input.
|
||||
* To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified COMP peripheral.
|
||||
* - COMP_InvertingInput specifies the inverting input of COMP
|
||||
* - COMP_NonInvertingInput specifies the non inverting input of COMP
|
||||
* - COMP_Output connect COMP output to selected timer
|
||||
* input (Input capture / Output Compare Reference Clear / Break Input)
|
||||
* - COMP_BlankingSrce specifies the blanking source of COMP
|
||||
* - COMP_OutputPol select output polarity
|
||||
* - COMP_Hysteresis configures COMP hysteresis value
|
||||
* - COMP_Mode configures COMP power mode
|
||||
* @note COMP_Hysteresis must be configured only for STM32F303xC. Otherwise, COMP_Hysteresis
|
||||
* must be kept at reset value(COMP_Hysteresis_No).
|
||||
* @note COMP_Mode field is only applicable for STM32F303xC devices.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
|
||||
assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
|
||||
assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
|
||||
assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
|
||||
|
||||
/*!< Get the COMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
|
||||
|
||||
/*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
|
||||
tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
|
||||
|
||||
/*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
|
||||
/*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
|
||||
/*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
|
||||
/*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
|
||||
/*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
|
||||
/*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
|
||||
/*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
|
||||
/*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
|
||||
tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
|
||||
COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
|
||||
COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
|
||||
|
||||
/*!< Write to COMPx_CSR register */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each COMP_InitStruct member with its default value.
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
|
||||
COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
|
||||
COMP_InitStruct->COMP_Output = COMP_Output_None;
|
||||
COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
|
||||
COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
|
||||
COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
|
||||
COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the COMP peripheral.
|
||||
* @note If the selected comparator is locked, enable/disable can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param NewState: new state of the COMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* When enabled, the comparator compares the non inverting input with
|
||||
* the inverting input and the comparison result is available
|
||||
* on comparator output.
|
||||
* When disabled, the comparator doesn't perform comparison and the
|
||||
* output level is low.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected COMPx peripheral */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected COMP peripheral */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the SW1 switch.
|
||||
* @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @note This switch is solely intended to redirect signals onto high
|
||||
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
|
||||
* @param NewState: New state of the analog switch.
|
||||
* This parameter can be
|
||||
* ENABLE so the SW1 is closed; PA1 is connected to PA4
|
||||
* or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close SW1 switch */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open SW1 switch */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @retval Returns the selected comparator output level: low or high.
|
||||
*
|
||||
*/
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
|
||||
{
|
||||
uint32_t compout = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if selected comparator output is high */
|
||||
if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
|
||||
{
|
||||
compout = COMP_OutputLevel_High;
|
||||
}
|
||||
else
|
||||
{
|
||||
compout = COMP_OutputLevel_Low;
|
||||
}
|
||||
|
||||
/* Return the comparator output level */
|
||||
return (uint32_t)(compout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group2 Window mode control function
|
||||
* @brief Window mode control function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Window mode control function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the window mode.
|
||||
* Window mode for comparators makes use of two comparators:
|
||||
* COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
|
||||
* In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
|
||||
* non inverting inputs are connected together and only COMPx-1 non
|
||||
* inverting input can be used.
|
||||
* e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
|
||||
* is to be used.
|
||||
* @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
|
||||
* to select the COMP peripheral.
|
||||
* param NewState: new state of the window mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
|
||||
* When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_COMP_WINDOW(COMP_Selection));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the window mode */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the window mode */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group3 COMP configuration locking function
|
||||
* @brief COMP1, COMP2,...COMP7 configuration locking function
|
||||
* COMP1, COMP2,...COMP7 configuration can be locked each separately.
|
||||
* Unlocking is performed by system reset.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration Lock function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator (COMP1/COMP2) configuration.
|
||||
* @note Locking the configuration means that all control bits are read-only.
|
||||
* To unlock the comparator configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of CRC computation unit peripheral:
|
||||
* + Configuration of the CRC computation unit
|
||||
* + CRC computation of one/many 32-bit data
|
||||
* + CRC Independent register (IDR) access
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
|
||||
function.
|
||||
(#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
|
||||
(#) Set the polynomial coefficients using CRC_SetPolynomial();
|
||||
(#) If required, select the reverse operation on input data
|
||||
using CRC_ReverseInputDataSelect();
|
||||
(#) If required, enable the reverse operation on output data
|
||||
using CRC_ReverseOutputDataCmd(Enable);
|
||||
(#) If required, set the initialization remainder value using
|
||||
CRC_SetInitRegister();
|
||||
(#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
|
||||
or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
|
||||
data buffer.
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_crc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
|
||||
* @brief Configuration of the CRC computation unit functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes CRC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_DeInit(void)
|
||||
{
|
||||
/* Set DR register to reset value */
|
||||
CRC->DR = 0xFFFFFFFF;
|
||||
/* Set the POL register to the reset value: 0x04C11DB7 */
|
||||
CRC->POL = 0x04C11DB7;
|
||||
/* Reset IDR register */
|
||||
CRC->IDR = 0x00;
|
||||
/* Set INIT register to reset value */
|
||||
CRC->INIT = 0xFFFFFFFF;
|
||||
/* Reset the CRC calculation unit */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC calculation unit and sets INIT register content in DR register.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR |= CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the polynomial size.
|
||||
* @param CRC_PolSize: Specifies the polynomial size.
|
||||
* This parameter can be:
|
||||
* @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
|
||||
{
|
||||
uint32_t tmpcr = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
|
||||
|
||||
/* Get CR register value */
|
||||
tmpcr = CRC->CR;
|
||||
|
||||
/* Reset POL_SIZE bits */
|
||||
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
|
||||
/* Set the polynomial size */
|
||||
tmpcr |= (uint32_t)CRC_PolSize;
|
||||
|
||||
/* Write to CR register */
|
||||
CRC->CR = (uint32_t)tmpcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the reverse operation to be performed on input data.
|
||||
* @param CRC_ReverseInputData: Specifies the reverse operation on input data.
|
||||
* This parameter can be:
|
||||
* @arg CRC_ReverseInputData_No: No reverse operation is performed
|
||||
* @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
|
||||
* @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
|
||||
* @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
|
||||
{
|
||||
uint32_t tmpcr = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
|
||||
|
||||
/* Get CR register value */
|
||||
tmpcr = CRC->CR;
|
||||
|
||||
/* Reset REV_IN bits */
|
||||
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
|
||||
/* Set the reverse operation */
|
||||
tmpcr |= (uint32_t)CRC_ReverseInputData;
|
||||
|
||||
/* Write to CR register */
|
||||
CRC->CR = (uint32_t)tmpcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disable the reverse operation on output data.
|
||||
* The reverse operation on output data is performed on 32-bit.
|
||||
* @param NewState: new state of the reverse operation on output data.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable reverse operation on output data */
|
||||
CRC->CR |= CRC_CR_REV_OUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable reverse operation on output data */
|
||||
CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the INIT register.
|
||||
* @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
|
||||
* @param CRC_InitValue: Programmable initial CRC value
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue)
|
||||
{
|
||||
CRC->INIT = CRC_InitValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the polynomial coefficients.
|
||||
* @param CRC_Pol: Polynomial to be used for CRC calculation.
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetPolynomial(uint32_t CRC_Pol)
|
||||
{
|
||||
CRC->POL = CRC_Pol;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
|
||||
* @brief CRC computation of one/many 32-bit data functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC computation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param CRC_Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data)
|
||||
{
|
||||
CRC->DR = CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 16-bit CRC of a given 16-bit data.
|
||||
* @param CRC_Data: data half-word(16-bit) to compute its CRC
|
||||
* @retval 16-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
|
||||
{
|
||||
*(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 8-bit CRC of a given 8-bit data.
|
||||
* @param CRC_Data: 8-bit data to compute its CRC
|
||||
* @retval 8-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
|
||||
{
|
||||
*(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
|
||||
* @brief CRC Independent Register (IDR) access (write/read) functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC Independent Register (IDR) access functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Stores an 8-bit data in the Independent Data(ID) register.
|
||||
* @param CRC_IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue)
|
||||
{
|
||||
CRC->IDR = CRC_IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,754 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
===============================================================================
|
||||
[..] The device integrates two 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC1 integrates two DAC channels:
|
||||
(++) DAC1 channel 1 with DAC1_OUT1 as output
|
||||
(++) DAC1 channel 2 with DAC1_OUT2 as output
|
||||
(++) The two channels can be used independently or simultaneously (dual mode)
|
||||
|
||||
(#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output
|
||||
|
||||
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
|
||||
DAC_SetChannel1Data()/DAC_SetChannel2Data.
|
||||
|
||||
[..] Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
|
||||
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
|
||||
(++) To trigger DAC conversions by TIM3 instead of TIM8 follow
|
||||
this sequence:
|
||||
(+++) Enable SYSCFG APB clock by calling
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
(+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init()
|
||||
(+++) Remap the DAC trigger from TIM8 to TIM3 by calling
|
||||
SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE)
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
[..] Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
|
||||
[..] Refer to the device datasheet for more details about output impedance
|
||||
value with and without output buffer.
|
||||
|
||||
[..] Both DAC channels can be used to generate:
|
||||
(+) Noise wave using DAC_WaveGeneration_Noise
|
||||
(+) Triangle wave using DAC_WaveGeneration_Triangle
|
||||
|
||||
[..] Wave generation can be disabled using DAC_WaveGeneration_None
|
||||
|
||||
[..] The DAC data format can be:
|
||||
(+) 8-bit right alignment using DAC_Align_8b_R
|
||||
(+) 12-bit left alignment using DAC_Align_12b_L
|
||||
(+) 12-bit right alignment using DAC_Align_12b_R
|
||||
|
||||
[..] The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation:
|
||||
(+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register.
|
||||
VREF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
||||
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
[..] A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
DAC_DMACmd()
|
||||
DMA1 requests are mapped as following:
|
||||
(+) DAC channel1 is mapped on DMA1 channel3 which must be already
|
||||
configured
|
||||
(+) DAC channel2 is mapped on DMA1 channel4 which must be already
|
||||
configured
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable DAC APB1 clock to get write access to DAC registers
|
||||
using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
|
||||
|
||||
(+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
|
||||
in analog mode.
|
||||
|
||||
(+) Configure the DAC channel using DAC_Init()
|
||||
|
||||
(+) Enable the DAC channel using DAC_Cmd()
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_dac.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 DAC channels configuration
|
||||
* @brief DAC channels configuration: trigger, output buffer, data format
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DAC channels configuration: trigger, output buffer, data format #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(DAC_TypeDef* DACx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
|
||||
if (DACx == DAC1)
|
||||
{
|
||||
/* Enable DAC1 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
|
||||
/* Release DAC1 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable DAC2 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
|
||||
/* Release DAC2 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch));
|
||||
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DACx->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch);
|
||||
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DACx->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_Buffer_Switch member */
|
||||
DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the DAC channel is enabled the trigger source can no more
|
||||
* be modified.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param DACx: where x can be 1 to select the DAC1 peripheral.
|
||||
* @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_LIST1_PERIPH(DACx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DACx->SWTRIGR |= DUAL_SWTRIG_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DACx: where x can be 1 to select the DAC1 peripheral.
|
||||
* @note Wave generation is not available in DAC2.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_LIST1_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DACx->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DACx->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data: Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DACx;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DACx: where x can be 1 to select the DAC peripheral.
|
||||
* @note This function is available only for DAC1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_LIST1_PERIPH(DACx));
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DACx;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel DAC.
|
||||
* @param DACx: where x can be 1 to select the DAC peripheral.
|
||||
* @note This function isn't applicable for DAC2.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_LIST1_PERIPH(DACx));
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DACx;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DACx;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 DMA management functions
|
||||
* @brief DMA management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
|
||||
* TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
|
||||
* must be already configured.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DACx->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's pending flags.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DACx->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's interrupt pending bits.
|
||||
* @param DACx: where x can be 1 or 2 to select the DAC peripheral.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_PERIPH(DACx));
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DACx->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Debug MCU (DBGMCU) peripheral:
|
||||
* + Device and Revision ID management
|
||||
* + Peripherals Configuration
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
|
||||
* @brief Device and Revision ID management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Device and Revision ID management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
|
||||
* @brief Peripherals Configuration
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripherals Configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures low power mode behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
|
||||
* @param NewState: new state of the specified low power mode in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB1 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
|
||||
* Core is halted.
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
|
||||
* Core is halted.
|
||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
|
||||
* Core is halted.
|
||||
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
|
||||
* @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when
|
||||
* Core is halted.
|
||||
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB1FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB2 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
|
||||
* @arg DBGMCU_TIM20_STOP: TIM20 counter stopped when Core is halted.
|
||||
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB2FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,866 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access controller (DMA):
|
||||
* + Initialization and Configuration
|
||||
* + Data Counter
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable The DMA controller clock using
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
|
||||
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
|
||||
(#) Enable and configure the peripheral to be connected to the DMA channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is necessary).
|
||||
(#) For a given Channel, program the Source and Destination addresses,
|
||||
the transfer Direction, the Buffer Size, the Peripheral and Memory
|
||||
Incrementation mode and Data Size, the Circular or Normal mode,
|
||||
the channel transfer Priority and the Memory-to-Memory transfer
|
||||
mode (if needed) using the DMA_Init() function.
|
||||
(#) Enable the NVIC and the corresponding interrupt(s) using the function
|
||||
DMA_ITConfig() if you need to use DMA interrupts.
|
||||
(#) Enable the DMA channel using the DMA_Cmd() function.
|
||||
(#) Activate the needed channel Request using PPP_DMACmd() function for
|
||||
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
|
||||
The function allowing this operation is provided in each PPP peripheral
|
||||
driver (ie. SPI_DMACmd for SPI peripheral).
|
||||
(#) Optionally, you can configure the number of data to be transferred
|
||||
when the channel is disabled (ie. after each Transfer Complete event
|
||||
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
|
||||
And you can get the number of remaining data to be transferred using
|
||||
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
|
||||
enabled and running).
|
||||
(#) To control DMA events you can use one of the following two methods:
|
||||
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
|
||||
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
|
||||
phase and DMA_GetITStatus() function into interrupt routines in
|
||||
communication phase.
|
||||
After checking on a flag you should clear it using DMA_ClearFlag()
|
||||
function. And after checking on an interrupt event you should
|
||||
clear it using DMA_ClearITPendingBit() function.
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_dma.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
|
||||
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||
#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to initialize the DMA channel
|
||||
source and destination addresses, incrementation and data sizes, transfer
|
||||
direction, buffer size, circular/normal mode selection, memory-to-memory
|
||||
mode selection and channel priority value.
|
||||
[..] The DMA_Init() function follows the DMA configuration procedures as described
|
||||
in reference manual (RM00316).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified parameters
|
||||
* in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_MASK;
|
||||
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 Data Counter functions
|
||||
* @brief Data Counter functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Data Counter functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides function allowing to configure and read the buffer
|
||||
size (number of data to be transferred).The DMA data counter can be written
|
||||
only when the DMA channel is disabled (ie. after transfer complete event).
|
||||
[..] The following function can be used to write the Channel data counter value:
|
||||
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
|
||||
[..]
|
||||
(@) It is advised to use this function rather than DMA_Init() in situations
|
||||
where only the Data buffer needs to be reloaded.
|
||||
[..] The DMA data counter can be read to indicate the number of remaining transfers
|
||||
for the relative DMA channel. This counter is decremented at the end of each
|
||||
data transfer and when the transfer is complete:
|
||||
(+) If Normal mode is selected: the counter is set to 0.
|
||||
(+) If Circular mode is selected: the counter is reloaded with the initial
|
||||
value(configured before enabling the DMA channel).
|
||||
[..] The following function can be used to read the Channel data counter value:
|
||||
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to configure the DMA Interrupt
|
||||
sources and check or clear the flags or pending bits status.
|
||||
The user should identify which mode will be used in his application to manage
|
||||
the DMA controller events: Polling mode or Interrupt mode.
|
||||
|
||||
*** Polling Mode ***
|
||||
====================
|
||||
[..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller
|
||||
number, x : DMA channel number):
|
||||
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
|
||||
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
|
||||
above occurred.
|
||||
[..]
|
||||
(@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
|
||||
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
[..] In this Mode it is advised to use the following functions:
|
||||
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
|
||||
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
|
||||
|
||||
*** Interrupt Mode ***
|
||||
======================
|
||||
[..] Each DMA channel can be managed through 4 Interrupts:
|
||||
(+) Interrupt Source
|
||||
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
|
||||
(##) DMA_IT_GL: to indicate that at least one of the interrupts described
|
||||
above occurred.
|
||||
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
|
||||
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
|
||||
[..] In this Mode it is advised to use the following functions:
|
||||
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
|
||||
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAy_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
|
||||
* relative to the same channel is set (Transfer Complete, Half-transfer
|
||||
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
|
||||
* DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR ;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAy_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAy_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
|
||||
* relative to the same channel (Transfer Complete, Half-transfer Complete and
|
||||
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA2->IFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA1->IFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
|
||||
* interrupts relative to the same channel is set (Transfer Complete,
|
||||
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
|
||||
* DMAy_IT_HTx or DMAy_IT_TEx).
|
||||
*
|
||||
* @retval The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMA */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMAy_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
|
||||
* interrupts relative to the same channel (Transfer Complete, Half-transfer
|
||||
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
|
||||
* DMAy_IT_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA2->IFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA1->IFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,349 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### EXTI features #####
|
||||
===============================================================================
|
||||
[..] External interrupt/event lines are mapped as following:
|
||||
(#) All available GPIO pins are connected to the 16 external
|
||||
interrupt/event lines from EXTI0 to EXTI15.
|
||||
(#) EXTI line 16 is connected to the PVD output
|
||||
(#) EXTI line 17 is connected to the RTC Alarm event
|
||||
(#) EXTI line 18 is connected to USB Device wakeup event
|
||||
(#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
|
||||
(#) EXTI line 20 is connected to the RTC wakeup event
|
||||
(#) EXTI line 21 is connected to the Comparator 1 wakeup event
|
||||
(#) EXTI line 22 is connected to the Comparator 2 wakeup event
|
||||
(#) EXTI line 23 is connected to the I2C1 wakeup event
|
||||
(#) EXTI line 24 is connected to the I2C2 wakeup event
|
||||
(#) EXTI line 25 is connected to the USART1 wakeup event
|
||||
(#) EXTI line 26 is connected to the USART2 wakeup event
|
||||
(#) EXTI line 27 is reserved
|
||||
(#) EXTI line 28 is connected to the USART3 wakeup event
|
||||
(#) EXTI line 29 is connected to the Comparator 3 event
|
||||
(#) EXTI line 30 is connected to the Comparator 4 event
|
||||
(#) EXTI line 31 is connected to the Comparator 5 event
|
||||
(#) EXTI line 32 is connected to the Comparator 6 event
|
||||
(#) EXTI line 33 is connected to the Comparator 7 event
|
||||
(#) EXTI line 34 is connected for thr UART4 wakeup event
|
||||
(#) EXTI line 35 is connected for the UART5 wakeup event
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..] In order to use an I/O pin as an external interrupt source,
|
||||
follow steps below:
|
||||
(#) Configure the I/O in input mode using GPIO_Init().
|
||||
(#) Select the input source pin for the EXTI line using
|
||||
SYSCFG_EXTILineConfig().
|
||||
(#) Select the mode(interrupt, event) and configure the trigger
|
||||
selection (Rising, falling or both) using EXTI_Init(). For the
|
||||
internal interrupt, the trigger selection is not needed
|
||||
(the active edge is always the rising one).
|
||||
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
|
||||
(#) Optionally, you can generate a software interrupt using the function
|
||||
EXTI_GenerateSWInterrupt().
|
||||
[..]
|
||||
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
||||
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_exti.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x1F800000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->SWIER = 0x00000000;
|
||||
EXTI->PR = 0xE07FFFFF;
|
||||
EXTI->IMR2 = 0x0000000C;
|
||||
EXTI->EMR2 = 0x00000000;
|
||||
EXTI->RTSR2 = 0x00000000;
|
||||
EXTI->FTSR2 = 0x00000000;
|
||||
EXTI->SWIER2 = 0x00000000;
|
||||
EXTI->PR2 = 0x00000003;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
|
||||
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
|
||||
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
|
||||
* pending bit will be set.
|
||||
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
|
||||
* contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
|
||||
|
||||
*(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
|
||||
/* Select the trigger for the selected interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
|
||||
|
||||
*(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
||||
* will be generated.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
|
||||
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
||||
* @brief EXTI Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the EXTI Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
|
||||
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..20).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
|
||||
|
||||
*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,545 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration functions
|
||||
* + GPIO Read and Write functions
|
||||
* + GPIO Alternate functions configuration functions
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
In output mode, the speed is configurable: Low, Medium, Fast or High.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel,
|
||||
DAC output or comparator input.
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC, DAC and comparators, configure the desired pin in
|
||||
analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
|
||||
(++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function.
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
|
||||
(+++) Call GPIO_Init() function.
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
(#) During and just after reset, the alternate functions are not active
|
||||
and the GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
|
||||
general-purpose (PC14 and PC15, respectively) when the LSE
|
||||
oscillator is off. The LSE has priority over the GPIO function.
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
|
||||
(PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
|
||||
the priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_gpio.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset
|
||||
* values.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO
|
||||
* peripheral.
|
||||
* @note GPIO_Pin: selects the pin to be configured:
|
||||
* GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
|
||||
* GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
|
||||
* and GPIO_Pin_10 for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/*-------------------------- Configure the port pins -----------------------*/
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration */
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
/* Use temporary variable to update PUPDR register configuration, to avoid
|
||||
unexpected transition in the GPIO pin configuration. */
|
||||
tmpreg = GPIOx->PUPDR;
|
||||
tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
GPIOx->PUPDR = tmpreg;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit */
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit */
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be :
|
||||
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
|
||||
* (0..2, 4, 6, 9..10) for GPIOF.
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the port bit to read.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be :
|
||||
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
|
||||
* (0..2, 4, 6, 9..10) for GPIOF.
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be :
|
||||
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
|
||||
* (0..2, 4, 6, 9..10) for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be :
|
||||
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
|
||||
* (0..2, 4, 6, 9..10) for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be :
|
||||
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
|
||||
* (0..2, 4, 6, 9..10) for GPIOF.
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enumeration values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data
|
||||
* register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
|
||||
* @brief GPIO Alternate functions configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A, B, C, D, E, F, G or H) to select the GPIO peripheral.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AF: selects the pin to be used as Alternate function.
|
||||
* This parameter can be one of the following value:
|
||||
* @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
|
||||
* TRACED, TRACECK.
|
||||
* @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
|
||||
* @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
|
||||
* @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
|
||||
* @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
|
||||
* @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
|
||||
* @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
|
||||
* @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
|
||||
* USART2, USART3.
|
||||
* @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
|
||||
* COMP6_OUT.
|
||||
* @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
|
||||
* @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
|
||||
* @arg GPIO_AF_11: TIM1, TIM8.
|
||||
* @arg GPIO_AF_12: TIM1, HRTIM.
|
||||
* @arg GPIO_AF_13: HRTIM, AOP2_OUT.
|
||||
* @arg GPIO_AF_14: USBDM, USBDP.
|
||||
* @arg GPIO_AF_15: OUT.
|
||||
* @note The pin should already been configured in Alternate Function mode(AF)
|
||||
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
* @note Refer to the Alternate function mapping table in the device datasheet
|
||||
* for the detailed mapping of the system and peripherals alternate
|
||||
* function I/O pins.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,288 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent watchdog (IWDG) peripheral:
|
||||
* + Prescaler and Counter configuration
|
||||
* + IWDG activation
|
||||
* + Flag management
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### IWDG features #####
|
||||
===============================================================================
|
||||
[..] The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
[..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
The IWDG counter should be reloaded at regular intervals to prevent
|
||||
an MCU reset.
|
||||
[..] The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
[..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
|
||||
reset occurs.
|
||||
[..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM16 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
For more information, please refer to the STM32F30x Reference manual.
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..] This driver allows to use IWDG peripheral with either window option enabled
|
||||
or disabled. To do so follow one of the two procedures below.
|
||||
(#) Window option is enabled:
|
||||
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
in software mode (no need to enable the LSI, it will be enabled
|
||||
by hardware).
|
||||
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
|
||||
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
|
||||
(++) Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
This value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
|
||||
(++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
|
||||
|
||||
(#) Window option is disabled:
|
||||
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
|
||||
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
|
||||
(++) Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
This value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
|
||||
(++) reload the IWDG counter at regular intervals during normal operation
|
||||
to prevent an MCU reset, using IWDG_ReloadCounter() function.
|
||||
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
in software mode (no need to enable the LSI, it will be enabled
|
||||
by hardware).
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_iwdg.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
|
||||
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
|
||||
* @brief Prescaler and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Prescaler and Counter configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload: specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RLR = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_RELOAD;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the IWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
|
||||
IWDG->WINR = WindowValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IWDG activation function
|
||||
* @brief IWDG activation function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IWDG activation function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group3 Flag management function
|
||||
* @brief Flag management function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Flag management function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||
* @arg IWDG_FLAG_WVU: Counter Window Value Update on going
|
||||
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### How to configure Interrupts using driver #####
|
||||
===============================================================================
|
||||
[..] This section provide functions allowing to configure the NVIC interrupts
|
||||
(IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
(#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
||||
function according to the following table.
|
||||
The table below gives the allowed values of the pre-emption priority
|
||||
and subpriority according to the Priority Grouping configuration
|
||||
performed by NVIC_PriorityGroupConfig function.
|
||||
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
[..]
|
||||
(@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
|
||||
the IRQ priority will be managed only by subpriority.
|
||||
The sub-priority is only used to sort pending exception priorities,
|
||||
and does not affect active exceptions.
|
||||
(@) Lower priority values gives higher priority.
|
||||
(@) Priority Order:
|
||||
(#@) Lowest Preemption priority.
|
||||
(#@) Lowest Subpriority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_misc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
|
||||
* 4 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
|
||||
* 3 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
|
||||
* 2 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
|
||||
* 1 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
|
||||
* 0 bits for subpriority.
|
||||
* @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
|
||||
* interrupt. This interrupts priority is managed only with subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM
|
||||
* @arg NVIC_VectTab_FLASH
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND
|
||||
* @arg NVIC_LP_SLEEPDEEP
|
||||
* @arg NVIC_LP_SLEEPONEXIT
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_opamp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral:
|
||||
* + OPAMP Configuration
|
||||
* + OPAMP calibration
|
||||
*
|
||||
@verbatim
|
||||
|
||||
==============================================================================
|
||||
##### OPAMP Peripheral Features #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
|
||||
|
||||
(+) The OPAMPs non inverting input can be selected among the list shown by
|
||||
table below.
|
||||
|
||||
(+) The OPAMPs inverting input can be selected among the list shown by
|
||||
table below.
|
||||
|
||||
(+) The OPAMPs outputs can be internally connected to the inverting input
|
||||
(follower mode)
|
||||
(+) The OPAMPs outputs can be internally connected to resistor feedback
|
||||
output (Programmable Gain Amplifier mode)
|
||||
|
||||
(+) The OPAMPs outputs can be internally connected to ADC
|
||||
|
||||
(+) The OPAMPs can be calibrated to compensate the offset compensation
|
||||
|
||||
(+) Timer-controlled Mux for automatic switch of inverting and
|
||||
non-inverting input
|
||||
|
||||
OPAMPs inverting/non-inverting inputs:
|
||||
+--------------------------------------------------------------+
|
||||
| | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
| | PGA | OK | OK | OK | OK |
|
||||
| Inverting Input | Vout | OK | OK | OK | OK |
|
||||
| | IO1 | PC5 | PC5 | PB10 | PB10 |
|
||||
| | IO2 | PA3 | PA5 | PB2 | PD8 |
|
||||
|-----------------|--------|--------|--------|--------|--------|
|
||||
| | IO1 | PA7 | PD14 | PB13 | PD11 |
|
||||
| Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 |
|
||||
| Input | IO3 | PA3 | PB0 | PA1 | PA4 |
|
||||
| | IO4 | PA1 | PA7 | PB0 | PB13 |
|
||||
+--------------------------------------------------------------+
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the OPAMP
|
||||
of all STM32F30x devices.
|
||||
|
||||
To use the OPAMP, perform the following steps:
|
||||
|
||||
(#) Enable the SYSCFG APB clock to get write access to OPAMP
|
||||
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
(#) Configure the OPAMP input in analog mode using GPIO_Init()
|
||||
|
||||
(#) Configure the OPAMP using OPAMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the non-inverting inverting input
|
||||
|
||||
(#) Enable the OPAMP using OPAMP_Cmd() function
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_opamp.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP
|
||||
* @brief OPAMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93)
|
||||
#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF)
|
||||
#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes OPAMP peripheral registers to their default reset values.
|
||||
* @note Deinitialization can't be performed if the OPAMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_DeInit(uint32_t OPAMP_Selection)
|
||||
{
|
||||
/*!< Set OPAMP_CSR register to reset value */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the OPAMP peripheral according to the specified parameters
|
||||
* in OPAMP_InitStruct
|
||||
* @note If the selected OPAMP is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified OPAMP peripheral.
|
||||
* - OPAMP_InvertingInput specifies the inverting input of OPAMP
|
||||
* - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
|
||||
assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
|
||||
|
||||
/*!< Get the OPAMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
|
||||
|
||||
/*!< Clear the inverting and non inverting bits selection bits */
|
||||
tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
|
||||
|
||||
/*!< Configure OPAMP: inverting and non inverting inputs */
|
||||
tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
|
||||
|
||||
/*!< Write to OPAMPx_CSR register */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each OPAMP_InitStruct member with its default value.
|
||||
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
|
||||
{
|
||||
OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
|
||||
OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the feedback resistor gain.
|
||||
* @note If the selected OPAMP is locked, gain configuration can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param NewState: new state of the OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
|
||||
assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
|
||||
|
||||
/* Reset the configuration bits */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
|
||||
|
||||
/* Set the new configuration */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the OPAMP's internal reference.
|
||||
* @note This feature is used when calibration enabled or OPAMP's reference
|
||||
* connected to the non inverting input.
|
||||
* @note If the selected OPAMP is locked, Vref configuration can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param OPAMP_Vref: This parameter can be:
|
||||
* OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
|
||||
* OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
|
||||
* OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
|
||||
* OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_VREF(OPAMP_Vref));
|
||||
|
||||
/*!< Get the OPAMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
|
||||
|
||||
/*!< Clear the CALSEL bits */
|
||||
tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
|
||||
|
||||
/*!< Configure OPAMP reference */
|
||||
tmpreg |= (uint32_t)(OPAMP_Vref);
|
||||
|
||||
/*!< Write to OPAMPx_CSR register */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect the internal reference to the OPAMP's non inverting input.
|
||||
* @note If the selected OPAMP is locked, Vref configuration can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param NewState: new state of the OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Connect the internal reference to the OPAMP's non inverting input */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disconnect the internal reference to the OPAMP's non inverting input */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables connecting the OPAMP's internal reference to ADC.
|
||||
* @note If the selected OPAMP is locked, Vref connection can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param NewState: new state of the Vrefint output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable output internal reference */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable output internal reference */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled
|
||||
* mux mode according to the specified parameters in OPAMP_InitStruct.
|
||||
* @note If the selected OPAMP is locked, timer-controlled mux configuration
|
||||
* can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified OPAMP peripheral.
|
||||
* - OPAMP_InvertingInput specifies the inverting input of OPAMP
|
||||
* - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
|
||||
* @note PGA and Vout can't be selected as secondary inverting input.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
|
||||
assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
|
||||
|
||||
/*!< Get the OPAMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
|
||||
|
||||
/*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
|
||||
tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
|
||||
|
||||
/*!< Configure OPAMP: secondary inverting and non inverting inputs */
|
||||
tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
|
||||
|
||||
/*!< Write to OPAMPx_CSR register */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the timer-controlled mux mode.
|
||||
* @note If the selected OPAMP is locked, enable/disable can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param NewState: new state of the OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the timer-controlled Mux mode */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the timer-controlled Mux mode */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the OPAMP peripheral.
|
||||
* @note If the selected OPAMP is locked, enable/disable can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param NewState: new state of the OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected OPAMPx peripheral */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected OPAMPx peripheral */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) during calibration of the selected OPAMP.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* - OPAMP output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - OPAMP output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @note OPAMP output level is provided only during calibration phase.
|
||||
* @retval Returns the selected OPAMP output level: low or high.
|
||||
*
|
||||
*/
|
||||
uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
|
||||
{
|
||||
uint32_t opampout = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
|
||||
/* Check if selected OPAMP output is high */
|
||||
if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
|
||||
{
|
||||
opampout = OPAMP_OutputLevel_High;
|
||||
}
|
||||
else
|
||||
{
|
||||
opampout = OPAMP_OutputLevel_Low;
|
||||
}
|
||||
|
||||
/* Return the OPAMP output level */
|
||||
return (uint32_t)(opampout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the trimming mode.
|
||||
* @param OffsetTrimming: the selected offset trimming mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
|
||||
* calibration
|
||||
* @arg OPAMP_Trimming_User: user trimming values are used for offset
|
||||
* calibration
|
||||
* @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
|
||||
* function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
|
||||
* trimming value.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
|
||||
|
||||
/* Reset USERTRIM bit */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
|
||||
|
||||
/* Select trimming mode */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the trimming value of the OPAMP.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param OPAMP_Input: the selected OPAMP input.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
|
||||
* @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
|
||||
* @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
|
||||
* or equal to 0x0000001F.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
|
||||
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
|
||||
|
||||
/*!< Get the OPAMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
|
||||
|
||||
/*!< Clear the trimming bits */
|
||||
tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<<OPAMP_Input));
|
||||
|
||||
/*!< Configure the new trimming value */
|
||||
tmpreg |= (uint32_t)(OPAMP_TrimValue<<OPAMP_Input);
|
||||
|
||||
/*!< Write to OPAMPx_CSR register */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start or stop the calibration of selected OPAMP peripheral.
|
||||
* @note If the selected OPAMP is locked, start/stop can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @param NewState: new state of the OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Start the OPAMPx calibration */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_CALON);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Stop the OPAMPx calibration */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_CALON);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Group2 OPAMP configuration locking function
|
||||
* @brief OPAMP1,...OPAMP4 configuration locking function
|
||||
* OPAMP1,...OPAMP4 configuration can be locked each separately.
|
||||
* Unlocking is performed by system reset.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration Lock function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected OPAMP configuration.
|
||||
* @note Locking the configuration means that all control bits are read-only.
|
||||
* To unlock the OPAMP configuration, perform a system reset.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
|
||||
* to select the OPAMP peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_LockConfig(uint32_t OPAMP_Selection)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
|
||||
/* Set the lock bit corresponding to selected OPAMP */
|
||||
*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_LOCK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,538 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Backup Domain Access
|
||||
* + PVD configuration
|
||||
* + WakeUp pins configuration
|
||||
* + Low Power modes configuration
|
||||
* + Flags management
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_pwr.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* --------- PWR registers bit address in the alias region ---------- */
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
|
||||
/* Alias word address of DBP bit */
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
#define DBP_BitNumber 0x08
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BitNumber 0x04
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group1 Backup Domain Access function
|
||||
* @brief Backup Domain Access function
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Backup Domain Access function #####
|
||||
==============================================================================
|
||||
|
||||
[..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
|
||||
and RTC backup registers) are protected against possible stray write accesses.
|
||||
[..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @param NewState: new state of the access to the RTC and backup registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group2 PVD configuration functions
|
||||
* @brief PVD configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### PVD configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
|
||||
selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
|
||||
PVD threshold. This event is internally connected to the EXTI line16
|
||||
and can generate an interrupt if enabled through the EXTI registers.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_0: PVD detection level set to 2.18V
|
||||
* @arg PWR_PVDLevel_1: PVD detection level set to 2.28V
|
||||
* @arg PWR_PVDLevel_2: PVD detection level set to 2.38V
|
||||
* @arg PWR_PVDLevel_3: PVD detection level set to 2.48V
|
||||
* @arg PWR_PVDLevel_4: PVD detection level set to 2.58V
|
||||
* @arg PWR_PVDLevel_5: PVD detection level set to 2.68V
|
||||
* @arg PWR_PVDLevel_6: PVD detection level set to 2.78V
|
||||
* @arg PWR_PVDLevel_7: PVD detection level set to 2.88V
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PLS[7:5] bits */
|
||||
tmpreg &= CR_PLS_MASK;
|
||||
|
||||
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group3 WakeUp pins configuration functions
|
||||
* @brief WakeUp pins configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp pins configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
|
||||
forced in input pull down configuration and are active on rising edges.
|
||||
(+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
|
||||
WakeUp Pin 3 on PE.06.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param PWR_WakeUpPin: specifies the WakeUpPin.
|
||||
* This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the EWUPx pin */
|
||||
PWR->CSR |= PWR_WakeUpPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the EWUPx pin */
|
||||
PWR->CSR &= ~PWR_WakeUpPin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Group4 Low Power modes configuration functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Low Power modes configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The devices feature three low-power modes:
|
||||
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
|
||||
(+) Standby mode: VCORE domain powered off
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
(++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register
|
||||
contents are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
|
||||
function with regulator in LowPower or with Regulator ON.
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
|
||||
or any internal IPs (I2C or UASRT) wakeup event.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..] The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
|
||||
The VCORE domain is consequently powered off. The PLL, the HSI, and the HSE
|
||||
oscillator are also switched off. SRAM and register
|
||||
contents are lost except for the Backup domain (RTC registers, RTC backup
|
||||
registers and Standby circuitry).
|
||||
|
||||
[..] The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
|
||||
event, a time-stamp event, or a comparator event, without depending on an
|
||||
external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode
|
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||||
(+++) Configure the correspondent comparator EXTI Line to be sensitive to
|
||||
the selected edges (falling, rising or falling and rising)
|
||||
(Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* @note Reset pad (still available)
|
||||
* @note RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
|
||||
* time-stamp, RTC Alarm out, or RTC clock calibration out.
|
||||
* @note WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
|
||||
* @note The Wakeup flag (WUF) need to be cleared at application level before to call this function.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM )
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group5 Flags management functions
|
||||
* @brief Flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the PWR_PVDCmd() function.
|
||||
* @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
|
||||
* flag indicates the state of the internal voltage reference, VREFINT.
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,569 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the SYSCFG peripheral:
|
||||
* + Remapping the memory mapped at 0x00000000
|
||||
* + Remapping the DMA channels
|
||||
* + Enabling I2C fast mode plus driving capability for I2C plus
|
||||
* + Remapping USB interrupt line
|
||||
* + Configuring the EXTI lines connection to the GPIO port
|
||||
* + Configuring the CLASSB requirements
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..] The SYSCFG registers can be accessed only when the SYSCFG
|
||||
interface APB clock is enabled.
|
||||
[..] To enable SYSCFG APB clock use:
|
||||
RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_syscfg.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG
|
||||
* @brief SYSCFG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Reset value of SYSCFG_CFGR1 register */
|
||||
#define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
|
||||
|
||||
/* ------------ SYSCFG registers bit address in the alias region -------------*/
|
||||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CFGR1 Register ---*/
|
||||
/* Alias word address of USB_IT_RMP bit */
|
||||
#define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
|
||||
#define USBITRMP_BitNumber 0x05
|
||||
#define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
|
||||
|
||||
/* --- CFGR2 Register ---*/
|
||||
/* Alias word address of BYP_ADDR_PAR bit */
|
||||
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
|
||||
#define BYPADDRPAR_BitNumber 0x04
|
||||
#define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
|
||||
* @brief SYSCFG Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### SYSCFG Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SYSCFG registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
* @note MEM_MODE bits are not affected by APB reset.
|
||||
* MEM_MODE bits took the value from the user option bytes.
|
||||
*/
|
||||
void SYSCFG_DeInit(void)
|
||||
{
|
||||
/* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
|
||||
SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
|
||||
/* Set FPU Interrupt Enable bits to default value */
|
||||
SYSCFG->CFGR1 |= 0x7C000000;
|
||||
/* Reset RAM Write protection bits to default value */
|
||||
SYSCFG->RCR = 0x00000000;
|
||||
/* Set EXTICRx registers to reset value */
|
||||
SYSCFG->EXTICR[0] = 0;
|
||||
SYSCFG->EXTICR[1] = 0;
|
||||
SYSCFG->EXTICR[2] = 0;
|
||||
SYSCFG->EXTICR[3] = 0;
|
||||
/* Set CFGR2 register to reset value */
|
||||
SYSCFG->CFGR2 = 0;
|
||||
/* Set CFGR3 register to reset value */
|
||||
SYSCFG->CFGR3 = 0;
|
||||
/* Set CFGR4 register to reset value */
|
||||
SYSCFG->CFGR4 = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the memory mapping at address 0x00000000.
|
||||
* @param SYSCFG_MemoryRemap: selects the memory remapping.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_FMC: External memory through FMC
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
|
||||
{
|
||||
uint32_t tmpcfgr1 = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
|
||||
|
||||
/* Get CFGR1 register value */
|
||||
tmpcfgr1 = SYSCFG->CFGR1;
|
||||
|
||||
/* Clear MEM_MODE bits */
|
||||
tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
|
||||
|
||||
/* Set the new MEM_MODE bits value */
|
||||
tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
|
||||
|
||||
/* Set CFGR1 register with the new memory remap configuration */
|
||||
SYSCFG->CFGR1 = tmpcfgr1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the DMA channels remapping.
|
||||
* @param SYSCFG_DMARemap: selects the DMA channels remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
|
||||
* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
|
||||
* @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
|
||||
* @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
|
||||
* @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
|
||||
* @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
|
||||
* @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
|
||||
* @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
|
||||
* @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
|
||||
* @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
|
||||
* @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
|
||||
* @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
|
||||
* @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
|
||||
* @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
|
||||
* @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
|
||||
* @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
|
||||
* @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
|
||||
* @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
|
||||
* @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
|
||||
* @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
|
||||
* @param NewState: new state of the DMA channel remapping.
|
||||
* This parameter can be: Enable or Disable.
|
||||
* @note When enabled, DMA channel of the selected peripheral is remapped
|
||||
* @note When disabled, Default DMA channel is mapped to the selected peripheral
|
||||
* @note
|
||||
* By default TIM17 DMA requests is mapped to channel 1
|
||||
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
|
||||
* to remap TIM17 DMA requests to DMA1 channel 2
|
||||
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
|
||||
* to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the DMA channel */
|
||||
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* use the default DMA channel mapping */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the DMA channel */
|
||||
SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* use the default DMA channel mapping */
|
||||
SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the remapping capabilities of DAC/TIM triggers.
|
||||
* @param SYSCFG_TriggerRemap: selects the trigger to be remapped.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
|
||||
* @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
|
||||
* @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
|
||||
* @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
|
||||
* @param NewState: new state of the trigger mapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note ENABLE: Enable fast mode plus driving capability for selected pin
|
||||
* @note DISABLE: Disable fast mode plus driving capability for selected pin
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the trigger */
|
||||
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the default trigger mapping */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the trigger */
|
||||
SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the default trigger mapping */
|
||||
SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the remapping capabilities of encoder mode.
|
||||
* @ note This feature implement the so-called M/T method for measuring speed
|
||||
* and position using quadrature encoders.
|
||||
* @param SYSCFG_EncoderRemap: selects the remap option for encoder mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_EncoderRemap_No: No remap
|
||||
* @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
|
||||
* @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
|
||||
* @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
|
||||
|
||||
/* Reset the encoder mode remapping bits */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
|
||||
|
||||
/* Set the selected configuration */
|
||||
SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Remaps the USB interrupt lines.
|
||||
* @param NewState: new state of the mapping of USB interrupt lines.
|
||||
* This parameter can be:
|
||||
* @param ENABLE: Remap the USB interrupt line as following:
|
||||
* @arg USB Device High Priority (USB_HP) interrupt mapped to line 74.
|
||||
* @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75.
|
||||
* @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
|
||||
* @param DISABLE: Use the default USB interrupt line:
|
||||
* @arg USB Device High Priority (USB_HP) interrupt mapped to line 19.
|
||||
* @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20.
|
||||
* @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Remap the USB interrupt lines */
|
||||
*(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the I2C fast mode plus driving capability.
|
||||
* @param SYSCFG_I2CFastModePlus: selects the pin.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
|
||||
* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
|
||||
* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
|
||||
* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
|
||||
* @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
|
||||
* @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
|
||||
* @arg SYSCFG_I2CFastModePlus_I2C3: Configure fast mode plus driving capability for I2C3 pins
|
||||
* @param NewState: new state of the DMA channel remapping.
|
||||
* This parameter can be:
|
||||
* @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
|
||||
* @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable fast mode plus driving capability for selected I2C pin */
|
||||
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable fast mode plus driving capability for selected I2C pin */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected SYSCFG interrupts.
|
||||
* @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_IT_IXC: Inexact Interrupt
|
||||
* @arg SYSCFG_IT_IDC: Input denormal Interrupt
|
||||
* @arg SYSCFG_IT_OFC: Overflow Interrupt
|
||||
* @arg SYSCFG_IT_UFC: Underflow Interrupt
|
||||
* @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
|
||||
* @arg SYSCFG_IT_IOC: Invalid operation Interrupt
|
||||
* @param NewState: new state of the specified SYSCFG interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SYSCFG_IT(SYSCFG_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SYSCFG interrupts */
|
||||
SYSCFG->CFGR1 |= SYSCFG_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SYSCFG interrupts */
|
||||
SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
|
||||
* for EXTI lines where x can be (A, B, C, D, E, F, G, H).
|
||||
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
|
||||
* This parameter can be EXTI_PinSourcex where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
|
||||
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connects the selected parameter to the break input of TIM1.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
* @param SYSCFG_Break: selects the configuration to be connected to break
|
||||
* input of TIM1
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
|
||||
* @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
|
||||
* @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
|
||||
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the parity check on RAM.
|
||||
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||
* To re-enable the parity check on RAM perform a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_BypassParityCheckDisable(void)
|
||||
{
|
||||
/* Disable the address parity check on RAM */
|
||||
*(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the remapping capabilities of DAC/TIM triggers.
|
||||
* @param SYSCFG_ADCTriggerRemap: selects the ADC trigger to be remapped.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg REMAPADCTRIGGER_ADC12_EXT2: Input trigger of ADC12 regular channel EXT2
|
||||
* @arg REMAPADCTRIGGER_ADC12_EXT3: Input trigger of ADC12 regular channel EXT3
|
||||
* @arg REMAPADCTRIGGER_ADC12_EXT5: Input trigger of ADC12 regular channel EXT5
|
||||
* @arg REMAPADCTRIGGER_ADC12_EXT13: Input trigger of ADC12 regular channel EXT13
|
||||
* @arg REMAPADCTRIGGER_ADC12_EXT15: Input trigger of ADC12 regular channel EXT15
|
||||
* @arg REMAPADCTRIGGER_ADC12_JEXT3: Input trigger of ADC12 injected channel JEXT3
|
||||
* @arg REMAPADCTRIGGER_ADC12_JEXT6: Input trigger of ADC12 injected channel JEXT6
|
||||
* @arg REMAPADCTRIGGER_ADC12_JEXT13: Input trigger of ADC12 injected channel JEXT16
|
||||
* @arg REMAPADCTRIGGER_ADC34_EXT5: Input trigger of ADC34 regular channel EXT5
|
||||
* @arg REMAPADCTRIGGER_ADC34_EXT6: Input trigger of ADC34 regular channel EXT6
|
||||
* @arg REMAPADCTRIGGER_ADC34_EXT15: Input trigger of ADC34 regular channel EXT15
|
||||
* @arg REMAPADCTRIGGER_ADC34_JEXT5: Input trigger of ADC34 injected channel JEXT5
|
||||
* @arg REMAPADCTRIGGER_ADC34_JEXT11: Input trigger of ADC34 injected channel JEXT11
|
||||
* @arg REMAPADCTRIGGER_ADC34_JEXT14: Input trigger of ADC34 injected channel JEXT14
|
||||
* @param NewState: new state of the trigger mapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note ENABLE: Enable fast mode plus driving capability for selected pin
|
||||
* @note DISABLE: Disable fast mode plus driving capability for selected pin
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_ADCTriggerRemapConfig(uint32_t SYSCFG_ADCTriggerRemap, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_ADC_TRIGGER_REMAP(SYSCFG_ADCTriggerRemap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the trigger */
|
||||
SYSCFG->CFGR4 |= (uint32_t)SYSCFG_ADCTriggerRemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the default trigger mapping */
|
||||
SYSCFG->CFGR4 &= (uint32_t)(~SYSCFG_ADCTriggerRemap);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the ICODE SRAM write protection.
|
||||
* @note Enabling the ICODE SRAM write protection locks the configuration bit.
|
||||
* To disable the ICODE SRAM write protection perform a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
|
||||
|
||||
/* Enable the write-protection on the selected ICODE SRAM page */
|
||||
SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SYSCFG flag is set or not.
|
||||
* @param SYSCFG_Flag: specifies the SYSCFG flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
|
||||
* @retval The new state of SYSCFG_Flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
|
||||
|
||||
/* Check the status of the specified SPI flag */
|
||||
if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
|
||||
{
|
||||
/* SYSCFG_Flag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SYSCFG_Flag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SYSCFG_Flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected SYSCFG flag.
|
||||
* @param SYSCFG_Flag: selects the flag to be cleared.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
|
||||
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,304 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Window watchdog (WWDG) peripheral:
|
||||
* + Prescaler, Refresh window and Counter configuration
|
||||
* + WWDG activation
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
==============================================================================
|
||||
##### WWDG features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
time period, unless the program refreshes the counter (downcounter)
|
||||
before to reach 0x3F value (i.e. a reset is generated when the counter
|
||||
value rolls over from 0x40 to 0x3F).
|
||||
[..] An MCU reset is also generated if the counter value is refreshed
|
||||
before the counter has reached the refresh window value. This
|
||||
implies that the counter must be refreshed in a limited window.
|
||||
|
||||
[..] Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
|
||||
[..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
|
||||
reset occurs.
|
||||
|
||||
[..] The WWDG counter input clock is derived from the APB clock divided
|
||||
by a programmable prescaler.
|
||||
|
||||
[..] WWDG counter clock = PCLK1 / Prescaler.
|
||||
[..] WWDG timeout = (WWDG counter clock) * (counter value).
|
||||
|
||||
[..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
|
||||
function.
|
||||
|
||||
(#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
|
||||
|
||||
(#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
|
||||
|
||||
(#) Set the WWDG counter value and start it using WWDG_Enable() function.
|
||||
When the WWDG is enabled the counter value should be configured to
|
||||
a value greater than 0x40 to prevent generating an immediate reset.
|
||||
|
||||
(#) Optionally you can enable the Early wakeup interrupt which is
|
||||
generated when the counter reach 0x40.
|
||||
Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
|
||||
(#) Then the application program must refresh the WWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
WWDG_SetCounter() function. This operation must occur only when
|
||||
the counter value is lower than the refresh window value,
|
||||
programmed using WWDG_SetWindowValue().
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_wwdg.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* --------------------- WWDG registers bit mask ---------------------------- */
|
||||
/* CFR register bit mask */
|
||||
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
|
||||
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_MASK ((uint8_t)0x7F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
|
||||
* @brief Prescaler, Refresh window and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Prescaler, Refresh window and Counter configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpreg = WWDG->CFR & CFR_W_MASK;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
WWDG->CFR |= WWDG_CFR_EWI;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = Counter & BIT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group2 WWDG activation functions
|
||||
* @brief WWDG activation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WWDG activation function #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
WWDG->CR = WWDG_CR_WDGA | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if ((WWDG->SR) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->SR = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 31. July 2014
|
||||
* $Revision: V1.4.4
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
//extern const q31_t realCoefAQ31[1024];
|
||||
//extern const q31_t realCoefBQ31[1024];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 31. July 2014
|
||||
* $Revision: V1.4.4
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,637 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.00
|
||||
* @date 28. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,880 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.00
|
||||
* @date 28. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,697 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.00
|
||||
* @date 22. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32) ) >> 32))
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/* not yet supported */
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,85 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-August-2015
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30X_CONF_H
|
||||
#define __STM32F30X_CONF_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Comment the line below to disable peripheral header file inclusion */
|
||||
#include "stm32f30x_adc.h"
|
||||
#include "stm32f30x_can.h"
|
||||
#include "stm32f30x_crc.h"
|
||||
#include "stm32f30x_comp.h"
|
||||
#include "stm32f30x_dac.h"
|
||||
#include "stm32f30x_dbgmcu.h"
|
||||
#include "stm32f30x_dma.h"
|
||||
#include "stm32f30x_exti.h"
|
||||
#include "stm32f30x_flash.h"
|
||||
#include "stm32f30x_fmc.h"
|
||||
#include "stm32f30x_gpio.h"
|
||||
#include "stm32f30x_hrtim.h"
|
||||
#include "stm32f30x_syscfg.h"
|
||||
#include "stm32f30x_i2c.h"
|
||||
#include "stm32f30x_iwdg.h"
|
||||
#include "stm32f30x_opamp.h"
|
||||
#include "stm32f30x_pwr.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
#include "stm32f30x_rtc.h"
|
||||
#include "stm32f30x_spi.h"
|
||||
#include "stm32f30x_tim.h"
|
||||
#include "stm32f30x_usart.h"
|
||||
#include "stm32f30x_wwdg.h"
|
||||
#include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F30X_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,357 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 27-February-2014
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F30x devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f30x_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f30x.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* Supported STM32F30x device
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL(HSI)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*----------------------------------------------------------------------------
|
||||
* PLLMUL | 16
|
||||
*-----------------------------------------------------------------------------
|
||||
* PREDIV | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB Clock | DISABLE
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 64000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR &= 0xF87FC00C;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF80FFFF;
|
||||
|
||||
/* Reset PREDIV1[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
|
||||
/* At this stage the HSI is already enabled and used as System clock source */
|
||||
|
||||
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
|
||||
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK / 2 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 27-February-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F30X_H
|
||||
#define __SYSTEM_STM32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F30X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Boot\main.c
|
||||
* \brief Bootloader application source file.
|
||||
* \ingroup Boot_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "stm32f30x.h" /* STM32 registers and drivers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return Program return code.
|
||||
**
|
||||
****************************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader */
|
||||
BootInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* run the bootloader task */
|
||||
BootTask();
|
||||
}
|
||||
|
||||
/* program should never get here */
|
||||
return 0;
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* enable the GPIO_LED Clock */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
|
||||
/* configure the GPIO_LED pin */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
/* turn the LED off */
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_3);
|
||||
|
||||
/* configure the D1 (PA9) pin as digital input for backdoor entry */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/* enable UART peripheral clock */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
/* enable GPIO peripheral clock for transmitter and receiver pins */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
/* connect the pin to the peripherals alternate function */
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_7);
|
||||
/* configure USART Tx as alternate function */
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
/* configure USART Rx as alternate function */
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
#endif
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/* enable clocks for CAN1 transmitter and receiver pins */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
/* select alternate function for the CAN1 pins */
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_9);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_9);
|
||||
/* configure CAN1 RX and TX pins */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
/* enable CAN1 clock */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
|
||||
#endif
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,288 @@
|
|||
S02100002E2E5C62696E5C64656D6F70726F675F73746D3332663330332E7372656345
|
||||
S3150800200000300020312F00087F2F0008812F00089C
|
||||
S31508002010832F0008852F0008872F0008000000007E
|
||||
S31508002020000000000000000000000000892F0008E2
|
||||
S315080020308B2F0008000000008D2F00084D30000887
|
||||
S31508002040912F0008932F0008952F0008972F000856
|
||||
S31508002050992F00089B2F00089D2F00089F2F000826
|
||||
S31508002060A12F0008A32F0008A52F0008A72F0008F6
|
||||
S31508002070A92F0008AB2F0008AD2F0008AF2F0008C6
|
||||
S31508002080B12F0008B32F0008B52F0008B72F000896
|
||||
S31508002090B92F0008BB2F0008BD2F0008BF2F000866
|
||||
S315080020A0C12F0008C32F0008C52F0008C72F000836
|
||||
S315080020B0C92F0008CB2F000800000000CD2F00080C
|
||||
S315080020C0CF2F00080000000000000000D12F0008F4
|
||||
S315080020D000000000D32F0008D52F0008D72F0008CE
|
||||
S315080020E0D92F0008DB2F00080000000000000000C0
|
||||
S315080020F000000000000000000000000000000000D2
|
||||
S3150800210000000000000000000000000000000000C1
|
||||
S315080021100000000000000000DD2F0008DF2F000887
|
||||
S3150800212000000000000000000000000000000000A1
|
||||
S315080021300000000000000000000000000000000091
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S315080030E0FEE70000F8B500BFF8BC08BC9E4670476E
|
||||
S315080030F0F8B500BFF8BC08BC9E4670470502060234
|
||||
S31508003100060307030803090309040A040B040C044D
|
||||
S315080031100C050D050E050F050F06100610071008FD
|
||||
S31108003120430000003400002000000000FE
|
||||
S30D0800312CBCF0FF7F0100000062
|
||||
S31508003134010002000400060008000A000C00100042
|
||||
S31508003144200040008000000100000000000000008C
|
||||
S31508003154000000000102030401020304060708092B
|
||||
S315080031640090D003000000000000000000000000EA
|
||||
S31508003174000000000000000000000000000000003D
|
||||
S3150800318400000000203100080000000000000000D4
|
||||
S31508003194000000000000000000000000000000001D
|
||||
S315080031A4000000000000000000000000000000000D
|
||||
S315080031B400000000000000000000000000000000FD
|
||||
S311080031C400000000B12100088D21000861
|
||||
S70508002000D2
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Prog\boot.c
|
||||
* \brief Demo program bootloader interface source file.
|
||||
* \ingroup Prog_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
static void BootComUartInit(void);
|
||||
static void BootComUartCheckActivationRequest(void);
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
static void BootComCanInit(void);
|
||||
static void BootComCanCheckActivationRequest(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComInit(void)
|
||||
{
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
BootComUartInit();
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
BootComCanInit();
|
||||
#endif
|
||||
} /*** end of BootComInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComCheckActivationRequest(void)
|
||||
{
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
BootComUartCheckActivationRequest();
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
BootComCanCheckActivationRequest();
|
||||
#endif
|
||||
} /*** end of BootComCheckActivationRequest ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Bootloader activation function.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootActivate(void)
|
||||
{
|
||||
/* perform software reset to activate the bootoader again */
|
||||
NVIC_SystemReset();
|
||||
} /*** end of BootActivate ***/
|
||||
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the UART communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComUartInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
USART_InitTypeDef USART_InitStruct;
|
||||
|
||||
/* enable UART peripheral clock */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
/* enable GPIO peripheral clock for transmitter and receiver pins */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
/* connect the pin to the peripherals alternate function */
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_7);
|
||||
/* configure USART Tx as alternate function */
|
||||
GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
/* configure USART Rx as alternate function */
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* configure UART communication parameters */
|
||||
USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE;
|
||||
USART_InitStruct.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStruct.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStruct.USART_Parity = USART_Parity_No;
|
||||
USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART2, &USART_InitStruct);
|
||||
/* enable UART */
|
||||
USART_Cmd(USART2, ENABLE);
|
||||
} /*** end of BootComUartInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComUartCheckActivationRequest(void)
|
||||
{
|
||||
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
|
||||
static unsigned char xcpCtoRxLength;
|
||||
static unsigned char xcpCtoRxInProgress = 0;
|
||||
|
||||
/* start of cto packet received? */
|
||||
if (xcpCtoRxInProgress == 0)
|
||||
{
|
||||
/* store the message length when received */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
|
||||
{
|
||||
/* indicate that a cto packet is being received */
|
||||
xcpCtoRxInProgress = 1;
|
||||
|
||||
/* reset packet data count */
|
||||
xcpCtoRxLength = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* store the next packet byte */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
|
||||
{
|
||||
/* increment the packet data count */
|
||||
xcpCtoRxLength++;
|
||||
|
||||
/* check to see if the entire packet was received */
|
||||
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||
{
|
||||
/* done with cto packet reception */
|
||||
xcpCtoRxInProgress = 0;
|
||||
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComUartCheckActivationRequest ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives a communication interface byte if one is present.
|
||||
** \param data Pointer to byte where the data is to be stored.
|
||||
** \return 1 if a byte was received, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data)
|
||||
{
|
||||
/* check flag to see if a byte was received */
|
||||
if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == SET)
|
||||
{
|
||||
/* retrieve and store the newly received byte */
|
||||
*data = (unsigned char)USART_ReceiveData(USART2);
|
||||
/* all done */
|
||||
return 1;
|
||||
}
|
||||
/* still here to no new byte received */
|
||||
return 0;
|
||||
} /*** end of UartReceiveByte ***/
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Structure type for grouping CAN bus timing related information. */
|
||||
typedef struct t_can_bus_timing
|
||||
{
|
||||
unsigned char tseg1; /**< CAN time segment 1 */
|
||||
unsigned char tseg2; /**< CAN time segment 2 */
|
||||
} tCanBusTiming;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
|
||||
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
|
||||
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
|
||||
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
|
||||
* 100%. This array contains possible and valid time quanta configurations with
|
||||
* a sample point between 68..78%.
|
||||
*/
|
||||
static const tCanBusTiming canTiming[] =
|
||||
{ /* TQ | TSEG1 | TSEG2 | SP */
|
||||
/* ------------------------- */
|
||||
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
|
||||
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
|
||||
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
|
||||
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
|
||||
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
|
||||
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
|
||||
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
|
||||
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
|
||||
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
|
||||
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
|
||||
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
|
||||
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
|
||||
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
|
||||
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
|
||||
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
|
||||
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
|
||||
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
|
||||
{ 16, 8 } /* 25 | 16 | 8 | 68% */
|
||||
};
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Search algorithm to match the desired baudrate to a possible bus
|
||||
** timing configuration.
|
||||
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
|
||||
** \param prescaler Pointer to where the value for the prescaler will be stored.
|
||||
** \param tseg1 Pointer to where the value for TSEG2 will be stored.
|
||||
** \param tseg2 Pointer to where the value for TSEG2 will be stored.
|
||||
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
|
||||
unsigned char *tseg1, unsigned char *tseg2)
|
||||
{
|
||||
unsigned char cnt;
|
||||
|
||||
/* loop through all possible time quanta configurations to find a match */
|
||||
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
|
||||
{
|
||||
if (((BOOT_CPU_SYSTEM_SPEED_KHZ/2) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
|
||||
{
|
||||
/* compute the prescaler that goes with this TQ configuration */
|
||||
*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/2)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
|
||||
|
||||
/* make sure the prescaler is valid */
|
||||
if ( (*prescaler > 0) && (*prescaler <= 1024) )
|
||||
{
|
||||
/* store the bustiming configuration */
|
||||
*tseg1 = canTiming[cnt].tseg1;
|
||||
*tseg2 = canTiming[cnt].tseg2;
|
||||
/* found a good bus timing configuration */
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* could not find a good bus timing configuration */
|
||||
return 0;
|
||||
} /*** end of CanGetSpeedConfig ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the CAN communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComCanInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
CAN_InitTypeDef CAN_InitStructure;
|
||||
CAN_FilterInitTypeDef CAN_FilterInitStructure;
|
||||
unsigned short prescaler;
|
||||
unsigned char tseg1, tseg2;
|
||||
|
||||
/* enable clocks for CAN1 transmitter and receiver pins */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
/* select alternate function for the CAN1 pins */
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_9);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_9);
|
||||
/* configure CAN1 RX and TX pins */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
/* enable CAN1 clock */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
|
||||
/* CAN register init */
|
||||
CAN_DeInit(CAN1);
|
||||
CAN_StructInit(&CAN_InitStructure);
|
||||
/* obtain the bittiming configuration for this baudrate */
|
||||
CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
|
||||
/* CAN controller init */
|
||||
CAN_InitStructure.CAN_TTCM = DISABLE;
|
||||
CAN_InitStructure.CAN_ABOM = DISABLE;
|
||||
CAN_InitStructure.CAN_AWUM = DISABLE;
|
||||
CAN_InitStructure.CAN_NART = DISABLE;
|
||||
CAN_InitStructure.CAN_RFLM = DISABLE;
|
||||
CAN_InitStructure.CAN_TXFP = DISABLE;
|
||||
CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
|
||||
/* CAN Baudrate init */
|
||||
CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
|
||||
CAN_InitStructure.CAN_BS1 = tseg1 - 1;
|
||||
CAN_InitStructure.CAN_BS2 = tseg2 - 1;
|
||||
CAN_InitStructure.CAN_Prescaler = prescaler;
|
||||
CAN_Init(CAN1, &CAN_InitStructure);
|
||||
/* CAN filter init - receive all messages */
|
||||
CAN_FilterInitStructure.CAN_FilterNumber = 0;
|
||||
CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
|
||||
CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
|
||||
CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
|
||||
CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
|
||||
CAN_FilterInit(&CAN_FilterInitStructure);
|
||||
} /*** end of BootComCanInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComCanCheckActivationRequest(void)
|
||||
{
|
||||
CanRxMsg RxMessage;
|
||||
|
||||
/* check if a new message was received */
|
||||
if (CAN_MessagePending(CAN1, CAN_FIFO0) > 0)
|
||||
{
|
||||
/* receive the message */
|
||||
CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
|
||||
if (RxMessage.StdId == BOOT_COM_CAN_RX_MSG_ID)
|
||||
{
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((RxMessage.Data[0] == 0xff) && (RxMessage.Data[1] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComCanCheckActivationRequest ***/
|
||||
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of boot.c *************************************/
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Prog\boot.h
|
||||
* \brief Demo program bootloader interface header file.
|
||||
* \ingroup Prog_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BOOT_H
|
||||
#define BOOT_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void BootComInit(void);
|
||||
void BootComCheckActivationRequest(void);
|
||||
void BootActivate(void);
|
||||
|
||||
|
||||
#endif /* BOOT_H */
|
||||
/*********************************** end of boot.h *************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,183 @@
|
|||
/* ---------------------------------------------------------------------------- */
|
||||
/* Em::Blocks embedded development Support */
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/* Copyright (c) 2014, EmBlocks */
|
||||
/* */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following condition is met: */
|
||||
/* */
|
||||
/* - Redistributions of source code must retain the above copyright notice, */
|
||||
/* this list of conditions and the disclaimer below. */
|
||||
/* */
|
||||
/* EmBlocks's name may not be used to endorse or promote products derived from */
|
||||
/* this software without specific prior written permission. */
|
||||
/* */
|
||||
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY EBLOCKS "AS IS" AND ANY EXPRESS OR */
|
||||
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
|
||||
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL EMBLOCKS BE LIABLE FOR ANY DIRECT, INDIRECT, */
|
||||
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
|
||||
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
|
||||
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
|
||||
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
|
||||
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the STM32F303K8
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
/* reserve space for the OpenBLT bootloader which occupies the first part
|
||||
* of flash.
|
||||
*/
|
||||
ROM (rx) : ORIGIN = 0x08002000, LENGTH = 64K-8K
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > ROM
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > ROM
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Prog\header.h
|
||||
* \brief Generic header file.
|
||||
* \ingroup Prog_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef HEADER_H
|
||||
#define HEADER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "../Boot/blt_conf.h" /* bootloader configuration */
|
||||
#include "stm32f30x.h" /* STM32 registers and drivers */
|
||||
#include "boot.h" /* bootloader interface driver */
|
||||
#include "led.h" /* LED driver */
|
||||
#include "timer.h" /* Timer driver */
|
||||
|
||||
|
||||
#endif /* HEADER_H */
|
||||
/*********************************** end of header.h ***********************************/
|
||||
|
|
@ -0,0 +1,873 @@
|
|||
# depslib dependency file v1.0
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_adc.c
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_adc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436355286 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\stm32f30x.h
|
||||
"core_cm4.h"
|
||||
"system_stm32f30x.h"
|
||||
<stdint.h>
|
||||
"stm32f30x_conf.h"
|
||||
|
||||
1436355025 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cm4.h
|
||||
<stdint.h>
|
||||
<core_cmInstr.h>
|
||||
<core_cmFunc.h>
|
||||
<core_cmSimd.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cminstr.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cmfunc.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355024 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\cmsis\core_cmsimd.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436355286 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\system_stm32f30x.h
|
||||
|
||||
1439555739 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\stm32f30x_conf.h
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_crc.h"
|
||||
"stm32f30x_comp.h"
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_dbgmcu.h"
|
||||
"stm32f30x_dma.h"
|
||||
"stm32f30x_exti.h"
|
||||
"stm32f30x_flash.h"
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_hrtim.h"
|
||||
"stm32f30x_syscfg.h"
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_iwdg.h"
|
||||
"stm32f30x_opamp.h"
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_can.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_crc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_comp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dac.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dbgmcu.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_dma.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_exti.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_flash.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_fmc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_gpio.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_hrtim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_syscfg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_i2c.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_iwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_opamp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_pwr.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_rcc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_rtc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_spi.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542507 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_tim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_usart.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542506 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_wwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\inc\stm32f30x_misc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_can.c
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_comp.c
|
||||
"stm32f30x_comp.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_crc.c
|
||||
"stm32f30x_crc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dac.c
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dbgmcu.c
|
||||
"stm32f30x_dbgmcu.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_dma.c
|
||||
"stm32f30x_dma.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_exti.c
|
||||
"stm32f30x_exti.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_flash.c
|
||||
"stm32f30x_flash.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_fmc.c
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_gpio.c
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_hrtim.c
|
||||
"stm32f30x_hrtim.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_i2c.c
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_iwdg.c
|
||||
"stm32f30x_iwdg.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_misc.c
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_opamp.c
|
||||
"stm32f30x_opamp.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_pwr.c
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_rcc.c
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_rtc.c
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_spi.c
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_syscfg.c
|
||||
"stm32f30x_syscfg.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_tim.c
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_usart.c
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436542505 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\lib\spl\src\stm32f30x_wwdg.c
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1471084291 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\main.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1471084169 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\startup_stm32f30x.s
|
||||
|
||||
1471086847 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\system_stm32f30x.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1452185562 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\assert.c
|
||||
"header.h"
|
||||
|
||||
1461838668 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\header.h
|
||||
<stdint.h>
|
||||
<stdlib.h>
|
||||
"os.h"
|
||||
"hw.h"
|
||||
"app.h"
|
||||
|
||||
1452185952 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\os\os.h
|
||||
|
||||
1471085506 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\hw.h
|
||||
"stm32f30x.h"
|
||||
"led.h"
|
||||
|
||||
1452186099 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\led.h
|
||||
|
||||
1452185785 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\app.h
|
||||
"assert.h"
|
||||
|
||||
1452185438 c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\assert.h
|
||||
|
||||
1471086902 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\hw.c
|
||||
"header.h"
|
||||
|
||||
1471086227 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\hw\led.c
|
||||
"header.h"
|
||||
|
||||
1471086926 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\app\app.c
|
||||
"header.h"
|
||||
|
||||
1452185952 source:c:\users\voorburg\desktop\stm32f303_emblocks_os\src\os\os.c
|
||||
"os.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_adc.c
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_adc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\stm32f30x.h
|
||||
"core_cm4.h"
|
||||
"system_stm32f30x.h"
|
||||
<stdint.h>
|
||||
"stm32f30x_conf.h"
|
||||
|
||||
1436351425 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cm4.h
|
||||
<stdint.h>
|
||||
<core_cmInstr.h>
|
||||
<core_cmFunc.h>
|
||||
<core_cmSimd.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cminstr.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cmfunc.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\cmsis\core_cmsimd.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\system_stm32f30x.h
|
||||
|
||||
1439552139 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\stm32f30x_conf.h
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_crc.h"
|
||||
"stm32f30x_comp.h"
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_dbgmcu.h"
|
||||
"stm32f30x_dma.h"
|
||||
"stm32f30x_exti.h"
|
||||
"stm32f30x_flash.h"
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_hrtim.h"
|
||||
"stm32f30x_syscfg.h"
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_iwdg.h"
|
||||
"stm32f30x_opamp.h"
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_can.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_crc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_comp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dac.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dbgmcu.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_dma.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_exti.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_flash.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_fmc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_gpio.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_hrtim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_syscfg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_i2c.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_iwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_opamp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_pwr.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_rcc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_rtc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_spi.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_tim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_usart.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_wwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\inc\stm32f30x_misc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_can.c
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_comp.c
|
||||
"stm32f30x_comp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_crc.c
|
||||
"stm32f30x_crc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dac.c
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dbgmcu.c
|
||||
"stm32f30x_dbgmcu.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_dma.c
|
||||
"stm32f30x_dma.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_exti.c
|
||||
"stm32f30x_exti.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_flash.c
|
||||
"stm32f30x_flash.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_fmc.c
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_gpio.c
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_hrtim.c
|
||||
"stm32f30x_hrtim.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_i2c.c
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_iwdg.c
|
||||
"stm32f30x_iwdg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_misc.c
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_opamp.c
|
||||
"stm32f30x_opamp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_pwr.c
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_rcc.c
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_rtc.c
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_spi.c
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_syscfg.c
|
||||
"stm32f30x_syscfg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_tim.c
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_usart.c
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\spl\src\stm32f30x_wwdg.c
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1471083247 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\lib\system_stm32f30x.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1478878702 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\app.c
|
||||
"header.h"
|
||||
|
||||
1461835068 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\header.h
|
||||
<stdint.h>
|
||||
<stdlib.h>
|
||||
"os.h"
|
||||
"hw.h"
|
||||
"app.h"
|
||||
|
||||
1452182352 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\os\os.h
|
||||
|
||||
1471081906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\hw.h
|
||||
"stm32f30x.h"
|
||||
"led.h"
|
||||
|
||||
1452182499 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\led.h
|
||||
|
||||
1452182185 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\app.h
|
||||
"assert.h"
|
||||
|
||||
1452181838 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\assert.h
|
||||
|
||||
1452181962 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\app\assert.c
|
||||
"header.h"
|
||||
|
||||
1471083302 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\hw.c
|
||||
"header.h"
|
||||
|
||||
1471082627 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\led.c
|
||||
"header.h"
|
||||
|
||||
1471080569 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\hw\startup_stm32f30x.s
|
||||
|
||||
1452182352 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\src\os\os.c
|
||||
"os.h"
|
||||
|
||||
1479114435 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\hooks.c
|
||||
"boot.h"
|
||||
"led.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1477216154 c:\work\software\openblt\target\source\boot.h
|
||||
"types.h"
|
||||
"assert.h"
|
||||
"blt_conf.h"
|
||||
"plausibility.h"
|
||||
"cpu.h"
|
||||
"cop.h"
|
||||
"nvm.h"
|
||||
"timer.h"
|
||||
"backdoor.h"
|
||||
"file.h"
|
||||
"com.h"
|
||||
|
||||
1478879101 c:\work\software\openblt\target\source\armcm4_stm32f3\types.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\assert.h
|
||||
|
||||
1479122668 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\blt_conf.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\plausibility.h
|
||||
|
||||
1476728168 c:\work\software\openblt\target\source\cpu.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\cop.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\nvm.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\timer.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\backdoor.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\file.h
|
||||
"ff.h"
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\com.h
|
||||
"xcp.h"
|
||||
|
||||
1476783465 c:\work\software\openblt\target\source\xcp.h
|
||||
|
||||
1478880688 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\led.h
|
||||
|
||||
1479111264 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\led.c
|
||||
"boot.h"
|
||||
"led.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1479116640 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\boot\main.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1478878881 source:c:\work\software\openblt\target\source\armcm4_stm32f3\can.c
|
||||
"boot.h"
|
||||
|
||||
1478878920 source:c:\work\software\openblt\target\source\armcm4_stm32f3\cpu.c
|
||||
"boot.h"
|
||||
|
||||
1479114071 source:c:\work\software\openblt\target\source\armcm4_stm32f3\flash.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
"flash_layout.c"
|
||||
|
||||
1478879160 source:c:\work\software\openblt\target\source\armcm4_stm32f3\gcc\cpu_comp.c
|
||||
"boot.h"
|
||||
|
||||
1478879348 source:c:\work\software\openblt\target\source\armcm4_stm32f3\gcc\cstart.s
|
||||
|
||||
1478879055 source:c:\work\software\openblt\target\source\armcm4_stm32f3\nvm.c
|
||||
"boot.h"
|
||||
"flash.h"
|
||||
|
||||
1478879042 c:\work\software\openblt\target\source\armcm4_stm32f3\flash.h
|
||||
|
||||
1478879086 source:c:\work\software\openblt\target\source\armcm4_stm32f3\timer.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1479116679 source:c:\work\software\openblt\target\source\armcm4_stm32f3\uart.c
|
||||
"boot.h"
|
||||
"stm32f30x.h"
|
||||
|
||||
1477295250 source:c:\work\software\openblt\target\source\assert.c
|
||||
"boot.h"
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\backdoor.c
|
||||
"boot.h"
|
||||
|
||||
1476728156 source:c:\work\software\openblt\target\source\boot.c
|
||||
"boot.h"
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\com.c
|
||||
"boot.h"
|
||||
"can.h"
|
||||
"uart.h"
|
||||
"usb.h"
|
||||
"net.h"
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\can.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\uart.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\usb.h
|
||||
|
||||
1469431761 c:\work\software\openblt\target\source\net.h
|
||||
|
||||
1469431756 source:c:\work\software\openblt\target\source\cop.c
|
||||
"boot.h"
|
||||
|
||||
1469281006 source:c:\work\software\openblt\target\source\file.c
|
||||
"boot.h"
|
||||
<string.h>
|
||||
<ctype.h>
|
||||
|
||||
1469431757 source:c:\work\software\openblt\target\source\net.c
|
||||
"boot.h"
|
||||
"netdev.h"
|
||||
"uip.h"
|
||||
"uip_arp.h"
|
||||
|
||||
1476783463 source:c:\work\software\openblt\target\source\xcp.c
|
||||
"boot.h"
|
||||
|
||||
1479124699 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\boot.c
|
||||
"header.h"
|
||||
|
||||
1479117171 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\header.h
|
||||
"../Boot/blt_conf.h"
|
||||
"stm32f30x.h"
|
||||
"boot.h"
|
||||
"led.h"
|
||||
"timer.h"
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\stm32f30x.h
|
||||
"core_cm4.h"
|
||||
"system_stm32f30x.h"
|
||||
<stdint.h>
|
||||
"stm32f30x_conf.h"
|
||||
|
||||
1436351425 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\cmsis\core_cm4.h
|
||||
<stdint.h>
|
||||
<core_cmInstr.h>
|
||||
<core_cmFunc.h>
|
||||
<core_cmSimd.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\cmsis\core_cminstr.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\cmsis\core_cmfunc.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351424 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\cmsis\core_cmsimd.h
|
||||
<cmsis_iar.h>
|
||||
<cmsis_ccs.h>
|
||||
<cmsis_csm.h>
|
||||
|
||||
1436351686 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\system_stm32f30x.h
|
||||
|
||||
1439552139 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\stm32f30x_conf.h
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_crc.h"
|
||||
"stm32f30x_comp.h"
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_dbgmcu.h"
|
||||
"stm32f30x_dma.h"
|
||||
"stm32f30x_exti.h"
|
||||
"stm32f30x_flash.h"
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_hrtim.h"
|
||||
"stm32f30x_syscfg.h"
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_iwdg.h"
|
||||
"stm32f30x_opamp.h"
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_adc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_can.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_crc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_comp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_dac.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_dbgmcu.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_dma.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_exti.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_flash.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_fmc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_gpio.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_hrtim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_syscfg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_i2c.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_iwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_opamp.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_pwr.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_rcc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_rtc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_spi.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538907 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_tim.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_usart.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538906 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_wwdg.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1436538905 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\inc\stm32f30x_misc.h
|
||||
"stm32f30x.h"
|
||||
|
||||
1479117075 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\boot.h
|
||||
|
||||
1479117106 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\led.h
|
||||
|
||||
1479117152 c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\timer.h
|
||||
|
||||
1479122242 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\led.c
|
||||
"header.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_adc.c
|
||||
"stm32f30x_adc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_can.c
|
||||
"stm32f30x_can.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_comp.c
|
||||
"stm32f30x_comp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_crc.c
|
||||
"stm32f30x_crc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_dac.c
|
||||
"stm32f30x_dac.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_dbgmcu.c
|
||||
"stm32f30x_dbgmcu.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_dma.c
|
||||
"stm32f30x_dma.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_exti.c
|
||||
"stm32f30x_exti.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_flash.c
|
||||
"stm32f30x_flash.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_fmc.c
|
||||
"stm32f30x_fmc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_gpio.c
|
||||
"stm32f30x_gpio.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_hrtim.c
|
||||
"stm32f30x_hrtim.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_i2c.c
|
||||
"stm32f30x_i2c.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_iwdg.c
|
||||
"stm32f30x_iwdg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_misc.c
|
||||
"stm32f30x_misc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_opamp.c
|
||||
"stm32f30x_opamp.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_pwr.c
|
||||
"stm32f30x_pwr.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_rcc.c
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_rtc.c
|
||||
"stm32f30x_rtc.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_spi.c
|
||||
"stm32f30x_spi.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_syscfg.c
|
||||
"stm32f30x_syscfg.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_tim.c
|
||||
"stm32f30x_tim.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_usart.c
|
||||
"stm32f30x_usart.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1436538905 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\spl\src\stm32f30x_wwdg.c
|
||||
"stm32f30x_wwdg.h"
|
||||
"stm32f30x_rcc.h"
|
||||
|
||||
1479118125 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\lib\system_stm32f30x.c
|
||||
"stm32f30x.h"
|
||||
|
||||
1479117116 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\main.c
|
||||
"header.h"
|
||||
|
||||
1479118057 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\startup_stm32f30x.s
|
||||
|
||||
1479117141 source:c:\work\software\openblt\target\demo\armcm4_stm32f3_nucleo_f303k8_gcc\prog\timer.c
|
||||
"header.h"
|
||||
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<EmBitz_project_file>
|
||||
<EmBitzVersion release="1.00" revision="0" />
|
||||
<FileVersion major="1" minor="0" />
|
||||
<Project>
|
||||
<Option title="stm32f303" />
|
||||
<Option pch_mode="2" />
|
||||
<Option compiler="armgcc_eb" />
|
||||
<Option virtualFolders="Libs\;Libs\cmsis\;Libs\SPL\;Srcs\;" />
|
||||
<Build>
|
||||
<Target title="Debug">
|
||||
<Option output="..\bin\demoprog_stm32f303.elf" />
|
||||
<Option object_output="..\obj\" />
|
||||
<Option type="0" />
|
||||
<Option compiler="armgcc_eb" />
|
||||
<Option projectDeviceOptionsRelation="0" />
|
||||
<Compiler>
|
||||
<Add option="-Wall" />
|
||||
<Add option="-fdata-sections" />
|
||||
<Add option="-ffunction-sections" />
|
||||
<Add option="-O0" />
|
||||
<Add option="-g3" />
|
||||
<Add option="-Og" />
|
||||
</Compiler>
|
||||
<Assembler>
|
||||
<Add option="-Wa,--gdwarf-2" />
|
||||
</Assembler>
|
||||
<Linker>
|
||||
<Add option="-Wl,--gc-sections" />
|
||||
</Linker>
|
||||
</Target>
|
||||
</Build>
|
||||
<Device>
|
||||
<Add option="$device=cortex-m4" />
|
||||
<Add option="$lscript=./../cfg/stm32f303k8_flash.ld" />
|
||||
<Add option="$stack=0x0100" />
|
||||
<Add option="$heap=0x0000" />
|
||||
</Device>
|
||||
<Compiler>
|
||||
<Add option="-mfloat-abi=soft" />
|
||||
<Add option="-fno-strict-aliasing" />
|
||||
<Add symbol="STM32F303K8" />
|
||||
<Add symbol="STM32F334x8" />
|
||||
<Add symbol="USE_STDPERIPH_DRIVER" />
|
||||
<Add directory="..\src" />
|
||||
<Add directory="..\src\app" />
|
||||
<Add directory="..\src\hw" />
|
||||
<Add directory="..\src\os" />
|
||||
<Add directory="..\lib" />
|
||||
<Add directory="..\lib\cmsis" />
|
||||
<Add directory="..\lib\SPL\inc" />
|
||||
</Compiler>
|
||||
<Linker>
|
||||
<Add option="-eb_lib=n" />
|
||||
<Add option="-eb_start_files" />
|
||||
</Linker>
|
||||
<ExtraCommands>
|
||||
<Add after="arm-none-eabi-objcopy -O srec $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).elf $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).srec" />
|
||||
<Mode before="0" />
|
||||
<Mode after="1" />
|
||||
</ExtraCommands>
|
||||
<Unit filename="..\boot.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\boot.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\header.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\led.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\led.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_common_tables.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_const_structs.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\arm_math.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cm4.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmFunc.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmInstr.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\cmsis\core_cmSimd.h">
|
||||
<Option virtualFolder="Libs\cmsis\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_adc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_can.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_comp.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_crc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dac.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dbgmcu.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_dma.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_exti.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_flash.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_fmc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_gpio.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_hrtim.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_i2c.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_iwdg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_misc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_opamp.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_pwr.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_rcc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_rtc.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_spi.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_syscfg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_tim.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_usart.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\inc\stm32f30x_wwdg.h">
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_adc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_can.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_comp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_crc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dac.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dbgmcu.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_dma.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_exti.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_flash.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_fmc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_gpio.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_hrtim.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_i2c.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_iwdg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_misc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_opamp.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_pwr.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_rcc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_rtc.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_spi.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_syscfg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_tim.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_usart.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\SPL\src\stm32f30x_wwdg.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\SPL\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\stm32f30x.h">
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\stm32f30x_conf.h">
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\system_stm32f30x.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\lib\system_stm32f30x.h">
|
||||
<Option virtualFolder="Libs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\main.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\startup_stm32f30x.S">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\timer.c">
|
||||
<Option compilerVar="CC" />
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Unit filename="..\timer.h">
|
||||
<Option virtualFolder="Srcs\" />
|
||||
</Unit>
|
||||
<Extensions>
|
||||
<code_completion />
|
||||
<debugger>
|
||||
<target_debugging_settings target="Debug" active_interface="ST-link">
|
||||
<debug_interface interface_id="ST-link" ip_address="localhost" ip_port="4242" path="${EMBITZ}\share\contrib" executable="STLinkGDB.exe" description="..\cfg\STM32F303x.svd" dont_start_server="false" backoff_time="1000" options="2" reg_filter="0" active_family="STMicroelectronics" gdb_before_conn="" gdb_after_conn="">
|
||||
<family_options family_id="STMicroelectronics">
|
||||
<option opt_id="ID_JTAG_SWD" opt_value="swd" />
|
||||
<option opt_id="ID_VECTOR_START" opt_value="0x08000000" />
|
||||
<option opt_id="ID_RESET_TYPE" opt_value="System" />
|
||||
<option opt_id="ID_LOAD_PROGRAM" opt_value="1" />
|
||||
<option opt_id="ID_SEMIHOST_CHECK" opt_value="0" />
|
||||
<option opt_id="ID_RAM_EXEC" opt_value="0" />
|
||||
<option opt_id="ID_VEC_TABLE" opt_value="1" />
|
||||
<option opt_id="ID_DONT_CONN_RESET" opt_value="0" />
|
||||
<option opt_id="ID_ALL_MODE_DEBUG" opt_value="0" />
|
||||
<option opt_id="ID_DEV_ADDR" opt_value="" />
|
||||
<option opt_id="ID_VERBOSE_LEVEL" opt_value="3" />
|
||||
</family_options>
|
||||
</debug_interface>
|
||||
</target_debugging_settings>
|
||||
</debugger>
|
||||
<envvars />
|
||||
</Extensions>
|
||||
</Project>
|
||||
</EmBitz_project_file>
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<EmBitz_layout_file>
|
||||
<ActiveTarget name="Debug" />
|
||||
<File name="..\boot.c" open="1" top="1" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="13124" topLine="288" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\boot.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="275" topLine="0" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\header.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="1954" topLine="0" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\led.c" open="1" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="2185" topLine="9" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\led.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="251" topLine="0" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_gpio.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="10201" topLine="250" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\inc\stm32f30x_rcc.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="31070" topLine="671" />
|
||||
</Cursor>
|
||||
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|
||||
<File name="..\lib\SPL\src\stm32f30x_gpio.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="17830" topLine="456" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\lib\SPL\src\stm32f30x_usart.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="79457" topLine="1866" />
|
||||
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|
||||
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|
||||
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|
||||
<Cursor>
|
||||
<Cursor1 position="8138" topLine="177" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\main.c" open="1" top="0" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="1915" topLine="21" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\startup_stm32f30x.S" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="2856" topLine="120" />
|
||||
</Cursor>
|
||||
</File>
|
||||
<File name="..\timer.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="1088" topLine="0" />
|
||||
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|
||||
</File>
|
||||
<File name="..\timer.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
|
||||
<Cursor>
|
||||
<Cursor1 position="255" topLine="0" />
|
||||
</Cursor>
|
||||
</File>
|
||||
</EmBitz_layout_file>
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Prog\led.c
|
||||
* \brief LED driver source file.
|
||||
* \ingroup Prog_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Toggle interval time in milliseconds. */
|
||||
#define LED_TOGGLE_MS (500)
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the LED. The board doesn't have a dedicted LED so an
|
||||
** indicator on the LCD is used instead.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* enable the GPIO_LED Clock */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
|
||||
/* configure the GPIO_LED pin */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
/* turn the LED off */
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_3);
|
||||
} /*** end of LedInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Toggles the LED at a fixed time interval.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedToggle(void)
|
||||
{
|
||||
static unsigned char led_toggle_state = 0;
|
||||
static unsigned long timer_counter_last = 0;
|
||||
unsigned long timer_counter_now;
|
||||
|
||||
/* check if toggle interval time passed */
|
||||
timer_counter_now = TimerGet();
|
||||
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
|
||||
{
|
||||
/* not yet time to toggle */
|
||||
return;
|
||||
}
|
||||
|
||||
/* determine toggle action */
|
||||
if (led_toggle_state == 0)
|
||||
{
|
||||
led_toggle_state = 1;
|
||||
/* turn the LED on */
|
||||
GPIO_SetBits(GPIOB, GPIO_Pin_3);
|
||||
}
|
||||
else
|
||||
{
|
||||
led_toggle_state = 0;
|
||||
/* turn the LED off */
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_3);
|
||||
}
|
||||
|
||||
/* store toggle time to determine next toggle interval */
|
||||
timer_counter_last = timer_counter_now;
|
||||
} /*** end of LedToggle ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_STM32F3_Nucleo_F303K8_GCC\Prog\led.h
|
||||
* \brief LED driver header file.
|
||||
* \ingroup Prog_ARMCM4_STM32F3_Nucleo_F303K8_GCC
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedInit(void);
|
||||
void LedToggle(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,820 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_ADC_H
|
||||
#define __STM32F30x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_resolution */
|
||||
uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
|
||||
regular group conversion.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of injected channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_Injected_channels_conversion */
|
||||
uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for injected channel group.
|
||||
This parameter must range from 1 to 4. */
|
||||
uint32_t ADC_InjecSequence1;
|
||||
uint32_t ADC_InjecSequence2;
|
||||
uint32_t ADC_InjecSequence3;
|
||||
uint32_t ADC_InjecSequence4;
|
||||
}ADC_InjectedInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
|
||||
independent or multi mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
|
||||
and slave ADCs.
|
||||
This parameter can be a value of @ref ADC_Clock */
|
||||
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of
|
||||
@ref ADC_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
|
||||
This parameter can be a value of @ref ADC_DMA_Mode_definition */
|
||||
uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value between 0x0 and 0xF */
|
||||
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
/** @defgroup ADC_ContinuousConvMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
|
||||
#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
|
||||
#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
|
||||
((MODE) == ADC_ContinuousConvMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_OverunMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
|
||||
#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
|
||||
#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
|
||||
((MODE) == ADC_OverrunMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_AutoInjecMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
|
||||
#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
|
||||
#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
|
||||
((MODE) == ADC_AutoInjec_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
|
||||
#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
|
||||
#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
|
||||
#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
|
||||
|
||||
#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
|
||||
|
||||
#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
|
||||
#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
|
||||
#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
|
||||
#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
|
||||
#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
|
||||
#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
|
||||
#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
|
||||
#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
|
||||
#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
|
||||
#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
|
||||
#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
|
||||
#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
|
||||
#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
|
||||
#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
|
||||
#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
|
||||
#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
|
||||
#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
|
||||
#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
|
||||
#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
|
||||
#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
|
||||
#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
|
||||
#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
|
||||
#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
|
||||
#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
|
||||
#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
|
||||
#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
|
||||
#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
|
||||
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || \
|
||||
((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || \
|
||||
((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18))
|
||||
#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
|
||||
#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
|
||||
#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
|
||||
#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
|
||||
#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
|
||||
#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
|
||||
#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
|
||||
((MODE) == ADC_Mode_InjSimul) || \
|
||||
((MODE) == ADC_Mode_RegSimul) || \
|
||||
((MODE) == ADC_Mode_Interleave) || \
|
||||
((MODE) == ADC_Mode_AltTrig))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Clock
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
|
||||
#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
|
||||
#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
|
||||
#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
|
||||
#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
|
||||
#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
|
||||
#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
|
||||
((MODE) == ADC_DMAAccessMode_1) || \
|
||||
((MODE) == ADC_DMAAccessMode_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
|
||||
#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
|
||||
#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
|
||||
#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
|
||||
#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
|
||||
#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
|
||||
#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_2Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_4Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_19Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_61Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_181Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_601Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
|
||||
#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
|
||||
#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
|
||||
#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
|
||||
#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
|
||||
#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
|
||||
#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
|
||||
#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
|
||||
#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
|
||||
#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
|
||||
#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
|
||||
#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
|
||||
#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
|
||||
#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
|
||||
#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
|
||||
#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
|
||||
#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
|
||||
#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
|
||||
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_5) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_6) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_7) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_8) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_9) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_10) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_11) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_12) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_13) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_14) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_15) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_16) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_17) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Sequence_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
|
||||
#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
|
||||
#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
|
||||
#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
|
||||
#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_2) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_3) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Calibration_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
|
||||
#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
|
||||
|
||||
#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_DMA_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
|
||||
#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
|
||||
|
||||
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
|
||||
#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
|
||||
#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
|
||||
#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
|
||||
#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
|
||||
#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
|
||||
#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
|
||||
#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
|
||||
#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
|
||||
#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
|
||||
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
|
||||
((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
|
||||
((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
|
||||
((IT) == ADC_IT_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
|
||||
#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
|
||||
#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
|
||||
#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
|
||||
#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
|
||||
((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
|
||||
((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
|
||||
((FLAG) == ADC_FLAG_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Common_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
|
||||
#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
|
||||
#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
|
||||
#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
|
||||
#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
|
||||
|
||||
#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
|
||||
#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
|
||||
#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
|
||||
#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
|
||||
#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
|
||||
#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
|
||||
((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
|
||||
((FLAG) == ADC_FLAG_MSTJQOVF) || \
|
||||
((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
|
||||
((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
|
||||
((FLAG) == ADC_FLAG_SLVJQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_two_sampling_delay_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
|
||||
void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
|
||||
void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DisableCmd(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
|
||||
void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor, Vrefint and Vbat management function */
|
||||
void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
|
||||
void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
|
||||
|
||||
void ADC_StartConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
|
||||
void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
|
||||
void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* ADC Dual Modes Configuration functions *************************************/
|
||||
FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,643 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CAN_H
|
||||
#define __STM32F30x_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode_status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
|
||||
an empty mailbox */
|
||||
/* Legacy defines */
|
||||
#define CANTXFAILED CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* CAN Frames Transmission functions ******************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* CAN Frames Reception functions *********************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* CAN Bus Error management functions *****************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CAN_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_COMP_H
|
||||
#define __STM32F30x_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
|
||||
uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_NonInvertingInput */
|
||||
|
||||
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMP_Output */
|
||||
|
||||
uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPoloarity */
|
||||
|
||||
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
|
||||
and allows to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMP_Mode */
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
|
||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
|
||||
#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
|
||||
#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
|
||||
#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
|
||||
#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
|
||||
#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2) || \
|
||||
((PERIPH) == COMP_Selection_COMP3) || \
|
||||
((PERIPH) == COMP_Selection_COMP4) || \
|
||||
((PERIPH) == COMP_Selection_COMP5) || \
|
||||
((PERIPH) == COMP_Selection_COMP6) || \
|
||||
((PERIPH) == COMP_Selection_COMP7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
|
||||
|
||||
#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
|
||||
PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
|
||||
PC0 for COMP7) connected to comparator inverting input */
|
||||
|
||||
#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
|
||||
PB15 for COMP6) connected to comparator inverting input.
|
||||
It is valid only for STM32F303xC devices */
|
||||
|
||||
#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
|
||||
((INPUT) == COMP_InvertingInput_IO1) || \
|
||||
((INPUT) == COMP_InvertingInput_IO2) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC2OUT1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
|
||||
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
|
||||
PA0 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
|
||||
PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
|
||||
((INPUT) == COMP_NonInvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
|
||||
|
||||
/* Output Redirection common for all comparators COMP1...COMP7 */
|
||||
#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
|
||||
#define COMP_Output_TIM20BKIN ((uint32_t)0x00003000) /*!< COMP output connected to TIM20 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM20BKIN2 ((uint32_t)0x00003400) /*!< COMP output connected to TIM20 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input2 */
|
||||
|
||||
/* Output Redirection common for COMP1 and COMP2 */
|
||||
#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
|
||||
#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
|
||||
#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
|
||||
#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
|
||||
#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP2 */
|
||||
#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
|
||||
#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
|
||||
#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
|
||||
#define COMP_Output_TIM20OCREFCLR ((uint32_t)0x00003C00) /*!< COMP output connected to TIM20 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP3 */
|
||||
#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
|
||||
#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
|
||||
#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
|
||||
#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP4 */
|
||||
#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
|
||||
#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
|
||||
#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
|
||||
#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
|
||||
#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
|
||||
|
||||
#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
|
||||
#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
|
||||
#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
|
||||
|
||||
/* Output Redirection specific to COMP5 */
|
||||
#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
|
||||
#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
|
||||
#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP6 */
|
||||
#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
|
||||
#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
|
||||
|
||||
#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
|
||||
#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
|
||||
#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
|
||||
|
||||
/* Output Redirection specific to COMP7 */
|
||||
#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
|
||||
#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
|
||||
#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM16BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM16IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM17BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
|
||||
((OUTPUT) == COMP_Output_HRTIM1_EE8_2) || \
|
||||
((OUTPUT) == COMP_Output_TIM20BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM20BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2)|| \
|
||||
((OUTPUT) == COMP_Output_TIM20OCREFCLR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* No blanking source can be selected for all comparators */
|
||||
#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1 and COMP2 */
|
||||
#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2 and COMP5 */
|
||||
#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP3 and COMP6 */
|
||||
#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source for COMP4 */
|
||||
#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
|
||||
#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
|
||||
|
||||
#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPoloarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
|
||||
|
||||
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
|
||||
((POL) == COMP_OutputPol_Inverted))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the hysteresis level */
|
||||
#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
|
||||
#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
|
||||
#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
|
||||
#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
|
||||
|
||||
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Low) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Mode
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the power consumption values */
|
||||
#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
|
||||
#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
|
||||
#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
|
||||
#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
|
||||
|
||||
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
|
||||
((MODE) == COMP_Mode_LowPower) || \
|
||||
((MODE) == COMP_Mode_MediumSpeed) || \
|
||||
((MODE) == COMP_Mode_HighSpeed))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_WindowMode
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
|
||||
((WINDOW) == COMP_Selection_COMP4) || \
|
||||
((WINDOW) == COMP_Selection_COMP6))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the COMP configuration to the default reset state ****/
|
||||
void COMP_DeInit(uint32_t COMP_Selection);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
||||
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
|
||||
/* COMP configuration locking function ****************************************/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CRC_H
|
||||
#define __STM32F30x_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_ReverseInputData
|
||||
* @{
|
||||
*/
|
||||
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
|
||||
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
|
||||
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
|
||||
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
|
||||
|
||||
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
|
||||
((DATA) == CRC_ReverseInputData_8bits) || \
|
||||
((DATA) == CRC_ReverseInputData_16bits) || \
|
||||
((DATA) == CRC_ReverseInputData_32bits))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_PolynomialSize
|
||||
* @{
|
||||
*/
|
||||
#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
|
||||
|
||||
#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
|
||||
((SIZE) == CRC_PolSize_8) || \
|
||||
((SIZE) == CRC_PolSize_16) || \
|
||||
((SIZE) == CRC_PolSize_32))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Configuration of the CRC computation unit **********************************/
|
||||
void CRC_DeInit(void);
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue);
|
||||
void CRC_SetPolynomial(uint32_t CRC_Pol);
|
||||
|
||||
/* CRC computation ************************************************************/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
|
||||
/* Independent register (IDR) access (write/read) *****************************/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DAC_H
|
||||
#define __STM32F30x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
|
||||
the DAC channel output switch is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_buffer_switch */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
|
||||
((PERIPH) == DAC2))
|
||||
|
||||
#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
|
||||
#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
|
||||
((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_buffer_switch
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
|
||||
#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
|
||||
((STATE) == DAC_BufferSwitch_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(DAC_TypeDef* DACx);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DBGMCU_H
|
||||
#define __STM32F30x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
|
||||
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xBD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM20_STOP ((uint32_t)0x00000020)
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFC0) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Device and Revision ID management functions ********************************/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
|
||||
/* Peripherals Configuration functions ****************************************/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,436 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DMA_H
|
||||
#define __STM32F30x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_PeripheralDST DMA_CCR_DIR
|
||||
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
|
||||
((DIR) == DMA_DIR_PeripheralDST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralInc_Enable DMA_CCR_PINC
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
|
||||
((STATE) == DMA_PeripheralInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryInc_Enable DMA_CCR_MINC
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
|
||||
((STATE) == DMA_MemoryInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
|
||||
#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
|
||||
#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular DMA_CCR_CIRC
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh DMA_CCR_PL
|
||||
#define DMA_Priority_High DMA_CCR_PL_1
|
||||
#define DMA_Priority_Medium DMA_CCR_PL_0
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_M2M_Enable DMA_CCR_MEM2MEM
|
||||
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state ******/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
|
||||
/* Data Counter functions******************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the EXTI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_EXTI_H
|
||||
#define __STM32F30x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
|
||||
Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
|
||||
Connected to the RTC Alarm
|
||||
event */
|
||||
#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
|
||||
Connected to the USB Device
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
|
||||
Connected to the RTC Tamper
|
||||
and Time Stamp events */
|
||||
#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
|
||||
Connected to the RTC wakeup
|
||||
event */
|
||||
#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
|
||||
Connected to the Comparator 1
|
||||
event */
|
||||
#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
|
||||
Connected to the Comparator 2
|
||||
event */
|
||||
#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
|
||||
Connected to the I2C1 wakeup
|
||||
event */
|
||||
#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
|
||||
Connected to the I2C2 wakeup
|
||||
event */
|
||||
#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
|
||||
Connected to the USART1 wakeup
|
||||
event */
|
||||
#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
|
||||
Connected to the USART2 wakeup
|
||||
event */
|
||||
#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
|
||||
reserved */
|
||||
#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
|
||||
Connected to the USART3 wakeup
|
||||
event */
|
||||
#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
|
||||
Connected to the Comparator 3
|
||||
event */
|
||||
#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
|
||||
Connected to the Comparator 4
|
||||
event */
|
||||
#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
|
||||
Connected to the Comparator 5
|
||||
event */
|
||||
#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
|
||||
Connected to the Comparator 6
|
||||
event */
|
||||
#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
|
||||
Connected to the Comparator 7
|
||||
event */
|
||||
#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
|
||||
Connected to the USART4 wakeup
|
||||
event */
|
||||
#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
|
||||
Connected to the USART5 wakeup
|
||||
event */
|
||||
|
||||
#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
|
||||
#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
|
||||
((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
|
||||
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
|
||||
((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
|
||||
((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_FLASH_H
|
||||
#define __STM32F30x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_DATA_ADDRESS
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
|
||||
#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
|
||||
|
||||
#ifdef STM32F303xE
|
||||
#define OB_WRP_Pages62to263 ((uint32_t)0x80000000) /* Write protection of page 62 to 263 */
|
||||
#else
|
||||
#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F303xE */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Protection Level
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_BOOT1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Timeout_definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_Launch(void);
|
||||
FLASH_Status FLASH_OB_Erase(void);
|
||||
FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
|
||||
FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
|
||||
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
|
||||
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,722 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_fmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the FMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_FMC_H
|
||||
#define __STM32F30x_FMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 1 and 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 1 and 255.
|
||||
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 15.
|
||||
@note This parameter is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 2 and 16.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 2 and 17 in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FMC_Access_Mode */
|
||||
}FMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FMC_Memory_Type */
|
||||
|
||||
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
|
||||
|
||||
uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wrap_Mode */
|
||||
|
||||
uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Timing */
|
||||
|
||||
uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
|
||||
This parameter can be a value of @ref FMC_Write_Operation */
|
||||
|
||||
uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Signal */
|
||||
|
||||
uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FMC_Extended_Mode */
|
||||
|
||||
uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FMC_AsynchronousWait */
|
||||
|
||||
uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FMC_Write_Burst */
|
||||
|
||||
|
||||
FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
|
||||
|
||||
FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
|
||||
}FMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FMC NAND and PCCARD Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 255.*/
|
||||
|
||||
uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command de-assertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0 and 255 */
|
||||
}FMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NAND Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FMC_NAND_Bank */
|
||||
|
||||
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FMC_Wait_feature */
|
||||
|
||||
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FMC_NAND_Data_Width */
|
||||
|
||||
uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FMC_ECC */
|
||||
|
||||
uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 255. */
|
||||
|
||||
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
|
||||
}FMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FMC_Wait_feature */
|
||||
|
||||
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 255. */
|
||||
|
||||
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
|
||||
|
||||
FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
|
||||
}FMC_PCCARDInitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
|
||||
#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FMC_Bank1_NORSRAM4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FMC_NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FMC_DataAddressMux_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FMC_MemoryType_NOR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NORSRAM_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
|
||||
#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FMC_AsynchronousWait_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
|
||||
#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FMC_WaitSignalPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
|
||||
#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
|
||||
((MODE) == FMC_WrapMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
|
||||
#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FMC_WriteOperation_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
|
||||
#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FMC_ExtendedMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
|
||||
((BURST) == FMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Continous_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
|
||||
#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
|
||||
|
||||
#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
|
||||
((CCLOCK) == FMC_CClock_SyncAsync))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
|
||||
#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
|
||||
((MODE) == FMC_AccessMode_B) || \
|
||||
((MODE) == FMC_AccessMode_C) || \
|
||||
((MODE) == FMC_AccessMode_D))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FMC_Waitfeature_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_NAND_Data_Width
|
||||
* @{
|
||||
*/
|
||||
#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
|
||||
#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_ECC
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
|
||||
((STATE) == FMC_ECC_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
|
||||
#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FMC_ECCPageSize_8192Bytes))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
|
||||
#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
|
||||
((IT) == FMC_IT_Level) || \
|
||||
((IT) == FMC_IT_FallingEdge))
|
||||
|
||||
#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND) || \
|
||||
((BANK) == FMC_Bank4_PCCARD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMC_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FMC_FLAG_Level) || \
|
||||
((FLAG) == FMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
|
||||
((BANK) == FMC_Bank3_NAND) || \
|
||||
((BANK) == FMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* NOR/SRAM Controller functions **********************************************/
|
||||
void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
|
||||
void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
|
||||
void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
|
||||
void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
|
||||
/* NAND Controller functions **************************************************/
|
||||
void FMC_NANDDeInit(uint32_t FMC_Bank);
|
||||
void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
|
||||
void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
|
||||
void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
|
||||
uint32_t FMC_GetECC(uint32_t FMC_Bank);
|
||||
|
||||
/* PCCARD Controller functions ************************************************/
|
||||
void FMC_PCCARDDeInit(void);
|
||||
void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
|
||||
void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
|
||||
void FMC_PCCARDCmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
|
||||
FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
|
||||
void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
|
||||
ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
|
||||
void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_FMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_GPIO_H
|
||||
#define __STM32F30x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH))
|
||||
|
||||
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC)|| \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOF))
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
|
||||
GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
|
||||
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
|
||||
((SPEED) == GPIO_Speed_Level_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
|
||||
MCO, NJTRST, TRACED, TRACECK */
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
|
||||
USART1, USART2, USART3 */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
|
||||
COMP5_OUT, COMP6_OUT */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
|
||||
((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
|
||||
((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
|
||||
((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
|
||||
((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
|
||||
((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
|
||||
((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
|
||||
((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Speed_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
|
||||
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the GPIO configuration to the default reset state *****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,477 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.3
|
||||
* @date 10-July-2015
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_I2C_H
|
||||
#define __STM32F30x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual*/
|
||||
|
||||
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_Analog_Filter */
|
||||
|
||||
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between 0x00 and 0x0F */
|
||||
|
||||
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter can be a 7-bit or 10-bit address */
|
||||
|
||||
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
|
||||
/** @defgroup I2C_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
|
||||
((FILTER) == I2C_AnalogFilter_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint32_t)0x00000000)
|
||||
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
|
||||
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
|
||||
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_Ack_Disable I2C_CR2_NACK
|
||||
|
||||
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
|
||||
((ACK) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
|
||||
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
|
||||
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
|
||||
#define I2C_Direction_Receiver ((uint16_t)0x0400)
|
||||
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
|
||||
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
|
||||
|
||||
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_slave_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_own_address2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NoMask ((uint8_t)0x00)
|
||||
#define I2C_OA2_Mask01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_Mask02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_Mask03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_Mask04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_Mask05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_Mask06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_Mask07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
|
||||
((MASK) == I2C_OA2_Mask01) || \
|
||||
((MASK) == I2C_OA2_Mask02) || \
|
||||
((MASK) == I2C_OA2_Mask03) || \
|
||||
((MASK) == I2C_OA2_Mask04) || \
|
||||
((MASK) == I2C_OA2_Mask05) || \
|
||||
((MASK) == I2C_OA2_Mask06) || \
|
||||
((MASK) == I2C_OA2_Mask07))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_TIMINGR ((uint8_t)0x10)
|
||||
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
|
||||
#define I2C_Register_ISR ((uint8_t)0x18)
|
||||
#define I2C_Register_ICR ((uint8_t)0x1C)
|
||||
#define I2C_Register_PECR ((uint8_t)0x20)
|
||||
#define I2C_Register_RXDR ((uint8_t)0x24)
|
||||
#define I2C_Register_TXDR ((uint8_t)0x28)
|
||||
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_TIMINGR) || \
|
||||
((REGISTER) == I2C_Register_TIMEOUTR) || \
|
||||
((REGISTER) == I2C_Register_ISR) || \
|
||||
((REGISTER) == I2C_Register_ICR) || \
|
||||
((REGISTER) == I2C_Register_PECR) || \
|
||||
((REGISTER) == I2C_Register_RXDR) || \
|
||||
((REGISTER) == I2C_Register_TXDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_NACKF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
|
||||
((FLAG) == I2C_FLAG_BUSY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_TXIS I2C_ISR_TXIS
|
||||
#define I2C_IT_RXNE I2C_ISR_RXNE
|
||||
#define I2C_IT_ADDR I2C_ISR_ADDR
|
||||
#define I2C_IT_NACKF I2C_ISR_NACKF
|
||||
#define I2C_IT_STOPF I2C_ISR_STOPF
|
||||
#define I2C_IT_TC I2C_ISR_TC
|
||||
#define I2C_IT_TCR I2C_ISR_TCR
|
||||
#define I2C_IT_BERR I2C_ISR_BERR
|
||||
#define I2C_IT_ARLO I2C_ISR_ARLO
|
||||
#define I2C_IT_OVR I2C_ISR_OVR
|
||||
#define I2C_IT_PECERR I2C_ISR_PECERR
|
||||
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_IT_ALERT I2C_ISR_ALERT
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
|
||||
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
|
||||
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
|
||||
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Reload_Mode I2C_CR2_RELOAD
|
||||
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
|
||||
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
|
||||
|
||||
|
||||
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
|
||||
((MODE) == I2C_AutoEnd_Mode) || \
|
||||
((MODE) == I2C_SoftEnd_Mode))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_No_StartStop ((uint32_t)0x00000000)
|
||||
#define I2C_Generate_Stop I2C_CR2_STOP
|
||||
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_Generate_Start_Write I2C_CR2_START
|
||||
|
||||
|
||||
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
|
||||
((MODE) == I2C_Generate_Start_Read) || \
|
||||
((MODE) == I2C_Generate_Start_Write) || \
|
||||
((MODE) == I2C_No_StartStop))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
|
||||
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Communications handling functions ******************************************/
|
||||
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
|
||||
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
|
||||
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
|
||||
|
||||
/* SMBUS management functions ************************************************/
|
||||
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* I2C registers management functions *****************************************/
|
||||
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
|
||||
/* Data transfers management functions ****************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue