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Refs #139. Updated Rowley Crossworks projects to version 3.7.6 of the tool. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@224 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2017-05-03 10:57:12 +00:00
parent 34030310d1
commit 4562bc4280
303 changed files with 25167 additions and 174027 deletions
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BIN
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.elf
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Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.map
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Archive member included because of file (symbol)
C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a(libc_asm.o)
ARM Flash Debug/../../obj/can.o (__divsi3)
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Memory Configuration
Name Origin Length Attributes
UNPLACED_SECTIONS 0xffffffff 0x00000000 xw
AHB_Peripherals 0xffe00000 0x00200000 xw
VPB_Peripherals 0xe0000000 0x00200000 xw
BANK3 0x83000000 0x01000000 xw
BANK2 0x82000000 0x01000000 xw
External_SRAM 0x81000000 0x00100000 xw
External_FLASH 0x80000000 0x00400000 xr
SRAM 0x40000200 0x00001ce0 xw
FLASH 0x00000000 0x00002000 xr
*default* 0x00000000 0xffffffff
Linker script and memory map
0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000
0x00000000 __AHB_Peripherals_segment_end__ = 0x0
0xe0000000 __VPB_Peripherals_segment_start__ = 0xe0000000
0xe0200000 __VPB_Peripherals_segment_end__ = 0xe0200000
0x83000000 __BANK3_segment_start__ = 0x83000000
0x84000000 __BANK3_segment_end__ = 0x84000000
0x82000000 __BANK2_segment_start__ = 0x82000000
0x83000000 __BANK2_segment_end__ = 0x83000000
0x81000000 __External_SRAM_segment_start__ = 0x81000000
0x81100000 __External_SRAM_segment_end__ = 0x81100000
0x80000000 __External_FLASH_segment_start__ = 0x80000000
0x80400000 __External_FLASH_segment_end__ = 0x80400000
0x40000200 __SRAM_segment_start__ = 0x40000200
0x40001ee0 __SRAM_segment_end__ = 0x40001ee0
0x00000000 __FLASH_segment_start__ = 0x0
0x00002000 __FLASH_segment_end__ = 0x2000
0x00000400 __STACKSIZE__ = 0x400
0x00000100 __STACKSIZE_IRQ__ = 0x100
0x00000100 __STACKSIZE_FIQ__ = 0x100
0x00000000 __STACKSIZE_SVC__ = 0x0
0x00000000 __STACKSIZE_ABT__ = 0x0
0x00000000 __STACKSIZE_UND__ = 0x0
0x00000400 __HEAPSIZE__ = 0x400
0x80000000 __text2_load_start__ = ALIGN (__External_FLASH_segment_start__, 0x4)
.text2 0x80000000 0x0
0x80000000 __text2_start__ = .
*(.text2 .text2.*)
0x80000000 __text2_end__ = (__text2_start__ + SIZEOF (.text2))
0x80000000 __text2_load_end__ = __text2_end__
0x00000001 . = ASSERT (((__text2_end__ >= __External_FLASH_segment_start__) && (__text2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .text2 is too large to fit in External_FLASH memory segment)
0x80000000 __rodata2_load_start__ = ALIGN (__text2_end__, 0x4)
.rodata2 0x80000000 0x0
0x80000000 __rodata2_start__ = .
*(.rodata2 .rodata2.*)
0x80000000 __rodata2_end__ = (__rodata2_start__ + SIZEOF (.rodata2))
0x80000000 __rodata2_load_end__ = __rodata2_end__
0x00000001 . = ASSERT (((__rodata2_end__ >= __External_FLASH_segment_start__) && (__rodata2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .rodata2 is too large to fit in External_FLASH memory segment)
0x80000000 __data2_load_start__ = ALIGN (__rodata2_end__, 0x4)
.data2 0x81000000 0x0 load address 0x80000000
0x81000000 __data2_start__ = .
*(.data2 .data2.*)
0x81000000 __data2_end__ = (__data2_start__ + SIZEOF (.data2))
0x80000000 __data2_load_end__ = (__data2_load_start__ + SIZEOF (.data2))
0x80000000 __External_FLASH_segment_used_end__ = (ALIGN (__rodata2_end__, 0x4) + SIZEOF (.data2))
0x00000001 . = ASSERT ((((__data2_load_start__ + SIZEOF (.data2)) >= __External_FLASH_segment_start__) && ((__data2_load_start__ + SIZEOF (.data2)) <= (__External_FLASH_segment_start__ + 0x400000))), error: .data2 is too large to fit in External_FLASH memory segment)
.data2_run 0x81000000 0x0
0x81000000 __data2_run_start__ = .
0x81000000 . = MAX ((__data2_run_start__ + SIZEOF (.data2)), .)
0x81000000 __data2_run_end__ = (__data2_run_start__ + SIZEOF (.data2_run))
0x81000000 __data2_run_load_end__ = __data2_run_end__
0x00000001 . = ASSERT (((__data2_run_end__ >= __External_SRAM_segment_start__) && (__data2_run_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .data2_run is too large to fit in External_SRAM memory segment)
0x81000000 __bss2_load_start__ = ALIGN (__data2_run_end__, 0x4)
.bss2 0x81000000 0x0
0x81000000 __bss2_start__ = .
*(.bss2 .bss2.*)
0x81000000 __bss2_end__ = (__bss2_start__ + SIZEOF (.bss2))
0x81000000 __bss2_load_end__ = __bss2_end__
0x81000000 __External_SRAM_segment_used_end__ = (ALIGN (__data2_run_end__, 0x4) + SIZEOF (.bss2))
0x00000001 . = ASSERT (((__bss2_end__ >= __External_SRAM_segment_start__) && (__bss2_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .bss2 is too large to fit in External_SRAM memory segment)
0x40000200 __vectors_ram_load_start__ = __SRAM_segment_start__
.vectors_ram 0x40000200 0x3c
0x40000200 __vectors_ram_start__ = .
*(.vectors_ram .vectors_ram.*)
0x4000023c . = MAX ((__vectors_ram_start__ + 0x3c), .)
*fill* 0x40000200 0x3c 00
0x4000023c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram))
0x4000023c __vectors_ram_load_end__ = __vectors_ram_end__
0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .vectors_ram is too large to fit in SRAM memory segment)
0x00000000 __vectors_load_start__ = __FLASH_segment_start__
.vectors 0x00000000 0x34
0x00000000 __vectors_start__ = .
*(.vectors .vectors.*)
.vectors 0x00000000 0x34 ARM Flash Debug/../../obj/cstart.o
0x00000000 _vectors
0x00000034 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors))
0x00000034 __vectors_load_end__ = __vectors_end__
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .vectors is too large to fit in FLASH memory segment)
0x00000034 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
.init 0x00000034 0x20c
0x00000034 __init_start__ = .
*(.init .init.*)
*fill* 0x00000034 0xc 00
.init 0x00000040 0x200 ARM Flash Debug/../../obj/cstart.o
0x00000040 __start
0x00000040 Reset_Handler
0x00000158 exit
0x000001b4 undef_handler
0x000001b8 pabort_handler
0x000001bc dabort_handler
0x000001c0 fiq_handler
0x000001c4 irq_handler
0x00000240 __init_end__ = (__init_start__ + SIZEOF (.init))
0x00000240 __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .init is too large to fit in FLASH memory segment)
0x00000240 __text_load_start__ = ALIGN (__init_end__, 0x4)
.text 0x00000240 0x19f0
0x00000240 __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
.glue_7 0x00000000 0x0 linker stubs
.glue_7t 0x00000000 0x0 linker stubs
.text.main 0x00000240 0xa4 ARM Flash Debug/../../obj/main.o
0x00000240 main
.text.FlashGetSector
0x000002e4 0x64 ARM Flash Debug/../../obj/flash.o
.text.FlashWriteBlock
0x00000348 0x110 ARM Flash Debug/../../obj/flash.o
.text.FlashInitBlock
0x00000458 0x38 ARM Flash Debug/../../obj/flash.o
.text.FlashSwitchBlock
0x00000490 0x6c ARM Flash Debug/../../obj/flash.o
.text.FlashAddToBlock
0x000004fc 0xcc ARM Flash Debug/../../obj/flash.o
.text.FlashInit
0x000005c8 0x20 ARM Flash Debug/../../obj/flash.o
0x000005c8 FlashInit
.text.FlashWrite
0x000005e8 0x68 ARM Flash Debug/../../obj/flash.o
0x000005e8 FlashWrite
.text.FlashErase
0x00000650 0x130 ARM Flash Debug/../../obj/flash.o
0x00000650 FlashErase
.text.FlashWriteChecksum
0x00000780 0x80 ARM Flash Debug/../../obj/flash.o
0x00000780 FlashWriteChecksum
.text.FlashVerifyChecksum
0x00000800 0x48 ARM Flash Debug/../../obj/flash.o
0x00000800 FlashVerifyChecksum
.text.FlashDone
0x00000848 0x5c ARM Flash Debug/../../obj/flash.o
0x00000848 FlashDone
.text.FlashGetUserProgBaseAddress
0x000008a4 0x8 ARM Flash Debug/../../obj/flash.o
0x000008a4 FlashGetUserProgBaseAddress
.text.IrqGetCPSR
0x000008ac 0x8 ARM Flash Debug/../../obj/cpu_comp.o
.text.IrqSetCPSR
0x000008b4 0x8 ARM Flash Debug/../../obj/cpu_comp.o
.text.CpuIrqDisable
0x000008bc 0x18 ARM Flash Debug/../../obj/cpu_comp.o
0x000008bc CpuIrqDisable
.text.CanInit 0x000008d4 0xf8 ARM Flash Debug/../../obj/can.o
0x000008d4 CanInit
.text.CanTransmitPacket
0x000009cc 0xbc ARM Flash Debug/../../obj/can.o
0x000009cc CanTransmitPacket
.text.CanReceivePacket
0x00000a88 0xa4 ARM Flash Debug/../../obj/can.o
0x00000a88 CanReceivePacket
.text.CpuInit 0x00000b2c 0x10 ARM Flash Debug/../../obj/cpu.o
0x00000b2c CpuInit
.text.CpuMemCopy
0x00000b3c 0x44 ARM Flash Debug/../../obj/cpu.o
0x00000b3c CpuMemCopy
.text.CpuStartUserProgram
0x00000b80 0x50 ARM Flash Debug/../../obj/cpu.o
0x00000b80 CpuStartUserProgram
.text.NvmInit 0x00000bd0 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000bd0 NvmInit
.text.NvmWrite
0x00000be0 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000be0 NvmWrite
.text.NvmErase
0x00000bf0 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000bf0 NvmErase
.text.NvmVerifyChecksum
0x00000c00 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000c00 NvmVerifyChecksum
.text.NvmGetUserProgBaseAddress
0x00000c10 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000c10 NvmGetUserProgBaseAddress
.text.NvmDone 0x00000c20 0x1c ARM Flash Debug/../../obj/nvm.o
0x00000c20 NvmDone
.text.TimerInit
0x00000c3c 0x48 ARM Flash Debug/../../obj/timer.o
0x00000c3c TimerInit
.text.TimerReset
0x00000c84 0x20 ARM Flash Debug/../../obj/timer.o
0x00000c84 TimerReset
.text.TimerUpdate
0x00000ca4 0x38 ARM Flash Debug/../../obj/timer.o
0x00000ca4 TimerUpdate
.text.TimerGet
0x00000cdc 0x1c ARM Flash Debug/../../obj/timer.o
0x00000cdc TimerGet
.text.UartReceiveByte
0x00000cf8 0x28 ARM Flash Debug/../../obj/uart.o
.text.UartTransmitByte
0x00000d20 0x54 ARM Flash Debug/../../obj/uart.o
.text.UartInit
0x00000d74 0x40 ARM Flash Debug/../../obj/uart.o
0x00000d74 UartInit
.text.UartTransmitPacket
0x00000db4 0x84 ARM Flash Debug/../../obj/uart.o
0x00000db4 UartTransmitPacket
.text.UartReceivePacket
0x00000e38 0x108 ARM Flash Debug/../../obj/uart.o
0x00000e38 UartReceivePacket
.text.AssertFailure
0x00000f40 0xc ARM Flash Debug/../../obj/assert.o
0x00000f40 AssertFailure
.text.BackDoorCheck
0x00000f4c 0x54 ARM Flash Debug/../../obj/backdoor.o
0x00000f4c BackDoorCheck
.text.BackDoorInit
0x00000fa0 0x30 ARM Flash Debug/../../obj/backdoor.o
0x00000fa0 BackDoorInit
.text.BootInit
0x00000fd0 0x24 ARM Flash Debug/../../obj/boot.o
0x00000fd0 BootInit
.text.BootTask
0x00000ff4 0x1c ARM Flash Debug/../../obj/boot.o
0x00000ff4 BootTask
.text.ComInit 0x00001010 0x30 ARM Flash Debug/../../obj/com.o
0x00001010 ComInit
.text.ComTask 0x00001040 0x5c ARM Flash Debug/../../obj/com.o
0x00001040 ComTask
.text.ComFree 0x0000109c 0x4 ARM Flash Debug/../../obj/com.o
0x0000109c ComFree
.text.ComTransmitPacket
0x000010a0 0x4c ARM Flash Debug/../../obj/com.o
0x000010a0 ComTransmitPacket
.text.ComGetActiveInterfaceMaxRxLen
0x000010ec 0x38 ARM Flash Debug/../../obj/com.o
0x000010ec ComGetActiveInterfaceMaxRxLen
.text.ComGetActiveInterfaceMaxTxLen
0x00001124 0x38 ARM Flash Debug/../../obj/com.o
0x00001124 ComGetActiveInterfaceMaxTxLen
.text.ComIsConnected
0x0000115c 0x10 ARM Flash Debug/../../obj/com.o
0x0000115c ComIsConnected
.text.CopInit 0x0000116c 0x4 ARM Flash Debug/../../obj/cop.o
0x0000116c CopInit
.text.CopService
0x00001170 0x4 ARM Flash Debug/../../obj/cop.o
0x00001170 CopService
.text.XcpProtectResources
0x00001174 0x14 ARM Flash Debug/../../obj/xcp.o
.text.XcpSetCtoError
0x00001188 0x20 ARM Flash Debug/../../obj/xcp.o
.text.XcpInit 0x000011a8 0x28 ARM Flash Debug/../../obj/xcp.o
0x000011a8 XcpInit
.text.XcpIsConnected
0x000011d0 0x18 ARM Flash Debug/../../obj/xcp.o
0x000011d0 XcpIsConnected
.text.XcpPacketTransmitted
0x000011e8 0x14 ARM Flash Debug/../../obj/xcp.o
0x000011e8 XcpPacketTransmitted
.text.XcpPacketReceived
0x000011fc 0x538 ARM Flash Debug/../../obj/xcp.o
0x000011fc XcpPacketReceived
*fill* 0x00001734 0xc 00
.text.libc.__int32_div
0x00001740 0x470 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a(libc_asm.o)
0x00001740 __int32_div
0x00001740 __aeabi_idiv
0x00001740 __divsi3
0x00001a40 __aeabi_uidiv
0x00001a40 __uint32_div
0x00001a40 __udivsi3
.text.libc.__int32_mod
0x00001bb0 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a(libc_asm.o)
0x00001bb0 __modsi3
0x00001bb0 __int32_mod
.text.libc.__aeabi_idivmod
0x00001bd0 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a(libc_asm.o)
0x00001bd0 __aeabi_idivmod
0x00001c30 __text_end__ = (__text_start__ + SIZEOF (.text))
0x00001c30 __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .text is too large to fit in FLASH memory segment)
0x00001c30 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
.dtors 0x00001c30 0x0
0x00001c30 __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
0x00001c30 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
0x00001c30 __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .dtors is too large to fit in FLASH memory segment)
0x00001c30 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
.ctors 0x00001c30 0x0
0x00001c30 __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
0x00001c30 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
0x00001c30 __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .ctors is too large to fit in FLASH memory segment)
0x00001c30 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
.rodata 0x00001c30 0x250
0x00001c30 __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.flashLayout
0x00001c30 0xc0 ARM Flash Debug/../../obj/flash.o
.rodata.str1.4
0x00001cf0 0x7d ARM Flash Debug/../../obj/can.o
0x80 (size before relaxing)
*fill* 0x00001d6d 0x3 00
.rodata.canTiming
0x00001d70 0x48 ARM Flash Debug/../../obj/can.o
.rodata.str1.4
0x00001db8 0x80 ARM Flash Debug/../../obj/uart.o
.rodata.xcpStationId
0x00001e38 0x8 ARM Flash Debug/../../obj/xcp.o
.rodata.libc.__aeabi_uidiv
0x00001e40 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a(libc_asm.o)
0x00001e40 __RAL_uidiv_inverse_lut
0x00001e80 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
0x00001e80 __rodata_load_end__ = __rodata_end__
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .rodata is too large to fit in FLASH memory segment)
0x00001e80 __data_load_start__ = ALIGN (__rodata_end__, 0x4)
.data 0x4000023c 0x4 load address 0x00001e80
0x4000023c __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.comActiveInterface
0x4000023c 0x4 ARM Flash Debug/../../obj/com.o
0x40000240 __data_end__ = (__data_start__ + SIZEOF (.data))
0x00001e84 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x40000))), error: .data is too large to fit in FLASH memory segment)
.data_run 0x4000023c 0x4 load address 0x00001e80
0x4000023c __data_run_start__ = .
0x40000240 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
*fill* 0x4000023c 0x4 00
0x40000240 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
0x40000240 __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .data_run is too large to fit in SRAM memory segment)
0x40000240 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
.bss 0x40000240 0x4f4
0x40000240 __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
.bss.bootBlockInfo
0x40000240 0x204 ARM Flash Debug/../../obj/flash.o
.bss.blockInfo
0x40000444 0x204 ARM Flash Debug/../../obj/flash.o
.bss.millisecond_counter
0x40000648 0x4 ARM Flash Debug/../../obj/timer.o
.bss.free_running_counter_last
0x4000064c 0x4 ARM Flash Debug/../../obj/timer.o
.bss.xcpCtoRxLength.897
0x40000650 0x1 ARM Flash Debug/../../obj/uart.o
*fill* 0x40000651 0x3 00
.bss.xcpCtoReqPacket.896
0x40000654 0x44 ARM Flash Debug/../../obj/uart.o
.bss.xcpCtoRxInProgress.898
0x40000698 0x1 ARM Flash Debug/../../obj/uart.o
*fill* 0x40000699 0x3 00
.bss.xcpCtoRxStartTime.899
0x4000069c 0x4 ARM Flash Debug/../../obj/uart.o
.bss.backdoorOpen
0x400006a0 0x1 ARM Flash Debug/../../obj/backdoor.o
*fill* 0x400006a1 0x3 00
.bss.backdoorOpenTime
0x400006a4 0x4 ARM Flash Debug/../../obj/backdoor.o
.bss.xcpCtoReqPacket.891
0x400006a8 0x40 ARM Flash Debug/../../obj/com.o
.bss.xcpInfo 0x400006e8 0x4c ARM Flash Debug/../../obj/xcp.o
*(COMMON)
0x40000734 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
0x40000734 __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .bss is too large to fit in SRAM memory segment)
0x40000734 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
.non_init 0x40000734 0x0
0x40000734 __non_init_start__ = .
*(.non_init .non_init.*)
0x40000734 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
0x40000734 __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .non_init is too large to fit in SRAM memory segment)
0x40000734 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
.heap 0x40000734 0x400
0x40000734 __heap_start__ = .
*(.heap .heap.*)
0x40000b34 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
*fill* 0x40000734 0x400 00
0x40000b34 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
0x40000b34 __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .heap is too large to fit in SRAM memory segment)
0x40000b34 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
.stack 0x40000b34 0x400
0x40000b34 __stack_start__ = .
*(.stack .stack.*)
0x40000f34 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
*fill* 0x40000b34 0x400 00
0x40000f34 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
0x40000f34 __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack is too large to fit in SRAM memory segment)
0x40000f34 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
.stack_irq 0x40000f34 0x100
0x40000f34 __stack_irq_start__ = .
*(.stack_irq .stack_irq.*)
0x40001034 . = ALIGN (MAX ((__stack_irq_start__ + __STACKSIZE_IRQ__), .), 0x4)
*fill* 0x40000f34 0x100 00
0x40001034 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
0x40001034 __stack_irq_load_end__ = __stack_irq_end__
0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_irq is too large to fit in SRAM memory segment)
0x40001034 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
.stack_fiq 0x40001034 0x100
0x40001034 __stack_fiq_start__ = .
*(.stack_fiq .stack_fiq.*)
0x40001134 . = ALIGN (MAX ((__stack_fiq_start__ + __STACKSIZE_FIQ__), .), 0x4)
*fill* 0x40001034 0x100 00
0x40001134 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
0x40001134 __stack_fiq_load_end__ = __stack_fiq_end__
0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_fiq is too large to fit in SRAM memory segment)
0x40001134 __stack_svc_load_start__ = ALIGN (__stack_fiq_end__, 0x4)
.stack_svc 0x40001134 0x0
0x40001134 __stack_svc_start__ = .
*(.stack_svc .stack_svc.*)
0x40001134 . = ALIGN (MAX ((__stack_svc_start__ + __STACKSIZE_SVC__), .), 0x4)
0x40001134 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
0x40001134 __stack_svc_load_end__ = __stack_svc_end__
0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_svc is too large to fit in SRAM memory segment)
0x40001134 __stack_abt_load_start__ = ALIGN (__stack_svc_end__, 0x4)
.stack_abt 0x40001134 0x0
0x40001134 __stack_abt_start__ = .
*(.stack_abt .stack_abt.*)
0x40001134 . = ALIGN (MAX ((__stack_abt_start__ + __STACKSIZE_ABT__), .), 0x4)
0x40001134 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
0x40001134 __stack_abt_load_end__ = __stack_abt_end__
0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_abt is too large to fit in SRAM memory segment)
0x40001134 __stack_und_load_start__ = ALIGN (__stack_abt_end__, 0x4)
.stack_und 0x40001134 0x0
0x40001134 __stack_und_start__ = .
*(.stack_und .stack_und.*)
0x40001134 . = ALIGN (MAX ((__stack_und_start__ + __STACKSIZE_UND__), .), 0x4)
0x40001134 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
0x40001134 __stack_und_load_end__ = __stack_und_end__
0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_und is too large to fit in SRAM memory segment)
0x00001e84 __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
.fast 0x40001134 0x0 load address 0x00001e84
0x40001134 __fast_start__ = .
*(.fast .fast.*)
0x40001134 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
0x00001e84 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00001e84 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.fast))
0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x40000))), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x40001134 0x0
0x40001134 __fast_run_start__ = .
0x40001134 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
0x40001134 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x40001134 __fast_run_load_end__ = __fast_run_end__
0x40001134 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .fast_run is too large to fit in SRAM memory segment)
START GROUP
LOAD ARM Flash Debug/../../obj/hooks.o
LOAD ARM Flash Debug/../../obj/main.o
LOAD ARM Flash Debug/../../obj/extflash.o
LOAD ARM Flash Debug/../../obj/cstart.o
LOAD ARM Flash Debug/../../obj/flash.o
LOAD ARM Flash Debug/../../obj/cpu_comp.o
LOAD ARM Flash Debug/../../obj/can.o
LOAD ARM Flash Debug/../../obj/cpu.o
LOAD ARM Flash Debug/../../obj/nvm.o
LOAD ARM Flash Debug/../../obj/timer.o
LOAD ARM Flash Debug/../../obj/uart.o
LOAD ARM Flash Debug/../../obj/assert.o
LOAD ARM Flash Debug/../../obj/backdoor.o
LOAD ARM Flash Debug/../../obj/boot.o
LOAD ARM Flash Debug/../../obj/com.o
LOAD ARM Flash Debug/../../obj/cop.o
LOAD ARM Flash Debug/../../obj/xcp.o
LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libarm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v4t_a_le.a
END GROUP
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/../bin/openblt_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
.debug_info 0x00000000 0x1b23
.debug_info 0x00000000 0x5a ARM Flash Debug/../../obj/hooks.o
.debug_info 0x0000005a 0x116 ARM Flash Debug/../../obj/main.o
.debug_info 0x00000170 0x5a ARM Flash Debug/../../obj/extflash.o
.debug_info 0x000001ca 0x106 ARM Flash Debug/../../obj/cstart.o
.debug_info 0x000002d0 0x54c ARM Flash Debug/../../obj/flash.o
.debug_info 0x0000081c 0x105 ARM Flash Debug/../../obj/cpu_comp.o
.debug_info 0x00000921 0x201 ARM Flash Debug/../../obj/can.o
.debug_info 0x00000b22 0x14f ARM Flash Debug/../../obj/cpu.o
.debug_info 0x00000c71 0x177 ARM Flash Debug/../../obj/nvm.o
.debug_info 0x00000de8 0xf2 ARM Flash Debug/../../obj/timer.o
.debug_info 0x00000eda 0x1e1 ARM Flash Debug/../../obj/uart.o
.debug_info 0x000010bb 0xb2 ARM Flash Debug/../../obj/assert.o
.debug_info 0x0000116d 0xc0 ARM Flash Debug/../../obj/backdoor.o
.debug_info 0x0000122d 0x88 ARM Flash Debug/../../obj/boot.o
.debug_info 0x000012b5 0x1d6 ARM Flash Debug/../../obj/com.o
.debug_info 0x0000148b 0x86 ARM Flash Debug/../../obj/cop.o
.debug_info 0x00001511 0x612 ARM Flash Debug/../../obj/xcp.o
.debug_abbrev 0x00000000 0xc7a
.debug_abbrev 0x00000000 0x28 ARM Flash Debug/../../obj/hooks.o
.debug_abbrev 0x00000028 0xc5 ARM Flash Debug/../../obj/main.o
.debug_abbrev 0x000000ed 0x28 ARM Flash Debug/../../obj/extflash.o
.debug_abbrev 0x00000115 0x12 ARM Flash Debug/../../obj/cstart.o
.debug_abbrev 0x00000127 0x227 ARM Flash Debug/../../obj/flash.o
.debug_abbrev 0x0000034e 0xbc ARM Flash Debug/../../obj/cpu_comp.o
.debug_abbrev 0x0000040a 0x164 ARM Flash Debug/../../obj/can.o
.debug_abbrev 0x0000056e 0xaf ARM Flash Debug/../../obj/cpu.o
.debug_abbrev 0x0000061d 0xa3 ARM Flash Debug/../../obj/nvm.o
.debug_abbrev 0x000006c0 0x89 ARM Flash Debug/../../obj/timer.o
.debug_abbrev 0x00000749 0x11f ARM Flash Debug/../../obj/uart.o
.debug_abbrev 0x00000868 0x66 ARM Flash Debug/../../obj/assert.o
.debug_abbrev 0x000008ce 0x5b ARM Flash Debug/../../obj/backdoor.o
.debug_abbrev 0x00000929 0x3f ARM Flash Debug/../../obj/boot.o
.debug_abbrev 0x00000968 0x115 ARM Flash Debug/../../obj/com.o
.debug_abbrev 0x00000a7d 0x3f ARM Flash Debug/../../obj/cop.o
.debug_abbrev 0x00000abc 0x1be ARM Flash Debug/../../obj/xcp.o
.debug_line 0x00000000 0x1463
.debug_line 0x00000000 0x1d ARM Flash Debug/../../obj/hooks.o
.debug_line 0x0000001d 0x12f ARM Flash Debug/../../obj/main.o
.debug_line 0x0000014c 0x1d ARM Flash Debug/../../obj/extflash.o
.debug_line 0x00000169 0x13f ARM Flash Debug/../../obj/cstart.o
.debug_line 0x000002a8 0x2dd ARM Flash Debug/../../obj/flash.o
.debug_line 0x00000585 0x177 ARM Flash Debug/../../obj/cpu_comp.o
.debug_line 0x000006fc 0x11d ARM Flash Debug/../../obj/can.o
.debug_line 0x00000819 0x106 ARM Flash Debug/../../obj/cpu.o
.debug_line 0x0000091f 0x11e ARM Flash Debug/../../obj/nvm.o
.debug_line 0x00000a3d 0xfc ARM Flash Debug/../../obj/timer.o
.debug_line 0x00000b39 0x163 ARM Flash Debug/../../obj/uart.o
.debug_line 0x00000c9c 0x129 ARM Flash Debug/../../obj/assert.o
.debug_line 0x00000dc5 0x147 ARM Flash Debug/../../obj/backdoor.o
.debug_line 0x00000f0c 0xbc ARM Flash Debug/../../obj/boot.o
.debug_line 0x00000fc8 0x1c2 ARM Flash Debug/../../obj/com.o
.debug_line 0x0000118a 0xb0 ARM Flash Debug/../../obj/cop.o
.debug_line 0x0000123a 0x229 ARM Flash Debug/../../obj/xcp.o
.debug_str 0x00000000 0xfc6
.debug_str 0x00000000 0xe8 ARM Flash Debug/../../obj/hooks.o
0x106 (size before relaxing)
.debug_str 0x000000e8 0x9e ARM Flash Debug/../../obj/main.o
0x147 (size before relaxing)
.debug_str 0x00000186 0x65 ARM Flash Debug/../../obj/extflash.o
0x109 (size before relaxing)
.debug_str 0x000001eb 0x258 ARM Flash Debug/../../obj/flash.o
0x320 (size before relaxing)
.debug_str 0x00000443 0xcb ARM Flash Debug/../../obj/cpu_comp.o
0x17a (size before relaxing)
.debug_str 0x0000050e 0x117 ARM Flash Debug/../../obj/can.o
0x1e5 (size before relaxing)
.debug_str 0x00000625 0xc9 ARM Flash Debug/../../obj/cpu.o
0x196 (size before relaxing)
.debug_str 0x000006ee 0xcb ARM Flash Debug/../../obj/nvm.o
0x1a0 (size before relaxing)
.debug_str 0x000007b9 0xf0 ARM Flash Debug/../../obj/timer.o
0x19f (size before relaxing)
.debug_str 0x000008a9 0x12b ARM Flash Debug/../../obj/uart.o
0x204 (size before relaxing)
.debug_str 0x000009d4 0x94 ARM Flash Debug/../../obj/assert.o
0x143 (size before relaxing)
.debug_str 0x00000a68 0xae ARM Flash Debug/../../obj/backdoor.o
0x166 (size before relaxing)
.debug_str 0x00000b16 0x83 ARM Flash Debug/../../obj/boot.o
0x127 (size before relaxing)
.debug_str 0x00000b99 0x142 ARM Flash Debug/../../obj/com.o
0x220 (size before relaxing)
.debug_str 0x00000cdb 0x83 ARM Flash Debug/../../obj/cop.o
0x127 (size before relaxing)
.debug_str 0x00000d5e 0x268 ARM Flash Debug/../../obj/xcp.o
0x349 (size before relaxing)
.comment 0x00000000 0x4e
.comment 0x00000000 0x4e ARM Flash Debug/../../obj/hooks.o
0x4f (size before relaxing)
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/main.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/extflash.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/flash.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/cpu_comp.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/can.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/cpu.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/nvm.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/timer.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/uart.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/assert.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/backdoor.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/boot.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/com.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/cop.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/xcp.o
.ARM.attributes
0x00000000 0x10
.ARM.attributes
0x00000000 0x10 ARM Flash Debug/../../obj/hooks.o
.ARM.attributes
0x00000010 0x10 ARM Flash Debug/../../obj/main.o
.ARM.attributes
0x00000020 0x10 ARM Flash Debug/../../obj/extflash.o
.ARM.attributes
0x00000030 0x10 ARM Flash Debug/../../obj/cstart.o
.ARM.attributes
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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_UART_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_UART_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_UART_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_UART_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_UART_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (256)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (0)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

7
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/boot.dox
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/**
\defgroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks Bootloader
\brief Bootloader.
\ingroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
*/

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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\extflash.c
* \brief Bootloader external flash driver source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Value for an invalid flash sector. */
#define FLASH_INVALID_SECTOR (0xff)
/** \brief Value for an invalid flash address. */
#define FLASH_INVALID_ADDRESS (0xffffffff)
/** \brief Standard size of a flash block for writing. */
#define FLASH_WRITE_BLOCK_SIZE (512)
/** \brief Total numbers of sectors in array flashLayout[]. */
#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
/** \brief C3 Intel flash read array command. */
#define FLASH_CMD_READ_ARRAY_MODE (0xFF)
/** \brief C3 Intel flash read id command. */
#define FLASH_CMD_READ_ID_MODE (0x90)
/** \brief C3 Intel flash erase command. */
#define FLASH_CMD_ERASE_MODE (0x20)
/** \brief C3 Intel flash read status command. */
#define FLASH_CMD_READ_STATUS_MODE (0x70)
/** \brief C3 Intel flash change lock command. */
#define FLASH_CMD_CHANGE_LOCK_MODE (0x60)
/** \brief C3 Intel flash unlock sector command. */
#define FLASH_CMD_UNLOCK_SECTOR (0xD0)
/** \brief C3 Intel flash lock sector command. */
#define FLASH_CMD_LOCK_SECTOR (0x01)
/** \brief C3 Intel flash program command. */
#define FLASH_CMD_PROGRAM_MODE (0x40)
/** \brief C3 Intel flash erase confirm command. */
#define FLASH_CMD_ERASE_CONFIRM (0xD0)
/** \brief C3 Intel flash clear status command. */
#define FLASH_CMD_CLEAR_STATUS (0x50)
/** \brief C3 Intel flash lock bit. */
#define FLASH_LOCK_BIT (0x01)
/** \brief C3 Intel flash status ready bit. */
#define FLASH_STATUS_READY_BIT (0x80)
/** \brief C3 Intel flash locked error code. */
#define FLASH_ERR_LOCKED (0x02)
/** \brief C3 Intel flash Vpp range error code. */
#define FLASH_ERR_VPP_RANGE (0x08)
/** \brief C3 Intel flash program error code. */
#define FLASH_ERR_PROGRAM (0x10)
/** \brief C3 Intel flash command sequence error code. */
#define FLASH_ERR_CMD_SEQ (0x10)
/** \brief C3 Intel flash erase error code. */
#define FLASH_ERR_ERASE (0x20)
/** \brief Flash erase timeout value. */
#define FLASH_ERASE_TIMEOUT ((blt_int32u)5000000)
/** \brief Flash program timeout value. */
#define FLASH_PROGRAM_TIMEOUT ((blt_int32u)1000000)
/** \brief Supported Intel C3 flash manufacturer ID. */
#define FLASH_DEV_MAN_ID ((blt_int16u)0x0089)
/** \brief Supported Intel C3 flash device ID. */
#define FLASH_DEV_ID ((blt_int16u)0x88c3)
/** \brief Offset for reading manufacturer ID. */
#define FLASH_DEVINFO_MAN_ID ((blt_int16u)0x0000)
/** \brief Offset for reading device ID. */
#define FLASH_DEVINFO_DEV_ID ((blt_int16u)0x0001)
/** \brief Offset for reading lock status. */
#define FLASH_DEVINFO_LOCK_STATUS ((blt_int16u)0x0002)
/** \brief Runtime efficient macro for obtaining the manufacturer ID. */
#define ExtFlashGetManID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
FLASH_DEVINFO_MAN_ID))
/** \brief Runtime efficient macro for obtaining the device ID. */
#define ExtFlashGetDevID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
FLASH_DEVINFO_DEV_ID))
/** \brief Runtime efficient macro for obtaining the lock status. */
#define ExtFlashGetLockStatus(base) (ExtFlashGetDeviceInfo(base, \
FLASH_DEVINFO_LOCK_STATUS))
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Flash sector descriptor type. */
typedef struct
{
blt_addr sector_start; /**< sector start address */
blt_int32u sector_size; /**< sector size in bytes */
blt_int8u sector_num; /**< sector number */
} tFlashSector;
/** \brief Structure type for grouping flash block information.
* \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a
* flash block manager is implemented in this driver. this flash block manager
* depends on this flash block info structure. It holds the base address of
* the flash block and the data that should be programmed into the flash
* block.
*/
typedef struct
{
blt_addr base_addr; /**< Base address for the flash operation.*/
blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; /**< Data array. */
} tFlashBlockInfo;
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address);
static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len);
static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block);
static blt_bool ExtFlashEraseSector(blt_addr sector_base);
static blt_int16u ExtFlashGetDeviceInfo(blt_addr block_base, blt_int16u info);
static void ExtFlashLockSector(blt_addr sector_base);
static void ExtFlashUnlockSector(blt_addr sector_base);
static blt_int8u ExtFlashGetSector(blt_addr address);
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief Array wit the layout of the flash memory.
* \details The current layout supports the 2MB external C3 Intel flash:
* - manufacturer id = 0x0089
* - device id = 0x88c3 (16 Mbit bottom boot device)
* Note that what Intel calls a block in the user manual, is called a sector in this
* driver.
*/
static const tFlashSector flashLayout[] =
{
{ 0x80000000, 0x02000, 0}, /* flash sector 0 - 8 kbyte */
{ 0x80002000, 0x02000, 1}, /* flash sector 1 - 8 kbyte */
{ 0x80004000, 0x02000, 2}, /* flash sector 2 - 8 kbyte */
{ 0x80006000, 0x02000, 3}, /* flash sector 3 - 8 kbyte */
{ 0x80008000, 0x02000, 4}, /* flash sector 4 - 8 kbyte */
{ 0x8000A000, 0x02000, 5}, /* flash sector 5 - 8 kbyte */
{ 0x8000C000, 0x02000, 6}, /* flash sector 6 - 8 kbyte */
{ 0x8000E000, 0x02000, 7}, /* flash sector 7 - 8 kbyte */
{ 0x80010000, 0x10000, 8}, /* flash sector 8 - 64 kbyte */
{ 0x80020000, 0x10000, 9}, /* flash sector 9 - 64 kbyte */
{ 0x80030000, 0x10000, 10}, /* flash sector 10 - 64 kbyte */
{ 0x80040000, 0x10000, 11}, /* flash sector 11 - 64 kbyte */
{ 0x80050000, 0x10000, 12}, /* flash sector 12 - 64 kbyte */
{ 0x80060000, 0x10000, 13}, /* flash sector 13 - 64 kbyte */
{ 0x80070000, 0x10000, 14}, /* flash sector 14 - 64 kbyte */
{ 0x80080000, 0x10000, 15}, /* flash sector 15 - 64 kbyte */
{ 0x80090000, 0x10000, 16}, /* flash sector 16 - 64 kbyte */
{ 0x800A0000, 0x10000, 17}, /* flash sector 17 - 64 kbyte */
{ 0x800B0000, 0x10000, 18}, /* flash sector 18 - 64 kbyte */
{ 0x800C0000, 0x10000, 19}, /* flash sector 19 - 64 kbyte */
{ 0x800D0000, 0x10000, 20}, /* flash sector 20 - 64 kbyte */
{ 0x800E0000, 0x10000, 21}, /* flash sector 21 - 64 kbyte */
{ 0x800F0000, 0x10000, 22}, /* flash sector 22 - 64 kbyte */
{ 0x80100000, 0x10000, 23}, /* flash sector 23 - 64 kbyte */
{ 0x80110000, 0x10000, 24}, /* flash sector 24 - 64 kbyte */
{ 0x80120000, 0x10000, 25}, /* flash sector 25 - 64 kbyte */
{ 0x80130000, 0x10000, 26}, /* flash sector 26 - 64 kbyte */
{ 0x80140000, 0x10000, 27}, /* flash sector 27 - 64 kbyte */
{ 0x80150000, 0x10000, 28}, /* flash sector 28 - 64 kbyte */
{ 0x80160000, 0x10000, 29}, /* flash sector 29 - 64 kbyte */
{ 0x80170000, 0x10000, 30}, /* flash sector 30 - 64 kbyte */
{ 0x80180000, 0x10000, 31}, /* flash sector 31 - 64 kbyte */
{ 0x80190000, 0x10000, 32}, /* flash sector 32 - 64 kbyte */
{ 0x801A0000, 0x10000, 33}, /* flash sector 33 - 64 kbyte */
{ 0x801B0000, 0x10000, 34}, /* flash sector 34 - 64 kbyte */
{ 0x801C0000, 0x10000, 35}, /* flash sector 35 - 64 kbyte */
{ 0x801D0000, 0x10000, 36}, /* flash sector 36 - 64 kbyte */
{ 0x801E0000, 0x10000, 37}, /* flash sector 37 - 64 kbyte */
{ 0x801F0000, 0x10000, 38} /* flash sector 38 - 64 kbyte */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable with information about the flash block that is currently
* being operated on.
* \details The smallest amount of flash that can be programmed is
* FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver
* and stores info in this variable. Whenever new data should be flashed, it
* is first added to a RAM buffer, which is part of this variable. Whenever
* the RAM buffer, which has the size of a flash block, is full or data needs
* to be written to a different block, the contents of the RAM buffer are
* programmed to flash. The flash block manager requires some software
* overhead, yet results is faster flash programming because data is first
* harvested, ideally until there is enough to program an entire flash block,
* before the flash device is actually operated on.
*/
static tFlashBlockInfo blockInfo;
/************************************************************************************//**
** \brief Initializes the flash driver.
** \return none.
**
****************************************************************************************/
void ExtFlashInit(void)
{
/* init the flash block info struct by setting the address to an invalid address */
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
/* check the flash device identification */
if ((ExtFlashGetManID() != FLASH_DEV_MAN_ID) || (ExtFlashGetDevID() != FLASH_DEV_ID))
{
ASSERT_RT(BLT_FALSE);
}
} /*** end of ExtFlashInit ***/
/************************************************************************************//**
** \brief Writes the data to flash.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
/* make sure the addresses are within the flash device */
if ( (ExtFlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
(ExtFlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
{
return BLT_NVM_NOT_IN_RANGE;
}
/* let the block manager handle it */
if (ExtFlashAddToBlock(&blockInfo, addr, data, len) == BLT_FALSE)
{
return BLT_NVM_ERROR;
}
return BLT_NVM_OKAY;
} /*** end of FlashWrite ***/
/************************************************************************************//**
** \brief Erases the flash memory. Note that this function also checks that no
** data is erased outside the flash memory region.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len)
{
blt_int8u first_sector;
blt_int8u last_sector;
blt_int8u sectorIdx;
/* obtain the first and last sector number */
first_sector = ExtFlashGetSector(addr);
last_sector = ExtFlashGetSector(addr+len-1);
/* check them */
if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
{
return BLT_NVM_NOT_IN_RANGE;
}
/* erase the sectors one-by-one */
for (sectorIdx = first_sector; sectorIdx <= last_sector; sectorIdx++)
{
/* keep the watchdog happy */
CopService();
/* erase the sector */
if (ExtFlashEraseSector(flashLayout[sectorIdx].sector_start) == BLT_FALSE)
{
return BLT_NVM_ERROR;
}
}
/* done so return the result of the operation */
return BLT_NVM_OKAY;
} /*** end of ExtFlashErase ***/
/************************************************************************************//**
** \brief Finalizes the flash driver operations.
** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool ExtFlashDone(void)
{
/* check if there is still data waiting to be programmed */
if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
{
if (ExtFlashWriteBlock(&blockInfo) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* still here so all is okay */
return BLT_TRUE;
} /*** end of ExtFlashDone ***/
/************************************************************************************//**
** \brief Copies data currently in flash to the block->data and sets the
** base address.
** \param block Pointer to flash block info structure to operate on.
** \param address Base address of the block data.
** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address)
{
/* check address alignment */
if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
{
return BLT_FALSE;
}
/* make sure that we are initializing a new block and not the same one */
if (block->base_addr == address)
{
/* block already initialized, so nothing to do */
return BLT_TRUE;
}
/* set the base address and copies the current data from flash */
block->base_addr = address;
CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
return BLT_TRUE;
} /*** end of ExtFlashInitBlock ***/
/************************************************************************************//**
** \brief Switches blocks by programming the current one and initializing the next.
** \param block Pointer to flash block info structure to operate on.
** \param base_addr Base address for the next block.
** \return The pointer of the block info struct that is no being used, or a NULL
** pointer in case of error.
**
****************************************************************************************/
static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
{
/* need to switch to a new block, so program the current one and init the next */
if (ExtFlashWriteBlock(block) == BLT_FALSE)
{
return BLT_NULL;
}
/* initialize the new block when necessary */
if (ExtFlashInitBlock(block, base_addr) == BLT_FALSE)
{
return BLT_NULL;
}
/* still here to all is okay */
return block;
} /*** end of ExtFlashSwitchBlock ***/
/************************************************************************************//**
** \brief Programming is done per block. This function adds data to the block
** that is currently collecting data to be written to flash. If the
** address is outside of the current block, the current block is written
** to flash an a new block is initialized.
** \param block Pointer to flash block info structure to operate on.
** \param address Flash destination address.
** \param data Pointer to the byte array with data.
** \param len Number of bytes to add to the block.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len)
{
blt_addr current_base_addr;
blt_int8u *dst;
blt_int8u *src;
/* determine the current base address */
current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
/* make sure the blockInfo is not uninitialized */
if (block->base_addr == FLASH_INVALID_ADDRESS)
{
/* initialize the blockInfo struct for the current block */
if (ExtFlashInitBlock(block, current_base_addr) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* check if the new data fits in the current block */
if (block->base_addr != current_base_addr)
{
/* need to switch to a new block, so program the current one and init the next */
block = ExtFlashSwitchBlock(block, current_base_addr);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
}
/* add the data to the current block, but check for block overflow */
dst = &(block->data[address - block->base_addr]);
src = data;
do
{
/* keep the watchdog happy */
CopService();
/* buffer overflow? */
if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
{
/* need to switch to a new block, so program the current one and init the next */
block = ExtFlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
/* reset destination pointer */
dst = &(block->data[0]);
}
/* write the data to the buffer */
*dst = *src;
/* update pointers */
dst++;
src++;
/* decrement byte counter */
len--;
}
while (len > 0);
/* still here so all is good */
return BLT_TRUE;
} /*** end of ExtFlashAddToBlock ***/
/************************************************************************************//**
** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data array.
** \param block Pointer to flash block info structure to operate on.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block)
{
volatile blt_int16u *pAddr;
volatile blt_int16u *pData;
blt_bool result = BLT_TRUE;
volatile blt_int32u timeout = 0;
/* unlock the sector */
ExtFlashUnlockSector(block->base_addr);
/* init pointer to valid address in the flash block */
pAddr = (blt_int16u *)block->base_addr;
/* init pointer to start of block data */
pData = (blt_int16u *)block->data;
/* program all block data 16-bits at a time */
while ((blt_addr)pAddr < (block->base_addr+FLASH_WRITE_BLOCK_SIZE))
{
/* keep the watchdog happy */
CopService();
/* issue program setup command */
*pAddr = FLASH_CMD_PROGRAM_MODE;
/* write 16-bit data that is to be programmed to start programming operation */
*pAddr = *pData;
/* check status register for completion */
*pAddr = FLASH_CMD_READ_STATUS_MODE;
/* wait for completion or timeout */
while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_PROGRAM_TIMEOUT) )
{
timeout++;
}
/* check for possible errors */
if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_PROGRAM))!= 0) )
{
result = BLT_FALSE;
}
/* clear the status register */
*pAddr = FLASH_CMD_CLEAR_STATUS;
/* increment address and data pointers */
pAddr++;
pData++;
}
/* lock the sector. this also switches back to read array mode */
ExtFlashLockSector(block->base_addr);
/* inform the caller about the result */
return result;
} /*** end of ExtFlashWriteBlock ***/
/************************************************************************************//**
** \brief Erases the flash sector.
** \param sector_base Base address of the sector to erase.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashEraseSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
blt_bool result = BLT_TRUE;
volatile blt_int32u timeout = 0;
/* unlock the sector */
ExtFlashUnlockSector(sector_base);
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* issue erase setup command */
*pAddr = FLASH_CMD_ERASE_MODE;
/* issue erase confirm command */
*pAddr = FLASH_CMD_ERASE_CONFIRM;
/* check status register for completion */
*pAddr = FLASH_CMD_READ_STATUS_MODE;
/* wait for completion or timeout */
while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_ERASE_TIMEOUT) )
{
timeout++;
}
/* check for possible errors */
if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_ERASE))!= 0) )
{
result = BLT_FALSE;
}
/* clear the status register */
*pAddr = FLASH_CMD_CLEAR_STATUS;
/* lock the sector. this also switches back to read array mode */
ExtFlashLockSector(sector_base);
/* inform the caller about the result */
return result;
} /*** end of ExtFlashEraseSector ***/
/************************************************************************************//**
** \brief Locks the flash sector.
** \param sector_base Base address of the sector to lock.
** \return none.
**
****************************************************************************************/
static void ExtFlashLockSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
/* no need to lock a sector that is already locked */
if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0)
{
return;
}
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* switch to change lock mode */
*pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
/* unlock the sector */
*pAddr = FLASH_CMD_LOCK_SECTOR;
/* check that the sector is now actually locked */
ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0);
} /*** end of ExtFlashLockSector ***/
/************************************************************************************//**
** \brief Unlocks the flash sector.
** \param sector_base Base address of the sector to unlock.
** \return none.
**
****************************************************************************************/
static void ExtFlashUnlockSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
/* no need to unlock a sector that is already unlocked */
if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0)
{
return;
}
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* switch to change lock mode */
*pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
/* unlock the sector */
*pAddr = FLASH_CMD_UNLOCK_SECTOR;
/* check that the sector is now actually unlocked */
ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0);
} /*** end of ExtFlashUnlockSector ***/
/************************************************************************************//**
** \brief Obtains device information from the flash device.
** \param sector_base Base address of the sector to get the info from.
** \param info Identifier to the type of info to obtain.
** \return Device info.
**
****************************************************************************************/
static blt_int16u ExtFlashGetDeviceInfo(blt_addr sector_base, blt_int16u info)
{
volatile blt_int16u *pAddr;
blt_int16u readData;
/* init pointer to any valid address in the flash device */
pAddr = (blt_int16u *)sector_base + info;
/* switch to read identifier mode */
*pAddr = FLASH_CMD_READ_ID_MODE;
/* read the info */
readData = *pAddr;
/* switch back to reading mode */
*pAddr = FLASH_CMD_READ_ARRAY_MODE;
/* return the result */
return readData;
} /*** end of ExtFlashGetDeviceInfo ***/
/************************************************************************************//**
** \brief Determines the flash sector the address is in.
** \param address Address in the flash sector.
** \return Flash sector number or FLASH_INVALID_SECTOR
**
****************************************************************************************/
static blt_int8u ExtFlashGetSector(blt_addr address)
{
blt_int8u sectorIdx;
/* search through the sectors to find the right one */
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
{
/* keep the watchdog happy */
CopService();
/* is the address in this sector? */
if ( (address >= flashLayout[sectorIdx].sector_start) && \
(address < (flashLayout[sectorIdx].sector_start + \
flashLayout[sectorIdx].sector_size)) )
{
/* return the sector number */
return flashLayout[sectorIdx].sector_num;
}
}
/* still here so no valid sector found */
return FLASH_INVALID_SECTOR;
} /*** end of ExtFlashGetSector ***/
#endif
/*********************************** end of extflash.c *********************************/

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@ -1,42 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\extflash.h
* \brief Bootloader external flash driver header file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef EXTFLASH_H
#define EXTFLASH_H
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void ExtFlashInit(void);
blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len);
blt_bool ExtFlashDone(void);
#endif
#endif /* EXTFLASH_H */
/*********************************** end of extflash.h *********************************/

296
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c
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@ -1,296 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "lpc2294.h" /* CPU register definitions */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
/* configure the button connected to P0.16 as a digital input */
IO0DIR &= ~(1<<16);
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* button P0.16 has a pullup, so will read high by default. enter backdoor only when
* this button is pressed. this is the case when it reads low */
if ((IO0PIN & (1<<16)) == 0)
{
return BLT_TRUE;
}
return BLT_FALSE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
#include "extflash.h"
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
/* init the external flash driver */
ExtFlashInit();
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
/* attempt to write with the external flash driver */
return ExtFlashWrite(addr, len, data);
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
/* attempt to erase with the external flash driver */
return ExtFlashErase(addr, len);
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
/* finish up the operations of the external flash driver */
return ExtFlashDone();
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "FeaserKey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

67
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp
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@ -1,67 +0,0 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="lpc2294_crossworks" target="8" version="2">
<project Name="openblt_olimex_lpc_l2294_20mhz">
<configuration Name="Common" arm_library_optimization="Fast" arm_simulator_memory_simulation_filename="$(PackagesDir)/targets/Philips_LPC210X/LPC2000SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="LPC22;0x20000;0x4000;0x400000;0x100000;0x0;0x0" arm_target_loader_parameter="20000000" arm_use_gcc_libraries="No" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_preprocessor_definitions="__TARGET_PROCESSOR=LPC2294;OSCILLATOR_CLOCK_FREQUENCY=20000000" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../../../../Source;$(ProjectDir)/../../../../Source/ARM7_LPC2000;$(ProjectDir)/../../../../Source/ARM7_LPC2000/Crossworks" gcc_entry_point="Reset_Handler" gcc_optimization_level="Level 1" gcc_strip_symbols="No" link_include_standard_libraries="Yes" link_include_startup_code="No" linker_DebugIO_enabled="No" linker_additional_files="$(PackagesDir)/lib/liblpc2000$(LibExt)$(LIB)" linker_additional_options="" linker_keep_symbols="_vectors;EntryFromProg" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" project_directory="" project_type="Executable"/>
<configuration Name="RAM" target_reset_script="RAMReset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(PackagesDir)/targets/Olimex_LPC_E2294/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" target_reset_script="FLASHReset()"/>
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<folder Name="Demo">
<folder Name="Boot" file_name="">
<file file_name="../hooks.c"/>
<file file_name="../lpc2294.h"/>
<file file_name="../main.c"/>
<file file_name="../extflash.c"/>
<file file_name="../extflash.h"/>
<file file_name="../blt_conf.h"/>
</folder>
</folder>
<folder Name="Source" file_name="">
<folder Name="ARM7_LPC2000">
<folder Name="Crossworks" file_name="">
<file file_name="../../../../Source/ARM7_LPC2000/Crossworks/cstart.s"/>
<file file_name="../../../../Source/ARM7_LPC2000/Crossworks/flash.c"/>
<file file_name="../../../../Source/ARM7_LPC2000/Crossworks/flash.h"/>
<file file_name="../../../../Source/ARM7_LPC2000/Crossworks/cpu_comp.c"/>
</folder>
<file file_name="../../../../Source/ARM7_LPC2000/can.c"/>
<file file_name="../../../../Source/ARM7_LPC2000/cpu.c"/>
<file file_name="../../../../Source/ARM7_LPC2000/nvm.c"/>
<file file_name="../../../../Source/ARM7_LPC2000/timer.c"/>
<file file_name="../../../../Source/ARM7_LPC2000/types.h"/>
<file file_name="../../../../Source/ARM7_LPC2000/uart.c"/>
</folder>
<file file_name="../../../../Source/assert.c"/>
<file file_name="../../../../Source/assert.h"/>
<file file_name="../../../../Source/backdoor.c"/>
<file file_name="../../../../Source/backdoor.h"/>
<file file_name="../../../../Source/boot.c"/>
<file file_name="../../../../Source/boot.h"/>
<file file_name="../../../../Source/com.c"/>
<file file_name="../../../../Source/com.h"/>
<file file_name="../../../../Source/cop.c"/>
<file file_name="../../../../Source/cop.h"/>
<file file_name="../../../../Source/plausibility.h"/>
<file file_name="../../../../Source/xcp.c"/>
<file file_name="../../../../Source/xcp.h"/>
<file file_name="../../../../Source/can.h"/>
<file file_name="../../../../Source/cpu.h"/>
<file file_name="../../../../Source/nvm.h"/>
<file file_name="../../../../Source/timer.h"/>
<file file_name="../../../../Source/uart.h"/>
</folder>
</folder>
<folder Name="System Files">
<file file_name="$(PackagesDir)/targets/Olimex_LPC_E2294/LPC_E2294_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
</file>
<file file_name="../../../../Source/ARM7_LPC2000/Crossworks/memory.x">
<configuration Name="Common" file_type="Linker Script"/>
</file>
</folder>
</project>
<configuration Name="ARM Flash Debug" inherited_configurations="ARM;Flash;Debug"/>
<configuration Name="ARM" Platform="ARM" arm_instruction_set="ARM" arm_library_instruction_set="ARM" c_preprocessor_definitions="__ARM" hidden="Yes"/>
<configuration Name="Flash" c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
</solution>

57
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs
View File

@ -1,57 +0,0 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x80000200" numColumns="8" sizeText="32" dataSize="1" radix="16" name="openbtl_olimex_lpc_l2294_20mhz" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_lpc_l2294_20mhz" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_lpc_l2294_20mhz" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_lpc_l2294_20mhz" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="lpc2294_crossworks" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;openblt_olimex_lpc_l2294_20mhz" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;openblt_olimex_lpc_l2294_20mhz;Source Files" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;openblt_olimex_lpc_l2294_20mhz;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;openblt_olimex_lpc_l2294_20mhz;Source Files;Demo;Boot" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_lpc_l2294_20mhz" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_lpc_l2294_20mhz" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_lpc_l2294_20mhz" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_lpc_l2294_20mhz" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
<Trace enabled="Yes" />
</TraceWindow>
<Watch1>
<Watches active="1" update="Never" />
</Watch1>
<Watch2>
<Watches active="0" update="Never" />
</Watch2>
<Watch3>
<Watches active="0" update="Never" />
</Watch3>
<Watch4>
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" y="53" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" left="0" selected="1" name="unnamed" top="45" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_olimex_lpc_l2294_20mhz" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:\Work\software\OpenBLT\Target\Source\ARM7_LPC2000\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388479" debugSearchPath="" buildConfiguration="ARM Flash Debug" />
</session>

4
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt
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@ -1,4 +0,0 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

404
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h
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@ -1,404 +0,0 @@
/****************************************************************************************
| Description: NXP LPC2294 register definitions
| File Name: lpc2294.h
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
#ifndef LPC2294_H
#define LPC2294_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* EXTERNAL MEMORY CONTROLLER (EMC) */
#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
/* External Interrupts */
#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
/* SMemory mapping control. */
#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
/* Phase Locked Loop (PLL) */
#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
/* Power Control */
#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
/* VPB Divider */
#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
/* Memory Accelerator Module (MAM) */
#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
/* Vectored Interrupt Controller (VIC) */
#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
/* Pin Connect Block */
#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
/* General Purpose Input/Output (GPIO) */
#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define U0RBR (*((volatile unsigned char *) 0xE000C000))
#define U0THR (*((volatile unsigned char *) 0xE000C000))
#define U0IER (*((volatile unsigned char *) 0xE000C004))
#define U0IIR (*((volatile unsigned char *) 0xE000C008))
#define U0FCR (*((volatile unsigned char *) 0xE000C008))
#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
#define U0LSR (*((volatile unsigned char *) 0xE000C014))
#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
#define U0DLL (*((volatile unsigned char *) 0xE000C000))
#define U0DLM (*((volatile unsigned char *) 0xE000C004))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define U1RBR (*((volatile unsigned char *) 0xE0010000))
#define U1THR (*((volatile unsigned char *) 0xE0010000))
#define U1IER (*((volatile unsigned char *) 0xE0010004))
#define U1IIR (*((volatile unsigned char *) 0xE0010008))
#define U1FCR (*((volatile unsigned char *) 0xE0010008))
#define U1LCR (*((volatile unsigned char *) 0xE001000C))
#define U1MCR (*((volatile unsigned char *) 0xE0010010))
#define U1LSR (*((volatile unsigned char *) 0xE0010014))
#define U1MSR (*((volatile unsigned char *) 0xE0010018))
#define U1SCR (*((volatile unsigned char *) 0xE001001C))
#define U1DLL (*((volatile unsigned char *) 0xE0010000))
#define U1DLM (*((volatile unsigned char *) 0xE0010004))
/* I2C (8/16 bit data bus) */
#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
#define I2STAT (*((volatile unsigned long *) 0xE001C004))
#define I2DAT (*((volatile unsigned long *) 0xE001C008))
#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
/* SPI (Serial Peripheral Interface) */
/* only for lpc210x*/
#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
/* Timer 0 */
#define T0IR (*((volatile unsigned long *) 0xE0004000))
#define T0TCR (*((volatile unsigned long *) 0xE0004004))
#define T0TC (*((volatile unsigned long *) 0xE0004008))
#define T0PR (*((volatile unsigned long *) 0xE000400C))
#define T0PC (*((volatile unsigned long *) 0xE0004010))
#define T0MCR (*((volatile unsigned long *) 0xE0004014))
#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
#define T0CCR (*((volatile unsigned long *) 0xE0004028))
#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
#define T0EMR (*((volatile unsigned long *) 0xE000403C))
/* Timer 1 */
#define T1IR (*((volatile unsigned long *) 0xE0008000))
#define T1TCR (*((volatile unsigned long *) 0xE0008004))
#define T1TC (*((volatile unsigned long *) 0xE0008008))
#define T1PR (*((volatile unsigned long *) 0xE000800C))
#define T1PC (*((volatile unsigned long *) 0xE0008010))
#define T1MCR (*((volatile unsigned long *) 0xE0008014))
#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
#define T1CCR (*((volatile unsigned long *) 0xE0008028))
#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
#define T1EMR (*((volatile unsigned long *) 0xE000803C))
/* Pulse Width Modulator (PWM) */
#define PWMIR (*((volatile unsigned long *) 0xE0014000))
#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
#define PWMTC (*((volatile unsigned long *) 0xE0014008))
#define PWMPR (*((volatile unsigned long *) 0xE001400C))
#define PWMPC (*((volatile unsigned long *) 0xE0014010))
#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
#define PWMLER (*((volatile unsigned long *) 0xE0014050))
/* A/D CONVERTER */
#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
/* Real Time Clock */
#define ILR (*((volatile unsigned char *) 0xE0024000))
#define CTC (*((volatile unsigned short*) 0xE0024004))
#define CCR (*((volatile unsigned char *) 0xE0024008))
#define CIIR (*((volatile unsigned char *) 0xE002400C))
#define AMR (*((volatile unsigned char *) 0xE0024010))
#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
#define SEC (*((volatile unsigned char *) 0xE0024020))
#define MIN (*((volatile unsigned char *) 0xE0024024))
#define HOUR (*((volatile unsigned char *) 0xE0024028))
#define DOM (*((volatile unsigned char *) 0xE002402C))
#define DOW (*((volatile unsigned char *) 0xE0024030))
#define DOY (*((volatile unsigned short*) 0xE0024034))
#define MONTH (*((volatile unsigned char *) 0xE0024038))
#define YEAR (*((volatile unsigned short*) 0xE002403C))
#define ALSEC (*((volatile unsigned char *) 0xE0024060))
#define ALMIN (*((volatile unsigned char *) 0xE0024064))
#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
#define ALDOM (*((volatile unsigned char *) 0xE002406C))
#define ALDOW (*((volatile unsigned char *) 0xE0024070))
#define ALDOY (*((volatile unsigned short*) 0xE0024074))
#define ALMON (*((volatile unsigned char *) 0xE0024078))
#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
#define PREINT (*((volatile unsigned short*) 0xE0024080))
#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
/* Watchdog */
#define WDMOD (*((volatile unsigned char *) 0xE0000000))
#define WDTC (*((volatile unsigned long *) 0xE0000004))
#define WDFEED (*((volatile unsigned char *) 0xE0000008))
#define WDTV (*((volatile unsigned long *) 0xE000000C))
#endif /* LPC2294_H */
/*********************************** end of lpc2294.h **********************************/

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@ -1,174 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "lpc2294.h" /* CPU register definitions */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* initialize the microcontroller */
Init();
/* initialize the bootloader */
BootInit();
/* start the infinite program loop */
while (1)
{
/* run the bootloader task */
BootTask();
}
/* program should never get here */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
** configured equal to Fpll. The GPIO pin of the status LED is configured
** as digital output.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
blt_int8u m_sel; /* pll multiplier register value */
static blt_int8u pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
blt_int8u p_sel_cnt; /* loop counter to find p_sel */
blt_int32u f_cco; /* current controller oscillator */
/* check that pll multiplier value will be in the range 1..32 */
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ >= 1);
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ <= 32);
/* calculate MSEL: M = round(Fcclk / Fosc) */
m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ;
/* value for the PLLCFG register is -1 */
m_sel--;
/* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
for (p_sel_cnt=0; p_sel_cnt<sizeof(pll_dividers)/sizeof(pll_dividers[0]); p_sel_cnt++)
{
/* check f_cco with this pll divider */
f_cco = BOOT_CPU_SYSTEM_SPEED_KHZ * 2 * pll_dividers[p_sel_cnt];
if ( (f_cco >= 156000) && (f_cco <= 320000) )
{
/* found a valid pll divider value */
break;
}
}
/* check that a valid value was found */
ASSERT_RT(p_sel_cnt < (sizeof(pll_dividers)/sizeof(pll_dividers[0])));
/* set multiplier and divider values */
PLLCFG = (p_sel_cnt << 5) | m_sel;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable the PLL */
PLLCON = 0x1;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* wait for the PLL to lock to set frequency */
while(!(PLLSTAT & 0x400)) { ; }
/* connect the PLL as the clock source */
PLLCON = 0x3;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
* Fcclk >= 60 MHz: 4 clock cycles
* Fcclk >= 40 MHz: 3 clock cycles
* Fcclk >= 20 MHz: 2 clock cycles
* Fcclk < 20 MHz: 1 clock cycle
*/
MAMCR = 0x0;
#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
MAMTIM = 4;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
MAMTIM = 3;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
MAMTIM = 2;
#else
MAMTIM = 1;
#endif
MAMCR = 0x2;
/* setting peripheral Clock (pclk) to System Clock (cclk) */
VPBDIV = 0x1;
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* in this the external memory on the Olimex LPC-L2294 board is used so configure
* the memory banks for the external flash EEPROM and RAM
*/
/* external flash EEPROM:
* IDCY=3 (idle timing)
* WST1=4 (read timing)
* RBLE=1
* WST2=6 (write timing)
* MW=1 (16-bit data bus)
*/
BCFG0 = (0x3 << 0) | (0x4 << 5) | (0x1 << 10) | (0x6 << 11) | (0x1 << 28);
/* external RAM:
* IDCY=0 (idle timing)
* WST1=0 (read timing)
* RBLE=1
* WST2=0 (write timing)
* MW=2 (32-bit data bus)
*/
BCFG1 = (0x0 << 0) | (0x0 << 5) | (0x1 << 10) | (0x0 << 11) | (0x2 << 28);
/* configure use of data bus and strobe pins for the external memory */
PINSEL2 = 0x0F000924;
#endif
#if (BOOT_COM_UART_ENABLE > 0)
/* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
PINSEL0 |= 0x05;
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* configure P0.25 for CAN1 Rx functionality */
PINSEL1 |= 0x00040000L;
#endif
} /*** end of Init ***/
/*********************************** end of main.c *************************************/

BIN
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf
View File

Binary file not shown.

1487
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
View File

File diff suppressed because it is too large Load Diff

661
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.srec
View File

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Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c
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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c
* \brief Demo program bootloader interface source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
#if (BOOT_COM_UART_ENABLE > 0)
static void BootComUartInit(void);
static void BootComUartCheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
** \return none.
**
****************************************************************************************/
void BootComInit(void)
{
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartInit();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
void BootComCheckActivationRequest(void)
{
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartCheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
/************************************************************************************//**
** \brief Bootloader activation function. Performs a software reset by configuring
** and triggering the watchdog.
** \return none.
**
****************************************************************************************/
void BootActivate(void)
{
#define WDEN_BIT (0x01) /* watchdog enable bit (set only) */
#define WDRESET_BIT (0x02) /* watchdog reset enable bit */
/* configure a short timeout. not really interesting as we won't be using it */
WDTC = 1024;
/* enable the watchdog and configure it such that a watchdog timeout causes a reset */
WDMOD = WDEN_BIT | WDRESET_BIT;
/* start the watchdog */
WDFEED = 0xAA;
WDFEED = 0x55;
/* write invalid feed sequence to cause an instant reset */
WDFEED = 0xAA;
WDFEED = 0x00;
} /*** end of BootActivate ***/
#if (BOOT_COM_UART_ENABLE > 0)
/****************************************************************************************
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Divisor latch access bit. */
#define UART_DLAB (0x80)
/** \brief 8 data and 1 stop bit, no parity. */
#define UART_MODE_8N1 (0x03)
/** \brief FIFO reset and RX FIFO 1 deep. */
#define UART_FIFO_RX1 (0x07)
/** \brief Receiver data ready. */
#define UART_RDR (0x01)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static unsigned char UartReceiveByte(unsigned char *data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
static void BootComUartInit(void)
{
unsigned long baud_reg_value; /* baudrate register value */
/* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
PINSEL0 |= 0x05;
/* disable UART related interrupt generation. this driver works in polling mode */
U0IER = 0;
/* clear interrupt id register */
U0IIR = 0;
/* clear line status register */
U0LSR = 0;
/* set divisor latch DLAB = 1 so buadrate can be configured */
U0LCR = UART_DLAB;
/* Baudrate calculation:
* y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
* smartness to automatically round the value up/down using the following trick:
* y = x/n can round with y = (x + (n + 1)/2 ) / n
*/
baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
/* write the calculated baudrate selector value to the registers */
U0DLL = (unsigned char)baud_reg_value;
U0DLM = (unsigned char)(baud_reg_value >> 8);
/* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
U0LCR = UART_MODE_8N1;
/* enable and reset transmit and receive FIFO. necessary for UART operation */
U0FCR = UART_FIFO_RX1;
} /*** end of BootComUartInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComUartCheckActivationRequest(void)
{
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
static unsigned char xcpCtoRxLength;
static unsigned char xcpCtoRxInProgress = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == 0)
{
/* store the message length when received */
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
{
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = 1;
/* reset packet data count */
xcpCtoRxLength = 0;
}
}
else
{
/* store the next packet byte */
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* done with cto packet reception */
xcpCtoRxInProgress = 0;
/* check if this was an XCP CONNECT command */
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
}
} /*** end of BootComUartCheckActivationRequest ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return 1 if a byte was received, 0 otherwise.
**
****************************************************************************************/
static unsigned char UartReceiveByte(unsigned char *data)
{
/* check if a new byte was received by means of the RDR-bit */
if((U0LSR & UART_RDR) != 0)
{
/* store the received byte */
data[0] = U0RBR;
/* inform caller of the newly received byte */
return 1;
}
/* inform caller that no new data was received */
return 0;
} /*** end of UartReceiveByte ***/
#endif /* BOOT_COM_UART_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Transmit buffer 1 idle. */
#define CAN_TBS1 (0x00000004)
/** \brief Transmit buffer 1 complete. */
#define CAN_TCS1 (0x00000008)
/** \brief Receive buffer release. */
#define CAN_RRB (0x04)
/** \brief Receive buffer status. */
#define CAN_RBS (0x01)
/** \brief Transmission request. */
#define CAN_TR (0x01)
/** \brief Select tx buffer 1 for transmit. */
#define CAN_STB1 (0x20)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char tseg1; /**< CAN time segment 1 */
unsigned char tseg2; /**< CAN time segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
* 100%. This array contains possible and valid time quanta configurations with
* a sample point between 68..78%.
*/
static const tCanBusTiming canTiming[] =
{ /* TQ | TSEG1 | TSEG2 | SP */
/* ------------------------- */
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
{ 16, 8 } /* 25 | 16 | 8 | 68% */
};
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param btr Pointer to where the value for register CANxBTR will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned long *btr)
{
unsigned short prescaler;
unsigned char cnt;
/* loop through all possible time quanta configurations to find a match */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((BOOT_CPU_SYSTEM_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
{
/* compute the prescaler that goes with this TQ configuration */
prescaler = BOOT_CPU_SYSTEM_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
/* make sure the prescaler is valid */
if ( (prescaler > 0) && (prescaler <= 1024) )
{
/* store the prescaler and bustiming register value */
*btr = prescaler - 1;
*btr |= ((canTiming[cnt].tseg2 - 1) << 20) | ((canTiming[cnt].tseg1 - 1) << 16);
/* found a good bus timing configuration */
return 1;
}
}
}
/* could not find a good bus timing configuration */
return 0;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
unsigned long btr_reg_value;
/* configure acceptance filter for bypass mode so it receives all messages */
CANAFMR = 0x00000002L;
/* take CAN controller offline and go into reset mode */
CAN1MOD = 1;
/* disable all interrupts. driver only needs to work in polling mode */
CAN1IER = 0;
/* reset CAN controller status */
CAN1GSR = 0;
/* configure the bittiming */
if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btr_reg_value) == 1)
{
/* write the bittiming configuration to the register */
CAN1BTR = btr_reg_value;
}
/* enter normal operating mode and synchronize to the CAN bus */
CAN1MOD = 0;
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
unsigned char data[2];
/* check if a new message was received */
if ((CAN1SR & CAN_RBS) == 0)
{
return;
}
/* see if this is the message identifier that we are interested in */
if (CAN1RID != BOOT_COM_CAN_RX_MSG_ID)
{
return;
}
/* store the message data */
data[0] = (unsigned char)CAN1RDA;
data[1] = (unsigned char)(CAN1RDA >> 8);
/* release the receive buffer */
CAN1CMR = CAN_RRB;
/* check if this was an XCP CONNECT command */
if ((data[0] == 0xff) && (data[1] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

40
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h
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@ -1,40 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.h
* \brief Demo program bootloader interface header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BOOT_H
#define BOOT_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void BootComInit(void);
void BootComCheckActivationRequest(void);
void BootActivate(void);
#endif /* BOOT_H */
/*********************************** end of boot.h *************************************/

415
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s
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@ -1,415 +0,0 @@
/*****************************************************************************
* Copyright (c) 2001, 2002 Rowley Associates Limited. *
* *
* This file may be distributed under the terms of the License Agreement *
* provided with this software. *
* *
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions
* ------------------------
* APP_ENTRY_POINT
*
* Defines the application entry point function, if undefined this setting
* defaults to "main".
*
* INITIALIZE_STACKS
*
* If defined, the contents of the stacks will be initialized to a the
* value 0xCC.
*
* INITIALIZE_SECONDARY_SECTIONS
*
* If defined, the .text2, .data2 and .bss2 sections will be initialized.
*
* SUPERVISOR_START
*
* If defined, the application will start up in supervisor mode. If
* undefined the application will start up in system mode.
*
* FULL_LIBRARY
*
* If defined then
* - argc, argv are setup by the debug_getargs.
* - the exit symbol is defined and executes on return from main.
* - the exit symbol calls destructors, atexit functions and then debug_exit.
*
* If not defined then
* - argc and argv are zero.
* - the exit symbol is defined, executes on return from main and loops
*
*****************************************************************************/
.section .vectors, "ax"
.code 32
.align 0
.global _vectors
.global reset_handler
/*****************************************************************************
* Exception Vectors *
*****************************************************************************/
_vectors:
ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
.word 0xB9205F88 /* boot loader checksum */
ldr pc, [pc, #-0xFF0] /* irq handler */
ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */
reset_handler_address:
.word _start
undef_handler_address:
.word undef_handler
swi_handler_address:
.word swi_handler
pabort_handler_address:
.word pabort_handler
dabort_handler_address:
.word dabort_handler
fiq_handler_address:
.word fiq_handler
.section .init, "ax"
.code 32
.align 0
/******************************************************************************
* *
* Default exception handlers *
* *
******************************************************************************/
/******************************************************************************
* *
* Default exception handlers *
* These are declared weak symbols so they can be redefined in user code. *
* *
******************************************************************************/
undef_handler:
b undef_handler
swi_handler:
b swi_handler
pabort_handler:
b pabort_handler
dabort_handler:
b dabort_handler
fiq_handler:
b fiq_handler
irq_handler:
b irq_handler
.weak undef_handler, swi_handler, pabort_handler, dabort_handler, fiq_handler, irq_handler
.section .init, "ax"
.code 32
.align 4
#ifndef APP_ENTRY_POINT
#define APP_ENTRY_POINT main
#endif
#ifndef ARGSSPACE
#define ARGSSPACE 128
#endif
.weak _start
.global __start
.global __gccmain
.extern APP_ENTRY_POINT
.global exit
/*****************************************************************************
* Function : _start *
* Description : Main entry point and startup code for C system. *
*****************************************************************************/
_start:
__start:
mrs r0, cpsr
bic r0, r0, #0x1F
/* Setup stacks */
orr r1, r0, #0x1B /* Undefined mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_und_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
orr r1, r0, #0x17 /* Abort mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_abt_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
orr r1, r0, #0x12 /* IRQ mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_irq_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
orr r1, r0, #0x11 /* FIQ mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_fiq_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
orr r1, r0, #0x13 /* Supervisor mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_svc_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
#ifdef SUPERVISOR_START
/* Start application in supervisor mode */
ldr r1, =__stack_end__ /* Setup user/system mode stack */
#ifdef __ARM_EABI__
bic r1, r1, #0x7
#endif
mov r2, sp
stmfd r2!, {r1}
ldmfd r2, {sp}^
#else
/* Start application in system mode */
orr r1, r0, #0x1F /* System mode */
msr cpsr_cxsf, r1
ldr sp, =__stack_end__
#ifdef __ARM_EABI__
bic sp, sp, #0x7
#endif
#endif
#ifdef INITIALIZE_STACKS
mov r2, #0xCC
ldr r0, =__stack_und_start__
ldr r1, =__stack_und_end__
bl memory_set
ldr r0, =__stack_abt_start__
ldr r1, =__stack_abt_end__
bl memory_set
ldr r0, =__stack_irq_start__
ldr r1, =__stack_irq_end__
bl memory_set
ldr r0, =__stack_fiq_start__
ldr r1, =__stack_fiq_end__
bl memory_set
ldr r0, =__stack_svc_start__
ldr r1, =__stack_svc_end__
bl memory_set
ldr r0, =__stack_start__
ldr r1, =__stack_end__
bl memory_set
#endif
/* Copy initialised memory sections into RAM (if necessary). */
ldr r0, =__data_load_start__
ldr r1, =__data_start__
ldr r2, =__data_end__
bl memory_copy
ldr r0, =__text_load_start__
ldr r1, =__text_start__
ldr r2, =__text_end__
bl memory_copy
ldr r0, =__fast_load_start__
ldr r1, =__fast_start__
ldr r2, =__fast_end__
bl memory_copy
ldr r0, =__ctors_load_start__
ldr r1, =__ctors_start__
ldr r2, =__ctors_end__
bl memory_copy
ldr r0, =__dtors_load_start__
ldr r1, =__dtors_start__
ldr r2, =__dtors_end__
bl memory_copy
ldr r0, =__rodata_load_start__
ldr r1, =__rodata_start__
ldr r2, =__rodata_end__
bl memory_copy
#ifdef INITIALIZE_SECONDARY_SECTIONS
ldr r0, =__data2_load_start__
ldr r1, =__data2_start__
ldr r2, =__data2_end__
bl memory_copy
ldr r0, =__text2_load_start__
ldr r1, =__text2_start__
ldr r2, =__text2_end__
bl memory_copy
ldr r0, =__rodata2_load_start__
ldr r1, =__rodata2_start__
ldr r2, =__rodata2_end__
bl memory_copy
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
/* Zero the bss. */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
mov r2, #0
bl memory_set
#ifdef INITIALIZE_SECONDARY_SECTIONS
ldr r0, =__bss2_start__
ldr r1, =__bss2_end__
mov r2, #0
bl memory_set
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
/* Initialise the heap */
ldr r0, = __heap_start__
ldr r1, = __heap_end__
sub r1, r1, r0
cmp r1, #8
movge r2, #0
strge r2, [r0], #+4
strge r1, [r0]
/* Call constructors */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #+4
stmfd sp!, {r0-r1}
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
ldmfd sp!, {r0-r1}
b ctor_loop
ctor_end:
.type start, function
start:
/* Jump to application entry point */
#ifdef FULL_LIBRARY
mov r0, #ARGSSPACE
ldr r1, =args
ldr r2, =debug_getargs
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
ldr r1, =args
#else
mov r0, #0
mov r1, #0
#endif
ldr r2, =APP_ENTRY_POINT
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
exit:
#ifdef FULL_LIBRARY
mov r5, r0 // save the exit parameter/return result
/* Call destructors */
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
dtor_loop:
cmp r0, r1
beq dtor_end
ldr r2, [r0], #+4
stmfd sp!, {r0-r1}
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
ldmfd sp!, {r0-r1}
b dtor_loop
dtor_end:
/* Call atexit functions */
ldr r2, =_execute_at_exit_fns
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
/* Call debug_exit with return result/exit parameter */
mov r0, r5
ldr r2, =debug_exit
mov lr, pc
#ifdef __ARM_ARCH_3__
mov pc, r2
#else
bx r2
#endif
#endif
/* Returned from application entry point/debug_exit, loop forever. */
exit_loop:
b exit_loop
memory_copy:
cmp r0, r1
moveq pc, lr
subs r2, r2, r1
moveq pc, lr
/* if either pointer or length is not word aligned then byte copy */
orr r3, r0, r1
orr r3, r3, r2
tst r3, #0x3
bne 2f
/* word copy */
1:
ldr r3, [r0], #+4
str r3, [r1], #+4
subs r2, r2, #4
bne 1b
mov pc, lr
/* byte copy */
2:
ldrb r3, [r0], #+1
strb r3, [r1], #+1
subs r2, r2, #1
bne 2b
mov pc, lr
memory_set:
cmp r0, r1
moveq pc, lr
strb r2, [r0], #1
b memory_set
#ifdef FULL_LIBRARY
.bss
args:
.space ARGSSPACE
#endif
/* Setup attibutes of stack and heap sections so they don't take up unnecessary room in the elf file */
.section .stack, "wa", %nobits
.section .stack_abt, "wa", %nobits
.section .stack_irq, "wa", %nobits
.section .stack_fiq, "wa", %nobits
.section .stack_svc, "wa", %nobits
.section .stack_und, "wa", %nobits
.section .heap, "wa", %nobits

43
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h
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@ -1,43 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\header.h
* \brief Generic header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef HEADER_H
#define HEADER_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include "../Boot/blt_conf.h" /* bootloader configuration */
#include "lpc2294.h" /* CPU register definitions */
#include "boot.h" /* bootloader interface driver */
#include "irq.h" /* IRQ driver */
#include "led.h" /* LED driver */
#include "timer.h" /* Timer driver */
#endif /* HEADER_H */
/*********************************** end of header.h ***********************************/

40
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp
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<!DOCTYPE CrossStudio_Project_File>
<solution Name="lpc2294_crossworks" target="8" version="2">
<project Name="demoprog_olimex_lpc_l2294_20mhz">
<configuration Name="Common" arm_long_calls="Yes" arm_simulator_memory_simulation_filename="$(PackagesDir)/targets/Philips_LPC210X/LPC2000SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="LPC22;0x20000;0x4000;0x400000;0x100000;0x0;0x0" arm_target_loader_parameter="20000000" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_preprocessor_definitions="__TARGET_PROCESSOR=LPC2294;OSCILLATOR_CLOCK_FREQUENCY=20000000" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../../../../Source;$(ProjectDir)/../../../../Source/ARM7_LPC2000;$(ProjectDir)/../../../../Source/ARM7_LPC2000/Crossworks" gcc_entry_point="_start" gcc_optimization_level="None" link_include_standard_libraries="Yes" link_include_startup_code="No" linker_DebugIO_enabled="Yes" linker_additional_files="$(PackagesDir)/lib/liblpc2000$(LibExt)$(LIB)" linker_additional_options="" linker_keep_symbols="_vectors;EntryFromProg;ExtFlashTestData" linker_output_format="srec" project_directory="" project_type="Executable"/>
<configuration Name="RAM" target_reset_script="RAMReset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(PackagesDir)/targets/Olimex_LPC_E2294/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" target_reset_script="FLASHReset()"/>
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<folder Name="Demo">
<folder Name="Prog">
<file file_name="../boot.c"/>
<file file_name="../boot.h"/>
<file file_name="../cstart.s"/>
<file file_name="../header.h"/>
<file file_name="../irq.c"/>
<file file_name="../irq.h"/>
<file file_name="../led.c"/>
<file file_name="../led.h"/>
<file file_name="../lpc2294.h"/>
<file file_name="../main.c"/>
<file file_name="../timer.c"/>
<file file_name="../timer.h"/>
<file file_name="../vectors.c"/>
</folder>
</folder>
</folder>
<folder Name="System Files">
<file file_name="$(PackagesDir)/targets/Olimex_LPC_E2294/LPC_E2294_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
</file>
<file file_name="../memory.x">
<configuration Name="Common" file_type="Linker Script"/>
</file>
</folder>
</project>
<configuration Name="ARM Flash Debug" inherited_configurations="ARM;Flash;Debug"/>
<configuration Name="ARM" Platform="ARM" arm_instruction_set="ARM" arm_library_instruction_set="ARM" c_preprocessor_definitions="__ARM" hidden="Yes"/>
<configuration Name="Flash" c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
</solution>

60
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@ -1,60 +0,0 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="lpc2294_crossworks" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;demoprog_olimex_lpc_l2294_20mhz" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;demoprog_olimex_lpc_l2294_20mhz;Source Files" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;demoprog_olimex_lpc_l2294_20mhz;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="lpc2294_crossworks;demoprog_olimex_lpc_l2294_20mhz;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
<Trace enabled="Yes" />
</TraceWindow>
<Watch1>
<Watches active="1" update="Never" />
</Watch1>
<Watch2>
<Watches active="0" update="Never" />
</Watch2>
<Watch3>
<Watches active="0" update="Never" />
</Watch3>
<Watch4>
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" y="45" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" left="0" selected="0" name="unnamed" top="45" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c" y="85" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c" left="0" selected="0" name="unnamed" top="85" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.h" y="40" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.h" left="0" selected="0" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\header.h" y="0" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\header.h" left="0" selected="1" name="unnamed" top="0" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_lpc_l2294_20mhz" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388479" debugSearchPath="" buildConfiguration="ARM Flash Debug" />
</session>

4
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Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\irq.c
* \brief IRQ driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data definitions
****************************************************************************************/
/** \brief Interrupt status before disabling. Used for global interrupt en/disable. */
static unsigned long oldInterruptStatus;
/** \brief Interrupt nesting counter. Used for global interrupt en/disable. */
static unsigned char interruptNesting = 0;
/************************************************************************************//**
** \brief Obtains current value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \return CPSR value.
**
****************************************************************************************/
static unsigned long IrqGetCPSR(void)
{
unsigned long retval;
__asm__ volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
return retval;
} /*** end of IrqGetCPSR ***/
/************************************************************************************//**
** \brief Update value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \param val CPSR value.
** \return none.
**
****************************************************************************************/
static void IrqSetCPSR(unsigned long val)
{
__asm__ volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
} /*** end of IrqSetCPSR ***/
/************************************************************************************//**
** \brief Enables the generation IRQ interrupts. Typically called once during
** software startup after completion of the initialization.
** \return none.
**
****************************************************************************************/
void IrqInterruptEnable(void)
{
unsigned _cpsr;
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr & ~0x00000080);
} /*** end of IrqInterruptEnable ***/
/************************************************************************************//**
** \brief Disables the generation IRQ interrupts and stores information on
** whether or not the interrupts were already disabled before explicitly
** disabling them with this function. Normally used as a pair together
** with IrqInterruptRestore during a critical section.
** \return none.
**
****************************************************************************************/
void IrqInterruptDisable(void)
{
unsigned long _cpsr;
if (interruptNesting == 0)
{
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr | 0x00000080);
oldInterruptStatus = _cpsr;
}
interruptNesting++;
} /*** end of IrqInterruptDisable ***/
/************************************************************************************//**
** \brief Restore the generation IRQ interrupts to the setting it had prior to
** calling IrqInterruptDisable. Normally used as a pair together with
** IrqInterruptDisable during a critical section.
** \return none.
**
****************************************************************************************/
void IrqInterruptRestore(void)
{
unsigned _cpsr;
interruptNesting--;
if (interruptNesting == 0)
{
_cpsr = IrqGetCPSR();
IrqSetCPSR((_cpsr & ~0x00000080) | (oldInterruptStatus & 0x00000080));
}
} /*** end of IrqInterruptRestore ***/
/*********************************** end of irq.c **************************************/

40
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h
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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\irq.h
* \brief IRQ driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef IRQ_H
#define IRQ_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void IrqInterruptEnable(void);
void IrqInterruptDisable(void);
void IrqInterruptRestore(void);
#endif /* IRQ_H */
/*********************************** end of irq.h **************************************/

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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\led.c
* \brief LED driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Toggle interval time in milliseconds. */
#define LED_TOGGLE_MS (500)
/************************************************************************************//**
** \brief Initializes the LED.
** \return none.
**
****************************************************************************************/
void LedInit(void)
{
/* set io pins for led P1.23 */
IO1DIR |= 0x00800000;
/* turn the led off */
IO1SET = 0x00800000;
} /*** end of LedInit ***/
/************************************************************************************//**
** \brief Toggles the LED at a fixed time interval.
** \return none.
**
****************************************************************************************/
void LedToggle(void)
{
static unsigned char led_toggle_state = 0;
static unsigned long timer_counter_last = 0;
unsigned long timer_counter_now;
/* check if toggle interval time passed */
timer_counter_now = TimerGet();
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
{
/* not yet time to toggle */
return;
}
/* determine toggle action */
if (led_toggle_state == 0)
{
led_toggle_state = 1;
/* turn the LED on */
IO1CLR = 0x00800000;
}
else
{
led_toggle_state = 0;
/* turn the LED off */
IO1SET = 0x00800000;
}
/* store toggle time to determine next toggle interval */
timer_counter_last = timer_counter_now;
} /*** end of LedToggle ***/
/*********************************** end of led.c **************************************/

39
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h
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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\led.h
* \brief LED driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedInit(void);
void LedToggle(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h
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@ -1,404 +0,0 @@
/****************************************************************************************
| Description: NXP LPC2294 register definitions
| File Name: lpc2294.h
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
#ifndef LPC2294_H
#define LPC2294_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* EXTERNAL MEMORY CONTROLLER (EMC) */
#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
/* External Interrupts */
#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
/* SMemory mapping control. */
#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
/* Phase Locked Loop (PLL) */
#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
/* Power Control */
#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
/* VPB Divider */
#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
/* Memory Accelerator Module (MAM) */
#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
/* Vectored Interrupt Controller (VIC) */
#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
/* Pin Connect Block */
#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
/* General Purpose Input/Output (GPIO) */
#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define U0RBR (*((volatile unsigned char *) 0xE000C000))
#define U0THR (*((volatile unsigned char *) 0xE000C000))
#define U0IER (*((volatile unsigned char *) 0xE000C004))
#define U0IIR (*((volatile unsigned char *) 0xE000C008))
#define U0FCR (*((volatile unsigned char *) 0xE000C008))
#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
#define U0LSR (*((volatile unsigned char *) 0xE000C014))
#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
#define U0DLL (*((volatile unsigned char *) 0xE000C000))
#define U0DLM (*((volatile unsigned char *) 0xE000C004))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define U1RBR (*((volatile unsigned char *) 0xE0010000))
#define U1THR (*((volatile unsigned char *) 0xE0010000))
#define U1IER (*((volatile unsigned char *) 0xE0010004))
#define U1IIR (*((volatile unsigned char *) 0xE0010008))
#define U1FCR (*((volatile unsigned char *) 0xE0010008))
#define U1LCR (*((volatile unsigned char *) 0xE001000C))
#define U1MCR (*((volatile unsigned char *) 0xE0010010))
#define U1LSR (*((volatile unsigned char *) 0xE0010014))
#define U1MSR (*((volatile unsigned char *) 0xE0010018))
#define U1SCR (*((volatile unsigned char *) 0xE001001C))
#define U1DLL (*((volatile unsigned char *) 0xE0010000))
#define U1DLM (*((volatile unsigned char *) 0xE0010004))
/* I2C (8/16 bit data bus) */
#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
#define I2STAT (*((volatile unsigned long *) 0xE001C004))
#define I2DAT (*((volatile unsigned long *) 0xE001C008))
#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
/* SPI (Serial Peripheral Interface) */
/* only for lpc210x*/
#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
/* Timer 0 */
#define T0IR (*((volatile unsigned long *) 0xE0004000))
#define T0TCR (*((volatile unsigned long *) 0xE0004004))
#define T0TC (*((volatile unsigned long *) 0xE0004008))
#define T0PR (*((volatile unsigned long *) 0xE000400C))
#define T0PC (*((volatile unsigned long *) 0xE0004010))
#define T0MCR (*((volatile unsigned long *) 0xE0004014))
#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
#define T0CCR (*((volatile unsigned long *) 0xE0004028))
#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
#define T0EMR (*((volatile unsigned long *) 0xE000403C))
/* Timer 1 */
#define T1IR (*((volatile unsigned long *) 0xE0008000))
#define T1TCR (*((volatile unsigned long *) 0xE0008004))
#define T1TC (*((volatile unsigned long *) 0xE0008008))
#define T1PR (*((volatile unsigned long *) 0xE000800C))
#define T1PC (*((volatile unsigned long *) 0xE0008010))
#define T1MCR (*((volatile unsigned long *) 0xE0008014))
#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
#define T1CCR (*((volatile unsigned long *) 0xE0008028))
#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
#define T1EMR (*((volatile unsigned long *) 0xE000803C))
/* Pulse Width Modulator (PWM) */
#define PWMIR (*((volatile unsigned long *) 0xE0014000))
#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
#define PWMTC (*((volatile unsigned long *) 0xE0014008))
#define PWMPR (*((volatile unsigned long *) 0xE001400C))
#define PWMPC (*((volatile unsigned long *) 0xE0014010))
#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
#define PWMLER (*((volatile unsigned long *) 0xE0014050))
/* A/D CONVERTER */
#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
/* Real Time Clock */
#define ILR (*((volatile unsigned char *) 0xE0024000))
#define CTC (*((volatile unsigned short*) 0xE0024004))
#define CCR (*((volatile unsigned char *) 0xE0024008))
#define CIIR (*((volatile unsigned char *) 0xE002400C))
#define AMR (*((volatile unsigned char *) 0xE0024010))
#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
#define SEC (*((volatile unsigned char *) 0xE0024020))
#define MIN (*((volatile unsigned char *) 0xE0024024))
#define HOUR (*((volatile unsigned char *) 0xE0024028))
#define DOM (*((volatile unsigned char *) 0xE002402C))
#define DOW (*((volatile unsigned char *) 0xE0024030))
#define DOY (*((volatile unsigned short*) 0xE0024034))
#define MONTH (*((volatile unsigned char *) 0xE0024038))
#define YEAR (*((volatile unsigned short*) 0xE002403C))
#define ALSEC (*((volatile unsigned char *) 0xE0024060))
#define ALMIN (*((volatile unsigned char *) 0xE0024064))
#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
#define ALDOM (*((volatile unsigned char *) 0xE002406C))
#define ALDOW (*((volatile unsigned char *) 0xE0024070))
#define ALDOY (*((volatile unsigned short*) 0xE0024074))
#define ALMON (*((volatile unsigned char *) 0xE0024078))
#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
#define PREINT (*((volatile unsigned short*) 0xE0024080))
#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
/* Watchdog */
#define WDMOD (*((volatile unsigned char *) 0xE0000000))
#define WDTC (*((volatile unsigned long *) 0xE0000004))
#define WDFEED (*((volatile unsigned char *) 0xE0000008))
#define WDTV (*((volatile unsigned long *) 0xE000000C))
#endif /* LPC2294_H */
/*********************************** end of lpc2294.h **********************************/

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Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c
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@ -1,164 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c
* \brief Demo program application source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
/****************************************************************************************
* Constant data declarations
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/** \brief Array with test data to program in the external flash.
* \details ROM data allocated to the external flash on the Olimex LPC-L2294 board to
* test the programming of data in external flash. To test programming with
* the additional external flash driver, build the bootloader and this program
* with configurable BOOT_NVM_HOOKS_ENABLE set to 1 in blt_conf.h
*/
__attribute__((section (".rodata2"))) const unsigned long ExtFlashTestData[] =
{
0x00000000, 0x11111111, 0x22222222, 0x33333333,
0x44444444, 0x55555555, 0x66666666, 0x77777777,
0x88888888, 0x99999999, 0xAAAAAAAA, 0xBBBBBBBB,
0xCCCCCCCC, 0xDDDDDDDD, 0xEEEEEEEE, 0xFFFFFFFF
};
#endif
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* initialize the microcontroller */
Init();
/* initialize the bootloader interface */
BootComInit();
/* start the infinite program loop */
while (1)
{
/* toggle LED with a fixed frequency */
LedToggle();
/* check for bootloader activation request */
BootComCheckActivationRequest();
}
/* program should never get here */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
** configured equal to Fpll. The GPIO pin of the status LED is configured
** as digital output.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
unsigned char m_sel; /* pll multiplier register value */
unsigned char pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
unsigned char p_sel_cnt; /* loop counter to find p_sel */
unsigned long f_cco; /* current controller oscillator */
/* calculate MSEL: M = round(Fcclk / Fosc) */
m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ;
/* value for the PLLCFG register is -1 */
m_sel--;
/* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
for (p_sel_cnt=0; p_sel_cnt<sizeof(pll_dividers)/sizeof(pll_dividers[0]); p_sel_cnt++)
{
/* check f_cco with this pll divider */
f_cco = BOOT_CPU_SYSTEM_SPEED_KHZ * 2 * pll_dividers[p_sel_cnt];
if ( (f_cco >= 156000) && (f_cco <= 320000) )
{
/* found a valid pll divider value */
break;
}
}
/* set multiplier and divider values */
PLLCFG = (p_sel_cnt << 5) | m_sel;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable the PLL */
PLLCON = 0x1;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* wait for the PLL to lock to set frequency */
while(!(PLLSTAT & 0x400)) { ; }
/* connect the PLL as the clock source */
PLLCON = 0x3;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
* Fcclk >= 60 MHz: 4 clock cycles
* Fcclk >= 40 MHz: 3 clock cycles
* Fcclk >= 20 MHz: 2 clock cycles
* Fcclk < 20 MHz: 1 clock cycle
*/
MAMCR = 0x0;
#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
MAMTIM = 4;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
MAMTIM = 3;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
MAMTIM = 2;
#else
MAMTIM = 1;
#endif
MAMCR = 0x2;
/* setting peripheral Clock (pclk) to System Clock (cclk) */
VPBDIV = 0x1;
/* init the led driver */
LedInit();
/* init the timer driver */
TimerInit();
/* enable IRQ's */
IrqInterruptEnable();
} /*** end of Init ***/
/*********************************** end of main.c *************************************/

356
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x
View File

@ -1,356 +0,0 @@
MEMORY
{
UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000
VPB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000
BANK3 (wx) : ORIGIN = 0x83000000, LENGTH = 0x01000000
BANK2 (wx) : ORIGIN = 0x82000000, LENGTH = 0x01000000
External_SRAM (wx) : ORIGIN = 0x81000000, LENGTH = 0x00100000
External_FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00200000
SRAM (wx) : ORIGIN = 0x40000200, LENGTH = 0x00003CE0
FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 0x0003E000
}
SECTIONS
{
__AHB_Peripherals_segment_start__ = 0xffe00000;
__AHB_Peripherals_segment_end__ = 0x00000000;
__VPB_Peripherals_segment_start__ = 0xe0000000;
__VPB_Peripherals_segment_end__ = 0xe0200000;
__BANK3_segment_start__ = 0x83000000;
__BANK3_segment_end__ = 0x84000000;
__BANK2_segment_start__ = 0x82000000;
__BANK2_segment_end__ = 0x83000000;
__External_SRAM_segment_start__ = 0x81000000;
__External_SRAM_segment_end__ = 0x81100000;
__External_FLASH_segment_start__ = 0x80000000;
__External_FLASH_segment_end__ = 0x80200000;
__SRAM_segment_start__ = 0x40002000;
__SRAM_segment_end__ = 0x40003EE0;
__FLASH_segment_start__ = 0x00002000;
__FLASH_segment_end__ = 0x00040000;
__STACKSIZE__ = 1024;
__STACKSIZE_IRQ__ = 256;
__STACKSIZE_FIQ__ = 256;
__STACKSIZE_SVC__ = 256;
__STACKSIZE_ABT__ = 256;
__STACKSIZE_UND__ = 256;
__HEAPSIZE__ = 1024;
__text2_load_start__ = ALIGN(__External_FLASH_segment_start__ , 4);
.text2 ALIGN(__External_FLASH_segment_start__ , 4) : AT(ALIGN(__External_FLASH_segment_start__ , 4))
{
__text2_start__ = .;
*(.text2 .text2.*)
}
__text2_end__ = __text2_start__ + SIZEOF(.text2);
__text2_load_end__ = __text2_end__;
. = ASSERT(__text2_end__ >= __External_FLASH_segment_start__ && __text2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .text2 is too large to fit in External_FLASH memory segment");
__rodata2_load_start__ = ALIGN(__text2_end__ , 4);
.rodata2 ALIGN(__text2_end__ , 4) : AT(ALIGN(__text2_end__ , 4))
{
__rodata2_start__ = .;
*(.rodata2 .rodata2.*)
}
__rodata2_end__ = __rodata2_start__ + SIZEOF(.rodata2);
__rodata2_load_end__ = __rodata2_end__;
. = ASSERT(__rodata2_end__ >= __External_FLASH_segment_start__ && __rodata2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .rodata2 is too large to fit in External_FLASH memory segment");
__data2_load_start__ = ALIGN(__rodata2_end__ , 4);
.data2 ALIGN(__External_SRAM_segment_start__ , 4) : AT(ALIGN(__rodata2_end__ , 4))
{
__data2_start__ = .;
*(.data2 .data2.*)
}
__data2_end__ = __data2_start__ + SIZEOF(.data2);
__data2_load_end__ = __data2_load_start__ + SIZEOF(.data2);
__External_FLASH_segment_used_end__ = ALIGN(__rodata2_end__ , 4) + SIZEOF(.data2);
. = ASSERT((__data2_load_start__ + SIZEOF(.data2)) >= __External_FLASH_segment_start__ && (__data2_load_start__ + SIZEOF(.data2)) <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .data2 is too large to fit in External_FLASH memory segment");
.data2_run ALIGN(__External_SRAM_segment_start__ , 4) (NOLOAD) :
{
__data2_run_start__ = .;
. = MAX(__data2_run_start__ + SIZEOF(.data2), .);
}
__data2_run_end__ = __data2_run_start__ + SIZEOF(.data2_run);
__data2_run_load_end__ = __data2_run_end__;
. = ASSERT(__data2_run_end__ >= __External_SRAM_segment_start__ && __data2_run_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .data2_run is too large to fit in External_SRAM memory segment");
__bss2_load_start__ = ALIGN(__data2_run_end__ , 4);
.bss2 ALIGN(__data2_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data2_run_end__ , 4))
{
__bss2_start__ = .;
*(.bss2 .bss2.*)
}
__bss2_end__ = __bss2_start__ + SIZEOF(.bss2);
__bss2_load_end__ = __bss2_end__;
__External_SRAM_segment_used_end__ = ALIGN(__data2_run_end__ , 4) + SIZEOF(.bss2);
. = ASSERT(__bss2_end__ >= __External_SRAM_segment_start__ && __bss2_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .bss2 is too large to fit in External_SRAM memory segment");
__vectors_ram_load_start__ = __SRAM_segment_start__;
.vectors_ram __SRAM_segment_start__ (NOLOAD) : AT(__SRAM_segment_start__)
{
__vectors_ram_start__ = .;
*(.vectors_ram .vectors_ram.*)
. = MAX(__vectors_ram_start__ + 0x0000003C , .);
}
__vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
__vectors_ram_load_end__ = __vectors_ram_end__;
. = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
__vectors_load_start__ = __FLASH_segment_start__;
.vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
{
__vectors_start__ = .;
*(.vectors .vectors.*)
}
__vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
__vectors_load_end__ = __vectors_end__;
. = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
__init_load_start__ = ALIGN(__vectors_end__ , 4);
.init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
{
__init_start__ = .;
*(.init .init.*)
}
__init_end__ = __init_start__ + SIZEOF(.init);
__init_load_end__ = __init_end__;
. = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
__text_load_start__ = ALIGN(__init_end__ , 4);
.text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
{
__text_start__ = .;
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
}
__text_end__ = __text_start__ + SIZEOF(.text);
__text_load_end__ = __text_end__;
. = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
__dtors_load_start__ = ALIGN(__text_end__ , 4);
.dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
{
__dtors_start__ = .;
KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
}
__dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
__dtors_load_end__ = __dtors_end__;
. = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
__ctors_load_start__ = ALIGN(__dtors_end__ , 4);
.ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
{
__ctors_start__ = .;
KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
}
__ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
__ctors_load_end__ = __ctors_end__;
. = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
__rodata_load_start__ = ALIGN(__ctors_end__ , 4);
.rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
{
__rodata_start__ = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
}
__rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
__rodata_load_end__ = __rodata_end__;
. = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
__data_load_start__ = ALIGN(__rodata_end__ , 4);
.data ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
{
__data_start__ = .;
*(.data .data.* .gnu.linkonce.d.*)
}
__data_end__ = __data_start__ + SIZEOF(.data);
__data_load_end__ = __data_load_start__ + SIZEOF(.data);
. = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
.data_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
{
__data_run_start__ = .;
. = MAX(__data_run_start__ + SIZEOF(.data), .);
}
__data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
__data_run_load_end__ = __data_run_end__;
. = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .data_run is too large to fit in SRAM memory segment");
__bss_load_start__ = ALIGN(__data_run_end__ , 4);
.bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
{
__bss_start__ = .;
*(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
}
__bss_end__ = __bss_start__ + SIZEOF(.bss);
__bss_load_end__ = __bss_end__;
. = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .bss is too large to fit in SRAM memory segment");
__non_init_load_start__ = ALIGN(__bss_end__ , 4);
.non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
{
__non_init_start__ = .;
*(.non_init .non_init.*)
}
__non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
__non_init_load_end__ = __non_init_end__;
. = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .non_init is too large to fit in SRAM memory segment");
__heap_load_start__ = ALIGN(__non_init_end__ , 4);
.heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
{
__heap_start__ = .;
*(.heap .heap.*)
. = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
}
__heap_end__ = __heap_start__ + SIZEOF(.heap);
__heap_load_end__ = __heap_end__;
. = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .heap is too large to fit in SRAM memory segment");
__stack_load_start__ = ALIGN(__heap_end__ , 4);
.stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
{
__stack_start__ = .;
*(.stack .stack.*)
. = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
}
__stack_end__ = __stack_start__ + SIZEOF(.stack);
__stack_load_end__ = __stack_end__;
. = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack is too large to fit in SRAM memory segment");
__stack_irq_load_start__ = ALIGN(__stack_end__ , 4);
.stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
{
__stack_irq_start__ = .;
*(.stack_irq .stack_irq.*)
. = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4);
}
__stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
__stack_irq_load_end__ = __stack_irq_end__;
. = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_irq is too large to fit in SRAM memory segment");
__stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4);
.stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_irq_end__ , 4))
{
__stack_fiq_start__ = .;
*(.stack_fiq .stack_fiq.*)
. = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4);
}
__stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
__stack_fiq_load_end__ = __stack_fiq_end__;
. = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_fiq is too large to fit in SRAM memory segment");
__stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4);
.stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_fiq_end__ , 4))
{
__stack_svc_start__ = .;
*(.stack_svc .stack_svc.*)
. = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4);
}
__stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
__stack_svc_load_end__ = __stack_svc_end__;
. = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_svc is too large to fit in SRAM memory segment");
__stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4);
.stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_svc_end__ , 4))
{
__stack_abt_start__ = .;
*(.stack_abt .stack_abt.*)
. = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4);
}
__stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
__stack_abt_load_end__ = __stack_abt_end__;
. = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_abt is too large to fit in SRAM memory segment");
__stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4);
.stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_abt_end__ , 4))
{
__stack_und_start__ = .;
*(.stack_und .stack_und.*)
. = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4);
}
__stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
__stack_und_load_end__ = __stack_und_end__;
. = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_und is too large to fit in SRAM memory segment");
__fast_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
.fast ALIGN(__stack_und_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
{
__fast_start__ = .;
*(.fast .fast.*)
}
__fast_end__ = __fast_start__ + SIZEOF(.fast);
__fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
__FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.fast);
. = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
.fast_run ALIGN(__stack_und_end__ , 4) (NOLOAD) :
{
__fast_run_start__ = .;
. = MAX(__fast_run_start__ + SIZEOF(.fast), .);
}
__fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
__fast_run_load_end__ = __fast_run_end__;
__SRAM_segment_used_end__ = ALIGN(__stack_und_end__ , 4) + SIZEOF(.fast_run);
. = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .fast_run is too large to fit in SRAM memory segment");
}

7
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/prog.dox
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@ -1,7 +0,0 @@
/**
\defgroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks User Program
\brief User Program.
\ingroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
*/

112
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c
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@ -1,112 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\timer.c
* \brief Timer driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static unsigned long millisecond_counter;
/****************************************************************************************
* External functions
****************************************************************************************/
extern void TIMER0_ISR(void);
/************************************************************************************//**
** \brief Initializes the timer.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* configure timer0 as 1 ms software output compare */
T0MR0 = BOOT_CPU_SYSTEM_SPEED_KHZ-1;
/* enable interrupt and automatic reset upon compare */
T0MCR = 0x01 | 0x02;
/* enable the output compare */
T0TCR = 0x01;
/* set the interrupt service routine for the output compare event */
VICVectAddr0 = (unsigned long)TIMER0_ISR;
/* connect vectored IRQ slot 0 to Timer0's channel 4 */
VICVectCntl0 = 0x20 | 4;
/* enable the timer0 interrupt */
VICIntEnable = 0x10;
/* reset the millisecond counter */
TimerSet(0);
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Updates the millisecond timer. Should be called every millisecond by
** the timer interrupt service routine.
** \return none.
**
****************************************************************************************/
void TimerUpdate(void)
{
/* increment the millisecond counter */
millisecond_counter++;
} /*** end of TimerUpdate ***/
/************************************************************************************//**
** \brief Sets the initial counter value of the millisecond timer.
** \param timer_value initialize value of the millisecond timer.
** \return none.
**
****************************************************************************************/
void TimerSet(unsigned long timer_value)
{
/* set the millisecond counter */
millisecond_counter = timer_value;
} /*** end of TimerSet ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
unsigned long TimerGet(void)
{
/* read and return the millisecond counter value */
return millisecond_counter;
} /*** end of TimerGet ***/
/*********************************** end of timer.c ************************************/

41
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h
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@ -1,41 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\timer.h
* \brief Timer driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TIMER_H
#define TIMER_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void TimerInit(void);
void TimerUpdate(void);
void TimerSet(unsigned long timer_value);
unsigned long TimerGet(void);
#endif /* TIMER_H */
/*********************************** end of timer.h ************************************/

57
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c
View File

@ -1,57 +0,0 @@
/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\vectors.c
* \brief Demo program interrupt vectors source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void __attribute__ ((interrupt("IRQ"))) TIMER0_ISR(void);
/************************************************************************************//**
** \brief Timer0 exception routine.
** \return none.
**
****************************************************************************************/
void TIMER0_ISR(void)
{
/* clear the interrupt flag */
T0IR = 0x01;
/* acknowledge interrupt */
VICVectAddr = 0;
/* process time tick */
TimerUpdate();
} /*** end of TIMER0_ISR ***/
/*********************************** end of vectors.c **********************************/

8
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/demo.dox
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@ -1,8 +0,0 @@
/**
\defgroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks Demo for Olimex LPC-L2294/Crossworks
\brief Preconfigured programs for the Olimex LPC-L2294 and the Crossworks IDE.
\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos
for detailed getting started instructions.
*/

BIN
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.elf
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Binary file not shown.

1973
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.map
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File diff suppressed because it is too large Load Diff

835
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.srec
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@ -1,426 +1,413 @@
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28
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/EFM32G880_crossworks.hzs
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@ -1,19 +1,22 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x4000" numColumns="8" sizeText="128" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x4000" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="128" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="EFM32G880_crossworks" name="unnamed" />
@ -21,20 +24,18 @@
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo;Boot" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo;Boot;Lib" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo;Boot;Lib;Cmsis" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_efm32g880" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_efm32g880" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_efm32g880" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_efm32g880" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -53,8 +54,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\users\voorburg\desktop\target\demo\armcm3_efm32_olimex_em32g880f128stk_crossworks\boot\lib\cmsis\cm3\devicesupport\energymicro\efm32\efm32.h" y="499" path="C:\users\voorburg\desktop\target\demo\armcm3_efm32_olimex_em32g880f128stk_crossworks\boot\lib\cmsis\cm3\devicesupport\energymicro\efm32\efm32.h" left="18" selected="0" name="unnamed" top="485" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Users\voorburg\Desktop\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" y="0" path="C:\Users\voorburg\Desktop\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" left="18" selected="1" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Default" x="0" debugPath="../main.c" y="0" path="../main.c" left="0" selected="1" name="unnamed" top="0" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_olimex_efm32g880" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:\Work\software\OpenBLT\Target\Source\ARMCM3_EFM32\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
<ARMCrossStudioWindow activeProject="openbtl_olimex_efm32g880" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:/Work/software/OpenBLT/Target/Source/ARMCM3_EFM32/Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
</session>

2
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/readme.txt
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@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

BIN
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.elf
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4085
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.map
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822
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.srec
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25
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/EFM32G880_crossworks.hzs
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@ -1,19 +1,22 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="EFM32G880_crossworks" name="unnamed" />
@ -24,16 +27,16 @@
<ProjectSessionItem path="EFM32G880_crossworks;demoprog_olimex_efm32g880;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -52,7 +55,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Users\voorburg\Desktop\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" y="0" path="C:\Users\voorburg\Desktop\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Default" x="0" debugPath="../main.c" y="0" path="../main.c" left="0" selected="1" name="unnamed" top="0" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_efm32g880" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
<ARMCrossStudioWindow activeProject="demoprog_olimex_efm32g880" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:/usr/feaser/software/OpenBLT/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
</session>

2
Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/readme.txt
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@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.elf
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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.map
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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.srec
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2
Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/readme.txt
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@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
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@ -1,106 +1,172 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="stm32f103_crossworks" target="8" version="2">
<project Name="openblt_olimex_stm32h103">
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="-I./..;-I./../lib/CMSIS/CM3/CoreSupport;-I./../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x;-I./../lib/USB_FS_DEVICE/inc;-I./../../../../Source;-I./../../../../Source/ARMCM3_STM32F1;-I./../../../../Source/ARMCM3_STM32F1/Crossworks" c_user_include_directories="$(TargetsDir)/STM32/include" gcc_optimization_level="Level 1" link_include_standard_libraries="Yes" linker_keep_symbols="_vectors;EntryFromProg" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)" target_reset_script="Reset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
<configuration
Name="Common"
Placement="Flash"
Target="STM32F103RB"
arm_architecture="v7M"
arm_core_type="Cortex-M3"
arm_linker_heap_size="128"
arm_linker_jtag_pad_pre_dr="1"
arm_linker_jtag_pad_pre_ir="5"
arm_linker_process_stack_size="0"
arm_linker_stack_size="128"
arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll"
arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000"
arm_target_debug_interface_type="ADIv5"
arm_target_loader_applicable_loaders="Flash"
arm_target_loader_default_loader="Flash"
arm_target_loader_parameter="8000000"
arm_use_gcc_libraries="Yes"
build_intermediate_directory="$(Configuration)/../../obj"
build_output_directory="$(ProjectDir)/../bin"
c_only_additional_options="-I./..;-I./../lib/CMSIS/CM3/CoreSupport;-I./../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x;-I./../lib/USB_FS_DEVICE/inc;-I./../../../../Source;-I./../../../../Source/ARMCM3_STM32F1;-I./../../../../Source/ARMCM3_STM32F1/Crossworks"
c_preprocessor_definitions=""
c_user_include_directories="$(TargetsDir)/STM32/include"
gcc_optimization_level="Level 1"
link_include_standard_libraries="Yes"
linker_keep_symbols="_vectors;EntryFromProg"
linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml"
linker_output_format="srec"
linker_printf_enabled="No"
linker_printf_width_precision_supported="No"
linker_scanf_enabled="No"
linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml"
oscillator_frequency="8MHz"
project_directory=""
project_type="Executable"
property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml"
target_get_partname_script="GetPartName()"
target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)"
target_reset_script="Reset()" />
<configuration
Name="Flash"
arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf"
arm_target_flash_loader_type="LIBMEM RPC Loader"
arm_target_loader_can_lock_all="No"
arm_target_loader_can_lock_range="No"
arm_target_loader_can_unlock_all="No"
arm_target_loader_can_unlock_range="No"
target_reset_script="FLASHReset()" />
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<folder Name="Demo">
<folder Name="Boot" file_name="">
<file file_name="../hooks.c"/>
<file file_name="../main.c"/>
<folder Name="Boot">
<file file_name="../hooks.c" />
<file file_name="../main.c" />
<folder Name="lib">
<folder Name="CoreSupport">
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.c"/>
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.h"/>
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.h" />
</folder>
<folder Name="DeviceSupport">
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" />
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c" />
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h" />
</folder>
<folder Name="UsbFullspeed">
<file file_name="../lib/USB_FS_DEVICE/inc/usb_core.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_def.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_init.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_int.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_lib.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_mem.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_regs.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_sil.h"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_type.h"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_core.c"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_init.c"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_int.c"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_mem.c"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_regs.c"/>
<file file_name="../lib/USB_FS_DEVICE/src/usb_sil.c"/>
<file file_name="../lib/USB_FS_DEVICE/inc/usb_core.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_def.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_init.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_int.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_lib.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_mem.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_regs.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_sil.h" />
<file file_name="../lib/USB_FS_DEVICE/inc/usb_type.h" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_core.c" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_init.c" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_int.c" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_mem.c" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_regs.c" />
<file file_name="../lib/USB_FS_DEVICE/src/usb_sil.c" />
</folder>
</folder>
<file file_name="../usb_conf.h"/>
<file file_name="../usb_desc.c"/>
<file file_name="../usb_desc.h"/>
<file file_name="../usb_endp.c"/>
<file file_name="../usb_istr.c"/>
<file file_name="../usb_istr.h"/>
<file file_name="../usb_prop.c"/>
<file file_name="../usb_prop.h"/>
<file file_name="../usb_pwr.c"/>
<file file_name="../usb_pwr.h"/>
<file file_name="../blt_conf.h"/>
<file file_name="../usb_conf.h" />
<file file_name="../usb_desc.c" />
<file file_name="../usb_desc.h" />
<file file_name="../usb_endp.c" />
<file file_name="../usb_istr.c" />
<file file_name="../usb_istr.h" />
<file file_name="../usb_prop.c" />
<file file_name="../usb_prop.h" />
<file file_name="../usb_pwr.c" />
<file file_name="../usb_pwr.h" />
<file file_name="../blt_conf.h" />
</folder>
</folder>
<folder Name="Source" file_name="">
<folder Name="ARMCM3_STM32F1" file_name="">
<folder Name="Crossworks" file_name="">
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cpu_comp.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cstart.s"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c"/>
<folder Name="Source">
<folder Name="ARMCM3_STM32F1">
<folder Name="Crossworks">
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cpu_comp.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cstart.s" />
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c" />
</folder>
<file file_name="../../../../Source/ARMCM3_STM32F1/can.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/cpu.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.h"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/nvm.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/timer.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/types.h"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/uart.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/usb.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/can.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/cpu.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.h" />
<file file_name="../../../../Source/ARMCM3_STM32F1/nvm.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/timer.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/types.h" />
<file file_name="../../../../Source/ARMCM3_STM32F1/uart.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/usb.c" />
</folder>
<file file_name="../../../../Source/assert.c"/>
<file file_name="../../../../Source/assert.h"/>
<file file_name="../../../../Source/backdoor.c"/>
<file file_name="../../../../Source/backdoor.h"/>
<file file_name="../../../../Source/boot.c"/>
<file file_name="../../../../Source/boot.h"/>
<file file_name="../../../../Source/com.c"/>
<file file_name="../../../../Source/com.h"/>
<file file_name="../../../../Source/cop.c"/>
<file file_name="../../../../Source/cop.h"/>
<file file_name="../../../../Source/plausibility.h"/>
<file file_name="../../../../Source/xcp.c"/>
<file file_name="../../../../Source/xcp.h"/>
<file file_name="../../../../Source/can.h"/>
<file file_name="../../../../Source/cpu.h"/>
<file file_name="../../../../Source/nvm.h"/>
<file file_name="../../../../Source/timer.h"/>
<file file_name="../../../../Source/uart.h"/>
<file file_name="../../../../Source/usb.h"/>
<file file_name="../../../../Source/assert.c" />
<file file_name="../../../../Source/assert.h" />
<file file_name="../../../../Source/backdoor.c" />
<file file_name="../../../../Source/backdoor.h" />
<file file_name="../../../../Source/boot.c" />
<file file_name="../../../../Source/boot.h" />
<file file_name="../../../../Source/com.c" />
<file file_name="../../../../Source/com.h" />
<file file_name="../../../../Source/cop.c" />
<file file_name="../../../../Source/cop.h" />
<file file_name="../../../../Source/plausibility.h" />
<file file_name="../../../../Source/xcp.c" />
<file file_name="../../../../Source/xcp.h" />
<file file_name="../../../../Source/can.h" />
<file file_name="../../../../Source/cpu.h" />
<file file_name="../../../../Source/nvm.h" />
<file file_name="../../../../Source/timer.h" />
<file file_name="../../../../Source/uart.h" />
<file file_name="../../../../Source/usb.h" />
</folder>
</folder>
<folder Name="System Files" file_name="">
<folder Name="System Files">
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/memory.x">
<configuration Name="Common" file_type="Linker Script"/>
<configuration Name="Common" file_type="Linker Script" />
</file>
</folder>
<configuration Name="Debug" c_only_additional_options=""/>
<configuration Name="Debug" c_only_additional_options="" />
</project>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
<configuration
Name="THUMB"
Platform="ARM"
arm_instruction_set="THUMB"
arm_library_instruction_set="THUMB"
c_preprocessor_definitions="__THUMB"
hidden="Yes" />
<configuration
Name="Debug"
build_debug_information="Yes"
c_preprocessor_definitions="DEBUG"
gcc_optimization_level="None"
hidden="Yes"
link_include_startup_code="No" />
<configuration
Name="THUMB Release"
inherited_configurations="THUMB;Release" />
<configuration
Name="Release"
build_debug_information="No"
c_additional_options="-g1"
c_preprocessor_definitions="NDEBUG"
gcc_optimization_level="Level 1"
hidden="Yes"
link_include_startup_code="No" />
</solution>

57
Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
View File

@ -1,23 +1,28 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<Breakpoints>
<Exceptions set="MemManage;UsageFault_Coprocessor;UsageFault_CheckingError;UsageFault_StateError;BusFault;ExceptionEntryReturnFault;HardFault" />
</Breakpoints>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x08004004" numColumns="8" sizeText="4" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x08004004" numColumns="8" sizeText="4" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x08004004" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="4" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x08004004" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="4" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32h103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32h103" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
@ -25,22 +30,28 @@
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Demo;Boot" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Demo;Boot;lib" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Demo;Boot;lib;CoreSupport" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Demo;Boot;lib;DeviceSupport" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Source" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Source;ARMCM3_STM32F1" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32h103;Source Files;Source;ARMCM3_STM32F1;Crossworks" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU - Current Context;CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openblt_olimex_stm32h103" />
<RegisterWindow openNodes="CPU" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openblt_olimex_stm32h103" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU - Current Context;CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openblt_olimex_stm32h103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openblt_olimex_stm32h103" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU - Current Context;CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openblt_olimex_stm32h103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openblt_olimex_stm32h103" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU - Current Context;CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openblt_olimex_stm32h103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32h103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openblt_olimex_stm32h103" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -48,8 +59,8 @@
</TraceWindow>
<Watch1>
<Watches active="1" update="Never" >
<Watchpoint linenumber="0" radix="-1" name="fifoCtrl[0]" expression="fifoCtrl[0]" filename="" />
<Watchpoint linenumber="0" radix="-1" name="fifoPipeBulkIN" expression="fifoPipeBulkIN" filename="" />
<Watchpoint evalMode="0" linenumber="0" numelements="0" radix="-1" name="fifoCtrl[0]" list="" expression="fifoCtrl[0]" filename="../ide" />
<Watchpoint evalMode="0" linenumber="0" numelements="0" radix="-1" name="fifoPipeBulkIN" list="" expression="fifoPipeBulkIN" filename="../ide" />
</Watches>
</Watch1>
<Watch2>
@ -62,7 +73,9 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32H103_Crossworks\Boot\main.c" y="48" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32H103_Crossworks\Boot\main.c" left="0" selected="1" name="unnamed" top="4" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="../main.c" y="48" path="../main.c" left="0" selected="1" name="unnamed" top="9" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Default" x="0" debugPath="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" y="64" path="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" left="0" selected="0" name="unnamed" top="31" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="" x="0" debugPath="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c" y="30" path="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c" left="0" selected="0" name="unnamed" top="17" />
</Files>
<ARMCrossStudioWindow activeProject="openblt_olimex_stm32h103" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:\Work\software\OpenBLT\Target\Source\ARMCM3_STM32F1\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
<ARMCrossStudioWindow activeProject="openblt_olimex_stm32h103" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:/Work/software/OpenBLT/Target/Source/ARMCM3_STM32F1/Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="3711" debugSearchPath="" buildConfiguration="THUMB Debug" />
</session>

784
Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
View File

@ -1,784 +0,0 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<hr>
<h2>Cortex-M3 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<h2>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a globel variable is used. A simple mechansim detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
</p>
<pre>
extern volatile int ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<h2>ITM Debug Support in uVision</h2>
<p>
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
display the debug data.
</p>
<p>Direction microcontroller system -&gt; uVision:</p>
<ul>
<li>
Characters received via ITM communication channel 0 are written in a printf style
to <strong>Debug (printf) Viewer</strong> window.
</li>
</ul>
<p>Direction uVision -&gt; microcontroller system:</p>
<ul>
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
</li>
</ul>
<h2>RTX Kernel awareness in uVision</h2>
<p>
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
No format overhead is necessary.<br>
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
to ITM communication channel 31.
</p>
<p>Following RTX events are traced:</p>
<ul>
<li>Task Create / Delete event
<ol>
<li>32 bit access. Task start address is transmitted</li>
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
High byte holds Create/Delete flag, Low byte holds TASK ID.
</li>
</ol>
</li>
<li>Task switch event
<ol>
<li>8 bit access. Task ID of current task is transmitted</li>
</ol>
</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
</li>
</ul>
<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
<hr>
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
All rights reserved.<br>
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
</p>
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<body>
<h1>Changes to CMSIS version V1.20</h1>
<hr>
<h2>1. Removed CMSIS Middelware packages</h2>
<p>
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
</p>
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h2>3. Changed startup concept</h2>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h3>Changed startup concept</h3>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h2>4. Advanced Debug Functions</h2>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h2>5. Core Register Bit Definitions</h2>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
<h2>7. DoxyGen Tags</h2>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h2>8. Folder Structure</h2>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2>9. Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
<li>
<p>
Removing core_cm3.c and core_cm0.c.
</p>
<p>
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
appropriate compiler intrinsics.
</p>
</li>
</ul>
<h2>10. Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> for ARM toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for GNU toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for IAR toolchain are provided.
</li>
<li>
No <strong>Tasking</strong> projects are provided yet.
</li>
</ul>

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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/readme.txt
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@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

209
Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
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@ -1,98 +1,144 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="stm32f103_crossworks" target="8" version="2">
<project Name="demoprog_olimex_stm32h103">
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_long_calls="No" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="" c_preprocessor_definitions="USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib/stdperiphlib;$(ProjectDir)/../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/CoreSupport;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x" gcc_optimization_level="None" link_include_standard_libraries="Yes" linker_keep_symbols="_vectors" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)" target_reset_script="Reset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
<configuration
Name="Common"
Placement="Flash"
Target="STM32F103RB"
arm_architecture="v7M"
arm_core_type="Cortex-M3"
arm_linker_heap_size="128"
arm_linker_jtag_pad_pre_dr="1"
arm_linker_jtag_pad_pre_ir="5"
arm_linker_process_stack_size="0"
arm_linker_stack_size="128"
arm_long_calls="No"
arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll"
arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000"
arm_target_debug_interface_type="ADIv5"
arm_target_loader_applicable_loaders="Flash"
arm_target_loader_default_loader="Flash"
arm_target_loader_parameter="8000000"
arm_use_gcc_libraries="Yes"
build_intermediate_directory="$(Configuration)/../../obj"
build_output_directory="$(ProjectDir)/../bin"
c_only_additional_options=""
c_preprocessor_definitions="USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3"
c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib/stdperiphlib;$(ProjectDir)/../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/CoreSupport;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x"
gcc_optimization_level="None"
link_include_standard_libraries="Yes"
linker_keep_symbols="_vectors"
linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml"
linker_output_format="srec"
linker_printf_enabled="No"
linker_printf_width_precision_supported="No"
linker_scanf_enabled="No"
linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml"
oscillator_frequency="8MHz"
project_directory=""
project_type="Executable"
property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml"
target_get_partname_script="GetPartName()"
target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)"
target_reset_script="Reset()" />
<configuration
Name="Flash"
arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf"
arm_target_flash_loader_type="LIBMEM RPC Loader"
arm_target_loader_can_lock_all="No"
arm_target_loader_can_lock_range="No"
arm_target_loader_can_unlock_all="No"
arm_target_loader_can_unlock_range="No"
target_reset_script="FLASHReset()" />
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<folder Name="Demo">
<folder Name="Prog">
<file file_name="../cstart.s"/>
<file file_name="../header.h"/>
<file file_name="../led.c"/>
<file file_name="../led.h"/>
<file file_name="../main.c"/>
<file file_name="../timer.c"/>
<file file_name="../timer.h"/>
<file file_name="../vectors.c"/>
<file file_name="../cstart.s" />
<file file_name="../header.h" />
<file file_name="../led.c" />
<file file_name="../led.h" />
<file file_name="../main.c" />
<file file_name="../timer.c" />
<file file_name="../timer.h" />
<file file_name="../vectors.c" />
</folder>
</folder>
</folder>
<folder Name="System Files">
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="../memory.x">
<configuration Name="Common" file_type="Linker Script"/>
<configuration Name="Common" file_type="Linker Script" />
</file>
</folder>
<configuration Name="Debug" c_only_additional_options=""/>
<configuration Name="Debug" c_only_additional_options="" />
<folder Name="Library Files">
<file file_name="../lib/stdperiphlib/stm32f10x_conf.h"/>
<file file_name="../lib/stdperiphlib/stm32f10x_conf.h" />
<folder Name="STM32F10x_StdPeriph_Driver">
<folder Name="inc">
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h" />
</folder>
<folder Name="src">
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c" />
</folder>
</folder>
<folder Name="CMSIS">
<folder Name="CM3">
<folder Name="CoreSupport">
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h" />
</folder>
<folder Name="DeviceSupport">
<folder Name="ST">
<folder Name="STM32F10x">
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" />
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c" />
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h" />
</folder>
</folder>
</folder>
@ -100,9 +146,30 @@
</folder>
</folder>
</project>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
<configuration
Name="THUMB"
Platform="ARM"
arm_instruction_set="THUMB"
arm_library_instruction_set="THUMB"
c_preprocessor_definitions="__THUMB"
hidden="Yes" />
<configuration
Name="Debug"
build_debug_information="Yes"
c_preprocessor_definitions="DEBUG"
gcc_optimization_level="None"
hidden="Yes"
link_include_startup_code="No" />
<configuration
Name="THUMB Release"
inherited_configurations="THUMB;Release" />
<configuration
Name="Release"
build_debug_information="No"
c_additional_options="-g1"
c_preprocessor_definitions="NDEBUG"
gcc_optimization_level="Level 1"
hidden="Yes"
link_include_startup_code="No" />
</solution>

25
Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
View File

@ -1,19 +1,22 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0" numColumns="8" sizeText="32" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="32" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
@ -23,16 +26,16 @@
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32h103;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="CPU" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -51,7 +54,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32H103_Crossworks\Prog\main.c" y="19" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32H103_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="15" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="../main.c" y="19" path="../main.c" left="0" selected="1" name="unnamed" top="15" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_stm32h103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
<ARMCrossStudioWindow activeProject="demoprog_olimex_stm32h103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:/usr/feaser/software/OpenBLT/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_Crossworks/Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
</session>

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Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
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@ -1,784 +0,0 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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<html>
<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<hr>
<h2>Cortex-M3 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<h2>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a globel variable is used. A simple mechansim detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
</p>
<pre>
extern volatile int ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<h2>ITM Debug Support in uVision</h2>
<p>
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
display the debug data.
</p>
<p>Direction microcontroller system -&gt; uVision:</p>
<ul>
<li>
Characters received via ITM communication channel 0 are written in a printf style
to <strong>Debug (printf) Viewer</strong> window.
</li>
</ul>
<p>Direction uVision -&gt; microcontroller system:</p>
<ul>
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
</li>
</ul>
<h2>RTX Kernel awareness in uVision</h2>
<p>
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
No format overhead is necessary.<br>
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
to ITM communication channel 31.
</p>
<p>Following RTX events are traced:</p>
<ul>
<li>Task Create / Delete event
<ol>
<li>32 bit access. Task start address is transmitted</li>
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
High byte holds Create/Delete flag, Low byte holds TASK ID.
</li>
</ol>
</li>
<li>Task switch event
<ol>
<li>8 bit access. Task ID of current task is transmitted</li>
</ol>
</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
</li>
</ul>
<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
<hr>
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
All rights reserved.<br>
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
</p>
</body>
</html>

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<html>
<head>
<title>CMSIS Changes</title>
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<body>
<h1>Changes to CMSIS version V1.20</h1>
<hr>
<h2>1. Removed CMSIS Middelware packages</h2>
<p>
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
</p>
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h2>3. Changed startup concept</h2>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h3>Changed startup concept</h3>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h2>4. Advanced Debug Functions</h2>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h2>5. Core Register Bit Definitions</h2>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
<h2>7. DoxyGen Tags</h2>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h2>8. Folder Structure</h2>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2>9. Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
<li>
<p>
Removing core_cm3.c and core_cm0.c.
</p>
<p>
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
appropriate compiler intrinsics.
</p>
</li>
</ul>
<h2>10. Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> for ARM toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for GNU toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for IAR toolchain are provided.
</li>
<li>
No <strong>Tasking</strong> projects are provided yet.
</li>
</ul>

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Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

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<!DOCTYPE CrossStudio_Project_File>
<solution Name="stm32f103_crossworks" target="8" version="2">
<project Name="openblt_olimex_stm32p103">
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="-I./..;-I./../lib/fatfs;-I./../lib/STM32F10x_StdPeriph_Driver;-I./../lib/STM32F10x_StdPeriph_Driver/inc;-I./../lib/CMSIS/CM3/CoreSupport;-I./../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x;-I./../../../../Source;-I./../../../../Source/third_party/fatfs/src;-I./../../../../Source/ARMCM3_STM32F1;-I./../../../../Source/ARMCM3_STM32F1/Crossworks" c_preprocessor_definitions="USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3" c_user_include_directories="$(TargetsDir)/STM32/include" gcc_optimization_level="Level 1" link_include_standard_libraries="Yes" linker_keep_symbols="_vectors;EntryFromProg" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)" target_reset_script="Reset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
<configuration
Name="Common"
Placement="Flash"
Target="STM32F103RB"
arm_architecture="v7M"
arm_core_type="Cortex-M3"
arm_linker_heap_size="128"
arm_linker_jtag_pad_pre_dr="1"
arm_linker_jtag_pad_pre_ir="5"
arm_linker_process_stack_size="0"
arm_linker_stack_size="128"
arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll"
arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000"
arm_target_debug_interface_type="ADIv5"
arm_target_loader_applicable_loaders="Flash"
arm_target_loader_default_loader="Flash"
arm_target_loader_parameter="8000000"
arm_use_gcc_libraries="Yes"
build_intermediate_directory="$(Configuration)/../../obj"
build_output_directory="$(ProjectDir)/../bin"
c_only_additional_options="-I./..;-I./../lib/fatfs;-I./../lib/STM32F10x_StdPeriph_Driver;-I./../lib/STM32F10x_StdPeriph_Driver/inc;-I./../lib/CMSIS/CM3/CoreSupport;-I./../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x;-I./../../../../Source;-I./../../../../Source/third_party/fatfs/src;-I./../../../../Source/ARMCM3_STM32F1;-I./../../../../Source/ARMCM3_STM32F1/Crossworks"
c_preprocessor_definitions="STM32F10X_MD;USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3"
c_user_include_directories="$(TargetsDir)/STM32/include"
gcc_optimization_level="Level 1"
link_include_standard_libraries="Yes"
linker_keep_symbols="_vectors;EntryFromProg"
linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml"
linker_output_format="srec"
linker_printf_enabled="No"
linker_printf_width_precision_supported="No"
linker_scanf_enabled="No"
linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml"
oscillator_frequency="8MHz"
project_directory=""
project_type="Executable"
property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml"
target_get_partname_script="GetPartName()"
target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)"
target_reset_script="Reset()" />
<configuration
Name="Flash"
arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf"
arm_target_flash_loader_type="LIBMEM RPC Loader"
arm_target_loader_can_lock_all="No"
arm_target_loader_can_lock_range="No"
arm_target_loader_can_unlock_all="No"
arm_target_loader_can_unlock_range="No"
target_reset_script="FLASHReset()" />
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<folder Name="Demo">
<folder Name="Boot" file_name="">
<file file_name="../hooks.c"/>
<file file_name="../main.c"/>
<file file_name="../stm32f10x.h"/>
<folder Name="Boot">
<file file_name="../hooks.c" />
<file file_name="../main.c" />
<file file_name="../stm32f10x.h" />
<folder Name="lib">
<folder Name="cmsis" file_name="">
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.c"/>
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.h"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"/>
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h"/>
<folder Name="cmsis">
<file file_name="../lib/CMSIS/CM3/CoreSupport/core_cm3.h" />
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" />
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c" />
<file file_name="../lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h" />
</folder>
<folder Name="fatfs" file_name="">
<file file_name="../lib/fatfs/ffconf.h"/>
<file file_name="../lib/fatfs/mmc.c"/>
<folder Name="fatfs">
<file file_name="../lib/fatfs/ffconf.h" />
<file file_name="../lib/fatfs/mmc.c" />
</folder>
<folder Name="stdperiphlib" file_name="">
<file file_name="../lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h"/>
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"/>
<folder Name="stdperiphlib">
<file file_name="../lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h" />
<file file_name="../lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h" />
</folder>
</folder>
<file file_name="../blt_conf.h"/>
<file file_name="../blt_conf.h" />
</folder>
</folder>
<folder Name="Source" file_name="">
<folder Name="ARMCM3_STM32F1" file_name="">
<folder Name="Crossworks" file_name=""/>
<file file_name="../../../../Source/ARMCM3_STM32F1/can.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/cpu.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.h"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/nvm.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/timer.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/types.h"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/uart.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/usb.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cpu_comp.c"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cstart.s"/>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c"/>
<folder Name="Source">
<folder Name="ARMCM3_STM32F1">
<folder Name="Crossworks" />
<file file_name="../../../../Source/ARMCM3_STM32F1/can.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/cpu.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/flash.h" />
<file file_name="../../../../Source/ARMCM3_STM32F1/nvm.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/timer.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/types.h" />
<file file_name="../../../../Source/ARMCM3_STM32F1/uart.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/usb.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cpu_comp.c" />
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/cstart.s" />
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/vectors.c" />
</folder>
<file file_name="../../../../Source/assert.c"/>
<file file_name="../../../../Source/assert.h"/>
<file file_name="../../../../Source/backdoor.c"/>
<file file_name="../../../../Source/backdoor.h"/>
<file file_name="../../../../Source/boot.c"/>
<file file_name="../../../../Source/boot.h"/>
<file file_name="../../../../Source/com.c"/>
<file file_name="../../../../Source/com.h"/>
<file file_name="../../../../Source/cop.c"/>
<file file_name="../../../../Source/cop.h"/>
<file file_name="../../../../Source/plausibility.h"/>
<file file_name="../../../../Source/xcp.c"/>
<file file_name="../../../../Source/xcp.h"/>
<file file_name="../../../../Source/file.c"/>
<file file_name="../../../../Source/file.h"/>
<file file_name="../../../../Source/assert.c" />
<file file_name="../../../../Source/assert.h" />
<file file_name="../../../../Source/backdoor.c" />
<file file_name="../../../../Source/backdoor.h" />
<file file_name="../../../../Source/boot.c" />
<file file_name="../../../../Source/boot.h" />
<file file_name="../../../../Source/com.c" />
<file file_name="../../../../Source/com.h" />
<file file_name="../../../../Source/cop.c" />
<file file_name="../../../../Source/cop.h" />
<file file_name="../../../../Source/plausibility.h" />
<file file_name="../../../../Source/xcp.c" />
<file file_name="../../../../Source/xcp.h" />
<file file_name="../../../../Source/file.c" />
<file file_name="../../../../Source/file.h" />
<folder Name="third_party">
<folder Name="fatfs" file_name="">
<file file_name="../../../../Source/third_party/fatfs/src/diskio.h"/>
<file file_name="../../../../Source/third_party/fatfs/src/ff.c"/>
<file file_name="../../../../Source/third_party/fatfs/src/ff.h"/>
<file file_name="../../../../Source/third_party/fatfs/src/integer.h"/>
<file file_name="../../../../Source/third_party/fatfs/src/option/unicode.c"/>
<folder Name="fatfs">
<file file_name="../../../../Source/third_party/fatfs/src/diskio.h" />
<file file_name="../../../../Source/third_party/fatfs/src/ff.c" />
<file file_name="../../../../Source/third_party/fatfs/src/ff.h" />
<file file_name="../../../../Source/third_party/fatfs/src/integer.h" />
<file file_name="../../../../Source/third_party/fatfs/src/option/unicode.c" />
</folder>
</folder>
<file file_name="../../../../Source/can.h"/>
<file file_name="../../../../Source/cpu.h"/>
<file file_name="../../../../Source/nvm.h"/>
<file file_name="../../../../Source/timer.h"/>
<file file_name="../../../../Source/uart.h"/>
<file file_name="../../../../Source/can.h" />
<file file_name="../../../../Source/cpu.h" />
<file file_name="../../../../Source/nvm.h" />
<file file_name="../../../../Source/timer.h" />
<file file_name="../../../../Source/uart.h" />
</folder>
</folder>
<folder Name="System Files" file_name="">
<folder Name="System Files">
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="../../../../Source/ARMCM3_STM32F1/Crossworks/memory.x">
<configuration Name="Common" file_type="Linker Script"/>
<configuration Name="Common" file_type="Linker Script" />
</file>
</folder>
<configuration Name="Debug" c_only_additional_options=""/>
<configuration Name="Debug" c_only_additional_options="" />
</project>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
<configuration
Name="THUMB"
Platform="ARM"
arm_instruction_set="THUMB"
arm_library_instruction_set="THUMB"
c_preprocessor_definitions="__THUMB"
hidden="Yes" />
<configuration
Name="Debug"
build_debug_information="Yes"
c_preprocessor_definitions="DEBUG"
gcc_optimization_level="None"
hidden="Yes"
link_include_startup_code="No" />
<configuration
Name="THUMB Release"
inherited_configurations="THUMB;Release" />
<configuration
Name="Release"
build_debug_information="No"
c_additional_options="-g1"
c_preprocessor_definitions="NDEBUG"
gcc_optimization_level="Level 1"
hidden="Yes"
link_include_startup_code="No" />
</solution>

45
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
View File

@ -1,19 +1,28 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<Breakpoints>
<Exceptions set="MemManage;UsageFault_Coprocessor;UsageFault_CheckingError;UsageFault_StateError;BusFault;ExceptionEntryReturnFault;HardFault" />
</Breakpoints>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x08004004" numColumns="8" sizeText="4" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x08004004" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="4" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x08004004" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="4" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32p103" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32p103" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32p103" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openbtl_olimex_stm32p103" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="openblt_olimex_stm32p103" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
@ -21,18 +30,24 @@
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32p103;Source Files" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32p103;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32p103;Source Files;Demo;Boot" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32p103;Source Files;Demo;Boot;lib" name="unnamed" />
<ProjectSessionItem path="stm32f103_crossworks;openblt_olimex_stm32p103;Source Files;Demo;Boot;lib;cmsis" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="CPU" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" name="openblt_olimex_stm32p103" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" name="openblt_olimex_stm32p103" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" name="openblt_olimex_stm32p103" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="openbtl_olimex_stm32p103" />
<RegisterWindow openNodes="CPU - Current Context" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" name="openblt_olimex_stm32p103" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -40,9 +55,9 @@
</TraceWindow>
<Watch1>
<Watches active="1" update="Never" >
<Watchpoint linenumber="124" radix="-1" name="free_running_counter_now" expression="free_running_counter_now" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
<Watchpoint linenumber="152" radix="-1" name="free_running_counter_accumulative" expression="free_running_counter_accumulative" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
<Watchpoint linenumber="121" radix="-1" name="free_running_counter_last" expression="free_running_counter_last" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
<Watchpoint evalMode="0" linenumber="124" numelements="0" radix="-1" name="free_running_counter_now" list="" expression="free_running_counter_now" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
<Watchpoint evalMode="0" linenumber="152" numelements="0" radix="-1" name="free_running_counter_accumulative" list="" expression="free_running_counter_accumulative" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
<Watchpoint evalMode="0" linenumber="121" numelements="0" radix="-1" name="free_running_counter_last" list="" expression="free_running_counter_last" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
</Watches>
</Watch1>
<Watch2>
@ -55,7 +70,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32P103_Crossworks\Boot\main.c" y="0" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32P103_Crossworks\Boot\main.c" left="18" selected="1" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="../main.c" y="51" path="../main.c" left="0" selected="1" name="unnamed" top="31" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_olimex_stm32p103" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:\Work\software\OpenBLT\Target\Source\ARMCM3_STM32F1\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
<ARMCrossStudioWindow activeProject="openblt_olimex_stm32p103" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="C:/Work/software/OpenBLT/Target/Source/ARMCM3_STM32F1/Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="3711" debugSearchPath="" buildConfiguration="THUMB Debug" />
</session>

784
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
View File

@ -1,784 +0,0 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<hr>
<h2>Cortex-M3 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<h2>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a globel variable is used. A simple mechansim detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
</p>
<pre>
extern volatile int ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<h2>ITM Debug Support in uVision</h2>
<p>
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
display the debug data.
</p>
<p>Direction microcontroller system -&gt; uVision:</p>
<ul>
<li>
Characters received via ITM communication channel 0 are written in a printf style
to <strong>Debug (printf) Viewer</strong> window.
</li>
</ul>
<p>Direction uVision -&gt; microcontroller system:</p>
<ul>
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
</li>
</ul>
<h2>RTX Kernel awareness in uVision</h2>
<p>
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
No format overhead is necessary.<br>
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
to ITM communication channel 31.
</p>
<p>Following RTX events are traced:</p>
<ul>
<li>Task Create / Delete event
<ol>
<li>32 bit access. Task start address is transmitted</li>
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
High byte holds Create/Delete flag, Low byte holds TASK ID.
</li>
</ol>
</li>
<li>Task switch event
<ol>
<li>8 bit access. Task ID of current task is transmitted</li>
</ol>
</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
</li>
</ul>
<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
<hr>
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
All rights reserved.<br>
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
</p>
</body>
</html>

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<h1>Changes to CMSIS version V1.20</h1>
<hr>
<h2>1. Removed CMSIS Middelware packages</h2>
<p>
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
</p>
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h2>3. Changed startup concept</h2>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h3>Changed startup concept</h3>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h2>4. Advanced Debug Functions</h2>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h2>5. Core Register Bit Definitions</h2>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
<h2>7. DoxyGen Tags</h2>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h2>8. Folder Structure</h2>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2>9. Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
<li>
<p>
Removing core_cm3.c and core_cm0.c.
</p>
<p>
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
appropriate compiler intrinsics.
</p>
</li>
</ul>
<h2>10. Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> for ARM toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for GNU toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for IAR toolchain are provided.
</li>
<li>
No <strong>Tasking</strong> projects are provided yet.
</li>
</ul>

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2
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/readme.txt
View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

213
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
View File

@ -1,100 +1,146 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="stm32f103_crossworks" target="8" version="2">
<project Name="demoprog_olimex_stm32p103">
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_long_calls="Yes" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="" c_preprocessor_definitions="USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib/stdperiphlib;$(ProjectDir)/../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/CoreSupport;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x" gcc_optimization_level="None" link_include_standard_libraries="Yes" linker_keep_symbols="_vectors" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)" target_reset_script="Reset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
<configuration
Name="Common"
Placement="Flash"
Target="STM32F103RB"
arm_architecture="v7M"
arm_core_type="Cortex-M3"
arm_linker_heap_size="128"
arm_linker_jtag_pad_pre_dr="1"
arm_linker_jtag_pad_pre_ir="5"
arm_linker_process_stack_size="0"
arm_linker_stack_size="128"
arm_long_calls="Yes"
arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll"
arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000"
arm_target_debug_interface_type="ADIv5"
arm_target_loader_applicable_loaders="Flash"
arm_target_loader_default_loader="Flash"
arm_target_loader_parameter="8000000"
arm_use_gcc_libraries="Yes"
build_intermediate_directory="$(Configuration)/../../obj"
build_output_directory="$(ProjectDir)/../bin"
c_only_additional_options=""
c_preprocessor_definitions="STM32F10X_MD;USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3"
c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib/stdperiphlib;$(ProjectDir)/../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/CoreSupport;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x"
gcc_optimization_level="None"
link_include_standard_libraries="Yes"
linker_keep_symbols="_vectors"
linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml"
linker_output_format="srec"
linker_printf_enabled="No"
linker_printf_width_precision_supported="No"
linker_scanf_enabled="No"
linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml"
oscillator_frequency="8MHz"
project_directory=""
project_type="Executable"
property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml"
target_get_partname_script="GetPartName()"
target_match_partname_script="MatchPartName(&quot;$(Target)&quot;)"
target_reset_script="Reset()" />
<configuration
Name="Flash"
arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf"
arm_target_flash_loader_type="LIBMEM RPC Loader"
arm_target_loader_can_lock_all="No"
arm_target_loader_can_lock_range="No"
arm_target_loader_can_unlock_all="No"
arm_target_loader_can_unlock_range="No"
target_reset_script="FLASHReset()" />
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
<folder Name="Demo">
<folder Name="Prog">
<file file_name="../cstart.s"/>
<file file_name="../header.h"/>
<file file_name="../led.c"/>
<file file_name="../led.h"/>
<file file_name="../main.c"/>
<file file_name="../timer.c"/>
<file file_name="../timer.h"/>
<file file_name="../vectors.c"/>
<file file_name="../boot.c"/>
<file file_name="../boot.h"/>
<file file_name="../cstart.s" />
<file file_name="../header.h" />
<file file_name="../led.c" />
<file file_name="../led.h" />
<file file_name="../main.c" />
<file file_name="../timer.c" />
<file file_name="../timer.h" />
<file file_name="../vectors.c" />
<file file_name="../boot.c" />
<file file_name="../boot.h" />
</folder>
</folder>
</folder>
<folder Name="System Files">
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="../memory.x">
<configuration Name="Common" file_type="Linker Script"/>
<configuration Name="Common" file_type="Linker Script" />
</file>
</folder>
<configuration Name="Debug" c_only_additional_options=""/>
<configuration Name="Debug" c_only_additional_options="" />
<folder Name="Library Files">
<file file_name="../lib/stdperiphlib/stm32f10x_conf.h"/>
<file file_name="../lib/stdperiphlib/stm32f10x_conf.h" />
<folder Name="STM32F10x_StdPeriph_Driver">
<folder Name="inc">
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h" />
</folder>
<folder Name="src">
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c"/>
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c" />
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c" />
</folder>
</folder>
<folder Name="CMSIS">
<folder Name="CM3">
<folder Name="CoreSupport">
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h" />
</folder>
<folder Name="DeviceSupport">
<folder Name="ST">
<folder Name="STM32F10x">
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h"/>
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" />
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c" />
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h" />
</folder>
</folder>
</folder>
@ -102,9 +148,30 @@
</folder>
</folder>
</project>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
<configuration
Name="THUMB"
Platform="ARM"
arm_instruction_set="THUMB"
arm_library_instruction_set="THUMB"
c_preprocessor_definitions="__THUMB"
hidden="Yes" />
<configuration
Name="Debug"
build_debug_information="Yes"
c_preprocessor_definitions="DEBUG"
gcc_optimization_level="None"
hidden="Yes"
link_include_startup_code="No" />
<configuration
Name="THUMB Release"
inherited_configurations="THUMB;Release" />
<configuration
Name="Release"
build_debug_information="No"
c_additional_options="-g1"
c_preprocessor_definitions="NDEBUG"
gcc_optimization_level="Level 1"
hidden="Yes"
link_include_startup_code="No" />
</solution>

25
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
View File

@ -1,19 +1,22 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<!DOCTYPE CrossStudio_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionProfileWindow/>
<FrameBufferWindow>
<FrameBufferWindow addressText="" bufferWidth="-1" bufferHeight="-1" addressSpace="" />
</FrameBufferWindow>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0" numColumns="8" sizeText="32" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="32" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" addressOrder="0" refreshPeriod="0" columnsText="" sizeText="" viewMode="0" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
@ -23,16 +26,16 @@
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32p103;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="CPU" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" decimalNodes="" octalNodes="" asciiNodes="" visibleNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -51,7 +54,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32P103_Crossworks\Prog\main.c" y="0" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_STM32F1_Olimex_STM32P103_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="../main.c" y="0" path="../main.c" left="0" selected="1" name="unnamed" top="0" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_stm32p103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
<ARMCrossStudioWindow activeProject="demoprog_olimex_stm32p103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:/usr/feaser/software/OpenBLT/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_Crossworks/Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
</session>

784
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
View File

@ -1,784 +0,0 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

2408
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
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616
Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h Normal file
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@ -0,0 +1,616 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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@ -0,0 +1,618 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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<body>
<h1>CMSIS Debug Support</h1>
<hr>
<h2>Cortex-M3 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<h2>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a globel variable is used. A simple mechansim detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
</p>
<pre>
extern volatile int ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<h2>ITM Debug Support in uVision</h2>
<p>
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
display the debug data.
</p>
<p>Direction microcontroller system -&gt; uVision:</p>
<ul>
<li>
Characters received via ITM communication channel 0 are written in a printf style
to <strong>Debug (printf) Viewer</strong> window.
</li>
</ul>
<p>Direction uVision -&gt; microcontroller system:</p>
<ul>
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
</li>
</ul>
<h2>RTX Kernel awareness in uVision</h2>
<p>
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
No format overhead is necessary.<br>
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
to ITM communication channel 31.
</p>
<p>Following RTX events are traced:</p>
<ul>
<li>Task Create / Delete event
<ol>
<li>32 bit access. Task start address is transmitted</li>
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
High byte holds Create/Delete flag, Low byte holds TASK ID.
</li>
</ol>
</li>
<li>Task switch event
<ol>
<li>8 bit access. Task ID of current task is transmitted</li>
</ol>
</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
</li>
</ul>
<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
<hr>
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
All rights reserved.<br>
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
</p>
</body>
</html>

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<body>
<h1>Changes to CMSIS version V1.20</h1>
<hr>
<h2>1. Removed CMSIS Middelware packages</h2>
<p>
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
</p>
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h2>3. Changed startup concept</h2>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h3>Changed startup concept</h3>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h2>4. Advanced Debug Functions</h2>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h2>5. Core Register Bit Definitions</h2>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
<h2>7. DoxyGen Tags</h2>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h2>8. Folder Structure</h2>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2>9. Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
<li>
<p>
Removing core_cm3.c and core_cm0.c.
</p>
<p>
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
appropriate compiler intrinsics.
</p>
</li>
</ul>
<h2>10. Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> for ARM toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for GNU toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for IAR toolchain are provided.
</li>
<li>
No <strong>Tasking</strong> projects are provided yet.
</li>
</ul>

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