- Added support for the STM32 ARM CortexM3 family with a demo for the Olimex STM32P103 board and Crossworks compiler.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@8 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg
parent
98aee4817f
commit
733ad572b2
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(__do_debug_operation_bkpt)
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C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
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Memory Configuration
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||||
|
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Name Origin Length Attributes
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||||
UNPLACED_SECTIONS 0xffffffff 0x00000000 xw
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||||
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||||
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||||
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||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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||||
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||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
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|
||||
0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .text is too large to fit in FLASH memory segment)
|
||||
0x08000d90 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
|
||||
|
||||
.dtors 0x08000d90 0x0
|
||||
0x08000d90 __dtors_start__ = .
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
*(.fini_array .fini_array.*)
|
||||
0x08000d90 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
|
||||
0x08000d90 __dtors_load_end__ = __dtors_end__
|
||||
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .dtors is too large to fit in FLASH memory segment)
|
||||
0x08000d90 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
|
||||
|
||||
.ctors 0x08000d90 0x0
|
||||
0x08000d90 __ctors_start__ = .
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
*(.init_array .init_array.*)
|
||||
0x08000d90 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
|
||||
0x08000d90 __ctors_load_end__ = __ctors_end__
|
||||
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .ctors is too large to fit in FLASH memory segment)
|
||||
0x08000d90 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
|
||||
|
||||
.rodata 0x08000d90 0x23c
|
||||
0x08000d90 __rodata_start__ = .
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
.rodata.str1.1
|
||||
0x08000d90 0x67 THUMB Debug/../../obj/main.o
|
||||
.rodata.str1.1
|
||||
0x08000df7 0x92 THUMB Debug/../../obj/vectors.o
|
||||
.rodata.str1.1
|
||||
0x08000e89 0x84 THUMB Debug/../../obj/uart.o
|
||||
*fill* 0x08000f0d 0x3 00
|
||||
.rodata.flashLayout
|
||||
0x08000f10 0xb4 THUMB Debug/../../obj/flash.o
|
||||
.rodata.xcpStationId
|
||||
0x08000fc4 0x8 THUMB Debug/../../obj/xcp.o
|
||||
0x08000fcc __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
|
||||
0x08000fcc __rodata_load_end__ = __rodata_end__
|
||||
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .rodata is too large to fit in FLASH memory segment)
|
||||
0x08000fcc __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
|
||||
|
||||
.ARM.exidx 0x08000fcc 0x0
|
||||
0x08000fcc __ARM.exidx_start__ = .
|
||||
0x08000fcc __exidx_start = __ARM.exidx_start__
|
||||
*(.ARM.exidx .ARM.exidx.*)
|
||||
0x08000fcc __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
|
||||
0x08000fcc __exidx_end = __ARM.exidx_end__
|
||||
0x08000fcc __ARM.exidx_load_end__ = __ARM.exidx_end__
|
||||
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .ARM.exidx is too large to fit in FLASH memory segment)
|
||||
0x08000fcc __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
|
||||
|
||||
.fast 0x20000000 0x0 load address 0x08000fcc
|
||||
0x20000000 __fast_start__ = .
|
||||
*(.fast .fast.*)
|
||||
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
|
||||
0x08000fcc __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
|
||||
0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x20000))), error: .fast is too large to fit in FLASH memory segment)
|
||||
|
||||
.fast_run 0x20000000 0x0
|
||||
0x20000000 __fast_run_start__ = .
|
||||
0x20000000 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
|
||||
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
|
||||
0x20000000 __fast_run_load_end__ = __fast_run_end__
|
||||
0x00000001 . = ASSERT (((__fast_run_end__ >= __RAM_segment_start__) && (__fast_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .fast_run is too large to fit in RAM memory segment)
|
||||
0x08000fcc __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
|
||||
|
||||
.data 0x20000000 0x0 load address 0x08000fcc
|
||||
0x20000000 __data_start__ = .
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
0x20000000 __data_end__ = (__data_start__ + SIZEOF (.data))
|
||||
0x08000fcc __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
|
||||
0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x20000))), error: .data is too large to fit in FLASH memory segment)
|
||||
|
||||
.data_run 0x20000000 0x0
|
||||
0x20000000 __data_run_start__ = .
|
||||
0x20000000 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
|
||||
0x20000000 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
|
||||
0x20000000 __data_run_load_end__ = __data_run_end__
|
||||
0x00000001 . = ASSERT (((__data_run_end__ >= __RAM_segment_start__) && (__data_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .data_run is too large to fit in RAM memory segment)
|
||||
0x20000000 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
|
||||
|
||||
.bss 0x20000000 0x4e8
|
||||
0x20000000 __bss_start__ = .
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
.bss.millisecond_counter
|
||||
0x20000000 0x2 THUMB Debug/../../obj/timer.o
|
||||
.bss.xcpCtoReqPacket.876
|
||||
0x20000002 0x41 THUMB Debug/../../obj/uart.o
|
||||
.bss.xcpCtoRxInProgress.878
|
||||
0x20000043 0x1 THUMB Debug/../../obj/uart.o
|
||||
.bss.xcpCtoRxLength.877
|
||||
0x20000044 0x1 THUMB Debug/../../obj/uart.o
|
||||
*fill* 0x20000045 0x3 00
|
||||
.bss.bootBlockInfo
|
||||
0x20000048 0x204 THUMB Debug/../../obj/flash.o
|
||||
.bss.blockInfo
|
||||
0x2000024c 0x204 THUMB Debug/../../obj/flash.o
|
||||
.bss.assert_failure_file
|
||||
0x20000450 0x4 THUMB Debug/../../obj/assert.o
|
||||
.bss.assert_failure_line
|
||||
0x20000454 0x4 THUMB Debug/../../obj/assert.o
|
||||
.bss.backdoorOpen
|
||||
0x20000458 0x1 THUMB Debug/../../obj/backdoor.o
|
||||
.bss.comEntryStateConnect
|
||||
0x20000459 0x1 THUMB Debug/../../obj/com.o
|
||||
.bss.xcpCtoReqPacket.855
|
||||
0x2000045a 0x40 THUMB Debug/../../obj/com.o
|
||||
*fill* 0x2000049a 0x2 00
|
||||
.bss.xcpInfo 0x2000049c 0x4c THUMB Debug/../../obj/xcp.o
|
||||
*(COMMON)
|
||||
0x200004e8 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
|
||||
0x200004e8 __bss_load_end__ = __bss_end__
|
||||
0x00000001 . = ASSERT (((__bss_end__ >= __RAM_segment_start__) && (__bss_end__ <= (__RAM_segment_start__ + 0x5000))), error: .bss is too large to fit in RAM memory segment)
|
||||
0x200004e8 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
|
||||
|
||||
.non_init 0x200004e8 0x0
|
||||
0x200004e8 __non_init_start__ = .
|
||||
*(.non_init .non_init.*)
|
||||
0x200004e8 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
|
||||
0x200004e8 __non_init_load_end__ = __non_init_end__
|
||||
0x00000001 . = ASSERT (((__non_init_end__ >= __RAM_segment_start__) && (__non_init_end__ <= (__RAM_segment_start__ + 0x5000))), error: .non_init is too large to fit in RAM memory segment)
|
||||
0x200004e8 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
|
||||
|
||||
.heap 0x200004e8 0x80
|
||||
0x200004e8 __heap_start__ = .
|
||||
*(.heap .heap.*)
|
||||
0x20000568 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
|
||||
*fill* 0x200004e8 0x80 00
|
||||
0x20000568 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
|
||||
0x20000568 __heap_load_end__ = __heap_end__
|
||||
0x00000001 . = ASSERT (((__heap_end__ >= __RAM_segment_start__) && (__heap_end__ <= (__RAM_segment_start__ + 0x5000))), error: .heap is too large to fit in RAM memory segment)
|
||||
0x20000568 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
|
||||
|
||||
.stack 0x20000568 0x100
|
||||
0x20000568 __stack_start__ = .
|
||||
*(.stack .stack.*)
|
||||
0x20000668 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
|
||||
*fill* 0x20000568 0x100 00
|
||||
0x20000668 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
|
||||
0x20000668 __stack_load_end__ = __stack_end__
|
||||
0x00000001 . = ASSERT (((__stack_end__ >= __RAM_segment_start__) && (__stack_end__ <= (__RAM_segment_start__ + 0x5000))), error: .stack is too large to fit in RAM memory segment)
|
||||
0x20000668 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
|
||||
|
||||
.stack_process 0x20000668 0x0
|
||||
0x20000668 __stack_process_start__ = .
|
||||
*(.stack_process .stack_process.*)
|
||||
0x20000668 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
|
||||
0x20000668 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
|
||||
0x20000668 __stack_process_load_end__ = __stack_process_end__
|
||||
0x00000001 . = ASSERT (((__stack_process_end__ >= __RAM_segment_start__) && (__stack_process_end__ <= (__RAM_segment_start__ + 0x5000))), error: .stack_process is too large to fit in RAM memory segment)
|
||||
0x20000668 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
|
||||
|
||||
.tbss 0x20000668 0x0
|
||||
0x20000668 __tbss_start__ = .
|
||||
*(.tbss .tbss.*)
|
||||
0x20000668 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
|
||||
0x20000668 __tbss_load_end__ = __tbss_end__
|
||||
0x00000001 . = ASSERT (((__tbss_end__ >= __RAM_segment_start__) && (__tbss_end__ <= (__RAM_segment_start__ + 0x5000))), error: .tbss is too large to fit in RAM memory segment)
|
||||
0x08000fcc __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
|
||||
|
||||
.tdata 0x20000668 0x0 load address 0x08000fcc
|
||||
0x20000668 __tdata_start__ = .
|
||||
*(.tdata .tdata.*)
|
||||
0x20000668 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
|
||||
0x08000fcc __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
|
||||
0x08000fcc __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
|
||||
0x00000001 . = ASSERT ((((__tdata_load_start__ + SIZEOF (.tdata)) >= __FLASH_segment_start__) && ((__tdata_load_start__ + SIZEOF (.tdata)) <= (__FLASH_segment_start__ + 0x20000))), error: .tdata is too large to fit in FLASH memory segment)
|
||||
|
||||
.tdata_run 0x20000668 0x0
|
||||
0x20000668 __tdata_run_start__ = .
|
||||
0x20000668 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
|
||||
0x20000668 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
|
||||
0x20000668 __tdata_run_load_end__ = __tdata_run_end__
|
||||
0x20000668 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
|
||||
0x00000001 . = ASSERT (((__tdata_run_end__ >= __RAM_segment_start__) && (__tdata_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .tdata_run is too large to fit in RAM memory segment)
|
||||
START GROUP
|
||||
LOAD THUMB Debug/../../obj/hooks.o
|
||||
LOAD THUMB Debug/../../obj/main.o
|
||||
LOAD THUMB Debug/../../obj/cstart.o
|
||||
LOAD THUMB Debug/../../obj/vectors.o
|
||||
LOAD THUMB Debug/../../obj/can.o
|
||||
LOAD THUMB Debug/../../obj/cpu.o
|
||||
LOAD THUMB Debug/../../obj/nvm.o
|
||||
LOAD THUMB Debug/../../obj/timer.o
|
||||
LOAD THUMB Debug/../../obj/uart.o
|
||||
LOAD THUMB Debug/../../obj/flash.o
|
||||
LOAD THUMB Debug/../../obj/assert.o
|
||||
LOAD THUMB Debug/../../obj/backdoor.o
|
||||
LOAD THUMB Debug/../../obj/boot.o
|
||||
LOAD THUMB Debug/../../obj/com.o
|
||||
LOAD THUMB Debug/../../obj/cop.o
|
||||
LOAD THUMB Debug/../../obj/xcp.o
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v7m_t_le.a
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v7m_t_le.a
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libcpp_v7m_t_le.a
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v7m_t_le.a
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_targetio_impl_v7m_t_le.a
|
||||
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v7m_t_le.a
|
||||
END GROUP
|
||||
OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_Crossworks/Boot/ide/../bin/openbtl_olimex_stm32p103.elf elf32-littlearm)
|
||||
|
||||
.debug_info 0x00000000 0x1fa0
|
||||
.debug_info 0x00000000 0x5e THUMB Debug/../../obj/hooks.o
|
||||
.debug_info 0x0000005e 0x32a THUMB Debug/../../obj/main.o
|
||||
.debug_info 0x00000388 0x114 THUMB Debug/../../obj/cstart.o
|
||||
.debug_info 0x0000049c 0xf4 THUMB Debug/../../obj/vectors.o
|
||||
.debug_info 0x00000590 0x5e THUMB Debug/../../obj/can.o
|
||||
.debug_info 0x000005ee 0x13d THUMB Debug/../../obj/cpu.o
|
||||
.debug_info 0x0000072b 0x15e THUMB Debug/../../obj/nvm.o
|
||||
.debug_info 0x00000889 0x187 THUMB Debug/../../obj/timer.o
|
||||
.debug_info 0x00000a10 0x300 THUMB Debug/../../obj/uart.o
|
||||
.debug_info 0x00000d10 0x7b4 THUMB Debug/../../obj/flash.o
|
||||
.debug_info 0x000014c4 0xe8 THUMB Debug/../../obj/assert.o
|
||||
.debug_info 0x000015ac 0xa8 THUMB Debug/../../obj/backdoor.o
|
||||
.debug_info 0x00001654 0x8c THUMB Debug/../../obj/boot.o
|
||||
.debug_info 0x000016e0 0x18e THUMB Debug/../../obj/com.o
|
||||
.debug_info 0x0000186e 0x8a THUMB Debug/../../obj/cop.o
|
||||
.debug_info 0x000018f8 0x5db THUMB Debug/../../obj/xcp.o
|
||||
.debug_info 0x00001ed3 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
|
||||
|
||||
.debug_abbrev 0x00000000 0xcd8
|
||||
.debug_abbrev 0x00000000 0x2a THUMB Debug/../../obj/hooks.o
|
||||
.debug_abbrev 0x0000002a 0x109 THUMB Debug/../../obj/main.o
|
||||
.debug_abbrev 0x00000133 0x14 THUMB Debug/../../obj/cstart.o
|
||||
.debug_abbrev 0x00000147 0xc0 THUMB Debug/../../obj/vectors.o
|
||||
.debug_abbrev 0x00000207 0x2a THUMB Debug/../../obj/can.o
|
||||
.debug_abbrev 0x00000231 0xb1 THUMB Debug/../../obj/cpu.o
|
||||
.debug_abbrev 0x000002e2 0xbc THUMB Debug/../../obj/nvm.o
|
||||
.debug_abbrev 0x0000039e 0x13a THUMB Debug/../../obj/timer.o
|
||||
.debug_abbrev 0x000004d8 0x16d THUMB Debug/../../obj/uart.o
|
||||
.debug_abbrev 0x00000645 0x279 THUMB Debug/../../obj/flash.o
|
||||
.debug_abbrev 0x000008be 0x7e THUMB Debug/../../obj/assert.o
|
||||
.debug_abbrev 0x0000093c 0x5d THUMB Debug/../../obj/backdoor.o
|
||||
.debug_abbrev 0x00000999 0x41 THUMB Debug/../../obj/boot.o
|
||||
.debug_abbrev 0x000009da 0xcb THUMB Debug/../../obj/com.o
|
||||
.debug_abbrev 0x00000aa5 0x41 THUMB Debug/../../obj/cop.o
|
||||
.debug_abbrev 0x00000ae6 0x1cd THUMB Debug/../../obj/xcp.o
|
||||
.debug_abbrev 0x00000cb3 0x25 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
|
||||
|
||||
.debug_line 0x00000000 0x12f0
|
||||
.debug_line 0x00000000 0x1d THUMB Debug/../../obj/hooks.o
|
||||
.debug_line 0x0000001d 0x1d6 THUMB Debug/../../obj/main.o
|
||||
.debug_line 0x000001f3 0x15c THUMB Debug/../../obj/cstart.o
|
||||
.debug_line 0x0000034f 0xf1 THUMB Debug/../../obj/vectors.o
|
||||
.debug_line 0x00000440 0x1d THUMB Debug/../../obj/can.o
|
||||
.debug_line 0x0000045d 0x113 THUMB Debug/../../obj/cpu.o
|
||||
.debug_line 0x00000570 0x133 THUMB Debug/../../obj/nvm.o
|
||||
.debug_line 0x000006a3 0x140 THUMB Debug/../../obj/timer.o
|
||||
.debug_line 0x000007e3 0x17d THUMB Debug/../../obj/uart.o
|
||||
.debug_line 0x00000960 0x2aa THUMB Debug/../../obj/flash.o
|
||||
.debug_line 0x00000c0a 0xde THUMB Debug/../../obj/assert.o
|
||||
.debug_line 0x00000ce8 0xfb THUMB Debug/../../obj/backdoor.o
|
||||
.debug_line 0x00000de3 0xbf THUMB Debug/../../obj/boot.o
|
||||
.debug_line 0x00000ea2 0x138 THUMB Debug/../../obj/com.o
|
||||
.debug_line 0x00000fda 0xb7 THUMB Debug/../../obj/cop.o
|
||||
.debug_line 0x00001091 0x1eb THUMB Debug/../../obj/xcp.o
|
||||
.debug_line 0x0000127c 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
|
||||
|
||||
.debug_str 0x00000000 0x10d6
|
||||
.debug_str 0x00000000 0xfc THUMB Debug/../../obj/hooks.o
|
||||
0x12c (size before relaxing)
|
||||
.debug_str 0x000000fc 0x162 THUMB Debug/../../obj/main.o
|
||||
0x241 (size before relaxing)
|
||||
.debug_str 0x0000025e 0xc1 THUMB Debug/../../obj/vectors.o
|
||||
0x190 (size before relaxing)
|
||||
.debug_str 0x0000031f 0x83 THUMB Debug/../../obj/can.o
|
||||
0x147 (size before relaxing)
|
||||
.debug_str 0x000003a2 0xe5 THUMB Debug/../../obj/cpu.o
|
||||
0x1b4 (size before relaxing)
|
||||
.debug_str 0x00000487 0xc0 THUMB Debug/../../obj/nvm.o
|
||||
0x1ac (size before relaxing)
|
||||
.debug_str 0x00000547 0xef THUMB Debug/../../obj/timer.o
|
||||
0x1c9 (size before relaxing)
|
||||
.debug_str 0x00000636 0x165 THUMB Debug/../../obj/uart.o
|
||||
0x257 (size before relaxing)
|
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S31508000838A019FFF7E7FEA5F1FF014C4244EB0104B6
|
||||
S31508000848FF2808BF44F001040646002C7DD18542DE
|
||||
S3150800085878D8002D73D00F2874D83D4B3D4A5A6076
|
||||
S3150800086802F188325A603422DA60DA6812F0010234
|
||||
S3150800087802D0FFF7BFFE65E01969374F41F002015C
|
||||
S315080008881961B846144600F04AF998F80830AB4298
|
||||
S3150800089804D10C235C43304B1C5906E001340F2C59
|
||||
S315080008A808F10C08EFD14FF0FF34DFF8AC800025CB
|
||||
S315080008B800F035F998F80830B34205D10C235D43A2
|
||||
S315080008C8254B53F8058006E001350F2D08F10C086D
|
||||
S315080008D8EED14FF0FF38002500F021F93B7AB342F4
|
||||
S315080008E805D11D4B0C2202FB05356B6804E0013562
|
||||
S315080008F80C370F2DF0D10023C4EB08089844C8F329
|
||||
S315080009088F280026124D0EE06C612B6943F04003D0
|
||||
S315080009182B6101E000F003F9EB68DA07FAD401362F
|
||||
S31508000928B6B204F580644645094BEDD31A6922F038
|
||||
S3150800093802021A61FFF75EFE0120BDE8F08128462B
|
||||
S31508000948BDE8F0812046BDE8F0810020BDE8F081C9
|
||||
S315080009580020024023016745100F00080D4B186850
|
||||
S31508000968043B1B68C0180C4B1B68C0180B4B1B684C
|
||||
S31508000978C0180B4B1B68C0180A4B1B68C0180A4BD3
|
||||
S315080009881B68C018094B1B68C018D0F1010038BF8E
|
||||
S315080009980020704704200008082000080C200008DA
|
||||
S315080009A81020000814200008182000085021000804
|
||||
S315080009B80E4B11B55A689C68A418DA68A4181A69FF
|
||||
S315080009C8A4185A69A4189A69DB69A418E418644231
|
||||
S315080009D80094FFF7C3FF844205D004216A460448F9
|
||||
S315080009E8FFF7F8FE00E0012018BD00BF4800002008
|
||||
S315080009F8502100080A4800B50368013302D0FFF7FA
|
||||
S31508000A081DFE58B107480368013306D0FFF716FEDE
|
||||
S31508000A18003018BF01205DF804FB01205DF804FBCF
|
||||
S31508000A28480000204C020020034B00B51860034B11
|
||||
S31508000A38196000F074F8FCE75004002054040020FC
|
||||
S31508000A4810B500F069F801280FD0084C2378012B57
|
||||
S31508000A580BD1FFF73DFD312807D900232370FFF78F
|
||||
S31508000A6823FDBDE81040FFF7D7BC10BD5804002089
|
||||
S31508000A78044B012200B51A70FFF704FD5DF804EB74
|
||||
S31508000A88FFF7DEBF5804002000B500F047F8FFF767
|
||||
S31508000A98EFFFFFF7E5FC5DF804EB00F009B800B5D1
|
||||
S31508000AA800F03DF800F01AF85DF804EBFFF7C8BF48
|
||||
S31508000AB801B5FF238DF8003000238DF8013000F0CA
|
||||
S31508000AC839F8FFF70FFD044B1B78012B02D168464E
|
||||
S31508000AD800F04EF808BD00BF5904002000B50648C6
|
||||
S31508000AE8FFF752FD012804D103485DF804EB00F02E
|
||||
S31508000AF83FB85DF804FB00BF5A04002000B5C9B228
|
||||
S31508000B08FFF704FD5DF804EB00F02AB8014B012253
|
||||
S31508000B181A7070475904002000F01AB870477047D1
|
||||
S31508000B28034BFE22DA7002221871A3F84420704794
|
||||
S31508000B389C040020054B00221A709A6483F8432007
|
||||
S31508000B48A3F844209A705A70704700BF9C04002086
|
||||
S31508000B58024B1878003018BF012070479C04002003
|
||||
S31508000B68024B002283F84320704700BF9C040020EC
|
||||
S31508000B7870B503780546FF2B784C0FD1E370102320
|
||||
S31508000B88012200212371402322706272A2726170C9
|
||||
S31508000B986171A371E371217208227DE02678012E1E
|
||||
S31508000BA840F0DB80F32B40D011D8CF2B00F0B7806C
|
||||
S31508000BB805D8C92B77D0CC2B40F0BA80B6E0D12B14
|
||||
S31508000BC800F0A7807CD3D22B40F0B28093E0FA2BB2
|
||||
S31508000BD847D006D8F52B0CD011D3F62B40F0A880B1
|
||||
S31508000BE81FE0FD2B4ED0FE2B59D0FC2B40F0A080E1
|
||||
S31508000BF846E042783F2A66D8201DA16C06E043786D
|
||||
S31508000C083F2B60D84168A1644278201DFFF716FC7F
|
||||
S31508000C18FF23E3706A78A36CD318A3646B7801334F
|
||||
S31508000C2874E0FF23E370436848E0FF23E37000237A
|
||||
S31508000C38A06C69681A4603E01C5C01331219D2B223
|
||||
S31508000C488B42F9D1454B0021DA71120E9A720122AC
|
||||
S31508000C581A7108221972597259719971A3F84420A0
|
||||
S31508000C6869E0FF23E3703E4B0722A3640023237140
|
||||
S31508000C786371A37123726372A372E271082345E054
|
||||
S31508000C88002056E0FF236278E3700023627123711F
|
||||
S31508000C98A371E37123720622A4F844204BE00023CB
|
||||
S31508000CA8237063703DE0421C3F21A06CFFF7DAFB16
|
||||
S31508000CB800283BD0FF23E370A36C3F33A36432E0DC
|
||||
S31508000CC843783E2B01D9222033E0FF23E370A4F8AA
|
||||
S31508000CD84460417821B9FFF7CBFB00282BD125E0E2
|
||||
S31508000CE81E4C821CA06CFFF7BDFBF8B16A78A36C92
|
||||
S31508000CF8D318A3641FE0FF23E3704022002323715F
|
||||
S31508000D086371E37123726372A2710723A4F84430EE
|
||||
S31508000D1811E0A06C6968FFF7A7FB10B906E0FFF7B2
|
||||
S31508000D289DFBFF23E370A4F8446004E0312000E04B
|
||||
S31508000D382020FFF7F5FE094C94F84330012B02D121
|
||||
S31508000D481020FFF7EDFEB4F844100648012384F88E
|
||||
S31508000D584330BDE87040FFF7D1BE70BD9C04002043
|
||||
S31508000D68C40F00089F04002000B503B400F008F873
|
||||
S31508000D7803BC02B4694609BE00F004F801BC00BD0C
|
||||
S30D08000D88704700BF704700BF69
|
||||
S31508000D90443A2F7573722F6665617365722F736F88
|
||||
S31508000DA06674776172652F4F70656E424C542F5486
|
||||
S31508000DB061726765742F44656D6F2F41524D434DBF
|
||||
S31508000DC0335F53544D33325F4F6C696D65785F53AB
|
||||
S31508000DD0544D3332503130335F43726F7373776FCC
|
||||
S31508000DE0726B732F426F6F742F6964652F2E2E2FC7
|
||||
S31508000DF06D61696E2E6300443A2F7573722F6665AE
|
||||
S31508000E00617365722F736F6674776172652F4F70A1
|
||||
S31508000E10656E424C542F5461726765742F44656D34
|
||||
S31508000E206F2F41524D434D335F53544D33325F4F0D
|
||||
S31508000E306C696D65785F53544D3332503130335F8A
|
||||
S31508000E4043726F7373776F726B732F426F6F742F62
|
||||
S31508000E506964652F2E2E2F2E2E2F2E2E2F2E2E2FF7
|
||||
S31508000E60536F757263652F41524D434D335F53542B
|
||||
S31508000E704D33322F43726F7373776F726B732F769E
|
||||
S31508000E806563746F72732E6300443A2F7573722FFD
|
||||
S31508000E906665617365722F736F6674776172652F05
|
||||
S31508000EA04F70656E424C542F5461726765742F44B7
|
||||
S31508000EB0656D6F2F41524D434D335F53544D333259
|
||||
S31508000EC05F4F6C696D65785F53544D3332503130DE
|
||||
S31508000ED0335F43726F7373776F726B732F426F6FE3
|
||||
S31508000EE0742F6964652F2E2E2F2E2E2F2E2E2F2E21
|
||||
S31508000EF02E2F536F757263652F41524D434D335FE5
|
||||
S31508000F0053544D33322F756172742E6300000000FE
|
||||
S31508000F100020000800200000010000000040000832
|
||||
S31508000F200020000002000000006000080020000009
|
||||
S31508000F3003000000008000080020000004000000F4
|
||||
S31508000F4000A00008002000000500000000C00008FE
|
||||
S31508000F50002000000600000000E000080020000055
|
||||
S31508000F60070000000000010800200000080000003B
|
||||
S31508000F7000200108002000000900000000400108C8
|
||||
S31508000F80002000000A0000000060010800200000A0
|
||||
S31508000F900B00000000800108002000000C00000083
|
||||
S31508000FA000A00108002000000D00000000C0010894
|
||||
S31508000FB0002000000E00000000E0010800200000EC
|
||||
S31108000FC00F0000004F70656E424C540094
|
||||
S705080001DB16
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader configuration header file
|
||||
| File Name: config.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef CONFIG_H
|
||||
#define CONFIG_H
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* To properly initialize the baudrate clocks of the communication interface, typically
|
||||
* the speed of the crystal oscillator and/or the speed at which the system runs is
|
||||
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
|
||||
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
|
||||
* not dependent on the targets architecture, the byte ordering needs to be known.
|
||||
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
|
||||
* big endian mode.
|
||||
*/
|
||||
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
|
||||
#define BOOT_CPU_SYSTEM_SPEED_KHZ (72000)
|
||||
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
|
||||
* in bits/second. Two CAN messages are reserved for communication with the host. The
|
||||
* message identifier for sending data from the target to the host is configured with
|
||||
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
|
||||
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
|
||||
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
|
||||
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
|
||||
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
|
||||
* CAN controller channel.
|
||||
*
|
||||
*/
|
||||
#define BOOT_COM_CAN_ENABLE (0)
|
||||
#define BOOT_COM_CAN_BAUDRATE (500000)
|
||||
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
|
||||
#define BOOT_COM_CAN_TX_MAX_DATA (8)
|
||||
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
|
||||
#define BOOT_COM_CAN_RX_MAX_DATA (8)
|
||||
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
|
||||
|
||||
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
|
||||
* in bits/second. The maximum amount of data bytes in a message for data transmission
|
||||
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
|
||||
* respectively. It is common for a microcontroller to have more than 1 UART interface
|
||||
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
|
||||
*
|
||||
*/
|
||||
#define BOOT_COM_UART_ENABLE (1)
|
||||
#define BOOT_COM_UART_BAUDRATE (57600)
|
||||
#define BOOT_COM_UART_TX_MAX_DATA (64)
|
||||
#define BOOT_COM_UART_RX_MAX_DATA (64)
|
||||
#define BOOT_COM_UART_CHANNEL_INDEX (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* It is possible to implement an application specific method to force the bootloader to
|
||||
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
|
||||
* situations where the user program does not run properly and therefore cannot
|
||||
* reactivate the bootloader. By enabling these hook functions, the application can
|
||||
* implement the backdoor, which overrides the default backdoor entry that is programmed
|
||||
* into the bootloader. When desired for security purposes, these hook functions can
|
||||
* also be implemented in a way that disables the backdoor entry altogether.
|
||||
*/
|
||||
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The NVM driver typically supports erase and program operations of the internal memory
|
||||
* present on the microcontroller. Through these hook functions the NVM driver can be
|
||||
* extended to support additional memory types such as external flash memory and serial
|
||||
* eeproms. The size of the internal memory in kilobytes is specified with configurable
|
||||
* BOOT_NVM_SIZE_KB.
|
||||
*/
|
||||
#define BOOT_NVM_HOOKS_ENABLE (0)
|
||||
#define BOOT_NVM_SIZE_KB (128)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The COP driver cannot be configured internally in the bootloader, because its use
|
||||
* and configuration is application specific. The bootloader does need to service the
|
||||
* watchdog in case it is used. When the application requires the use of a watchdog,
|
||||
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
|
||||
* hook functions.
|
||||
*/
|
||||
#define BOOT_COP_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
#endif /* CONFIG_H */
|
||||
/*********************************** end of config.h ***********************************/
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader callback source file
|
||||
| File Name: hooks.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
** NAME: BackDoorInitHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the backdoor entry option.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BackDoorInitHook(void)
|
||||
{
|
||||
/* configure the button connected to P0.16 as a digital input */
|
||||
IO0DIR &= ~(1<<16);
|
||||
} /*** end of BackDoorInitHook ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BackDoorEntryHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Checks if a backdoor entry is requested.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool BackDoorEntryHook(void)
|
||||
{
|
||||
/* button P0.16 has a pullup, so will read high by default. enter backdoor only when
|
||||
* this button is pressed. this is the case when it reads low */
|
||||
if ((IO0PIN & (1<<16)) == 0)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
return BLT_FALSE;
|
||||
} /*** end of BackDoorEntryHook ***/
|
||||
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
** NAME: NvmInitHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Callback that gets called at the start of the internal NVM driver
|
||||
** initialization routine.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInitHook(void)
|
||||
{
|
||||
} /*** end of NvmInitHook ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmWriteHook
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** data pointer to the data buffer.
|
||||
** RETURN VALUE: BTL_NVM_OKAY if successful, BTL_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BTL_NVM_ERROR is the write
|
||||
** operation failed.
|
||||
** DESCRIPTION: Callback that gets called at the start of the NVM driver write
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BTL_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||
** been written yet.
|
||||
**
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
return BTL_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmWriteHook ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmEraseHook
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** RETURN VALUE: BTL_NVM_OKAY if successful, BTL_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BTL_NVM_ERROR is the erase
|
||||
** operation failed.
|
||||
** DESCRIPTION: Callback that gets called at the start of the NVM driver erase
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BTL_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
||||
** hasn't been erased yet.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
return BTL_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmEraseHook ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmDoneHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Callback that gets called at the end of the NVM programming session.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDoneHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmDoneHook ***/
|
||||
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
** NAME: CopInitHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Callback that gets called at the end of the internal COP driver
|
||||
** initialization routine. It can be used to configure and enable the
|
||||
** watchdog.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopInitHook(void)
|
||||
{
|
||||
} /*** end of CopInitHook ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CopServiceHook
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Callback that gets called at the end of the internal COP driver
|
||||
** service routine. This gets called upon initialization and during
|
||||
** potential long lasting loops and routine. It can be used to service
|
||||
** the watchdog to prevent a watchdog reset.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopServiceHook(void)
|
||||
{
|
||||
} /*** end of CopServiceHook ***/
|
||||
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of hooks.c ************************************/
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Integrated Development Environment
|
||||
----------------------------------
|
||||
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
|
||||
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
<!DOCTYPE CrossStudio_Project_File>
|
||||
<solution Name="stm32f103_crossworks" target="8" version="2">
|
||||
<project Name="openbtl_olimex_stm32p103">
|
||||
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="-I./..;-I./../../../../Source;-I./../../../../Source/ARMCM3_STM32;-I./../../../../Source/ARMCM3_STM32/Crossworks" c_user_include_directories="$(TargetsDir)/STM32/include" gcc_optimization_level="Optimize For Size" link_include_standard_libraries="Yes" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName("$(Target)")" target_reset_script="Reset()"/>
|
||||
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
|
||||
<folder Name="Source Files">
|
||||
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
|
||||
<folder Name="Demo">
|
||||
<folder Name="Boot">
|
||||
<file file_name="../config.h"/>
|
||||
<file file_name="../hooks.c"/>
|
||||
<file file_name="../main.c"/>
|
||||
<file file_name="../stm32f10x.h"/>
|
||||
</folder>
|
||||
</folder>
|
||||
<folder Name="Source">
|
||||
<folder Name="ARMCM3_STM32">
|
||||
<folder Name="Crossworks">
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/Crossworks/cstart.s"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/Crossworks/vectors.c"/>
|
||||
</folder>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/can.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/can.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/cpu.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/cpu.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/nvm.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/nvm.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/timer.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/timer.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/types.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/uart.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/uart.h"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/flash.c"/>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/flash.h"/>
|
||||
</folder>
|
||||
<file file_name="../../../../Source/assert.c"/>
|
||||
<file file_name="../../../../Source/assert.h"/>
|
||||
<file file_name="../../../../Source/backdoor.c"/>
|
||||
<file file_name="../../../../Source/backdoor.h"/>
|
||||
<file file_name="../../../../Source/boot.c"/>
|
||||
<file file_name="../../../../Source/boot.h"/>
|
||||
<file file_name="../../../../Source/com.c"/>
|
||||
<file file_name="../../../../Source/com.h"/>
|
||||
<file file_name="../../../../Source/cop.c"/>
|
||||
<file file_name="../../../../Source/cop.h"/>
|
||||
<file file_name="../../../../Source/plausibility.h"/>
|
||||
<file file_name="../../../../Source/xcp.c"/>
|
||||
<file file_name="../../../../Source/xcp.h"/>
|
||||
</folder>
|
||||
</folder>
|
||||
<folder Name="System Files">
|
||||
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
|
||||
<configuration Name="Common" file_type="Reset Script"/>
|
||||
</file>
|
||||
<file file_name="../../../../Source/ARMCM3_STM32/Crossworks/memory.x">
|
||||
<configuration Name="Common" file_type="Linker Script"/>
|
||||
</file>
|
||||
</folder>
|
||||
<configuration Name="Debug" c_only_additional_options=""/>
|
||||
</project>
|
||||
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
|
||||
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
|
||||
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
|
||||
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
|
||||
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
|
||||
</solution>
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
<!DOCTYPE CrossStudio_for_ARM_Session_File>
|
||||
<session>
|
||||
<Bookmarks/>
|
||||
<Breakpoints/>
|
||||
<ETMWindow>
|
||||
<ETMRegister number="0" value="800" />
|
||||
<ETMRegister number="8" value="6f" />
|
||||
<ETMRegister number="9" value="1000000" />
|
||||
</ETMWindow>
|
||||
<ExecutionCountWindow/>
|
||||
<Memory1>
|
||||
<MemoryWindow autoEvaluate="0" addressText="0x08004004" numColumns="8" sizeText="4" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory1>
|
||||
<Memory2>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory2>
|
||||
<Memory3>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory3>
|
||||
<Memory4>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory4>
|
||||
<Project>
|
||||
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;openbtl_olimex_stm32p103" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;openbtl_olimex_stm32p103;Source Files" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;openbtl_olimex_stm32p103;Source Files;Demo" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;openbtl_olimex_stm32p103;Source Files;Demo;Boot" name="unnamed" />
|
||||
</Project>
|
||||
<Register1>
|
||||
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register1>
|
||||
<Register2>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register2>
|
||||
<Register3>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register3>
|
||||
<Register4>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register4>
|
||||
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
|
||||
<TraceWindow>
|
||||
<Trace enabled="Yes" />
|
||||
</TraceWindow>
|
||||
<Watch1>
|
||||
<Watches active="1" update="Never" >
|
||||
<Watchpoint linenumber="121" radix="-1" name="free_running_counter_last" expression="free_running_counter_last" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
|
||||
<Watchpoint linenumber="152" radix="-1" name="free_running_counter_accumulative" expression="free_running_counter_accumulative" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
|
||||
<Watchpoint linenumber="124" radix="-1" name="free_running_counter_now" expression="free_running_counter_now" filename="d:/usr/feaser/software/openblt/target/source/armcm3_stm32/timer.c" />
|
||||
</Watches>
|
||||
</Watch1>
|
||||
<Watch2>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch2>
|
||||
<Watch3>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch3>
|
||||
<Watch4>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch4>
|
||||
<Files>
|
||||
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="13" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Boot\main.c" y="57" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Boot\main.c" left="0" selected="1" name="unnamed" top="51" />
|
||||
</Files>
|
||||
<ARMCrossStudioWindow activeProject="openbtl_olimex_stm32p103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_STM32" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
|
||||
</session>
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader application source file
|
||||
| File Name: main.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "stm32f10x.h" /* microcontroller registers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: main
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: program return code
|
||||
** DESCRIPTION: This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader */
|
||||
BootInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* run the bootloader task */
|
||||
BootTask();
|
||||
}
|
||||
|
||||
/* program should never get here */
|
||||
return 0;
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: Init
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the microcontroller. The interrupts are disabled, the
|
||||
** clocks are configured and the flash wait states are configured.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;
|
||||
blt_int32u pll_multiplier;
|
||||
|
||||
/* reset the RCC clock configuration to the default reset state (for debug purpose) */
|
||||
/* set HSION bit */
|
||||
RCC->CR |= (blt_int32u)0x00000001;
|
||||
/* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
|
||||
RCC->CFGR &= (blt_int32u)0xF8FF0000;
|
||||
/* reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (blt_int32u)0xFEF6FFFF;
|
||||
/* reset HSEBYP bit */
|
||||
RCC->CR &= (blt_int32u)0xFFFBFFFF;
|
||||
/* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
|
||||
RCC->CFGR &= (blt_int32u)0xFF80FFFF;
|
||||
/* disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000;
|
||||
/* enable HSE */
|
||||
RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
|
||||
/* wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
}
|
||||
while((HSEStatus == 0) && (StartUpCounter != 1500));
|
||||
/* check if time out was reached */
|
||||
if ((RCC->CR & RCC_CR_HSERDY) == RESET)
|
||||
{
|
||||
/* cannot continue when HSE is not ready */
|
||||
ASSERT_RT(BLT_FALSE);
|
||||
}
|
||||
/* enable flash prefetch buffer */
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
/* reset flash wait state configuration to default 0 wait states */
|
||||
FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
|
||||
#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
|
||||
/* configure 2 flash wait states */
|
||||
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
|
||||
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
|
||||
/* configure 1 flash wait states */
|
||||
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
|
||||
#endif
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK/2 */
|
||||
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;
|
||||
/* PCLK1 = HCLK/2 */
|
||||
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;
|
||||
/* reset PLL configuration */
|
||||
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
|
||||
RCC_CFGR_PLLMULL));
|
||||
/* assert that the pll_multiplier is between 2 and 16 */
|
||||
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);
|
||||
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);
|
||||
/* calculate multiplier value */
|
||||
pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
|
||||
/* convert to register value */
|
||||
pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);
|
||||
/* set the PLL multiplier and clock source */
|
||||
RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
|
||||
/* enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
/* wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* select PLL as system clock source */
|
||||
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
|
||||
/* wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
|
||||
{
|
||||
}
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/* enable clock for USART2 peripheral */
|
||||
RCC->APB1ENR |= (blt_int32u)0x00020000;
|
||||
/* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */
|
||||
RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001);
|
||||
/* configure USART2 Tx (GPIOA2) as alternate function push-pull */
|
||||
/* first reset the configuration */
|
||||
GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8);
|
||||
/* CNF2[1:0] = %10 and MODE2[1:0] = %11 */
|
||||
GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8);
|
||||
/* configure USART2 Rx (GPIOA3) as alternate function input floating */
|
||||
/* first reset the configuration */
|
||||
GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12);
|
||||
/* CNF2[1:0] = %01 and MODE2[1:0] = %00 */
|
||||
GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12);
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */
|
||||
RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001);
|
||||
/* configure CAN Rx (GPIOB8) as alternate function input pull-up */
|
||||
/* first reset the configuration */
|
||||
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0);
|
||||
/* CNF8[1:0] = %10 and MODE8[1:0] = %00 */
|
||||
GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0);
|
||||
/* configure CAN Tx (GPIOB9) as alternate function push-pull */
|
||||
/* first reset the configuration */
|
||||
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4);
|
||||
/* CNF9[1:0] = %10 and MODE9[1:0] = %11 */
|
||||
GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4);
|
||||
/* remap CAN1 pins to PortB */
|
||||
AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13);
|
||||
AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13);
|
||||
/* enable clocks for CAN controller peripheral */
|
||||
RCC->APB1ENR |= (blt_int32u)0x02000000;
|
||||
#endif
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,254 @@
|
|||
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||||
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||||
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|
||||
S31508002CC880B482B000AF786039603B68002B0CD0BE
|
||||
S31508002CD84FF48053C4F202034FF48052C4F202023E
|
||||
S31508002CE8D1697A680A43DA610DE04FF48053C4F271
|
||||
S31508002CF802034FF48052C4F20202D1697A686FEA75
|
||||
S31508002D0802020A40DA6107F10807BD4680BC704727
|
||||
S31508002D1880B58CB000AF786039604FF00003FB626D
|
||||
S31508002D284FF00003BB624FF000037B624FF00003CD
|
||||
S31508002D383B624FF00003FB617B68FB617B681B8A7B
|
||||
S31508002D489BB2FB62FA6A4CF6FF731340FB623B6858
|
||||
S31508002D58DB88FA6A1343FB62FB6A9AB27B681A82B3
|
||||
S31508002D687B689B899BB2FB62FA6A4EF6F31313409B
|
||||
S31508002D78FB623B689A883B681B8913439AB23B688F
|
||||
S31508002D885B8913439BB2FA6A1343FB62FB6A9AB2DE
|
||||
S31508002D987B689A817B689B8A9BB2FB62FA6A4FF6C4
|
||||
S31508002DA8FF431340FB623B689B89FA6A1343FB623D
|
||||
S31508002DB8FB6A9AB27B689A8207F108031846FFF7F6
|
||||
S31508002DC86DFEFA694FF46053C4F201039A4202D1C0
|
||||
S31508002DD87B69BB6201E03B69BB627B689B899BB2E6
|
||||
S31508002DE89BB21BB2002B0FDABA6A13464FEA830363
|
||||
S31508002DF89B184FEA83029A183B681B684FEA4303F5
|
||||
S31508002E08B2FBF3F37B620EE0BA6A13464FEA830312
|
||||
S31508002E189B184FEA83029A183B681B684FEA830394
|
||||
S31508002E28B2FBF3F37B627A6A48F21F53C5F2EB13D7
|
||||
S31508002E38A3FB02134FEA53134FEA0313FB62FB6A19
|
||||
S31508002E484FEA13134FF0640202FB03F37A6AD31AA4
|
||||
S31508002E583B627B689B899BB29BB21BB2002B12DA3A
|
||||
S31508002E683B6A4FEAC30303F1320248F21F53C5F21D
|
||||
S31508002E78EB13A3FB02134FEA531303F00703FA6A8B
|
||||
S31508002E881343FB6211E03B6A4FEA031303F132026C
|
||||
S31508002E9848F21F53C5F2EB13A3FB02134FEA531369
|
||||
S31508002EA803F00F03FA6A1343FB62FB6A9AB27B685C
|
||||
S31508002EB81A8107F13007BD4680BD00BF80B482B0CD
|
||||
S31508002EC800AF786039603B68002B08D07B689B891F
|
||||
S31508002ED89BB243F400539AB27B689A8107E07B68F1
|
||||
S31508002EE89B899BB223F400539AB27B689A8107F1AF
|
||||
S31508002EF80807BD4680BC704780B481B000AF38600B
|
||||
S31508002F083B689B889BB24FEAC3534FEAD3539BB29D
|
||||
S31508002F18184607F10407BD4680BC704780B483B0DD
|
||||
S31508002F2800AF78600B463B804FF00003BB607B68B8
|
||||
S31508002F381B889AB23B8813409BB2002B03D04FF0EC
|
||||
S31508002F480103BB6002E04FF00003BB60BB6818468C
|
||||
S31508002F5807F10C07BD4680BC704700BF00B503B42F
|
||||
S31508002F6800F008F803BC02B4694609BE00F004F884
|
||||
S31108002F7801BC00BD704700BF704700BFD9
|
||||
S31508002F8400000000010203040102030406070809FD
|
||||
S30908002F940204060817
|
||||
S705080021F7DA
|
||||
|
|
@ -0,0 +1,375 @@
|
|||
/****************************************************************************************
|
||||
| Description: demo program bootloader interface source file
|
||||
| File Name: boot.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BootActivate
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Bootloader activation function.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootActivate(void)
|
||||
{
|
||||
void (*pEntryFromProgFnc)(void);
|
||||
|
||||
/* set pointer to the address of function EntryFromProg in the bootloader. note that
|
||||
* 1 is added to this address to enable a switch from Thumb2 to Thumb mode
|
||||
*/
|
||||
pEntryFromProgFnc = (void*)0x08000150 + 1;
|
||||
/* call EntryFromProg to activate the bootloader. */
|
||||
pEntryFromProgFnc();
|
||||
} /*** end of BootActivate ***/
|
||||
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BootComInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the UART communication interface
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
USART_InitTypeDef USART_InitStruct;
|
||||
|
||||
/* enable UART peripheral clock */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
/* enable GPIO peripheral clock for transmitter and receiver pins */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
|
||||
/* configure USART Tx as alternate function push-pull */
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
/* Configure USART Rx as alternate function input floating */
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
/* configure UART communcation parameters */
|
||||
USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE;
|
||||
USART_InitStruct.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStruct.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStruct.USART_Parity = USART_Parity_No;
|
||||
USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART2, &USART_InitStruct);
|
||||
/* enable UART */
|
||||
USART_Cmd(USART2, ENABLE);
|
||||
} /*** end of BootComInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BootComCheckActivationRequest
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComCheckActivationRequest(void)
|
||||
{
|
||||
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
|
||||
static unsigned char xcpCtoRxLength;
|
||||
static unsigned char xcpCtoRxInProgress = 0;
|
||||
|
||||
/* start of cto packet received? */
|
||||
if (xcpCtoRxInProgress == 0)
|
||||
{
|
||||
/* store the message length when received */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
|
||||
{
|
||||
/* indicate that a cto packet is being received */
|
||||
xcpCtoRxInProgress = 1;
|
||||
|
||||
/* reset packet data count */
|
||||
xcpCtoRxLength = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* store the next packet byte */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
|
||||
{
|
||||
/* increment the packet data count */
|
||||
xcpCtoRxLength++;
|
||||
|
||||
/* check to see if the entire packet was received */
|
||||
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||
{
|
||||
/* done with cto packet reception */
|
||||
xcpCtoRxInProgress = 0;
|
||||
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComCheckActivationRequest ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: UartReceiveByte
|
||||
** PARAMETER: data pointer to byte where the data is to be stored.
|
||||
** RETURN VALUE: 1 if a byte was received, 0 otherwise.
|
||||
** DESCRIPTION: Receives a communication interface byte if one is present.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data)
|
||||
{
|
||||
/* check flag to see if a byte was received */
|
||||
if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == SET)
|
||||
{
|
||||
/* retrieve and store the newly received byte */
|
||||
*data = (unsigned char)USART_ReceiveData(USART2);
|
||||
/* all done */
|
||||
return 1;
|
||||
}
|
||||
/* still here to no new byte received */
|
||||
return 0;
|
||||
} /*** end of UartReceiveByte ***/
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
typedef struct t_can_bus_timing
|
||||
{
|
||||
unsigned char tseg1; /* CAN time segment 1 */
|
||||
unsigned char tseg2; /* CAN time segment 2 */
|
||||
} tCanBusTiming; /* bus timing structure type */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/* According to the CAN protocol 1 bit-time can be made up of between 8..25 time quanta
|
||||
* (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC always being 1.
|
||||
* The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) * 100%. This array contains
|
||||
* possible and valid time quanta configurations with a sample point between 68..78%.
|
||||
*/
|
||||
static const tCanBusTiming canTiming[] =
|
||||
{ /* TQ | TSEG1 | TSEG2 | SP */
|
||||
/* ------------------------- */
|
||||
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
|
||||
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
|
||||
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
|
||||
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
|
||||
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
|
||||
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
|
||||
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
|
||||
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
|
||||
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
|
||||
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
|
||||
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
|
||||
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
|
||||
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
|
||||
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
|
||||
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
|
||||
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
|
||||
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
|
||||
{ 16, 8 } /* 25 | 16 | 8 | 68% */
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CanGetSpeedConfig
|
||||
** PARAMETER: baud The desired baudrate in kbps. Valid values are 10..1000.
|
||||
** prescaler Pointer to where the value for the prescaler will be stored.
|
||||
** tseg1 Pointer to where the value for TSEG2 will be stored.
|
||||
** tseg2 Pointer to where the value for TSEG2 will be stored.
|
||||
** RETURN VALUE: 1 if the CAN bustiming register values were found, 0 otherwise.
|
||||
** DESCRIPTION: Search algorithm to match the desired baudrate to a possible bus
|
||||
** timing configuration.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
|
||||
unsigned char *tseg1, unsigned char *tseg2)
|
||||
{
|
||||
unsigned char cnt;
|
||||
|
||||
/* loop through all possible time quanta configurations to find a match */
|
||||
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
|
||||
{
|
||||
if (((BOOT_CPU_SYSTEM_SPEED_KHZ/2) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
|
||||
{
|
||||
/* compute the prescaler that goes with this TQ configuration */
|
||||
*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/2)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
|
||||
|
||||
/* make sure the prescaler is valid */
|
||||
if ( (*prescaler > 0) && (*prescaler <= 1024) )
|
||||
{
|
||||
/* store the bustiming configuration */
|
||||
*tseg1 = canTiming[cnt].tseg1;
|
||||
*tseg2 = canTiming[cnt].tseg2;
|
||||
/* found a good bus timing configuration */
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* could not find a good bus timing configuration */
|
||||
return 0;
|
||||
} /*** end of CanGetSpeedConfig ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BootComInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the CAN communication interface
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
CAN_InitTypeDef CAN_InitStructure;
|
||||
CAN_FilterInitTypeDef CAN_FilterInitStructure;
|
||||
unsigned short prescaler;
|
||||
unsigned char tseg1, tseg2;
|
||||
|
||||
/* GPIO clock enable */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
/* Configure CAN pin: RX */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
/* Configure CAN pin: TX */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
/* Remap CAN1 pins to PortB */
|
||||
GPIO_PinRemapConfig(GPIO_Remap1_CAN1 , ENABLE);
|
||||
/* CAN1 Periph clock enable */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
|
||||
/* CAN register init */
|
||||
CAN_DeInit(CAN1);
|
||||
CAN_StructInit(&CAN_InitStructure);
|
||||
/* obtain the bittiming configuration for this baudrate */
|
||||
CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
|
||||
/* CAN controller init */
|
||||
CAN_InitStructure.CAN_TTCM = DISABLE;
|
||||
CAN_InitStructure.CAN_ABOM = DISABLE;
|
||||
CAN_InitStructure.CAN_AWUM = DISABLE;
|
||||
CAN_InitStructure.CAN_NART = DISABLE;
|
||||
CAN_InitStructure.CAN_RFLM = DISABLE;
|
||||
CAN_InitStructure.CAN_TXFP = DISABLE;
|
||||
CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
|
||||
/* CAN Baudrate init */
|
||||
CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
|
||||
CAN_InitStructure.CAN_BS1 = tseg1 - 1;
|
||||
CAN_InitStructure.CAN_BS2 = tseg2 - 1;
|
||||
CAN_InitStructure.CAN_Prescaler = prescaler;
|
||||
CAN_Init(CAN1, &CAN_InitStructure);
|
||||
/* CAN filter init - receive all messages */
|
||||
CAN_FilterInitStructure.CAN_FilterNumber = 0;
|
||||
CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
|
||||
CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
|
||||
CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
|
||||
CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
|
||||
CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
|
||||
CAN_FilterInit(&CAN_FilterInitStructure);
|
||||
} /*** end of BootComInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: BootComCheckActivationRequest
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComCheckActivationRequest(void)
|
||||
{
|
||||
CanRxMsg RxMessage;
|
||||
|
||||
/* check if a new message was received */
|
||||
if (CAN_MessagePending(CAN1, CAN_FIFO0) > 0)
|
||||
{
|
||||
/* receive the message */
|
||||
CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
|
||||
if (RxMessage.StdId == BOOT_COM_CAN_RX_MSG_ID)
|
||||
{
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((RxMessage.Data[0] == 0xff) && (RxMessage.Data[1] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComCheckActivationRequest ***/
|
||||
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of boot.c *************************************/
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/****************************************************************************************
|
||||
| Description: demo program bootloader interface header file
|
||||
| File Name: boot.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef BOOT_H
|
||||
#define BOOT_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void BootComInit(void);
|
||||
void BootComCheckActivationRequest(void);
|
||||
|
||||
|
||||
#endif /* BOOT_H */
|
||||
/*********************************** end of boot.h *************************************/
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2009 Rowley Associates Limited. *
|
||||
* *
|
||||
* This file may be distributed under the terms of the License Agreement *
|
||||
* provided with this software. *
|
||||
* *
|
||||
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
|
||||
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Preprocessor Definitions
|
||||
* ------------------------
|
||||
* APP_ENTRY_POINT
|
||||
*
|
||||
* Defines the application entry point function, if undefined this setting
|
||||
* defaults to "main".
|
||||
*
|
||||
* USE_PROCESS_STACK
|
||||
*
|
||||
* If defined, thread mode will be configured to use the process stack if
|
||||
* the size of the process stack is greater than zero bytes in length.
|
||||
*
|
||||
* INITIALIZE_STACK
|
||||
*
|
||||
* If defined, the contents of the stack will be initialized to a the
|
||||
* value 0xCC.
|
||||
*
|
||||
* INITIALIZE_SECONDARY_SECTIONS
|
||||
*
|
||||
* If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
|
||||
*
|
||||
* FULL_LIBRARY
|
||||
*
|
||||
* If defined then
|
||||
* - argc, argv are setup by the debug_getargs.
|
||||
* - the exit symbol is defined and executes on return from main.
|
||||
* - the exit symbol calls destructors, atexit functions and then debug_exit.
|
||||
*
|
||||
* If not defined then
|
||||
* - argc and argv are zero.
|
||||
* - the exit symbol is defined, executes on return from main and loops
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef APP_ENTRY_POINT
|
||||
#define APP_ENTRY_POINT main
|
||||
#endif
|
||||
|
||||
#ifndef ARGSSPACE
|
||||
#define ARGSSPACE 128
|
||||
#endif
|
||||
|
||||
.global _start
|
||||
.extern APP_ENTRY_POINT
|
||||
.global exit
|
||||
.global reset_handler
|
||||
|
||||
.section .init, "ax"
|
||||
.code 16
|
||||
.align 2
|
||||
.thumb_func
|
||||
|
||||
_start:
|
||||
ldr r1, =__stack_end__
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
mov sp, r1
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
ldr r0, =__stack_start__
|
||||
bl memory_set
|
||||
#endif
|
||||
|
||||
#ifdef USE_PROCESS_STACK
|
||||
/* Set up process stack if size > 0 */
|
||||
ldr r1, =__stack_process_end__
|
||||
ldr r0, =__stack_process_start__
|
||||
sub r2, r1, r0
|
||||
beq 1f
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
msr psp, r1
|
||||
mov r2, #2
|
||||
msr control, r2
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
bl memory_set
|
||||
#endif
|
||||
1:
|
||||
#endif
|
||||
/* Copy initialised memory sections into RAM (if necessary). */
|
||||
ldr r0, =__data_load_start__
|
||||
ldr r1, =__data_start__
|
||||
ldr r2, =__data_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text_load_start__
|
||||
ldr r1, =__text_start__
|
||||
ldr r2, =__text_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__fast_load_start__
|
||||
ldr r1, =__fast_start__
|
||||
ldr r2, =__fast_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__ctors_load_start__
|
||||
ldr r1, =__ctors_start__
|
||||
ldr r2, =__ctors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__dtors_load_start__
|
||||
ldr r1, =__dtors_start__
|
||||
ldr r2, =__dtors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata_load_start__
|
||||
ldr r1, =__rodata_start__
|
||||
ldr r2, =__rodata_end__
|
||||
bl memory_copy
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__data2_load_start__
|
||||
ldr r1, =__data2_start__
|
||||
ldr r2, =__data2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text2_load_start__
|
||||
ldr r1, =__text2_start__
|
||||
ldr r2, =__text2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata2_load_start__
|
||||
ldr r1, =__rodata2_start__
|
||||
ldr r2, =__rodata2_end__
|
||||
bl memory_copy
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Zero the bss. */
|
||||
ldr r0, =__bss_start__
|
||||
ldr r1, =__bss_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__bss2_start__
|
||||
ldr r1, =__bss2_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Initialise the heap */
|
||||
ldr r0, = __heap_start__
|
||||
ldr r1, = __heap_end__
|
||||
sub r1, r1, r0
|
||||
cmp r1, #8
|
||||
blt 1f
|
||||
mov r2, #0
|
||||
str r2, [r0]
|
||||
add r0, r0, #4
|
||||
str r1, [r0]
|
||||
1:
|
||||
|
||||
/* Call constructors */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0]
|
||||
add r0, #4
|
||||
push {r0-r1}
|
||||
blx r2
|
||||
pop {r0-r1}
|
||||
b ctor_loop
|
||||
ctor_end:
|
||||
|
||||
/* Setup initial call frame */
|
||||
mov r0, #0
|
||||
mov lr, r0
|
||||
mov r12, sp
|
||||
|
||||
start:
|
||||
/* Jump to application entry point */
|
||||
#ifdef FULL_LIBRARY
|
||||
mov r0, #ARGSSPACE
|
||||
ldr r1, =args
|
||||
ldr r2, =debug_getargs
|
||||
blx r2
|
||||
ldr r1, =args
|
||||
#else
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
#endif
|
||||
ldr r2, =APP_ENTRY_POINT
|
||||
blx r2
|
||||
|
||||
.thumb_func
|
||||
exit:
|
||||
#ifdef FULL_LIBRARY
|
||||
mov r5, r0 // save the exit parameter/return result
|
||||
|
||||
/* Call destructors */
|
||||
ldr r0, =__dtors_start__
|
||||
ldr r1, =__dtors_end__
|
||||
dtor_loop:
|
||||
cmp r0, r1
|
||||
beq dtor_end
|
||||
ldr r2, [r0]
|
||||
add r0, #4
|
||||
push {r0-r1}
|
||||
blx r2
|
||||
pop {r0-r1}
|
||||
b dtor_loop
|
||||
dtor_end:
|
||||
|
||||
/* Call atexit functions */
|
||||
ldr r2, =_execute_at_exit_fns
|
||||
blx r2
|
||||
|
||||
/* Call debug_exit with return result/exit parameter */
|
||||
mov r0, r5
|
||||
ldr r2, =debug_exit
|
||||
blx r2
|
||||
#endif
|
||||
|
||||
/* Returned from application entry point, loop forever. */
|
||||
exit_loop:
|
||||
b exit_loop
|
||||
|
||||
.thumb_func
|
||||
memory_copy:
|
||||
cmp r0, r1
|
||||
beq 2f
|
||||
sub r2, r2, r1
|
||||
beq 2f
|
||||
1:
|
||||
ldrb r3, [r0]
|
||||
add r0, r0, #1
|
||||
strb r3, [r1]
|
||||
add r1, r1, #1
|
||||
sub r2, r2, #1
|
||||
bne 1b
|
||||
2:
|
||||
bx lr
|
||||
|
||||
.thumb_func
|
||||
memory_set:
|
||||
cmp r0, r1
|
||||
beq 1f
|
||||
strb r2, [r0]
|
||||
add r0, r0, #1
|
||||
b memory_set
|
||||
1:
|
||||
bx lr
|
||||
|
||||
.thumb_func
|
||||
|
||||
reset_handler:
|
||||
|
||||
#ifdef VECTORS_IN_RAM
|
||||
ldr r0, =__vectors_load_start__
|
||||
ldr r1, =__vectors_load_end__
|
||||
ldr r2, =_vectors_ram
|
||||
l0:
|
||||
cmp r0, r1
|
||||
beq l1
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r2], #4
|
||||
b l0
|
||||
l1:
|
||||
#endif
|
||||
|
||||
#ifdef __TARGET_F4XX
|
||||
#ifndef __NO_FPU
|
||||
movw r0, 0xED88
|
||||
movt r0, 0xE000
|
||||
ldr r1, [r0]
|
||||
orrs r1, r1, #(0xf << 20)
|
||||
str r1, [r0]
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Configure vector table offset register */
|
||||
ldr r0, =0xE000ED08
|
||||
#ifdef VECTORS_IN_RAM
|
||||
ldr r1, =_vectors_ram
|
||||
#else
|
||||
ldr r1, =_vectors
|
||||
#endif
|
||||
str r1, [r0]
|
||||
|
||||
b _start
|
||||
|
||||
|
||||
|
||||
#ifdef FULL_LIBRARY
|
||||
.bss
|
||||
args:
|
||||
.space ARGSSPACE
|
||||
#endif
|
||||
|
||||
/* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
|
||||
.section .stack, "wa", %nobits
|
||||
.section .stack_process, "wa", %nobits
|
||||
.section .heap, "wa", %nobits
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/****************************************************************************************
|
||||
| Description: generic header file
|
||||
| File Name: header.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef HEADER_H
|
||||
#define HEADER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "../Boot/config.h" /* bootloader configuration */
|
||||
#include "stm32f10x.h" /* STM32 register definitions */
|
||||
#include "stm32f10x_conf.h" /* STM32 peripheral drivers */
|
||||
#include "boot.h" /* bootloader interface driver */
|
||||
#include "irq.h" /* IRQ driver */
|
||||
#include "led.h" /* LED driver */
|
||||
#include "timer.h" /* Timer driver */
|
||||
|
||||
|
||||
#endif /* HEADER_H */
|
||||
/*********************************** end of header.h ***********************************/
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Integrated Development Environment
|
||||
----------------------------------
|
||||
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
|
||||
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
<!DOCTYPE CrossStudio_Project_File>
|
||||
<solution Name="stm32f103_crossworks" target="8" version="2">
|
||||
<project Name="demoprog_olimex_stm32p103">
|
||||
<configuration Name="Common" Placement="Flash" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/STM32/STM32SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="STM32F103RB;0x20000;0x5000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_target_loader_parameter="8000000" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_only_additional_options="" c_preprocessor_definitions="USE_STDPERIPH_DRIVER ;VECT_TAB_FLASH;GCC_ARMCM3" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib/stdperiphlib;$(ProjectDir)/../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/CoreSupport;$(ProjectDir)/../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x" gcc_optimization_level="None" link_include_standard_libraries="Yes" linker_keep_symbols="_vectors" linker_memory_map_file="$(TargetsDir)/STM32/STM32F103RB_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/STM32/propertyGroups.xml" target_get_partname_script="GetPartName()" target_match_partname_script="MatchPartName("$(Target)")" target_reset_script="Reset()"/>
|
||||
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/STM32/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_target_loader_can_lock_all="No" arm_target_loader_can_lock_range="No" arm_target_loader_can_unlock_all="No" arm_target_loader_can_unlock_range="No" target_reset_script="FLASHReset()"/>
|
||||
<folder Name="Source Files">
|
||||
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
|
||||
<folder Name="Demo">
|
||||
<folder Name="Prog">
|
||||
<file file_name="../cstart.s"/>
|
||||
<file file_name="../header.h"/>
|
||||
<file file_name="../led.c"/>
|
||||
<file file_name="../led.h"/>
|
||||
<file file_name="../main.c"/>
|
||||
<file file_name="../stm32f10x.h"/>
|
||||
<file file_name="../timer.c"/>
|
||||
<file file_name="../timer.h"/>
|
||||
<file file_name="../vectors.c"/>
|
||||
<file file_name="../irq.c"/>
|
||||
<file file_name="../irq.h"/>
|
||||
<file file_name="../boot.c"/>
|
||||
<file file_name="../boot.h"/>
|
||||
</folder>
|
||||
</folder>
|
||||
</folder>
|
||||
<folder Name="System Files">
|
||||
<file file_name="$(TargetsDir)/STM32/STM32_Target.js">
|
||||
<configuration Name="Common" file_type="Reset Script"/>
|
||||
</file>
|
||||
<file file_name="../memory.x">
|
||||
<configuration Name="Common" file_type="Linker Script"/>
|
||||
</file>
|
||||
</folder>
|
||||
<configuration Name="Debug" c_only_additional_options=""/>
|
||||
<folder Name="Library Files">
|
||||
<file file_name="../lib/stdperiphlib/stm32f10x_conf.h"/>
|
||||
<folder Name="STM32F10x_StdPeriph_Driver">
|
||||
<folder Name="inc">
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h"/>
|
||||
</folder>
|
||||
<folder Name="src">
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c"/>
|
||||
<file file_name="../lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c"/>
|
||||
</folder>
|
||||
</folder>
|
||||
<folder Name="CMSIS">
|
||||
<folder Name="CM3">
|
||||
<folder Name="CoreSupport">
|
||||
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c"/>
|
||||
<file file_name="../lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h"/>
|
||||
</folder>
|
||||
<folder Name="DeviceSupport">
|
||||
<folder Name="ST">
|
||||
<folder Name="STM32F10x">
|
||||
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"/>
|
||||
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c"/>
|
||||
<file file_name="../lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h"/>
|
||||
</folder>
|
||||
</folder>
|
||||
</folder>
|
||||
</folder>
|
||||
</folder>
|
||||
</folder>
|
||||
</project>
|
||||
<configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug"/>
|
||||
<configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
|
||||
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
|
||||
<configuration Name="THUMB Release" inherited_configurations="THUMB;Release"/>
|
||||
<configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
|
||||
</solution>
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
<!DOCTYPE CrossStudio_for_ARM_Session_File>
|
||||
<session>
|
||||
<Bookmarks/>
|
||||
<Breakpoints/>
|
||||
<ETMWindow>
|
||||
<ETMRegister number="0" value="800" />
|
||||
<ETMRegister number="8" value="6f" />
|
||||
<ETMRegister number="9" value="1000000" />
|
||||
</ETMWindow>
|
||||
<ExecutionCountWindow/>
|
||||
<Memory1>
|
||||
<MemoryWindow autoEvaluate="0" addressText="0" numColumns="8" sizeText="32" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory1>
|
||||
<Memory2>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory2>
|
||||
<Memory3>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory3>
|
||||
<Memory4>
|
||||
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
|
||||
</Memory4>
|
||||
<Project>
|
||||
<ProjectSessionItem path="stm32f103_crossworks" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32p103" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32p103;Source Files" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32p103;Source Files;Demo" name="unnamed" />
|
||||
<ProjectSessionItem path="stm32f103_crossworks;demoprog_olimex_stm32p103;Source Files;Demo;Prog" name="unnamed" />
|
||||
</Project>
|
||||
<Register1>
|
||||
<RegisterWindow openNodes="CPU" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="CPU" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register1>
|
||||
<Register2>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register2>
|
||||
<Register3>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register3>
|
||||
<Register4>
|
||||
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
|
||||
</Register4>
|
||||
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
|
||||
<TraceWindow>
|
||||
<Trace enabled="Yes" />
|
||||
</TraceWindow>
|
||||
<Watch1>
|
||||
<Watches active="1" update="Never" />
|
||||
</Watch1>
|
||||
<Watch2>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch2>
|
||||
<Watch3>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch3>
|
||||
<Watch4>
|
||||
<Watches active="0" update="Never" />
|
||||
</Watch4>
|
||||
<Files>
|
||||
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="28" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Prog\main.c" y="144" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="129" />
|
||||
</Files>
|
||||
<ARMCrossStudioWindow activeProject="demoprog_olimex_stm32p103" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_STM32_Olimex_STM32P103_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="266111" debugSearchPath="" buildConfiguration="THUMB Debug" />
|
||||
</session>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/****************************************************************************************
|
||||
| Description: IRQ driver source file
|
||||
| File Name: irq.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data definitions
|
||||
****************************************************************************************/
|
||||
static unsigned char interruptNesting = 0; /* used for global interrupt en/disable */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: IrqInterruptEnable
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Enables the generation IRQ interrupts. Typically called once during
|
||||
** software startup after completion of the initialization.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptEnable(void)
|
||||
{
|
||||
__enable_irq();
|
||||
} /*** end of IrqInterruptEnable ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: HwInterruptDisable
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Disables the generation IRQ interrupts and stores information on
|
||||
** whether or not the interrupts were already disabled before explicitly
|
||||
** disabling them with this function. Normally used as a pair together
|
||||
** with IrqInterruptRestore during a critical section.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptDisable(void)
|
||||
{
|
||||
if (interruptNesting == 0)
|
||||
{
|
||||
__disable_irq();
|
||||
}
|
||||
interruptNesting++;
|
||||
} /*** end of IrqInterruptDisable ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: IrqInterruptRestore
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Restore the generation IRQ interrupts to the setting it had prior to
|
||||
** calling IrqInterruptDisable. Normally used as a pair together with
|
||||
** IrqInterruptDisable during a critical section.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptRestore(void)
|
||||
{
|
||||
interruptNesting--;
|
||||
if (interruptNesting == 0)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
} /*** end of IrqInterruptRestore ***/
|
||||
|
||||
|
||||
/*********************************** end of irq.c **************************************/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/****************************************************************************************
|
||||
| Description: IRQ driver header file
|
||||
| File Name: irq.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef IRQ_H
|
||||
#define IRQ_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void IrqInterruptEnable(void);
|
||||
void IrqInterruptDisable(void);
|
||||
void IrqInterruptRestore(void);
|
||||
|
||||
|
||||
#endif /* IRQ_H */
|
||||
/*********************************** end of irq.h **************************************/
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/****************************************************************************************
|
||||
| Description: LED driver source file
|
||||
| File Name: led.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#define LED_TOGGLE_MS (500) /* toggle interval time in millisecodns */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: LedInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the LED.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
gpio_init.GPIO_Pin = GPIO_Pin_12;
|
||||
gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
gpio_init.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(GPIOC, &gpio_init);
|
||||
} /*** end of LedInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: LedToggle
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Toggles the LED at a fixed time interval.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedToggle(void)
|
||||
{
|
||||
static unsigned char led_toggle_state = 0;
|
||||
static unsigned long timer_counter_last = 0;
|
||||
unsigned long timer_counter_now;
|
||||
|
||||
/* check if toggle interval time passed */
|
||||
timer_counter_now = TimerGet();
|
||||
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
|
||||
{
|
||||
/* not yet time to toggle */
|
||||
return;
|
||||
}
|
||||
|
||||
/* determine toggle action */
|
||||
if (led_toggle_state == 0)
|
||||
{
|
||||
led_toggle_state = 1;
|
||||
/* turn the LED on */
|
||||
GPIO_ResetBits(GPIOC, GPIO_Pin_12);
|
||||
}
|
||||
else
|
||||
{
|
||||
led_toggle_state = 0;
|
||||
/* turn the LED off */
|
||||
GPIO_SetBits(GPIOC, GPIO_Pin_12);
|
||||
}
|
||||
|
||||
/* store toggle time to determine next toggle interval */
|
||||
timer_counter_last = timer_counter_now;
|
||||
} /*** end of LedToggle ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/****************************************************************************************
|
||||
| Description: LED driver header file
|
||||
| File Name: led.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedInit(void);
|
||||
void LedToggle(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
|
|
@ -0,0 +1,784 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm3.c
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
|
||||
* @version V1.30
|
||||
* @date 30. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
__ASM uint32_t __get_PSP(void)
|
||||
{
|
||||
mrs r0, psp
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
__ASM void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
msr psp, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
__ASM uint32_t __get_MSP(void)
|
||||
{
|
||||
mrs r0, msp
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
__ASM void __set_MSP(uint32_t mainStackPointer)
|
||||
{
|
||||
msr msp, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
__ASM uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in signed short value with sign extension to integer
|
||||
*/
|
||||
__ASM int32_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
|
||||
/**
|
||||
* @brief Remove the exclusive lock created by ldrex
|
||||
*
|
||||
* Removes the exclusive lock which is created by ldrex.
|
||||
*/
|
||||
__ASM void __CLREX(void)
|
||||
{
|
||||
clrex
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value
|
||||
*
|
||||
* @return BasePriority
|
||||
*
|
||||
* Return the content of the base priority register
|
||||
*/
|
||||
__ASM uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
mrs r0, basepri
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value
|
||||
*
|
||||
* @param basePri BasePriority
|
||||
*
|
||||
* Set the base priority register
|
||||
*/
|
||||
__ASM void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
msr basepri, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value
|
||||
*
|
||||
* @return PriMask
|
||||
*
|
||||
* Return state of the priority mask bit from the priority mask register
|
||||
*/
|
||||
__ASM uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
mrs r0, primask
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value
|
||||
*
|
||||
* @param priMask PriMask
|
||||
*
|
||||
* Set the priority mask bit in the priority mask register
|
||||
*/
|
||||
__ASM void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
msr primask, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value
|
||||
*
|
||||
* @return FaultMask
|
||||
*
|
||||
* Return the content of the fault mask register
|
||||
*/
|
||||
__ASM uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
mrs r0, faultmask
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value
|
||||
*
|
||||
* @param faultMask faultMask value
|
||||
*
|
||||
* Set the fault mask register
|
||||
*/
|
||||
__ASM void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
msr faultmask, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Control Register value
|
||||
*
|
||||
* @return Control value
|
||||
*
|
||||
* Return the content of the control register
|
||||
*/
|
||||
__ASM uint32_t __get_CONTROL(void)
|
||||
{
|
||||
mrs r0, control
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Control Register value
|
||||
*
|
||||
* @param control Control value
|
||||
*
|
||||
* Set the control register
|
||||
*/
|
||||
__ASM void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
msr control, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
uint32_t __get_PSP(void)
|
||||
{
|
||||
__ASM("mrs r0, psp");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM("msr psp, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
uint32_t __get_MSP(void)
|
||||
{
|
||||
__ASM("mrs r0, msp");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM("msr msp, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
__ASM("rev16 r0, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse bit order of value
|
||||
*/
|
||||
uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
__ASM("rbit r0, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 8 bit values)
|
||||
*/
|
||||
uint8_t __LDREXB(uint8_t *addr)
|
||||
{
|
||||
__ASM("ldrexb r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 16 bit values
|
||||
*/
|
||||
uint16_t __LDREXH(uint16_t *addr)
|
||||
{
|
||||
__ASM("ldrexh r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 32 bit values
|
||||
*/
|
||||
uint32_t __LDREXW(uint32_t *addr)
|
||||
{
|
||||
__ASM("ldrex r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 8 bit values
|
||||
*/
|
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||
{
|
||||
__ASM("strexb r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 16 bit values
|
||||
*/
|
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||
{
|
||||
__ASM("strexh r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 32 bit values
|
||||
*/
|
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||
{
|
||||
__ASM("strex r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
uint32_t __get_PSP(void) __attribute__( ( naked ) );
|
||||
uint32_t __get_PSP(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n\t"
|
||||
"MOV r0, %0 \n\t"
|
||||
"BX lr \n\t" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
|
||||
void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n\t"
|
||||
"BX lr \n\t" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
uint32_t __get_MSP(void) __attribute__( ( naked ) );
|
||||
uint32_t __get_MSP(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n\t"
|
||||
"MOV r0, %0 \n\t"
|
||||
"BX lr \n\t" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
|
||||
void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n\t"
|
||||
"BX lr \n\t" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value
|
||||
*
|
||||
* @return BasePriority
|
||||
*
|
||||
* Return the content of the base priority register
|
||||
*/
|
||||
uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value
|
||||
*
|
||||
* @param basePri BasePriority
|
||||
*
|
||||
* Set the base priority register
|
||||
*/
|
||||
void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value
|
||||
*
|
||||
* @return PriMask
|
||||
*
|
||||
* Return state of the priority mask bit from the priority mask register
|
||||
*/
|
||||
uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value
|
||||
*
|
||||
* @param priMask PriMask
|
||||
*
|
||||
* Set the priority mask bit in the priority mask register
|
||||
*/
|
||||
void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value
|
||||
*
|
||||
* @return FaultMask
|
||||
*
|
||||
* Return the content of the fault mask register
|
||||
*/
|
||||
uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value
|
||||
*
|
||||
* @param faultMask faultMask value
|
||||
*
|
||||
* Set the fault mask register
|
||||
*/
|
||||
void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Control Register value
|
||||
*
|
||||
* @return Control value
|
||||
*
|
||||
* Return the content of the control register
|
||||
*/
|
||||
uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Control Register value
|
||||
*
|
||||
* @param control Control value
|
||||
*
|
||||
* Set the control register
|
||||
*/
|
||||
void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in integer value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in integer value
|
||||
*/
|
||||
uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in signed short value with sign extension to integer
|
||||
*/
|
||||
int32_t __REVSH(int16_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse bit order of value
|
||||
*/
|
||||
uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 8 bit value
|
||||
*/
|
||||
uint8_t __LDREXB(uint8_t *addr)
|
||||
{
|
||||
uint8_t result=0;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 16 bit values
|
||||
*/
|
||||
uint16_t __LDREXH(uint16_t *addr)
|
||||
{
|
||||
uint16_t result=0;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 32 bit values
|
||||
*/
|
||||
uint32_t __LDREXW(uint32_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 8 bit values
|
||||
*/
|
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 16 bit values
|
||||
*/
|
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 32 bit values
|
||||
*/
|
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,284 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F10x CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
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||||
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|
||||
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|
||||
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|
||||
{mso-style-next:Normal;
|
||||
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||||
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|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
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|
||||
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|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
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|
||||
text-decoration:underline;
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||||
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|
||||
p
|
||||
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|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--></head>
|
||||
<body lang="EN-US" link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../../Release_Notes.html">Back to Release page</a></span></td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
|
||||
<ol style="margin-top: 0cm;" start="1" type="1">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS
|
||||
update History</a><o:p></o:p></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
|
||||
</ol>
|
||||
<span style="font-family: "Times New Roman";"></span>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS
|
||||
update History</span></h2><br>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h
|
||||
</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt
|
||||
definition for STM32F10x High-density Value line devices.<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file provided within the CMSIS folder. <br>
|
||||
</span></li>
|
||||
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
|
||||
- 10/15/2010</span></h3>
|
||||
|
||||
<ol>
|
||||
<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>
|
||||
</ol>
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
|
||||
for <b>STM32F10x High-density Value line devices</b>.</span></li>
|
||||
</ul>
|
||||
<ol start="2">
|
||||
<li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>
|
||||
</ol>
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
|
||||
</li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="">
|
||||
|
||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif";">All
|
||||
STM32 devices definitions are commented by default. User has to select the
|
||||
appropriate device before starting else an error will be signaled on compile
|
||||
time.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
|
||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
|
||||
</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
|
||||
to select if the user want to place the Vector Table in internal SRAM.
|
||||
An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
|
||||
</span></li>
|
||||
|
||||
</ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
|
||||
startup files for STM32 High-density Value line devices:
|
||||
<span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>
|
||||
</ul>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
|
||||
- 04/16/2010</span></h3>
|
||||
|
||||
<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
|
||||
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
|
||||
for <b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
|
||||
</li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for </span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. </span><span style="font-size: 10pt; font-family: Verdana;"><br>
|
||||
</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
|
||||
startup files for STM32 XL-density devices:
|
||||
<span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ Handler (was missing in previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
|
||||
- 03/01/2010</span></h3>
|
||||
<ol style="margin-top: 0in;" start="1" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
|
||||
</ol>
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
|
||||
for <b>STM32 Low-density Value line (STM32F100x4/6) and
|
||||
Medium-density Value line (STM32F100x8/B) devices</b>. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
|
||||
|
||||
</ul>
|
||||
<ol style="margin-top: 0in;" start="2" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
|
||||
<ul>
|
||||
<li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
|
||||
</ul>
|
||||
<ol style="margin-top: 0in; list-style-type: decimal;" start="3">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
|
||||
|
||||
</ol>
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
|
||||
</li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
|
||||
the stm32f10x.h file to support new Value line devices features: CEC
|
||||
peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
|
||||
HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
|
||||
HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
|
||||
purposes.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
|
||||
</span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
|
||||
startup files for STM32 Low-density Value line devices:
|
||||
<span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
|
||||
files for STM32 Medium-density Value line devices:
|
||||
<span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
|
||||
To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
|
||||
</ul>
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
</ul>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
|
||||
enclosed firmware and all the related documentation are not covered by
|
||||
a License Agreement, if you need such License you can contact your
|
||||
local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
|
||||
PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
|
||||
SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
|
||||
ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
|
||||
CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
|
||||
CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
|
||||
THEIR PRODUCTS. <o:p></o:p></span></b></p>
|
||||
<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
</body></html>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,98 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f10x.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f10x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F10X_H
|
||||
#define __SYSTEM_STM32F10X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F10x_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F10X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
<html>
|
||||
|
||||
<head>
|
||||
<title>CMSIS Debug Support</title>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
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<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
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|
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|
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</style>
|
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</head>
|
||||
|
||||
<body>
|
||||
|
||||
<h1>CMSIS Debug Support</h1>
|
||||
|
||||
<hr>
|
||||
|
||||
<h2>Cortex-M3 ITM Debug Access</h2>
|
||||
<p>
|
||||
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
|
||||
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
|
||||
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
|
||||
communication channels are used by CMSIS to output the following information:
|
||||
</p>
|
||||
<ul>
|
||||
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
|
||||
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
|
||||
</ul>
|
||||
|
||||
<h2>Debug IN / OUT functions</h2>
|
||||
<p>CMSIS provides following debug functions:</p>
|
||||
<ul>
|
||||
<li>ITM_SendChar (uses ITM channel 0)</li>
|
||||
<li>ITM_ReceiveChar (uses global variable)</li>
|
||||
<li>ITM_CheckChar (uses global variable)</li>
|
||||
</ul>
|
||||
|
||||
<h3>ITM_SendChar</h3>
|
||||
<p>
|
||||
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
|
||||
the microcontroller system to the debug system. <br>
|
||||
Only a 8 bit value is transmitted.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
{
|
||||
/* check if debugger connected and ITM channel enabled for tracing */
|
||||
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
|
||||
(ITM->TCR & ITM_TCR_ITMENA) &&
|
||||
(ITM->TER & (1UL << 0)) )
|
||||
{
|
||||
while (ITM->PORT[0].u32 == 0);
|
||||
ITM->PORT[0].u8 = (uint8_t)ch;
|
||||
}
|
||||
return (ch);
|
||||
}</pre>
|
||||
|
||||
<h3>ITM_ReceiveChar</h3>
|
||||
<p>
|
||||
ITM communication channel is only capable for OUT direction. For IN direction
|
||||
a globel variable is used. A simple mechansim detects if a character is received.
|
||||
The project to test need to be build with debug information.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
|
||||
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
|
||||
</p>
|
||||
<pre>
|
||||
extern volatile int ITM_RxBuffer; /* variable to receive characters */
|
||||
</pre>
|
||||
<p>
|
||||
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
|
||||
or contains a valid value.
|
||||
</p>
|
||||
<pre>
|
||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
|
||||
</pre>
|
||||
<p>
|
||||
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
|
||||
It returns the received character or '-1' if no character was available.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE int ITM_ReceiveChar (void) {
|
||||
int ch = -1; /* no character available */
|
||||
|
||||
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
||||
ch = ITM_RxBuffer;
|
||||
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
||||
}
|
||||
|
||||
return (ch);
|
||||
}
|
||||
</pre>
|
||||
|
||||
<h3>ITM_CheckChar</h3>
|
||||
<p>
|
||||
<strong>ITM_CheckChar</strong> is used to check if a character is received.
|
||||
</p>
|
||||
<pre>
|
||||
static __INLINE int ITM_CheckChar (void) {
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
||||
return (0); /* no character available */
|
||||
} else {
|
||||
return (1); /* character available */
|
||||
}
|
||||
}</pre>
|
||||
|
||||
|
||||
<h2>ITM Debug Support in uVision</h2>
|
||||
<p>
|
||||
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
|
||||
display the debug data.
|
||||
</p>
|
||||
<p>Direction microcontroller system -> uVision:</p>
|
||||
<ul>
|
||||
<li>
|
||||
Characters received via ITM communication channel 0 are written in a printf style
|
||||
to <strong>Debug (printf) Viewer</strong> window.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p>Direction uVision -> microcontroller system:</p>
|
||||
<ul>
|
||||
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
|
||||
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
|
||||
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
|
||||
</ul>
|
||||
|
||||
<p class="Note">Note</p>
|
||||
<ul>
|
||||
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<h2>RTX Kernel awareness in uVision</h2>
|
||||
<p>
|
||||
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
|
||||
No format overhead is necessary.<br>
|
||||
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
|
||||
to ITM communication channel 31.
|
||||
</p>
|
||||
|
||||
<p>Following RTX events are traced:</p>
|
||||
<ul>
|
||||
<li>Task Create / Delete event
|
||||
<ol>
|
||||
<li>32 bit access. Task start address is transmitted</li>
|
||||
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
|
||||
High byte holds Create/Delete flag, Low byte holds TASK ID.
|
||||
</li>
|
||||
</ol>
|
||||
</li>
|
||||
<li>Task switch event
|
||||
<ol>
|
||||
<li>8 bit access. Task ID of current task is transmitted</li>
|
||||
</ol>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p class="Note">Note</p>
|
||||
<ul>
|
||||
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<p class="MsoNormal"><span lang="EN-GB"> </span></p>
|
||||
|
||||
<hr>
|
||||
|
||||
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
|
||||
All rights reserved.<br>
|
||||
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
|
||||
</p>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
<html>
|
||||
|
||||
<head>
|
||||
<title>CMSIS Changes</title>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
|
||||
<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
|
||||
<meta name="ProgId" content="FrontPage.Editor.Document">
|
||||
<style>
|
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|
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|
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Keil Software CHM Style Sheet
|
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-----------------------------------------------------------*/
|
||||
body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family:
|
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Verdana, Arial, 'Sans Serif' }
|
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a:link { color: #0000FF; text-decoration: underline }
|
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a:visited { color: #0000FF; text-decoration: underline }
|
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|
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a:hover { color: #FF0000; text-decoration: underline }
|
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h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
|
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text-align: Center; margin-right: 3 }
|
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|
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background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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line-height: 120%; font-style: normal }
|
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|
||||
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|
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|
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p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
|
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|
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|
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|
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|
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|
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|
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td.whDesc { padding-bottom: 6pt }
|
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|
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|
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padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
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padding-bottom: 2pt }
|
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/*-----------------------------------------------------------
|
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|
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|
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|
||||
</style>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
|
||||
<h1>Changes to CMSIS version V1.20</h1>
|
||||
|
||||
<hr>
|
||||
|
||||
<h2>1. Removed CMSIS Middelware packages</h2>
|
||||
<p>
|
||||
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
|
||||
</p>
|
||||
|
||||
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
|
||||
<p>
|
||||
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
|
||||
because the variable holds the clock value at which the core is running.
|
||||
</p>
|
||||
|
||||
<h2>3. Changed startup concept</h2>
|
||||
<p>
|
||||
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
|
||||
from main) has the weakness that it does not work for controllers which need a already
|
||||
configuerd clock system to configure the external memory controller.
|
||||
</p>
|
||||
|
||||
<h3>Changed startup concept</h3>
|
||||
<ul>
|
||||
<li>
|
||||
SystemInit() is called from startup file before <strong>premain</strong>.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemInit()</strong> configures the clock system and also configures
|
||||
an existing external memory controller.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemInit()</strong> must not use global variables.
|
||||
</li>
|
||||
<li>
|
||||
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
|
||||
</li>
|
||||
<li>
|
||||
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
|
||||
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
|
||||
and must be called whenever the core clock is changed.<br>
|
||||
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
|
||||
the current core clock.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h2>4. Advanced Debug Functions</h2>
|
||||
<p>
|
||||
ITM communication channel is only capable for OUT direction. To allow also communication for
|
||||
IN direction a simple concept is provided.
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
|
||||
</li>
|
||||
<li>
|
||||
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
|
||||
</li>
|
||||
<li>
|
||||
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
|
||||
</p>
|
||||
|
||||
|
||||
<h2>5. Core Register Bit Definitions</h2>
|
||||
<p>
|
||||
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
|
||||
defines correspond with the Cortex-M Technical Reference Manual.
|
||||
</p>
|
||||
<p>
|
||||
e.g. SysTick structure with bit definitions
|
||||
</p>
|
||||
<pre>
|
||||
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
|
||||
memory mapped structure for SysTick
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
|
||||
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
|
||||
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
|
||||
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
|
||||
|
||||
<h2>7. DoxyGen Tags</h2>
|
||||
<p>
|
||||
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
|
||||
using DoxyGen.
|
||||
</p>
|
||||
|
||||
<h2>8. Folder Structure</h2>
|
||||
<p>
|
||||
The folder structure is changed to differentiate the single support packages.
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li>CM0</li>
|
||||
<li>CM3
|
||||
<ul>
|
||||
<li>CoreSupport</li>
|
||||
<li>DeviceSupport</li>
|
||||
<ul>
|
||||
<li>Vendor
|
||||
<ul>
|
||||
<li>Device
|
||||
<ul>
|
||||
<li>Startup
|
||||
<ul>
|
||||
<li>Toolchain</li>
|
||||
<li>Toolchain</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Device</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Vendor</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Example
|
||||
<ul>
|
||||
<li>Toolchain
|
||||
<ul>
|
||||
<li>Device</li>
|
||||
<li>Device</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Toolchain</li>
|
||||
<li>...</li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</li>
|
||||
|
||||
<li>Documentation</li>
|
||||
</ul>
|
||||
|
||||
<h2>9. Open Points</h2>
|
||||
<p>
|
||||
Following points need to be clarified and solved:
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
<p>
|
||||
Equivalent C and Assembler startup files.
|
||||
</p>
|
||||
<p>
|
||||
Is there a need for having C startup files although assembler startup files are
|
||||
very efficient and do not need to be changed?
|
||||
<p/>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Placing of HEAP in external RAM.
|
||||
</p>
|
||||
<p>
|
||||
It must be possible to place HEAP in external RAM if the device supports an
|
||||
external memory controller.
|
||||
</p>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Placing of STACK /HEAP.
|
||||
</p>
|
||||
<p>
|
||||
STACK should always be placed at the end of internal RAM.
|
||||
</p>
|
||||
<p>
|
||||
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
|
||||
</p>
|
||||
</li>
|
||||
<li>
|
||||
<p>
|
||||
Removing core_cm3.c and core_cm0.c.
|
||||
</p>
|
||||
<p>
|
||||
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
|
||||
appropriate compiler intrinsics.
|
||||
</p>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h2>10. Limitations</h2>
|
||||
<p>
|
||||
The following limitations are not covered with the current CMSIS version:
|
||||
</p>
|
||||
<ul>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for ARM toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for GNU toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>C startup files</strong> for IAR toolchain are provided.
|
||||
</li>
|
||||
<li>
|
||||
No <strong>Tasking</strong> projects are provided yet.
|
||||
</li>
|
||||
</ul>
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -0,0 +1,342 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F10x Standard Peripherals Library Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
<style>
|
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|
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/* Style Definitions */
|
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p.MsoNormal, li.MsoNormal, div.MsoNormal
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{mso-style-parent:"";
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||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
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font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
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|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
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{color:blue;
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|
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a:visited, span.MsoHyperlinkFollowed
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p
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mso-margin-bottom-alt:auto;
|
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margin-left:0in;
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||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--></head>
|
||||
<body lang="EN-US" link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for STM32F10x Standard Peripherals Library Drivers
|
||||
(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
|
||||
<ol style="margin-top: 0cm;" start="1" type="1">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
|
||||
Drivers update History</a><o:p></o:p></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
|
||||
</ol>
|
||||
<span style="font-family: "Times New Roman";">
|
||||
</span>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
|
||||
Peripherals Library Drivers update History</span></h2><br>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c files:</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 5 new functions</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">3
|
||||
new functions controlling the counter errors: CAN_GetLastErrorCode(),
|
||||
CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().</span></li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to select the CAN operating mode: CAN_OperatingModeRequest().</span></li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to support CAN TT mode: CAN_TTComModeCmd().</span><span style="font-size: 10pt; font-family: Verdana;"><br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN_TransmitStatus() function updated to support all CAN transmit intermediate states<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c files:</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 1 new function:</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_NACKPositionConfig():
|
||||
This function configures the same bit (POS) as I2C_PECPositionConfig()
|
||||
but is intended to be used in I2C mode while I2C_PECPositionConfig() is
|
||||
intended to used in SMBUS mode.</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c files:</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the <span style="font-style: italic;">TIM_DMABurstLength_xBytes</span> definitions to <span style="font-style: italic;">TIM_DMABurstLength_xTansfers</span><br>
|
||||
</span></li>
|
||||
</ul>
|
||||
|
||||
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
|
||||
- 10/15/2010</span></h3>
|
||||
|
||||
<ol style="margin-top: 0in;" start="1" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
|
||||
</ol>
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>
|
||||
</ul>
|
||||
|
||||
<ol style="margin-top: 0in;" start="2" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
|
||||
</ol>
|
||||
|
||||
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>
|
||||
</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>
|
||||
</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions: updated to support new flags (were not
|
||||
supported in previous version). These flags are: CAN_FLAG_RQCP0,
|
||||
CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,
|
||||
CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0, CAN_FLAG_FOV0,
|
||||
CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>
|
||||
</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()
|
||||
function: add a check of the interrupt enable bit before getting the
|
||||
status of corresponding interrupt pending bit. <br>
|
||||
</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>
|
||||
</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>
|
||||
</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>
|
||||
<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>
|
||||
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
|
||||
- 04/16/2010</span></h3>
|
||||
|
||||
<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
|
||||
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>
|
||||
<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
|
||||
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:
|
||||
updated to support Bank2 of XL-density devices (up to 1MByte of Flash
|
||||
memory). For more details, refer to the description provided within
|
||||
stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>
|
||||
function: updated to check whether the last event contains the
|
||||
I2C_EVENT (instead of check whether the last event is equal to
|
||||
I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add
|
||||
detailed description of I2C events and how to manage them using the
|
||||
functions provided by this driver. For more information, refer to
|
||||
stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h: </span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br>
|
||||
#define
|
||||
SDIO_ReadWaitMode_CLK
|
||||
((uint32_t)0x00000000)<br> #define
|
||||
SDIO_ReadWaitMode_DATA2
|
||||
((uint32_t)0x00000001)<br>by<br> #define
|
||||
SDIO_ReadWaitMode_CLK
|
||||
((uint32_t)0x00000001)<br> #define
|
||||
SDIO_ReadWaitMode_DATA2
|
||||
((uint32_t)0x00000000)</span></li></ul></ul>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
|
||||
- 03/01/2010</span></h3>
|
||||
<ol style="margin-top: 0in;" start="1" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
|
||||
</ol>
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
|
||||
for <b>STM32 Low-density Value line (STM32F100x4/6) and
|
||||
Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost
|
||||
peripherals drivers were updated to support Value
|
||||
line devices features</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
|
||||
|
||||
</ul>
|
||||
<ol style="margin-top: 0in;" start="2" type="1">
|
||||
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
|
||||
</ol>
|
||||
<ul style="margin-top: 0in;" type="disc">
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
|
||||
firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART
|
||||
driver: add support for Oversampling by 8 mode and onebit method. 2
|
||||
functions has been added: USART_OverSampling8Cmd() and
|
||||
USART_OneBitMethodCmd().<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC
|
||||
driver: add new functions handling the DAC under run feature:
|
||||
DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()
|
||||
and DAC_ClearITPendingBit().</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH
|
||||
driver: the FLASH_EraseOptionBytes() function updated. This is now just
|
||||
erasing the option bytes without modifying the RDP status either
|
||||
enabled or disabled.</span></li>
|
||||
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR
|
||||
driver: the PWR_EnterSTOPMode() function updated. When woken up from
|
||||
STOP mode, this function resets again the SLEEPDEEP bit in the
|
||||
Cortex-M3 System Control register to allow Sleep mode entering.</span></li>
|
||||
|
||||
|
||||
</ul>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
|
||||
enclosed firmware and all the related documentation are not covered by
|
||||
a License Agreement, if you need such License you can contact your
|
||||
local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
|
||||
PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
|
||||
SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
|
||||
ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
|
||||
CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
|
||||
CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
|
||||
THEIR PRODUCTS. <o:p></o:p></span></b></p>
|
||||
<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
</body></html>
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32f10x.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NVIC_Priority_Table
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@code
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endcode
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_ADC_H
|
||||
#define __STM32F10x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_RegInjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult) || \
|
||||
((MODE) == ADC_Mode_FastInterl) || \
|
||||
((MODE) == ADC_Mode_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_AlterTrig))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_13Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_41Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_55Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_71Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_239Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_JEOC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(void);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the BKP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_BKP_H
|
||||
#define __STM32F10x_BKP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Tamper_Pin_active_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
|
||||
((LEVEL) == BKP_TamperPinLevel_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Second))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Data_Backup_Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_DR1 ((uint16_t)0x0004)
|
||||
#define BKP_DR2 ((uint16_t)0x0008)
|
||||
#define BKP_DR3 ((uint16_t)0x000C)
|
||||
#define BKP_DR4 ((uint16_t)0x0010)
|
||||
#define BKP_DR5 ((uint16_t)0x0014)
|
||||
#define BKP_DR6 ((uint16_t)0x0018)
|
||||
#define BKP_DR7 ((uint16_t)0x001C)
|
||||
#define BKP_DR8 ((uint16_t)0x0020)
|
||||
#define BKP_DR9 ((uint16_t)0x0024)
|
||||
#define BKP_DR10 ((uint16_t)0x0028)
|
||||
#define BKP_DR11 ((uint16_t)0x0040)
|
||||
#define BKP_DR12 ((uint16_t)0x0044)
|
||||
#define BKP_DR13 ((uint16_t)0x0048)
|
||||
#define BKP_DR14 ((uint16_t)0x004C)
|
||||
#define BKP_DR15 ((uint16_t)0x0050)
|
||||
#define BKP_DR16 ((uint16_t)0x0054)
|
||||
#define BKP_DR17 ((uint16_t)0x0058)
|
||||
#define BKP_DR18 ((uint16_t)0x005C)
|
||||
#define BKP_DR19 ((uint16_t)0x0060)
|
||||
#define BKP_DR20 ((uint16_t)0x0064)
|
||||
#define BKP_DR21 ((uint16_t)0x0068)
|
||||
#define BKP_DR22 ((uint16_t)0x006C)
|
||||
#define BKP_DR23 ((uint16_t)0x0070)
|
||||
#define BKP_DR24 ((uint16_t)0x0074)
|
||||
#define BKP_DR25 ((uint16_t)0x0078)
|
||||
#define BKP_DR26 ((uint16_t)0x007C)
|
||||
#define BKP_DR27 ((uint16_t)0x0080)
|
||||
#define BKP_DR28 ((uint16_t)0x0084)
|
||||
#define BKP_DR29 ((uint16_t)0x0088)
|
||||
#define BKP_DR30 ((uint16_t)0x008C)
|
||||
#define BKP_DR31 ((uint16_t)0x0090)
|
||||
#define BKP_DR32 ((uint16_t)0x0094)
|
||||
#define BKP_DR33 ((uint16_t)0x0098)
|
||||
#define BKP_DR34 ((uint16_t)0x009C)
|
||||
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||
|
||||
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
|
||||
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
|
||||
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
|
||||
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
|
||||
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
|
||||
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
|
||||
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
|
||||
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
|
||||
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
|
||||
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
|
||||
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
|
||||
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
|
||||
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
|
||||
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
|
||||
|
||||
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||
void BKP_ITConfig(FunctionalState NewState);
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||
FlagStatus BKP_GetFlagStatus(void);
|
||||
void BKP_ClearFlag(void);
|
||||
ITStatus BKP_GetITStatus(void);
|
||||
void BKP_ClearITPendingBit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_BKP_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,697 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CAN_H
|
||||
#define __STM32F10x_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
|
||||
((PERIPH) == CAN2))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of
|
||||
@ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of
|
||||
@ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 2.
|
||||
This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
|
||||
communication mode. This parameter can be set
|
||||
either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
|
||||
management. This parameter can be set either
|
||||
to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or
|
||||
DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
|
||||
retransmission mode. This parameter can be
|
||||
set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Operating_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Mode_Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
|
||||
#else
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
#define CANTXFAILE CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* Transmit functions *********************************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* Receive functions **********************************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* Error management functions *************************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CAN_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CEC_H
|
||||
#define __STM32F10x_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitTiming_Mode */
|
||||
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitPeriod_Mode */
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitTiming_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
|
||||
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||
|
||||
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
|
||||
((MODE) == CEC_BitTimingErrFreeMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitPeriod_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
|
||||
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||
|
||||
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
|
||||
((MODE) == CEC_BitPeriodFlexibleMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TERR CEC_CSR_TERR
|
||||
#define CEC_IT_TBTRF CEC_CSR_TBTRF
|
||||
#define CEC_IT_RERR CEC_CSR_RERR
|
||||
#define CEC_IT_RBTF CEC_CSR_RBTF
|
||||
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
|
||||
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Own_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ESR register flags
|
||||
*/
|
||||
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
|
||||
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
|
||||
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
|
||||
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
|
||||
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
|
||||
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
|
||||
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
|
||||
|
||||
/**
|
||||
* @brief CSR register flags
|
||||
*/
|
||||
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
|
||||
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
|
||||
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
|
||||
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
|
||||
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
|
||||
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
|
||||
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
|
||||
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
|
||||
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
|
||||
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
|
||||
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
|
||||
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
|
||||
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void CEC_DeInit(void);
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
|
||||
void CEC_Cmd(FunctionalState NewState);
|
||||
void CEC_ITConfig(FunctionalState NewState);
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
|
||||
void CEC_SendDataByte(uint8_t Data);
|
||||
uint8_t CEC_ReceiveDataByte(void);
|
||||
void CEC_StartOfMessage(void);
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState);
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG);
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CEC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CRC_H
|
||||
#define __STM32F10x_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CRC_ResetDR(void);
|
||||
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
void CRC_SetIDRegister(uint8_t IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CRC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DAC_H
|
||||
#define __STM32F10x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in High-density devices*/
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Connectivity line, Medium-density and Low-density Value Line devices */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Medium-density and Low-density Value Line devices*/
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
#endif
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DAC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DBGMCU_H
|
||||
#define __STM32F10x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
|
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
|
||||
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
|
||||
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
|
||||
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
|
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
|
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
|
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_DBGMCU_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,439 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DMA_H
|
||||
#define __STM32F10x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
||||
((DIR) == DMA_DIR_PeripheralSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DMA_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_EXTI_H
|
||||
#define __STM32F10x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FLASH_H
|
||||
#define __STM32F10x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Half_Cycle_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
|
||||
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
|
||||
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
|
||||
((STATE) == FLASH_HalfCycleAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Prefetch_Buffer_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
|
||||
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
|
||||
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
|
||||
((STATE) == FLASH_PrefetchBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Values to be used with STM32 Low and Medium density devices */
|
||||
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
|
||||
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
|
||||
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
|
||||
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
|
||||
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
|
||||
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
|
||||
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
|
||||
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
|
||||
|
||||
/* Values to be used with STM32 Medium-density devices */
|
||||
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
|
||||
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
|
||||
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
|
||||
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
|
||||
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
|
||||
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
|
||||
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
|
||||
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
|
||||
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
|
||||
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
|
||||
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
|
||||
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
|
||||
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
|
||||
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
|
||||
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
|
||||
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
|
||||
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
|
||||
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
|
||||
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
|
||||
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
|
||||
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
|
||||
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
|
||||
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
|
||||
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
|
||||
|
||||
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
|
||||
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 0 to 1 */
|
||||
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 2 to 3 */
|
||||
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 4 to 5 */
|
||||
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 6 to 7 */
|
||||
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 8 to 9 */
|
||||
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 10 to 11 */
|
||||
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 12 to 13 */
|
||||
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 14 to 15 */
|
||||
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 16 to 17 */
|
||||
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 18 to 19 */
|
||||
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 20 to 21 */
|
||||
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 22 to 23 */
|
||||
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 24 to 25 */
|
||||
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 26 to 27 */
|
||||
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 28 to 29 */
|
||||
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 30 to 31 */
|
||||
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 32 to 33 */
|
||||
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 34 to 35 */
|
||||
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 36 to 37 */
|
||||
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 38 to 39 */
|
||||
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 40 to 41 */
|
||||
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 42 to 43 */
|
||||
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 44 to 45 */
|
||||
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 46 to 47 */
|
||||
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 48 to 49 */
|
||||
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 50 to 51 */
|
||||
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 52 to 53 */
|
||||
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 54 to 55 */
|
||||
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 56 to 57 */
|
||||
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 58 to 59 */
|
||||
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 60 to 61 */
|
||||
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
|
||||
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
|
||||
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
|
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
|
||||
|
||||
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Boot
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank1(Default) */
|
||||
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank 2 or Bank 1,
|
||||
depending on the activation of the bank */
|
||||
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
|
||||
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#else
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
|
||||
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
|
||||
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR)|| \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
|
||||
#else
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------ Functions used for all STM32F10x devices -----*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
|
||||
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||
uint32_t FLASH_GetUserOptionByte(void);
|
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/*------------ New function used for all STM32F10x devices -----*/
|
||||
void FLASH_UnlockBank1(void);
|
||||
void FLASH_LockBank1(void);
|
||||
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||
FLASH_Status FLASH_GetBank1Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/*---- New Functions used only with STM32F10x_XL density devices -----*/
|
||||
void FLASH_UnlockBank2(void);
|
||||
void FLASH_LockBank2(void);
|
||||
FLASH_Status FLASH_EraseAllBank2Pages(void);
|
||||
FLASH_Status FLASH_GetBank2Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
|
||||
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_FLASH_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,733 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FSMC_H
|
||||
#define __STM32F10x_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The value of this parameter depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FSMC NAND and PCCARD Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 0xFF.*/
|
||||
|
||||
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NAND Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
}FSMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||
}FSMC_PCCARDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||
|
||||
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND))
|
||||
|
||||
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
/** @defgroup NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FSMC_DataAddressMux_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||
((MODE) == FSMC_WrapMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||
((BURST) == FSMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FSMC_Waitfeature_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FSMC_ECC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||||
((STATE) == FSMC_ECC_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_8192Bytes))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FSMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||||
((IT) == FSMC_IT_Level) || \
|
||||
((IT) == FSMC_IT_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_Level) || \
|
||||
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_PCCARDDeInit(void);
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState);
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_FSMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,385 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_GPIO_H
|
||||
#define __STM32F10x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG))
|
||||
|
||||
/**
|
||||
* @brief Output Maximum frequency selection
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_10MHz = 1,
|
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_50MHz
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
|
||||
((SPEED) == GPIO_Speed_50MHz))
|
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
|
||||
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
|
||||
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
|
||||
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit_SET and Bit_RESET enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Remap_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
|
||||
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
|
||||
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
to TIM2 Internal Trigger 1 for calibration
|
||||
(only for Connectivity line devices) */
|
||||
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
|
||||
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
only for High density Value line devices) */
|
||||
|
||||
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
|
||||
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
|
||||
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
|
||||
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
|
||||
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
|
||||
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
|
||||
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
|
||||
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
|
||||
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
|
||||
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
|
||||
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
|
||||
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
|
||||
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
|
||||
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
|
||||
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
|
||||
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
|
||||
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE))
|
||||
|
||||
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Ethernet_Media_Interface
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||
|
||||
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
|
||||
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,684 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_I2C_H
|
||||
#define __STM32F10x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
|
||||
((CYCLE) == I2C_DutyCycle_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
|
||||
((STATE) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DR ((uint8_t)0x10)
|
||||
#define I2C_Register_SR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_SR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CCR ((uint8_t)0x1C)
|
||||
#define I2C_Register_TRISE ((uint8_t)0x20)
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_CCR) || \
|
||||
((REGISTER) == I2C_Register_TRISE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
|
||||
((ALERT) == I2C_SMBusAlert_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
|
||||
((POSITION) == I2C_PECPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NCAK_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
|
||||
((POSITION) == I2C_NACKPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SR2 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/**
|
||||
* @brief SR1 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||
* current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
/*=========================== End of Events Description ==========================================*/
|
||||
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_clock_speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
****************************************************************************************
|
||||
*
|
||||
* I2C State Monitoring Functions
|
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring
|
||||
* depending on the application requirements and constraints:
|
||||
*
|
||||
*
|
||||
* 1) Basic state monitoring:
|
||||
* Using I2C_CheckEvent() function:
|
||||
* It compares the status registers (SR1 and SR2) content to a given event
|
||||
* (can be the combination of one or more flags).
|
||||
* It returns SUCCESS if the current status includes the given flags
|
||||
* and returns ERROR if one or more flags are missing in the current status.
|
||||
* - When to use:
|
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (RM0008).
|
||||
* - It is also suitable for users who need to define their own events.
|
||||
* - Limitations:
|
||||
* - If an error occurs (ie. error flags are set besides to the monitored flags),
|
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
* hold or corrupted real state.
|
||||
* In this case, it is advised to use error interrupts to monitor the error
|
||||
* events and handle them in the interrupt IRQ handler.
|
||||
*
|
||||
* @note
|
||||
* For error management, it is advised to use the following functions:
|
||||
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
|
||||
* in order to determine which error occurred.
|
||||
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||
* and/or I2C_GenerateStop() in order to clear the error flag and source,
|
||||
* and return to correct communication status.
|
||||
*
|
||||
*
|
||||
* 2) Advanced state monitoring:
|
||||
* Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
* by 16 bits and concatenated to Status Register 1).
|
||||
* - When to use:
|
||||
* - This function is suitable for the same applications above but it allows to
|
||||
* overcome the limitations of I2C_GetFlagStatus() function (see below).
|
||||
* The returned value could be compared to events already defined in the
|
||||
* library (stm32f10x_i2c.h) or to custom values defined by user.
|
||||
* - This function is suitable when multiple flags are monitored at the same time.
|
||||
* - At the opposite of I2C_CheckEvent() function, this function allows user to
|
||||
* choose when an event is accepted (when all events flags are set and no
|
||||
* other flags are set or just when the needed flags are set like
|
||||
* I2C_CheckEvent() function).
|
||||
* - Limitations:
|
||||
* - User may need to define his own events.
|
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags).
|
||||
*
|
||||
*
|
||||
* 3) Flag-based state monitoring:
|
||||
* Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
* one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
* - When to use:
|
||||
* - This function could be used for specific applications or in debug phase.
|
||||
* - It is suitable when only one flag checking is needed (most I2C events
|
||||
* are monitored through multiple flags).
|
||||
* - Limitations:
|
||||
* - When calling this function, the Status register is accessed. Some flags are
|
||||
* cleared when the status register is accessed. So checking the status
|
||||
* of one Flag, may clear other ones.
|
||||
* - Function may need to be called twice or more in order to monitor one
|
||||
* single event.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* 1) Basic state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/**
|
||||
*
|
||||
* 2) Advanced state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/**
|
||||
*
|
||||
* 3) Flag-based state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
/**
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_I2C_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_IWDG_H
|
||||
#define __STM32F10x_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_IWDG_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_PWR_H
|
||||
#define __STM32F10x_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Regulator_state_is_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU ((uint32_t)0x00000001)
|
||||
#define PWR_FLAG_SB ((uint32_t)0x00000002)
|
||||
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void PWR_DeInit(void);
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_PWR_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,727 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_RCC_H
|
||||
#define __STM32F10x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
|
||||
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PLL_entry_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||
|
||||
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
|
||||
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE_Div2))
|
||||
#else
|
||||
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_PREDIV1))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PLL_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
#ifndef STM32F10X_CL
|
||||
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||
((MUL) == RCC_PLLMul_16))
|
||||
|
||||
#else
|
||||
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
|
||||
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_6_5))
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PREDIV1_division_factor
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
|
||||
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
|
||||
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
|
||||
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
|
||||
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
|
||||
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
|
||||
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
|
||||
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
|
||||
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
|
||||
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
|
||||
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
|
||||
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
|
||||
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
|
||||
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
|
||||
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
|
||||
|
||||
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PREDIV1_clock_source
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_CL
|
||||
/* PREDIV1 clock source (for STM32 connectivity line devices) */
|
||||
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
|
||||
|
||||
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
|
||||
((SOURCE) == RCC_PREDIV1_Source_PLL2))
|
||||
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/* PREDIV1 clock source (for STM32 Value line devices) */
|
||||
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
/** @defgroup PREDIV2_division_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
|
||||
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
|
||||
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
|
||||
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
|
||||
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
|
||||
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
|
||||
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
|
||||
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
|
||||
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
|
||||
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
|
||||
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
|
||||
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
|
||||
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
|
||||
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
|
||||
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
|
||||
|
||||
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PLL2_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
|
||||
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
|
||||
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
|
||||
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
|
||||
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
|
||||
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
|
||||
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
|
||||
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
|
||||
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
|
||||
|
||||
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
|
||||
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
|
||||
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
|
||||
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
|
||||
((MUL) == RCC_PLL2Mul_20))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PLL3_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
|
||||
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
|
||||
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
|
||||
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
|
||||
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
|
||||
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
|
||||
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
|
||||
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
|
||||
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
|
||||
|
||||
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
|
||||
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
|
||||
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
|
||||
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
|
||||
((MUL) == RCC_PLL3Mul_20))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/** @defgroup System_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AHB_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB1_APB2_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
|
||||
#else
|
||||
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
|
||||
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
/** @defgroup USB_Device_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||||
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#else
|
||||
/** @defgroup USB_OTG_FS_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
|
||||
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
|
||||
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
/** @defgroup I2S2_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S3_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/** @defgroup ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
|
||||
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AHB_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
|
||||
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
|
||||
#else
|
||||
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
|
||||
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
|
||||
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
|
||||
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB2_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
|
||||
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB1_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Clock_source_to_output_on_MCO_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||
((MCO) == RCC_MCO_PLLCLK_Div2))
|
||||
#else
|
||||
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
|
||||
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
|
||||
#define RCC_MCO_XT1 ((uint8_t)0x0A)
|
||||
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
|
||||
|
||||
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
|
||||
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
|
||||
((MCO) == RCC_MCO_PLL3CLK))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_LPWRRST))
|
||||
#else
|
||||
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_LPWRRST))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||||
#endif
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||||
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||||
void RCC_PLL2Cmd(FunctionalState NewState);
|
||||
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||||
void RCC_PLL3Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||
#else
|
||||
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
||||
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_RCC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_RTC_H
|
||||
#define __STM32F10x_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_interrupts_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
|
||||
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
|
||||
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
|
||||
#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
|
||||
((IT) == RTC_IT_SEC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_interrupts_flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
|
||||
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
|
||||
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
|
||||
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
|
||||
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
|
||||
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
|
||||
((FLAG) == RTC_FLAG_SEC))
|
||||
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
|
||||
void RTC_EnterConfigMode(void);
|
||||
void RTC_ExitConfigMode(void);
|
||||
uint32_t RTC_GetCounter(void);
|
||||
void RTC_SetCounter(uint32_t CounterValue);
|
||||
void RTC_SetPrescaler(uint32_t PrescalerValue);
|
||||
void RTC_SetAlarm(uint32_t AlarmValue);
|
||||
uint32_t RTC_GetDivider(void);
|
||||
void RTC_WaitForLastTask(void);
|
||||
void RTC_WaitForSynchro(void);
|
||||
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint16_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint16_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_RTC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,531 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_sdio.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_SDIO_H
|
||||
#define __STM32F10x_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||
|
||||
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||
enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||
|
||||
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||
disabled when the bus is idle.
|
||||
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||
|
||||
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
|
||||
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||
|
||||
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||
|
||||
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a value between 0x00 and 0xFF. */
|
||||
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
|
||||
to a card as part of a command message. If a command
|
||||
contains an argument, it must be loaded into this register
|
||||
before writing the command to the command register */
|
||||
|
||||
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||
|
||||
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref SDIO_Response_Type */
|
||||
|
||||
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||
|
||||
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||
} SDIO_CmdInitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||
|
||||
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
|
||||
|
||||
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
|
||||
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||
|
||||
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
|
||||
is a read or write.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||
|
||||
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||
|
||||
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Edge
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
|
||||
((EDGE) == SDIO_ClockEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Bypass
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
|
||||
((BYPASS) == SDIO_ClockBypass_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Power_Save
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
|
||||
((SAVE) == SDIO_ClockPowerSave_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Bus_Wide
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
|
||||
((WIDE) == SDIO_BusWide_8b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
|
||||
((CONTROL) == SDIO_HardwareFlowControl_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Power_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SDIO_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Command_Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
|
||||
((RESPONSE) == SDIO_Response_Short) || \
|
||||
((RESPONSE) == SDIO_Response_Long))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Wait_Interrupt_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
|
||||
((WAIT) == SDIO_Wait_Pend))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_CPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
|
||||
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Block_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_32b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_64b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_128b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_256b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_512b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_1024b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2048b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4096b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8192b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16384b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
|
||||
((DIR) == SDIO_TransferDir_ToSDIO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
|
||||
((MODE) == SDIO_TransferMode_Block))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_DPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
||||
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
||||
((FLAG) == SDIO_FLAG_CMDREND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
||||
((FLAG) == SDIO_FLAG_DATAEND) || \
|
||||
((FLAG) == SDIO_FLAG_STBITERR) || \
|
||||
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXACT) || \
|
||||
((FLAG) == SDIO_FLAG_RXACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
||||
((FLAG) == SDIO_FLAG_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||
|
||||
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
||||
((IT) == SDIO_IT_DCRCFAIL) || \
|
||||
((IT) == SDIO_IT_CTIMEOUT) || \
|
||||
((IT) == SDIO_IT_DTIMEOUT) || \
|
||||
((IT) == SDIO_IT_TXUNDERR) || \
|
||||
((IT) == SDIO_IT_RXOVERR) || \
|
||||
((IT) == SDIO_IT_CMDREND) || \
|
||||
((IT) == SDIO_IT_CMDSENT) || \
|
||||
((IT) == SDIO_IT_DATAEND) || \
|
||||
((IT) == SDIO_IT_STBITERR) || \
|
||||
((IT) == SDIO_IT_DBCKEND) || \
|
||||
((IT) == SDIO_IT_CMDACT) || \
|
||||
((IT) == SDIO_IT_TXACT) || \
|
||||
((IT) == SDIO_IT_RXACT) || \
|
||||
((IT) == SDIO_IT_TXFIFOHE) || \
|
||||
((IT) == SDIO_IT_RXFIFOHF) || \
|
||||
((IT) == SDIO_IT_TXFIFOF) || \
|
||||
((IT) == SDIO_IT_RXFIFOF) || \
|
||||
((IT) == SDIO_IT_TXFIFOE) || \
|
||||
((IT) == SDIO_IT_RXFIFOE) || \
|
||||
((IT) == SDIO_IT_TXDAVL) || \
|
||||
((IT) == SDIO_IT_RXDAVL) || \
|
||||
((IT) == SDIO_IT_SDIOIT) || \
|
||||
((IT) == SDIO_IT_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Read_Wait_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
||||
((MODE) == SDIO_ReadWaitMode_DATA2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SDIO_DeInit(void);
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockCmd(FunctionalState NewState);
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||
uint32_t SDIO_GetPowerState(void);
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||
void SDIO_DMACmd(FunctionalState NewState);
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||
uint8_t SDIO_GetCommandResponse(void);
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
uint32_t SDIO_GetDataCounter(void);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
void SDIO_WriteData(uint32_t Data);
|
||||
uint32_t SDIO_GetFIFOCount(void);
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_SDIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,487 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the SPI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_SPI_H
|
||||
#define __STM32F10x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
|
||||
((DATASIZE) == SPI_DataSize_8b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx) || \
|
||||
((MODE) == I2S_Mode_MasterRx) )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
|
||||
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_SPI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,412 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_USART_H
|
||||
#define __STM32F10x_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3))
|
||||
|
||||
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4))
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_0_5) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE ((uint16_t)0x0360)
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
|
||||
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|
||||
|| ((USART_FLAG) != USART_FLAG_CTS))
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_USART_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_WWDG_H
|
||||
#define __STM32F10x_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM
|
||||
* @arg NVIC_VectTab_FLASH
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple
|
||||
* of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND
|
||||
* @arg NVIC_LP_SLEEPDEEP
|
||||
* @arg NVIC_LP_SLEEPONEXIT
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,308 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the BKP firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP
|
||||
* @brief BKP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ BKP registers bit address in the alias region --------------- */
|
||||
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ----*/
|
||||
|
||||
/* Alias word address of TPAL bit */
|
||||
#define CR_OFFSET (BKP_OFFSET + 0x30)
|
||||
#define TPAL_BitNumber 0x01
|
||||
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TPE bit */
|
||||
#define TPE_BitNumber 0x00
|
||||
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TPIE bit */
|
||||
#define CSR_OFFSET (BKP_OFFSET + 0x34)
|
||||
#define TPIE_BitNumber 0x02
|
||||
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TIF bit */
|
||||
#define TIF_BitNumber 0x09
|
||||
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEF bit */
|
||||
#define TEF_BitNumber 0x08
|
||||
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
|
||||
|
||||
/* ---------------------- BKP registers bit mask ------------------------ */
|
||||
|
||||
/* RTCCR register bit mask */
|
||||
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
|
||||
#define RTCCR_MASK ((uint16_t)0xFC7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup BKP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_DeInit(void)
|
||||
{
|
||||
RCC_BackupResetCmd(ENABLE);
|
||||
RCC_BackupResetCmd(DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Tamper Pin active level.
|
||||
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
|
||||
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
|
||||
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin activation.
|
||||
* @param NewState: new state of the Tamper Pin activation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||
* @param NewState: new state of the Tamper Pin Interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the RTC output source to output on the Tamper pin.
|
||||
* @param BKP_RTCOutputSource: specifies the RTC output source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
|
||||
* divided by 64 on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
|
||||
* the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
|
||||
* the Tamper pin.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CCO, ASOE and ASOS bits */
|
||||
tmpreg &= RTCCR_MASK;
|
||||
|
||||
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
|
||||
tmpreg |= BKP_RTCOutputSource;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets RTC Clock Calibration value.
|
||||
* @param CalibrationValue: specifies the RTC Clock Calibration value.
|
||||
* This parameter must be a number between 0 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CAL[6:0] bits */
|
||||
tmpreg &= RTCCR_CAL_MASK;
|
||||
/* Set CAL[6:0] bits according to CalibrationValue value */
|
||||
tmpreg |= CalibrationValue;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes user data to the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @param Data: data to write
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads data from the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @retval The content of the specified Data Backup Register
|
||||
*/
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
return (*(__IO uint16_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus BKP_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Event pending flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearFlag(void)
|
||||
{
|
||||
/* Set CTE bit to clear Tamper Pin Event flag */
|
||||
BKP->CSR |= BKP_CSR_CTE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||
*/
|
||||
ITStatus BKP_GetITStatus(void)
|
||||
{
|
||||
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearITPendingBit(void)
|
||||
{
|
||||
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
|
||||
BKP->CSR |= BKP_CSR_CTI;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,433 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the CEC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC
|
||||
* @brief CEC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ CEC registers bit address in the alias region ----------- */
|
||||
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CFGR Register ---*/
|
||||
|
||||
/* Alias word address of PE bit */
|
||||
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
|
||||
#define PE_BitNumber 0x00
|
||||
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of IE bit */
|
||||
#define IE_BitNumber 0x01
|
||||
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TSOM bit */
|
||||
#define CSR_OFFSET (CEC_OFFSET + 0x10)
|
||||
#define TSOM_BitNumber 0x00
|
||||
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEOM bit */
|
||||
#define TEOM_BitNumber 0x01
|
||||
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
|
||||
|
||||
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
|
||||
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the CEC peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_DeInit(void)
|
||||
{
|
||||
/* Enable CEC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
|
||||
/* Release CEC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC peripheral according to the specified
|
||||
* parameters in the CEC_InitStruct.
|
||||
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* CEC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
|
||||
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
|
||||
|
||||
/*---------------------------- CEC CFGR Configuration -----------------*/
|
||||
/* Get the CEC CFGR value */
|
||||
tmpreg = CEC->CFGR;
|
||||
|
||||
/* Clear BTEM and BPEM bits */
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
|
||||
/* Configure CEC: Bit Timing Error and Bit Period Error */
|
||||
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
|
||||
|
||||
/* Write to CEC CFGR register*/
|
||||
CEC->CFGR = tmpreg;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified CEC peripheral.
|
||||
* @param NewState: new state of the CEC peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
|
||||
|
||||
if(NewState == DISABLE)
|
||||
{
|
||||
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
|
||||
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CEC interrupt.
|
||||
* @param NewState: new state of the CEC interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Defines the Own Address of the CEC device.
|
||||
* @param CEC_OwnAddress: The CEC own address
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
|
||||
|
||||
/* Set the CEC own address */
|
||||
CEC->OAR = CEC_OwnAddress;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the CEC prescaler value.
|
||||
* @param CEC_Prescaler: CEC prescaler new value
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
|
||||
|
||||
/* Set the Prescaler value*/
|
||||
CEC->PRES = CEC_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits single data through the CEC peripheral.
|
||||
* @param Data: the data to transmit.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SendDataByte(uint8_t Data)
|
||||
{
|
||||
/* Transmit Data */
|
||||
CEC->TXD = Data ;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the CEC peripheral.
|
||||
* @param None
|
||||
* @retval The received data.
|
||||
*/
|
||||
uint8_t CEC_ReceiveDataByte(void)
|
||||
{
|
||||
/* Receive Data */
|
||||
return (uint8_t)(CEC->RXD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a new message.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_StartOfMessage(void)
|
||||
{
|
||||
/* Starts of new message */
|
||||
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits message with or without an EOM bit.
|
||||
* @param NewState: new state of the CEC Tx End Of Message.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* The data byte will be transmitted with or without an EOM bit*/
|
||||
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the CEC flag status
|
||||
* @param CEC_FLAG: specifies the CEC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_BTE: Bit Timing Error
|
||||
* @arg CEC_FLAG_BPE: Bit Period Error
|
||||
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_SBE: Start Bit Error
|
||||
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
|
||||
* @arg CEC_FLAG_LINE: Line Error
|
||||
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_TEOM: Tx End Of Message
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval The new state of CEC_FLAG (SET or RESET)
|
||||
*/
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t cecreg = 0, cecbase = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
||||
|
||||
/* Get the CEC peripheral base address */
|
||||
cecbase = (uint32_t)(CEC_BASE);
|
||||
|
||||
/* Read flag register index */
|
||||
cecreg = CEC_FLAG >> 28;
|
||||
|
||||
/* Get bit[23:0] of the flag */
|
||||
CEC_FLAG &= FLAG_Mask;
|
||||
|
||||
if(cecreg != 0)
|
||||
{
|
||||
/* Flag in CEC ESR Register */
|
||||
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
|
||||
|
||||
/* Get the CEC ESR register address */
|
||||
cecbase += 0xC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the CEC CSR register address */
|
||||
cecbase += 0x10;
|
||||
}
|
||||
|
||||
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* CEC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the CEC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's pending flags.
|
||||
* @param CEC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC flags */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
||||
* @param CEC_IT: specifies the CEC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval The new state of CEC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
/* Get the CEC IT enable bit status */
|
||||
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
|
||||
|
||||
/* Check the status of the specified CEC interrupt */
|
||||
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* CEC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the CEC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's interrupt pending bits.
|
||||
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC interrupt pending bits */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the CRC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_crc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC Data register (DR).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||
{
|
||||
CRC->DR = Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t IDValue)
|
||||
{
|
||||
CRC->IDR = IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,571 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DAC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel
|
||||
* DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DBGMCU firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
|
||||
* @param NewState: new state of the specified peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DMA firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_Mask;
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAy_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR ;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAy_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAy_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA2->IFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA1->IFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMA */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMA_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA2->IFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA1->IFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the EXTI firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_exti.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt.
|
||||
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,866 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the FSMC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC
|
||||
* @brief FSMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- FSMC registers bit mask ---------------------------- */
|
||||
|
||||
/* FSMC BCRx Mask */
|
||||
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||
|
||||
/* FSMC PCRx Mask */
|
||||
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||
* reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
|
||||
/* FSMC_Bank1_NORSRAM1 */
|
||||
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||
}
|
||||
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
||||
else
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||
}
|
||||
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Set the FSMC_Bank2 registers to their reset values */
|
||||
FSMC_Bank2->PCR2 = 0x00000018;
|
||||
FSMC_Bank2->SR2 = 0x00000040;
|
||||
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||
}
|
||||
/* FSMC_Bank3_NAND */
|
||||
else
|
||||
{
|
||||
/* Set the FSMC_Bank3 registers to their reset values */
|
||||
FSMC_Bank3->PCR3 = 0x00000018;
|
||||
FSMC_Bank3->SR3 = 0x00000040;
|
||||
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
|
||||
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDDeInit(void)
|
||||
{
|
||||
/* Set the FSMC_Bank4 registers to their reset values */
|
||||
FSMC_Bank4->PCR4 = 0x00000018;
|
||||
FSMC_Bank4->SR4 = 0x00000000;
|
||||
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||
* parameters in the FSMC_NORSRAMInitStruct.
|
||||
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure that contains the configuration information for
|
||||
* the FSMC NOR/SRAM specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
||||
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
||||
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
||||
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
||||
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
||||
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
||||
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
||||
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
||||
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
||||
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
||||
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
||||
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||
}
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||
{
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||
* parameters in the FSMC_NANDInitStruct.
|
||||
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* NAND specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
|
||||
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
|
||||
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
|
||||
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
|
||||
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
|
||||
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||
PCR_MemoryType_NAND |
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NANDInitStruct->FSMC_ECC |
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
|
||||
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* FSMC_Bank2_NAND registers configuration */
|
||||
FSMC_Bank2->PCR2 = tmppcr;
|
||||
FSMC_Bank2->PMEM2 = tmppmem;
|
||||
FSMC_Bank2->PATT2 = tmppatt;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FSMC_Bank3_NAND registers configuration */
|
||||
FSMC_Bank3->PCR3 = tmppcr;
|
||||
FSMC_Bank3->PMEM3 = tmppmem;
|
||||
FSMC_Bank3->PATT3 = tmppatt;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC PCCARD Bank according to the specified
|
||||
* parameters in the FSMC_PCCARDInitStruct.
|
||||
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* PCCARD Bank.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
|
||||
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
||||
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
|
||||
FSMC_MemoryDataWidth_16b |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Reset NOR/SRAM Init structure parameters values */
|
||||
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
/* Reset NAND Init structure parameters values */
|
||||
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
||||
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Reset PCCARD Init structure parameters values */
|
||||
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NAND Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the PCCARD Memory Bank.
|
||||
* @param NewState: new state of the PCCARD Memory Bank.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC NAND ECC feature.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the error correction code register value.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval The Error Correction Code (ECC) value.
|
||||
*/
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||
{
|
||||
uint32_t eccval = 0x00000000;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Get the ECCR2 register value */
|
||||
eccval = FSMC_Bank2->ECCR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the ECCR3 register value */
|
||||
eccval = FSMC_Bank3->ECCR3;
|
||||
}
|
||||
/* Return the error correction code value */
|
||||
return(eccval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified FSMC interrupts.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @param NewState: new state of the specified FSMC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 |= FSMC_IT;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
|
||||
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC flag is set or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
||||
* @retval The new state of FSMC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
/* Get the flag status */
|
||||
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's pending flags.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC interrupt has occurred or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval The new state of FSMC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
itstatus = tmpsr & FSMC_IT;
|
||||
|
||||
itenable = tmpsr & (FSMC_IT >> 3);
|
||||
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's interrupt pending bits.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,650 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the GPIO firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ RCC registers bit address in the alias region ----------------*/
|
||||
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- EVENTCR Register -----*/
|
||||
|
||||
/* Alias word address of EVOE bit */
|
||||
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
|
||||
#define EVOE_BitNumber ((uint8_t)0x07)
|
||||
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
|
||||
|
||||
|
||||
/* --- MAPR Register ---*/
|
||||
/* Alias word address of MII_RMII_SEL bit */
|
||||
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
|
||||
#define MII_RMII_SEL_BitNumber ((u8)0x17)
|
||||
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||
|
||||
|
||||
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
|
||||
/*---------------------------- GPIO Mode Configuration -----------------------*/
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
/* Output mode */
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
/*---------------------------- GPIO CRL Configuration ------------------------*/
|
||||
/* Configure the eight low port pins */
|
||||
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CRL;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding low control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRL = tmpreg;
|
||||
}
|
||||
/*---------------------------- GPIO CRH Configuration ------------------------*/
|
||||
/* Configure the eight high port pins */
|
||||
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||
{
|
||||
tmpreg = GPIOx->CRH;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
/* Get the port pins position */
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding high control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRH = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* @param GPIO_PinSource: specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmpreg = AFIO->EVCR;
|
||||
/* Clear the PORT[6:4] and PIN[3:0] bits */
|
||||
tmpreg &= EVCR_PORTPINCONFIG_MASK;
|
||||
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||
tmpreg |= GPIO_PinSource;
|
||||
AFIO->EVCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Event Output.
|
||||
* @param NewState: new state of the Event output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIO_Remap: selects the pin to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
|
||||
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
|
||||
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||||
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
|
||||
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
|
||||
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
|
||||
* When the SPI3/I2S3 is remapped using this function, the SWJ is configured
|
||||
* to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
|
||||
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
|
||||
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
|
||||
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
|
||||
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
* only for High density Value line devices)
|
||||
* @param NewState: new state of the port pin remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_REMAP(GPIO_Remap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpreg = AFIO->MAPR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = AFIO->MAPR;
|
||||
}
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
}
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->MAPR2 = tmpreg;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->MAPR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* @param GPIO_PinSource: specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the Ethernet media interface.
|
||||
* @note This function applies only to STM32 Connectivity line devices.
|
||||
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_ETH_MediaInterface_MII: MII mode
|
||||
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||
{
|
||||
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
|
||||
|
||||
/* Configure MII_RMII selection bit */
|
||||
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,190 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the IWDG firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_iwdg.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_Reload ((uint16_t)0xAAAA)
|
||||
#define KR_KEY_Enable ((uint16_t)0xCCCC)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload: specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RLR = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the PWR firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_pwr.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------- PWR registers bit address in the alias region ---------- */
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
|
||||
/* Alias word address of DBP bit */
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
#define DBP_BitNumber 0x08
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BitNumber 0x04
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of EWUP bit */
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
#define EWUP_BitNumber 0x08
|
||||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
* @param NewState: new state of the access to the RTC and backup registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
|
||||
* @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
|
||||
* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
|
||||
* @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
|
||||
* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
|
||||
* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
|
||||
* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
|
||||
* @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PLS[7:5] bits */
|
||||
tmpreg &= CR_PLS_MASK;
|
||||
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
/* Set LPDS bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Clear Wake-up flag */
|
||||
PWR->CR |= PWR_CR_CWUF;
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM )
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @arg PWR_FLAG_PVDO: PVD Output
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,339 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the RTC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_rtc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC
|
||||
* @brief RTC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
|
||||
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified RTC interrupts.
|
||||
* @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @param NewState: new state of the specified RTC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_IT(RTC_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RTC->CRH |= RTC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CRH &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters the RTC configuration mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_EnterConfigMode(void)
|
||||
{
|
||||
/* Set the CNF flag to enter in the Configuration Mode */
|
||||
RTC->CRL |= RTC_CRL_CNF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits from the RTC configuration mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ExitConfigMode(void)
|
||||
{
|
||||
/* Reset the CNF flag to exit from the Configuration Mode */
|
||||
RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the RTC counter value.
|
||||
* @param None
|
||||
* @retval RTC counter value.
|
||||
*/
|
||||
uint32_t RTC_GetCounter(void)
|
||||
{
|
||||
uint16_t tmp = 0;
|
||||
tmp = RTC->CNTL;
|
||||
return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC counter value.
|
||||
* @param CounterValue: RTC counter new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetCounter(uint32_t CounterValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
/* Set RTC COUNTER MSB word */
|
||||
RTC->CNTH = CounterValue >> 16;
|
||||
/* Set RTC COUNTER LSB word */
|
||||
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC prescaler value.
|
||||
* @param PrescalerValue: RTC prescaler new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_PRESCALER(PrescalerValue));
|
||||
|
||||
RTC_EnterConfigMode();
|
||||
/* Set RTC PRESCALER MSB word */
|
||||
RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||
/* Set RTC PRESCALER LSB word */
|
||||
RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC alarm value.
|
||||
* @param AlarmValue: RTC alarm new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
/* Set the ALARM MSB word */
|
||||
RTC->ALRH = AlarmValue >> 16;
|
||||
/* Set the ALARM LSB word */
|
||||
RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the RTC divider value.
|
||||
* @param None
|
||||
* @retval RTC Divider value.
|
||||
*/
|
||||
uint32_t RTC_GetDivider(void)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
|
||||
tmp |= RTC->DIVL;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until last write operation on RTC registers has finished.
|
||||
* @note This function must be called before any write to RTC registers.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_WaitForLastTask(void)
|
||||
{
|
||||
/* Loop until RTOFF flag is set */
|
||||
while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
|
||||
* are synchronized with RTC APB clock.
|
||||
* @note This function must be called before any read operation after an APB reset
|
||||
* or an APB clock stop.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_WaitForSynchro(void)
|
||||
{
|
||||
/* Clear RSF flag */
|
||||
RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||
/* Loop until RSF flag is set */
|
||||
while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RTC flag is set or not.
|
||||
* @param RTC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one the following values:
|
||||
* @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
|
||||
* @arg RTC_FLAG_RSF: Registers Synchronized flag
|
||||
* @arg RTC_FLAG_OW: Overflow flag
|
||||
* @arg RTC_FLAG_ALR: Alarm flag
|
||||
* @arg RTC_FLAG_SEC: Second flag
|
||||
* @retval The new state of RTC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
|
||||
|
||||
if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RTC's pending flags.
|
||||
* @param RTC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
|
||||
* an APB reset or an APB Clock stop.
|
||||
* @arg RTC_FLAG_OW: Overflow flag
|
||||
* @arg RTC_FLAG_ALR: Alarm flag
|
||||
* @arg RTC_FLAG_SEC: Second flag
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
|
||||
|
||||
/* Clear the corresponding RTC flag */
|
||||
RTC->CRL &= (uint16_t)~RTC_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RTC interrupt has occurred or not.
|
||||
* @param RTC_IT: specifies the RTC interrupts sources to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @retval The new state of the RTC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_GET_IT(RTC_IT));
|
||||
|
||||
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
|
||||
if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RTC's interrupt pending bits.
|
||||
* @param RTC_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_IT(RTC_IT));
|
||||
|
||||
/* Clear the corresponding RTC pending bit */
|
||||
RTC->CRL &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,799 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_sdio.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the SDIO firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_sdio.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO
|
||||
* @brief SDIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ SDIO registers bit address in the alias region ----------- */
|
||||
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* Alias word address of CLKEN bit */
|
||||
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
|
||||
#define CLKEN_BitNumber 0x08
|
||||
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* Alias word address of SDIOSUSPEND bit */
|
||||
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||
#define SDIOSUSPEND_BitNumber 0x0B
|
||||
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ENCMDCOMPL bit */
|
||||
#define ENCMDCOMPL_BitNumber 0x0C
|
||||
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of NIEN bit */
|
||||
#define NIEN_BitNumber 0x0D
|
||||
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ATACMD bit */
|
||||
#define ATACMD_BitNumber 0x0E
|
||||
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* Alias word address of DMAEN bit */
|
||||
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||
#define DMAEN_BitNumber 0x03
|
||||
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTART bit */
|
||||
#define RWSTART_BitNumber 0x08
|
||||
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTOP bit */
|
||||
#define RWSTOP_BitNumber 0x09
|
||||
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWMOD bit */
|
||||
#define RWMOD_BitNumber 0x0A
|
||||
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
|
||||
|
||||
/* Alias word address of SDIOEN bit */
|
||||
#define SDIOEN_BitNumber 0x0B
|
||||
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
|
||||
|
||||
/* ---------------------- SDIO registers bit mask ------------------------ */
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* CLKCR register clear mask */
|
||||
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||
|
||||
/* --- PWRCTRL Register ---*/
|
||||
|
||||
/* SDIO PWRCTRL Mask */
|
||||
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* SDIO DCTRL Clear Mask */
|
||||
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* CMD Register clear mask */
|
||||
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||
|
||||
/* SDIO RESP Registers Address */
|
||||
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DeInit(void)
|
||||
{
|
||||
SDIO->POWER = 0x00000000;
|
||||
SDIO->CLKCR = 0x00000000;
|
||||
SDIO->ARG = 0x00000000;
|
||||
SDIO->CMD = 0x00000000;
|
||||
SDIO->DTIMER = 0x00000000;
|
||||
SDIO->DLEN = 0x00000000;
|
||||
SDIO->DCTRL = 0x00000000;
|
||||
SDIO->ICR = 0x00C007FF;
|
||||
SDIO->MASK = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO peripheral according to the specified
|
||||
* parameters in the SDIO_InitStruct.
|
||||
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
|
||||
* that contains the configuration information for the SDIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
|
||||
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
|
||||
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
|
||||
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
|
||||
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
|
||||
|
||||
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
|
||||
/* Get the SDIO CLKCR value */
|
||||
tmpreg = SDIO->CLKCR;
|
||||
|
||||
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
|
||||
tmpreg &= CLKCR_CLEAR_MASK;
|
||||
|
||||
/* Set CLKDIV bits according to SDIO_ClockDiv value */
|
||||
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
|
||||
/* Set BYPASS bit according to SDIO_ClockBypass value */
|
||||
/* Set WIDBUS bits according to SDIO_BusWide value */
|
||||
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
|
||||
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
|
||||
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||
|
||||
/* Write to SDIO CLKCR */
|
||||
SDIO->CLKCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||
* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
/* SDIO_InitStruct members default value */
|
||||
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO Clock.
|
||||
* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClockCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the power status of the controller.
|
||||
* @param SDIO_PowerState: new state of the Power state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_PowerState_OFF
|
||||
* @arg SDIO_PowerState_ON
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
|
||||
|
||||
SDIO->POWER &= PWR_PWRCTRL_MASK;
|
||||
SDIO->POWER |= SDIO_PowerState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the power status of the controller.
|
||||
* @param None
|
||||
* @retval Power status of the controller. The returned value can
|
||||
* be one of the following:
|
||||
* - 0x00: Power OFF
|
||||
* - 0x02: Power UP
|
||||
* - 0x03: Power ON
|
||||
*/
|
||||
uint32_t SDIO_GetPowerState(void)
|
||||
{
|
||||
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO interrupts.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @param NewState: new state of the specified SDIO interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_IT(SDIO_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the SDIO interrupts */
|
||||
SDIO->MASK |= SDIO_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the SDIO interrupts */
|
||||
SDIO->MASK &= ~SDIO_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO DMA request.
|
||||
* @param NewState: new state of the selected SDIO DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DMACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO Command according to the specified
|
||||
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
|
||||
* structure that contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
|
||||
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
|
||||
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
|
||||
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
|
||||
|
||||
/*---------------------------- SDIO ARG Configuration ------------------------*/
|
||||
/* Set the SDIO Argument value */
|
||||
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||
|
||||
/*---------------------------- SDIO CMD Configuration ------------------------*/
|
||||
/* Get the SDIO CMD value */
|
||||
tmpreg = SDIO->CMD;
|
||||
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
|
||||
tmpreg &= CMD_CLEAR_MASK;
|
||||
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
|
||||
/* Set WAITRESP bits according to SDIO_Response value */
|
||||
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
|
||||
/* Set CPSMEN bits according to SDIO_CPSM value */
|
||||
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
|
||||
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||
|
||||
/* Write to SDIO CMD */
|
||||
SDIO->CMD = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
|
||||
{
|
||||
/* SDIO_CmdInitStruct members default value */
|
||||
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns command index of last command for which response received.
|
||||
* @param None
|
||||
* @retval Returns the command index of the last command response received.
|
||||
*/
|
||||
uint8_t SDIO_GetCommandResponse(void)
|
||||
{
|
||||
return (uint8_t)(SDIO->RESPCMD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns response received from the card for the last command.
|
||||
* @param SDIO_RESP: Specifies the SDIO response register.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_RESP1: Response Register 1
|
||||
* @arg SDIO_RESP2: Response Register 2
|
||||
* @arg SDIO_RESP3: Response Register 3
|
||||
* @arg SDIO_RESP4: Response Register 4
|
||||
* @retval The Corresponding response register value.
|
||||
*/
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_RESP(SDIO_RESP));
|
||||
|
||||
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||
|
||||
return (*(__IO uint32_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO data path according to the specified
|
||||
* parameters in the SDIO_DataInitStruct.
|
||||
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
|
||||
* contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
|
||||
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
|
||||
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
|
||||
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
|
||||
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
|
||||
|
||||
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
||||
/* Set the SDIO Data TimeOut value */
|
||||
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||
|
||||
/*---------------------------- SDIO DLEN Configuration -----------------------*/
|
||||
/* Set the SDIO DataLength value */
|
||||
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||
|
||||
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
||||
/* Get the SDIO DCTRL value */
|
||||
tmpreg = SDIO->DCTRL;
|
||||
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||
tmpreg &= DCTRL_CLEAR_MASK;
|
||||
/* Set DEN bit according to SDIO_DPSM value */
|
||||
/* Set DTMODE bit according to SDIO_TransferMode value */
|
||||
/* Set DTDIR bit according to SDIO_TransferDir value */
|
||||
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
||||
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
|
||||
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||
|
||||
/* Write to SDIO DCTRL */
|
||||
SDIO->DCTRL = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
/* SDIO_DataInitStruct members default value */
|
||||
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns number of remaining data bytes to be transferred.
|
||||
* @param None
|
||||
* @retval Number of remaining data bytes to be transferred
|
||||
*/
|
||||
uint32_t SDIO_GetDataCounter(void)
|
||||
{
|
||||
return SDIO->DCOUNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one data word from Rx FIFO.
|
||||
* @param None
|
||||
* @retval Data received
|
||||
*/
|
||||
uint32_t SDIO_ReadData(void)
|
||||
{
|
||||
return SDIO->FIFO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write one data word to Tx FIFO.
|
||||
* @param Data: 32-bit data word to write.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_WriteData(uint32_t Data)
|
||||
{
|
||||
SDIO->FIFO = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||
* @param None
|
||||
* @retval Remaining number of words.
|
||||
*/
|
||||
uint32_t SDIO_GetFIFOCount(void)
|
||||
{
|
||||
return SDIO->FIFOCNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Start SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Stop SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets one of the two options of inserting read wait interval.
|
||||
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
||||
* This parameter can be:
|
||||
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
|
||||
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode Operation.
|
||||
* @param NewState: new state of SDIO specific operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||
* @param NewState: new state of the SD I/O Mode suspend command.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the command completion signal.
|
||||
* @param NewState: new state of command completion signal.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CE-ATA interrupt.
|
||||
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends CE-ATA command (CMD61).
|
||||
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO flag is set or not.
|
||||
* @param SDIO_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode.
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval The new state of SDIO_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
||||
|
||||
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's pending flags.
|
||||
* @param SDIO_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
|
||||
|
||||
SDIO->ICR = SDIO_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @retval The new state of SDIO_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_GET_IT(SDIO_IT));
|
||||
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's interrupt pending bits.
|
||||
* @param SDIO_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
|
||||
|
||||
SDIO->ICR = SDIO_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,908 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_spi.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the SPI firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_spi.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI
|
||||
* @brief SPI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CR1_SPE_Set ((uint16_t)0x0040)
|
||||
#define CR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2S I2SE mask */
|
||||
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CR1_CRCNext_Set ((uint16_t)0x1000)
|
||||
|
||||
/* SPI CRCEN mask */
|
||||
#define CR1_CRCEN_Set ((uint16_t)0x2000)
|
||||
#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||
|
||||
/* SPI SSOE mask */
|
||||
#define CR2_SSOE_Set ((uint16_t)0x0004)
|
||||
#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||
|
||||
/* SPI registers Masks */
|
||||
#define CR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||
|
||||
/* SPI or I2S mode selection masks */
|
||||
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||
|
||||
/* I2S clock source selection masks */
|
||||
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||
* reset values (Affects also the I2Ss).
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
if (SPIx == SPI1)
|
||||
{
|
||||
/* Enable SPI1 reset state */
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||
/* Release SPI1 from reset state */
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||
}
|
||||
else if (SPIx == SPI2)
|
||||
{
|
||||
/* Enable SPI2 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||
/* Release SPI2 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SPIx == SPI3)
|
||||
{
|
||||
/* Enable SPI3 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||||
/* Release SPI3 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the SPI_InitStruct.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Check the SPI parameters */
|
||||
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
|
||||
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
|
||||
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
|
||||
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
|
||||
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
|
||||
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
|
||||
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
|
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
|
||||
|
||||
/*---------------------------- SPIx CR1 Configuration ------------------------*/
|
||||
/* Get the SPIx CR1 value */
|
||||
tmpreg = SPIx->CR1;
|
||||
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
|
||||
tmpreg &= CR1_CLEAR_Mask;
|
||||
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
|
||||
master/salve mode, CPOL and CPHA */
|
||||
/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
|
||||
/* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
|
||||
/* Set LSBFirst bit according to SPI_FirstBit value */
|
||||
/* Set BR bits according to SPI_BaudRatePrescaler value */
|
||||
/* Set CPOL bit according to SPI_CPOL value */
|
||||
/* Set CPHA bit according to SPI_CPHA value */
|
||||
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||
/* Write to SPIx CR1 */
|
||||
SPIx->CR1 = tmpreg;
|
||||
|
||||
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
|
||||
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||
|
||||
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
|
||||
/* Write to SPIx CRCPOLY */
|
||||
SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the I2S_InitStruct.
|
||||
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral
|
||||
* (configured in I2S mode).
|
||||
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral
|
||||
* configured in I2S mode.
|
||||
* @note
|
||||
* The function calculates the optimal prescaler needed to obtain the most
|
||||
* accurate audio frequency (depending on the I2S clock source, the PLL values
|
||||
* and the product configuration). But in case the prescaler value is greater
|
||||
* than 511, the default value (0x02) will be configured instead. *
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||
uint32_t tmp = 0;
|
||||
RCC_ClocksTypeDef RCC_Clocks;
|
||||
uint32_t sourceclock = 0;
|
||||
|
||||
/* Check the I2S parameters */
|
||||
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
|
||||
assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
|
||||
assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
|
||||
assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
|
||||
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
|
||||
assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
|
||||
|
||||
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
|
||||
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
|
||||
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||
SPIx->I2SPR = 0x0002;
|
||||
|
||||
/* Get the I2SCFGR register value */
|
||||
tmpreg = SPIx->I2SCFGR;
|
||||
|
||||
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
|
||||
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||
{
|
||||
i2sodd = (uint16_t)0;
|
||||
i2sdiv = (uint16_t)2;
|
||||
}
|
||||
/* If the requested audio frequency is not the default, compute the prescaler */
|
||||
else
|
||||
{
|
||||
/* Check the frame length (For the Prescaler computing) */
|
||||
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||
{
|
||||
/* Packet length is 16 bits */
|
||||
packetlength = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Packet length is 32 bits */
|
||||
packetlength = 2;
|
||||
}
|
||||
|
||||
/* Get the I2S clock source mask depending on the peripheral number */
|
||||
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||
{
|
||||
/* The mask is relative to I2S2 */
|
||||
tmp = I2S2_CLOCK_SRC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The mask is relative to I2S3 */
|
||||
tmp = I2S3_CLOCK_SRC;
|
||||
}
|
||||
|
||||
/* Check the I2S clock source configuration depending on the Device:
|
||||
Only Connectivity line devices have the PLL3 VCO clock */
|
||||
#ifdef STM32F10X_CL
|
||||
if((RCC->CFGR2 & tmp) != 0)
|
||||
{
|
||||
/* Get the configuration bits of RCC PLL3 multiplier */
|
||||
tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
|
||||
|
||||
/* Get the value of the PLL3 multiplier */
|
||||
if((tmp > 5) && (tmp < 15))
|
||||
{
|
||||
/* Multiplier is between 8 and 14 (value 15 is forbidden) */
|
||||
tmp += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (tmp == 15)
|
||||
{
|
||||
/* Multiplier is 20 */
|
||||
tmp = 20;
|
||||
}
|
||||
}
|
||||
/* Get the PREDIV2 value */
|
||||
sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
|
||||
|
||||
/* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
|
||||
sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||
}
|
||||
#else /* STM32F10X_HD */
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||
{
|
||||
/* MCLK output is enabled */
|
||||
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MCLK output is disabled */
|
||||
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
|
||||
/* Remove the floating point */
|
||||
tmp = tmp / 10;
|
||||
|
||||
/* Check the parity of the divider */
|
||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||
|
||||
/* Compute the i2sdiv prescaler */
|
||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||
|
||||
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||
i2sodd = (uint16_t) (i2sodd << 8);
|
||||
}
|
||||
|
||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||
{
|
||||
/* Set the default values */
|
||||
i2sdiv = 2;
|
||||
i2sodd = 0;
|
||||
}
|
||||
|
||||
/* Write to SPIx I2SPR register the computed value */
|
||||
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||
|
||||
/* Configure the I2S with the SPI_InitStruct values */
|
||||
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
|
||||
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
|
||||
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||
|
||||
/* Write to SPIx I2SCFGR */
|
||||
SPIx->I2SCFGR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SPI_InitStruct member with its default value.
|
||||
* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
|
||||
{
|
||||
/*--------------- Reset SPI init structure parameters values -----------------*/
|
||||
/* Initialize the SPI_Direction member */
|
||||
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||
/* initialize the SPI_Mode member */
|
||||
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||
/* initialize the SPI_DataSize member */
|
||||
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||
/* Initialize the SPI_CPOL member */
|
||||
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||
/* Initialize the SPI_CPHA member */
|
||||
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||
/* Initialize the SPI_NSS member */
|
||||
SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
|
||||
/* Initialize the SPI_BaudRatePrescaler member */
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
/* Initialize the SPI_FirstBit member */
|
||||
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
/* Initialize the SPI_CRCPolynomial member */
|
||||
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each I2S_InitStruct member with its default value.
|
||||
* @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
|
||||
{
|
||||
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||
/* Initialize the I2S_Mode member */
|
||||
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||
|
||||
/* Initialize the I2S_Standard member */
|
||||
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||
|
||||
/* Initialize the I2S_DataFormat member */
|
||||
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||
|
||||
/* Initialize the I2S_MCLKOutput member */
|
||||
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||
|
||||
/* Initialize the I2S_AudioFreq member */
|
||||
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||
|
||||
/* Initialize the I2S_CPOL member */
|
||||
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral */
|
||||
SPIx->CR1 |= CR1_SPE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral */
|
||||
SPIx->CR1 &= CR1_SPE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
|
||||
* @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
|
||||
* @arg SPI_I2S_IT_ERR: Error interrupt mask
|
||||
* @param NewState: new state of the specified SPI/I2S interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||
{
|
||||
uint16_t itpos = 0, itmask = 0 ;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S interrupt */
|
||||
SPIx->CR2 |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S interrupt */
|
||||
SPIx->CR2 &= (uint16_t)~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
|
||||
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
|
||||
* @param NewState: new state of the selected SPI/I2S DMA transfer request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S DMA requests */
|
||||
SPIx->CR2 |= SPI_I2S_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S DMA requests */
|
||||
SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param Data : Data to be transmitted.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Write in the DR register the data to be sent */
|
||||
SPIx->DR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @retval The value of the received data.
|
||||
*/
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Return the data in the DR register */
|
||||
return SPIx->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
|
||||
* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
|
||||
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||
{
|
||||
/* Set NSS pin internally by software */
|
||||
SPIx->CR1 |= SPI_NSSInternalSoft_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset NSS pin internally by software */
|
||||
SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SS output for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx SS output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI SS output */
|
||||
SPIx->CR2 |= CR2_SSOE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI SS output */
|
||||
SPIx->CR2 &= CR2_SSOE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the data size for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_DataSize: specifies the SPI data size.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_DataSize_16b: Set data frame format to 16bit
|
||||
* @arg SPI_DataSize_8b: Set data frame format to 8bit
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
|
||||
/* Clear DFF bit */
|
||||
SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||
/* Set new DFF bit value */
|
||||
SPIx->CR1 |= SPI_DataSize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmit the SPIx CRC value.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Enable the selected SPI CRC transmission */
|
||||
SPIx->CR1 |= CR1_CRCNext_Set;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx CRC value calculation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI CRC calculation */
|
||||
SPIx->CR1 |= CR1_CRCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI CRC calculation */
|
||||
SPIx->CR1 &= CR1_CRCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_CRC: specifies the CRC register to be read.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CRC_Tx: Selects Tx CRC register
|
||||
* @arg SPI_CRC_Rx: Selects Rx CRC register
|
||||
* @retval The selected CRC register value..
|
||||
*/
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
|
||||
{
|
||||
uint16_t crcreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_CRC(SPI_CRC));
|
||||
if (SPI_CRC != SPI_CRC_Rx)
|
||||
{
|
||||
/* Get the Tx CRC register */
|
||||
crcreg = SPIx->TXCRCR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the Rx CRC register */
|
||||
crcreg = SPIx->RXCRCR;
|
||||
}
|
||||
/* Return the selected CRC register */
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval The CRC Polynomial register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Return the CRC polynomial register */
|
||||
return SPIx->CRCPR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_Direction_Tx: Selects Tx transmission direction
|
||||
* @arg SPI_Direction_Rx: Selects Rx receive direction
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_DIRECTION(SPI_Direction));
|
||||
if (SPI_Direction == SPI_Direction_Tx)
|
||||
{
|
||||
/* Set the Tx only mode */
|
||||
SPIx->CR1 |= SPI_Direction_Tx;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Rx only mode */
|
||||
SPIx->CR1 &= SPI_Direction_Rx;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
|
||||
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
|
||||
* @arg SPI_I2S_FLAG_BSY: Busy flag.
|
||||
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
|
||||
* @arg SPI_FLAG_MODF: Mode Fault flag.
|
||||
* @arg SPI_FLAG_CRCERR: CRC Error flag.
|
||||
* @arg I2S_FLAG_UDR: Underrun Error flag.
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag.
|
||||
* @retval The new state of SPI_I2S_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
|
||||
/* Check the status of the specified SPI/I2S flag */
|
||||
if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
/* SPI_I2S_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_FLAG: specifies the SPI flag to clear.
|
||||
* This function clears only CRCERR flag.
|
||||
* @note
|
||||
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||
* operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
|
||||
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||
* SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||
* write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) flag */
|
||||
SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
|
||||
* @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
|
||||
* @arg SPI_I2S_IT_OVR: Overrun interrupt.
|
||||
* @arg SPI_IT_MODF: Mode Fault interrupt.
|
||||
* @arg SPI_IT_CRCERR: CRC Error interrupt.
|
||||
* @arg I2S_IT_UDR: Underrun Error interrupt.
|
||||
* @retval The new state of SPI_I2S_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Get the SPI/I2S IT mask */
|
||||
itmask = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = 0x01 << itmask;
|
||||
|
||||
/* Get the SPI_I2S_IT enable bit status */
|
||||
enablestatus = (SPIx->CR2 & itmask) ;
|
||||
|
||||
/* Check the status of the specified SPI/I2S interrupt */
|
||||
if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||
{
|
||||
/* SPI_I2S_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
|
||||
* This function clears only CRCERR interrupt pending bit.
|
||||
* @note
|
||||
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
|
||||
* followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||
* operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
|
||||
* followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
|
||||
* the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
uint16_t itpos = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
|
||||
SPIx->SR = (uint16_t)~itpos;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,224 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the WWDG firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_wwdg.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ----------- WWDG registers bit address in the alias region ----------- */
|
||||
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
|
||||
|
||||
/* Alias word address of EWI bit */
|
||||
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
|
||||
#define EWI_BitNumber 0x09
|
||||
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
|
||||
|
||||
/* --------------------- WWDG registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_WDGA_Set ((uint32_t)0x00000080)
|
||||
|
||||
/* CFR register bit mask */
|
||||
#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||
#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_Mask ((uint8_t)0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpreg = WWDG->CFR & CFR_W_Mask;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= WindowValue & (uint32_t) BIT_Mask;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = Counter & BIT_Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
WWDG->CR = CR_WDGA_Set | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(WWDG->SR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->SR = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 08-April-2011
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CONF_H
|
||||
#define __STM32F10x_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
|
||||
#include "stm32f10x_adc.h"
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_can.h"
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_crc.h"
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_exti.h"
|
||||
#include "stm32f10x_flash.h"
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_i2c.h"
|
||||
#include "stm32f10x_iwdg.h"
|
||||
#include "stm32f10x_pwr.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
#include "stm32f10x_rtc.h"
|
||||
#include "stm32f10x_sdio.h"
|
||||
#include "stm32f10x_spi.h"
|
||||
#include "stm32f10x_tim.h"
|
||||
#include "stm32f10x_usart.h"
|
||||
#include "stm32f10x_wwdg.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F10x_CONF_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/****************************************************************************************
|
||||
| Description: demo program application source file
|
||||
| File Name: main.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: main
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: program return code
|
||||
** DESCRIPTION: This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader interface */
|
||||
BootComInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* toggle LED with a fixed frequency */
|
||||
LedToggle();
|
||||
/* check for bootloader activation request */
|
||||
BootComCheckActivationRequest();
|
||||
}
|
||||
|
||||
/* program should never get here */
|
||||
return 0;
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: Init
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the microcontroller.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
volatile unsigned long StartUpCounter = 0, HSEStatus = 0;
|
||||
unsigned long pll_multiplier;
|
||||
|
||||
/* reset the RCC clock configuration to the default reset state (for debug purpose) */
|
||||
/* set HSION bit */
|
||||
RCC->CR |= (unsigned long)0x00000001;
|
||||
/* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
|
||||
RCC->CFGR &= (unsigned long)0xF8FF0000;
|
||||
/* reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (unsigned long)0xFEF6FFFF;
|
||||
/* reset HSEBYP bit */
|
||||
RCC->CR &= (unsigned long)0xFFFBFFFF;
|
||||
/* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
|
||||
RCC->CFGR &= (unsigned long)0xFF80FFFF;
|
||||
/* disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000;
|
||||
/* enable HSE */
|
||||
RCC->CR |= ((unsigned long)RCC_CR_HSEON);
|
||||
/* wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
}
|
||||
while((HSEStatus == 0) && (StartUpCounter != 1500));
|
||||
/* check if time out was reached */
|
||||
if ((RCC->CR & RCC_CR_HSERDY) == RESET)
|
||||
{
|
||||
/* cannot continue when HSE is not ready */
|
||||
while (1) { ; }
|
||||
}
|
||||
/* enable flash prefetch buffer */
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
/* reset flash wait state configuration to default 0 wait states */
|
||||
FLASH->ACR &= (unsigned long)((unsigned long)~FLASH_ACR_LATENCY);
|
||||
#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
|
||||
/* configure 2 flash wait states */
|
||||
FLASH->ACR |= (unsigned long)FLASH_ACR_LATENCY_2;
|
||||
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
|
||||
/* configure 1 flash wait states */
|
||||
FLASH->ACR |= (unsigned long)FLASH_ACR_LATENCY_1;
|
||||
#endif
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (unsigned long)RCC_CFGR_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK/2 */
|
||||
RCC->CFGR |= (unsigned long)RCC_CFGR_PPRE2_DIV2;
|
||||
/* PCLK1 = HCLK/2 */
|
||||
RCC->CFGR |= (unsigned long)RCC_CFGR_PPRE1_DIV2;
|
||||
/* reset PLL configuration */
|
||||
RCC->CFGR &= (unsigned long)((unsigned long)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
|
||||
RCC_CFGR_PLLMULL));
|
||||
/* calculate multiplier value */
|
||||
pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
|
||||
/* convert to register value */
|
||||
pll_multiplier = (unsigned long)((pll_multiplier - 2) << 18);
|
||||
/* set the PLL multiplier and clock source */
|
||||
RCC->CFGR |= (unsigned long)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
|
||||
/* enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
/* wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* select PLL as system clock source */
|
||||
RCC->CFGR &= (unsigned long)((unsigned long)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (unsigned long)RCC_CFGR_SW_PLL;
|
||||
/* wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (unsigned long)RCC_CFGR_SWS) != (unsigned long)0x08)
|
||||
{
|
||||
}
|
||||
/* init the led driver */
|
||||
LedInit();
|
||||
/* init the timer driver */
|
||||
TimerInit();
|
||||
/* enable IRQ's, because they were initially disabled by the bootloader */
|
||||
IrqInterruptEnable();
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
MEMORY
|
||||
{
|
||||
UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
|
||||
FLASH (rx) : ORIGIN = 0x08002000, LENGTH = 0x00020000-0x2000
|
||||
RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00005000
|
||||
USB_CAN_RAM (wx) : ORIGIN = 0x40006000, LENGTH = 0x00000200
|
||||
CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__FLASH_segment_start__ = 0x08002000;
|
||||
__FLASH_segment_end__ = 0x08020000;
|
||||
__RAM_segment_start__ = 0x20000000;
|
||||
__RAM_segment_end__ = 0x20005000;
|
||||
__USB_CAN_RAM_segment_start__ = 0x40006000;
|
||||
__USB_CAN_RAM_segment_end__ = 0x40006200;
|
||||
__CM3_System_Control_Space_segment_start__ = 0xe000e000;
|
||||
__CM3_System_Control_Space_segment_end__ = 0xe000f000;
|
||||
|
||||
__STACKSIZE__ = 256;
|
||||
__STACKSIZE_PROCESS__ = 0;
|
||||
__STACKSIZE_IRQ__ = 0;
|
||||
__STACKSIZE_FIQ__ = 0;
|
||||
__STACKSIZE_SVC__ = 0;
|
||||
__STACKSIZE_ABT__ = 0;
|
||||
__STACKSIZE_UND__ = 0;
|
||||
__HEAPSIZE__ = 128;
|
||||
|
||||
__vectors_ram_load_start__ = ALIGN(__RAM_segment_start__ , 256);
|
||||
.vectors_ram ALIGN(__RAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__RAM_segment_start__ , 256))
|
||||
{
|
||||
__vectors_ram_start__ = .;
|
||||
*(.vectors_ram .vectors_ram.*)
|
||||
}
|
||||
__vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
|
||||
|
||||
__vectors_ram_load_end__ = __vectors_ram_end__;
|
||||
|
||||
. = ASSERT(__vectors_ram_end__ >= __RAM_segment_start__ && __vectors_ram_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .vectors_ram is too large to fit in RAM memory segment");
|
||||
|
||||
__vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
|
||||
.vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
|
||||
{
|
||||
__vectors_start__ = .;
|
||||
*(.vectors .vectors.*)
|
||||
}
|
||||
__vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
|
||||
|
||||
__vectors_load_end__ = __vectors_end__;
|
||||
|
||||
. = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .vectors is too large to fit in FLASH memory segment");
|
||||
|
||||
__init_load_start__ = ALIGN(__vectors_end__ , 4);
|
||||
.init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
|
||||
{
|
||||
__init_start__ = .;
|
||||
*(.init .init.*)
|
||||
}
|
||||
__init_end__ = __init_start__ + SIZEOF(.init);
|
||||
|
||||
__init_load_end__ = __init_end__;
|
||||
|
||||
. = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .init is too large to fit in FLASH memory segment");
|
||||
|
||||
__text_load_start__ = ALIGN(__init_end__ , 4);
|
||||
.text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
|
||||
{
|
||||
__text_start__ = .;
|
||||
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
|
||||
}
|
||||
__text_end__ = __text_start__ + SIZEOF(.text);
|
||||
|
||||
__text_load_end__ = __text_end__;
|
||||
|
||||
. = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .text is too large to fit in FLASH memory segment");
|
||||
|
||||
__dtors_load_start__ = ALIGN(__text_end__ , 4);
|
||||
.dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
|
||||
{
|
||||
__dtors_start__ = .;
|
||||
KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) KEEP (*(.fini_array .fini_array.*))
|
||||
}
|
||||
__dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
|
||||
|
||||
__dtors_load_end__ = __dtors_end__;
|
||||
|
||||
. = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .dtors is too large to fit in FLASH memory segment");
|
||||
|
||||
__ctors_load_start__ = ALIGN(__dtors_end__ , 4);
|
||||
.ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
|
||||
{
|
||||
__ctors_start__ = .;
|
||||
KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*(.init_array .init_array.*))
|
||||
}
|
||||
__ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
|
||||
|
||||
__ctors_load_end__ = __ctors_end__;
|
||||
|
||||
. = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ctors is too large to fit in FLASH memory segment");
|
||||
|
||||
__rodata_load_start__ = ALIGN(__ctors_end__ , 4);
|
||||
.rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
|
||||
{
|
||||
__rodata_start__ = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
}
|
||||
__rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
|
||||
|
||||
__rodata_load_end__ = __rodata_end__;
|
||||
|
||||
. = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .rodata is too large to fit in FLASH memory segment");
|
||||
|
||||
__ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
|
||||
.ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
|
||||
{
|
||||
__ARM.exidx_start__ = .;
|
||||
__exidx_start = __ARM.exidx_start__;
|
||||
*(.ARM.exidx .ARM.exidx.*)
|
||||
}
|
||||
__ARM.exidx_end__ = __ARM.exidx_start__ + SIZEOF(.ARM.exidx);
|
||||
|
||||
__exidx_end = __ARM.exidx_end__;
|
||||
__ARM.exidx_load_end__ = __ARM.exidx_end__;
|
||||
|
||||
. = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ARM.exidx is too large to fit in FLASH memory segment");
|
||||
|
||||
__fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
|
||||
.fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
|
||||
{
|
||||
__fast_start__ = .;
|
||||
*(.fast .fast.*)
|
||||
}
|
||||
__fast_end__ = __fast_start__ + SIZEOF(.fast);
|
||||
|
||||
__fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
|
||||
|
||||
. = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .fast is too large to fit in FLASH memory segment");
|
||||
|
||||
.fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__fast_run_start__ = .;
|
||||
. = MAX(__fast_run_start__ + SIZEOF(.fast), .);
|
||||
}
|
||||
__fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
|
||||
|
||||
__fast_run_load_end__ = __fast_run_end__;
|
||||
|
||||
. = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .fast_run is too large to fit in RAM memory segment");
|
||||
|
||||
__data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
|
||||
.data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
}
|
||||
__data_end__ = __data_start__ + SIZEOF(.data);
|
||||
|
||||
__data_load_end__ = __data_load_start__ + SIZEOF(.data);
|
||||
|
||||
. = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .data is too large to fit in FLASH memory segment");
|
||||
|
||||
.data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__data_run_start__ = .;
|
||||
. = MAX(__data_run_start__ + SIZEOF(.data), .);
|
||||
}
|
||||
__data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
|
||||
|
||||
__data_run_load_end__ = __data_run_end__;
|
||||
|
||||
. = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .data_run is too large to fit in RAM memory segment");
|
||||
|
||||
__bss_load_start__ = ALIGN(__data_run_end__ , 4);
|
||||
.bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
|
||||
}
|
||||
__bss_end__ = __bss_start__ + SIZEOF(.bss);
|
||||
|
||||
__bss_load_end__ = __bss_end__;
|
||||
|
||||
. = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .bss is too large to fit in RAM memory segment");
|
||||
|
||||
__non_init_load_start__ = ALIGN(__bss_end__ , 4);
|
||||
.non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
|
||||
{
|
||||
__non_init_start__ = .;
|
||||
*(.non_init .non_init.*)
|
||||
}
|
||||
__non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
|
||||
|
||||
__non_init_load_end__ = __non_init_end__;
|
||||
|
||||
. = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .non_init is too large to fit in RAM memory segment");
|
||||
|
||||
__heap_load_start__ = ALIGN(__non_init_end__ , 4);
|
||||
.heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
|
||||
{
|
||||
__heap_start__ = .;
|
||||
*(.heap .heap.*)
|
||||
. = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
|
||||
}
|
||||
__heap_end__ = __heap_start__ + SIZEOF(.heap);
|
||||
|
||||
__heap_load_end__ = __heap_end__;
|
||||
|
||||
. = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .heap is too large to fit in RAM memory segment");
|
||||
|
||||
__stack_load_start__ = ALIGN(__heap_end__ , 4);
|
||||
.stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
|
||||
{
|
||||
__stack_start__ = .;
|
||||
*(.stack .stack.*)
|
||||
. = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
|
||||
}
|
||||
__stack_end__ = __stack_start__ + SIZEOF(.stack);
|
||||
|
||||
__stack_load_end__ = __stack_end__;
|
||||
|
||||
. = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .stack is too large to fit in RAM memory segment");
|
||||
|
||||
__stack_process_load_start__ = ALIGN(__stack_end__ , 4);
|
||||
.stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
|
||||
{
|
||||
__stack_process_start__ = .;
|
||||
*(.stack_process .stack_process.*)
|
||||
. = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
|
||||
}
|
||||
__stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
|
||||
|
||||
__stack_process_load_end__ = __stack_process_end__;
|
||||
|
||||
. = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .stack_process is too large to fit in RAM memory segment");
|
||||
|
||||
__tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
|
||||
.tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
|
||||
{
|
||||
__tbss_start__ = .;
|
||||
*(.tbss .tbss.*)
|
||||
}
|
||||
__tbss_end__ = __tbss_start__ + SIZEOF(.tbss);
|
||||
|
||||
__tbss_load_end__ = __tbss_end__;
|
||||
|
||||
. = ASSERT(__tbss_end__ >= __RAM_segment_start__ && __tbss_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .tbss is too large to fit in RAM memory segment");
|
||||
|
||||
__tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
|
||||
.tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
|
||||
{
|
||||
__tdata_start__ = .;
|
||||
*(.tdata .tdata.*)
|
||||
}
|
||||
__tdata_end__ = __tdata_start__ + SIZEOF(.tdata);
|
||||
|
||||
__tdata_load_end__ = __tdata_load_start__ + SIZEOF(.tdata);
|
||||
|
||||
__FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
|
||||
|
||||
. = ASSERT((__tdata_load_start__ + SIZEOF(.tdata)) >= __FLASH_segment_start__ && (__tdata_load_start__ + SIZEOF(.tdata)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .tdata is too large to fit in FLASH memory segment");
|
||||
|
||||
.tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__tdata_run_start__ = .;
|
||||
. = MAX(__tdata_run_start__ + SIZEOF(.tdata), .);
|
||||
}
|
||||
__tdata_run_end__ = __tdata_run_start__ + SIZEOF(.tdata_run);
|
||||
|
||||
__tdata_run_load_end__ = __tdata_run_end__;
|
||||
|
||||
__RAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
|
||||
|
||||
. = ASSERT(__tdata_run_end__ >= __RAM_segment_start__ && __tdata_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .tdata_run is too large to fit in RAM memory segment");
|
||||
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,102 @@
|
|||
/****************************************************************************************
|
||||
| Description: Timer driver source file
|
||||
| File Name: timer.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
static unsigned long millisecond_counter;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: TimerInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerInit(void)
|
||||
{
|
||||
/* configure the SysTick timer for 1 ms period */
|
||||
SysTick_Config(BOOT_CPU_SYSTEM_SPEED_KHZ);
|
||||
/* reset the millisecond counter */
|
||||
TimerSet(0);
|
||||
} /*** end of TimerInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: TimerSet
|
||||
** PARAMETER: timer_value initialize value of the millisecond timer.
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Sets the initial counter value of the millisecond timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerSet(unsigned long timer_value)
|
||||
{
|
||||
/* set the millisecond counter */
|
||||
millisecond_counter = timer_value;
|
||||
} /*** end of TimerSet ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: TimerGet
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: current value of the millisecond timer
|
||||
** DESCRIPTION: Obtains the counter value of the millisecond timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
unsigned long TimerGet(void)
|
||||
{
|
||||
/* read and return the millisecond counter value */
|
||||
return millisecond_counter;
|
||||
} /*** end of TimerGet ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: TimerISRHandler
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Interrupt service routine of the timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerISRHandler(void)
|
||||
{
|
||||
/* increment the millisecond counter */
|
||||
millisecond_counter++;
|
||||
} /*** end of TimerISRHandler ***/
|
||||
|
||||
|
||||
/*********************************** end of timer.c ************************************/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/****************************************************************************************
|
||||
| Description: Timer driver header file
|
||||
| File Name: timer.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef TIMER_H
|
||||
#define TIMER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void TimerInit(void);
|
||||
void TimerSet(unsigned long timer_value);
|
||||
unsigned long TimerGet(void);
|
||||
void TimerISRHandler(void);
|
||||
|
||||
#endif /* TIMER_H */
|
||||
/*********************************** end of timer.h ************************************/
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader interrupt vector table source file
|
||||
| File Name: vectors.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void reset_handler(void); /* implemented in cstart.s */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External data declarations
|
||||
****************************************************************************************/
|
||||
extern unsigned long __stack_end__; /* stack end address (memory.x) */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: UnusedISR
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Catch-all for unused interrrupt service routines.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void UnusedISR(void)
|
||||
{
|
||||
/* unexpected interrupt occured, so halt the system */
|
||||
while (1) { ; }
|
||||
} /*** end of UnusedISR ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* I N T E R R U P T V E C T O R T A B L E
|
||||
****************************************************************************************/
|
||||
typedef union
|
||||
{
|
||||
void (*func)(void); /* for ISR function pointers */
|
||||
unsigned long ptr; /* for stack pointer entry */
|
||||
}tIsrFunc; /* type for vector table entries */
|
||||
|
||||
__attribute__ ((section(".vectors")))
|
||||
const tIsrFunc _vectors[] =
|
||||
{
|
||||
{ .ptr = (unsigned long)&__stack_end__ }, /* the initial stack pointer */
|
||||
reset_handler, /* the reset handler */
|
||||
UnusedISR, /* NMI Handler */
|
||||
UnusedISR, /* Hard Fault Handler */
|
||||
UnusedISR, /* MPU Fault Handler */
|
||||
UnusedISR, /* Bus Fault Handler */
|
||||
UnusedISR, /* Usage Fault Handler */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* SVCall Handler */
|
||||
UnusedISR, /* Debug Monitor Handler */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* PendSV Handler */
|
||||
TimerISRHandler, /* SysTick Handler */
|
||||
UnusedISR, /* Window Watchdog */
|
||||
UnusedISR, /* PVD through EXTI Line detect */
|
||||
UnusedISR, /* Tamper */
|
||||
UnusedISR, /* RTC */
|
||||
UnusedISR, /* Flash */
|
||||
UnusedISR, /* RCC */
|
||||
UnusedISR, /* EXTI Line 0 */
|
||||
UnusedISR, /* EXTI Line 1 */
|
||||
UnusedISR, /* EXTI Line 2 */
|
||||
UnusedISR, /* EXTI Line 3 */
|
||||
UnusedISR, /* EXTI Line 4 */
|
||||
UnusedISR, /* DMA1 Channel 1 */
|
||||
UnusedISR, /* DMA1 Channel 2 */
|
||||
UnusedISR, /* DMA1 Channel 3 */
|
||||
UnusedISR, /* DMA1 Channel 4 */
|
||||
UnusedISR, /* DMA1 Channel 5 */
|
||||
UnusedISR, /* DMA1 Channel 6 */
|
||||
UnusedISR, /* DMA1 Channel 7 */
|
||||
UnusedISR, /* ADC1 and ADC2 */
|
||||
UnusedISR, /* CAN1 TX */
|
||||
UnusedISR, /* CAN1 RX0 */
|
||||
UnusedISR, /* CAN1 RX1 */
|
||||
UnusedISR, /* CAN1 SCE */
|
||||
UnusedISR, /* EXTI Line 9..5 */
|
||||
UnusedISR, /* TIM1 Break */
|
||||
UnusedISR, /* TIM1 Update */
|
||||
UnusedISR, /* TIM1 Trigger and Commutation */
|
||||
UnusedISR, /* TIM1 Capture Compare */
|
||||
UnusedISR, /* TIM2 */
|
||||
UnusedISR, /* TIM3 */
|
||||
UnusedISR, /* TIM4 */
|
||||
UnusedISR, /* I2C1 Event */
|
||||
UnusedISR, /* I2C1 Error */
|
||||
UnusedISR, /* I2C2 Event */
|
||||
UnusedISR, /* I2C1 Error */
|
||||
UnusedISR, /* SPI1 */
|
||||
UnusedISR, /* SPI2 */
|
||||
UnusedISR, /* USART1 */
|
||||
UnusedISR, /* USART2 */
|
||||
UnusedISR, /* USART3 */
|
||||
UnusedISR, /* EXTI Line 15..10 */
|
||||
UnusedISR, /* RTC alarm through EXTI line */
|
||||
UnusedISR, /* USB OTG FS Wakeup */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* TIM5 */
|
||||
UnusedISR, /* SPI3 */
|
||||
UnusedISR, /* UART4 */
|
||||
UnusedISR, /* UART5 */
|
||||
UnusedISR, /* TIM6 */
|
||||
UnusedISR, /* TIM7 */
|
||||
UnusedISR, /* DMA2 Channel1 */
|
||||
UnusedISR, /* DMA2 Channel2 */
|
||||
UnusedISR, /* DMA2 Channel3 */
|
||||
UnusedISR, /* DMA2 Channel4 */
|
||||
UnusedISR, /* DMA2 Channel5 */
|
||||
UnusedISR, /* Ethernet */
|
||||
UnusedISR, /* Ethernet Wakeup */
|
||||
UnusedISR, /* CAN2 TX */
|
||||
UnusedISR, /* CAN2 RX0 */
|
||||
UnusedISR, /* CAN2 RX1 */
|
||||
UnusedISR, /* CAN2 SCE */
|
||||
UnusedISR, /* USB OTG FS */
|
||||
(void*)0x55AA11EE, /* Reserved for OpenBLT checksum */
|
||||
};
|
||||
|
||||
|
||||
/************************************ end of hw.c **************************************/
|
||||
|
||||
|
||||
|
|
@ -84,7 +84,7 @@ void CpuStartUserProgram(void)
|
|||
/* set the address where the bootloader needs to jump to */
|
||||
pProgResetHandler = (void*)CPU_RAM_VECTORS_START_ADDR;
|
||||
|
||||
/* start the user program by acticating its reset interrupt service routine */
|
||||
/* start the user program by activating its reset interrupt service routine */
|
||||
pProgResetHandler();
|
||||
} /*** end of CpuStartUserProgram ***/
|
||||
|
||||
|
|
|
|||
|
|
@ -228,7 +228,7 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
|||
****************************************************************************************/
|
||||
static blt_bool UartTransmitByte(blt_int8u data)
|
||||
{
|
||||
/* check if tx holding register can accept new data and throw assertion error if not */
|
||||
/* check if tx holding register can accept new data */
|
||||
if ((U0LSR & UART_THRE) == 0)
|
||||
{
|
||||
/* UART not ready. should not happen */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,434 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2009 Rowley Associates Limited. *
|
||||
* *
|
||||
* This file may be distributed under the terms of the License Agreement *
|
||||
* provided with this software. *
|
||||
* *
|
||||
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
|
||||
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Preprocessor Definitions
|
||||
* ------------------------
|
||||
* APP_ENTRY_POINT
|
||||
*
|
||||
* Defines the application entry point function, if undefined this setting
|
||||
* defaults to "main".
|
||||
*
|
||||
* USE_PROCESS_STACK
|
||||
*
|
||||
* If defined, thread mode will be configured to use the process stack if
|
||||
* the size of the process stack is greater than zero bytes in length.
|
||||
*
|
||||
* INITIALIZE_STACK
|
||||
*
|
||||
* If defined, the contents of the stack will be initialized to a the
|
||||
* value 0xCC.
|
||||
*
|
||||
* INITIALIZE_SECONDARY_SECTIONS
|
||||
*
|
||||
* If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
|
||||
*
|
||||
* FULL_LIBRARY
|
||||
*
|
||||
* If defined then
|
||||
* - argc, argv are setup by the debug_getargs.
|
||||
* - the exit symbol is defined and executes on return from main.
|
||||
* - the exit symbol calls destructors, atexit functions and then debug_exit.
|
||||
*
|
||||
* If not defined then
|
||||
* - argc and argv are zero.
|
||||
* - the exit symbol is defined, executes on return from main and loops
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef APP_ENTRY_POINT
|
||||
#define APP_ENTRY_POINT main
|
||||
#endif
|
||||
|
||||
#ifndef ARGSSPACE
|
||||
#define ARGSSPACE 128
|
||||
#endif
|
||||
|
||||
.extern APP_ENTRY_POINT
|
||||
.global exit
|
||||
.global reset_handler
|
||||
.global EntryFromProg
|
||||
.extern ComSetConnectEntryState
|
||||
|
||||
.section .init, "ax"
|
||||
.code 16
|
||||
.align 2
|
||||
|
||||
.thumb_func
|
||||
/****************************************************************************************
|
||||
** NAME: EntryFromProg
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Called by the user program to activate the bootloader. Do not place
|
||||
** any assembly code before this function and the end of the vector
|
||||
** table. This guarantees that this function is located at address
|
||||
** 0x08000150. The user program can call this function from C in the
|
||||
** following way:
|
||||
** void ActivateBootloader(void)
|
||||
** {
|
||||
** void (*pEntryFromProgFnc)(void);
|
||||
**
|
||||
** pEntryFromProgFnc = (void*)0x08000150 + 1;
|
||||
** pEntryFromProgFnc();
|
||||
** }
|
||||
** Note that the + 1 added to the function address is neccassary to
|
||||
** enable a switch from Thumb2 to Thumb mode.
|
||||
**
|
||||
****************************************************************************************/
|
||||
EntryFromProg:
|
||||
/* disable interrupts first */
|
||||
cpsid i
|
||||
/* configure vector table offset register to use bootloader's vector table*/
|
||||
ldr r0, =0xE000ED08
|
||||
ldr r1, =_vectors
|
||||
str r1, [r0]
|
||||
/* initialize stack pointer */
|
||||
ldr r1, =__stack_end__
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
mov sp, r1
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
ldr r0, =__stack_start__
|
||||
bl memory_set
|
||||
#endif
|
||||
|
||||
#ifdef USE_PROCESS_STACK
|
||||
/* Set up process stack if size > 0 */
|
||||
ldr r1, =__stack_process_end__
|
||||
ldr r0, =__stack_process_start__
|
||||
sub r2, r1, r0
|
||||
beq 1f
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
msr psp, r1
|
||||
mov r2, #2
|
||||
msr control, r2
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
bl memory_set
|
||||
#endif
|
||||
1:
|
||||
#endif
|
||||
/* Copy initialised memory sections into RAM (if necessary). */
|
||||
ldr r0, =__data_load_start__
|
||||
ldr r1, =__data_start__
|
||||
ldr r2, =__data_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text_load_start__
|
||||
ldr r1, =__text_start__
|
||||
ldr r2, =__text_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__fast_load_start__
|
||||
ldr r1, =__fast_start__
|
||||
ldr r2, =__fast_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__ctors_load_start__
|
||||
ldr r1, =__ctors_start__
|
||||
ldr r2, =__ctors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__dtors_load_start__
|
||||
ldr r1, =__dtors_start__
|
||||
ldr r2, =__dtors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata_load_start__
|
||||
ldr r1, =__rodata_start__
|
||||
ldr r2, =__rodata_end__
|
||||
bl memory_copy
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__data2_load_start__
|
||||
ldr r1, =__data2_start__
|
||||
ldr r2, =__data2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text2_load_start__
|
||||
ldr r1, =__text2_start__
|
||||
ldr r2, =__text2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata2_load_start__
|
||||
ldr r1, =__rodata2_start__
|
||||
ldr r2, =__rodata2_end__
|
||||
bl memory_copy
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Zero the bss. */
|
||||
ldr r0, =__bss_start__
|
||||
ldr r1, =__bss_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__bss2_start__
|
||||
ldr r1, =__bss2_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Initialise the heap */
|
||||
ldr r0, = __heap_start__
|
||||
ldr r1, = __heap_end__
|
||||
sub r1, r1, r0
|
||||
cmp r1, #8
|
||||
blt 1f
|
||||
mov r2, #0
|
||||
str r2, [r0]
|
||||
add r0, r0, #4
|
||||
str r1, [r0]
|
||||
1:
|
||||
|
||||
/* Call constructors */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0]
|
||||
add r0, #4
|
||||
push {r0-r1}
|
||||
blx r2
|
||||
pop {r0-r1}
|
||||
b ctor_loop
|
||||
ctor_end:
|
||||
|
||||
/* Setup initial call frame */
|
||||
mov r0, #0
|
||||
mov lr, r0
|
||||
mov r12, sp
|
||||
|
||||
start:
|
||||
/* this part makes the difference with the normal reset_handler */
|
||||
bl ComSetConnectEntryState
|
||||
/* Jump to application entry point */
|
||||
#ifdef FULL_LIBRARY
|
||||
mov r0, #ARGSSPACE
|
||||
ldr r1, =args
|
||||
ldr r2, =debug_getargs
|
||||
blx r2
|
||||
ldr r1, =args
|
||||
#else
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
#endif
|
||||
ldr r2, =APP_ENTRY_POINT
|
||||
blx r2
|
||||
|
||||
.thumb_func
|
||||
/****************************************************************************************
|
||||
** NAME: reset_handler
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Reset interrupt service routine. Configures the stack, initializes
|
||||
** RAM and jumps to function main.
|
||||
**
|
||||
****************************************************************************************/
|
||||
reset_handler:
|
||||
/* disable interrupts first */
|
||||
cpsid i
|
||||
ldr r1, =__stack_end__
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
mov sp, r1
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
ldr r0, =__stack_start__
|
||||
bl memory_set
|
||||
#endif
|
||||
|
||||
#ifdef USE_PROCESS_STACK
|
||||
/* Set up process stack if size > 0 */
|
||||
ldr r1, =__stack_process_end__
|
||||
ldr r0, =__stack_process_start__
|
||||
sub r2, r1, r0
|
||||
beq 1f
|
||||
#ifdef __ARM_EABI__
|
||||
mov r2, #0x7
|
||||
bic r1, r2
|
||||
#endif
|
||||
msr psp, r1
|
||||
mov r2, #2
|
||||
msr control, r2
|
||||
#ifdef INITIALIZE_STACK
|
||||
mov r2, #0xCC
|
||||
bl memory_set
|
||||
#endif
|
||||
1:
|
||||
#endif
|
||||
/* Copy initialised memory sections into RAM (if necessary). */
|
||||
ldr r0, =__data_load_start__
|
||||
ldr r1, =__data_start__
|
||||
ldr r2, =__data_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text_load_start__
|
||||
ldr r1, =__text_start__
|
||||
ldr r2, =__text_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__fast_load_start__
|
||||
ldr r1, =__fast_start__
|
||||
ldr r2, =__fast_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__ctors_load_start__
|
||||
ldr r1, =__ctors_start__
|
||||
ldr r2, =__ctors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__dtors_load_start__
|
||||
ldr r1, =__dtors_start__
|
||||
ldr r2, =__dtors_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata_load_start__
|
||||
ldr r1, =__rodata_start__
|
||||
ldr r2, =__rodata_end__
|
||||
bl memory_copy
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__data2_load_start__
|
||||
ldr r1, =__data2_start__
|
||||
ldr r2, =__data2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__text2_load_start__
|
||||
ldr r1, =__text2_start__
|
||||
ldr r2, =__text2_end__
|
||||
bl memory_copy
|
||||
ldr r0, =__rodata2_load_start__
|
||||
ldr r1, =__rodata2_start__
|
||||
ldr r2, =__rodata2_end__
|
||||
bl memory_copy
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Zero the bss. */
|
||||
ldr r0, =__bss_start__
|
||||
ldr r1, =__bss_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#ifdef INITIALIZE_SECONDARY_SECTIONS
|
||||
ldr r0, =__bss2_start__
|
||||
ldr r1, =__bss2_end__
|
||||
mov r2, #0
|
||||
bl memory_set
|
||||
#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
|
||||
|
||||
/* Initialise the heap */
|
||||
ldr r0, = __heap_start__
|
||||
ldr r1, = __heap_end__
|
||||
sub r1, r1, r0
|
||||
cmp r1, #8
|
||||
blt 1f
|
||||
mov r2, #0
|
||||
str r2, [r0]
|
||||
add r0, r0, #4
|
||||
str r1, [r0]
|
||||
1:
|
||||
|
||||
/* Call constructors */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
ctor_loop2:
|
||||
cmp r0, r1
|
||||
beq ctor_end2
|
||||
ldr r2, [r0]
|
||||
add r0, #4
|
||||
push {r0-r1}
|
||||
blx r2
|
||||
pop {r0-r1}
|
||||
b ctor_loop2
|
||||
ctor_end2:
|
||||
|
||||
/* Setup initial call frame */
|
||||
mov r0, #0
|
||||
mov lr, r0
|
||||
mov r12, sp
|
||||
|
||||
start2:
|
||||
/* Jump to application entry point */
|
||||
#ifdef FULL_LIBRARY
|
||||
mov r0, #ARGSSPACE
|
||||
ldr r1, =args
|
||||
ldr r2, =debug_getargs
|
||||
blx r2
|
||||
ldr r1, =args
|
||||
#else
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
#endif
|
||||
ldr r2, =APP_ENTRY_POINT
|
||||
blx r2
|
||||
|
||||
.thumb_func
|
||||
exit:
|
||||
#ifdef FULL_LIBRARY
|
||||
mov r5, r0 // save the exit parameter/return result
|
||||
|
||||
/* Call destructors */
|
||||
ldr r0, =__dtors_start__
|
||||
ldr r1, =__dtors_end__
|
||||
dtor_loop:
|
||||
cmp r0, r1
|
||||
beq dtor_end
|
||||
ldr r2, [r0]
|
||||
add r0, #4
|
||||
push {r0-r1}
|
||||
blx r2
|
||||
pop {r0-r1}
|
||||
b dtor_loop
|
||||
dtor_end:
|
||||
|
||||
/* Call atexit functions */
|
||||
ldr r2, =_execute_at_exit_fns
|
||||
blx r2
|
||||
|
||||
/* Call debug_exit with return result/exit parameter */
|
||||
mov r0, r5
|
||||
ldr r2, =debug_exit
|
||||
blx r2
|
||||
#endif
|
||||
|
||||
/* Returned from application entry point, loop forever. */
|
||||
exit_loop:
|
||||
b exit_loop
|
||||
|
||||
.thumb_func
|
||||
memory_copy:
|
||||
cmp r0, r1
|
||||
beq 2f
|
||||
sub r2, r2, r1
|
||||
beq 2f
|
||||
1:
|
||||
ldrb r3, [r0]
|
||||
add r0, r0, #1
|
||||
strb r3, [r1]
|
||||
add r1, r1, #1
|
||||
sub r2, r2, #1
|
||||
bne 1b
|
||||
2:
|
||||
bx lr
|
||||
|
||||
.thumb_func
|
||||
memory_set:
|
||||
cmp r0, r1
|
||||
beq 1f
|
||||
strb r2, [r0]
|
||||
add r0, r0, #1
|
||||
b memory_set
|
||||
1:
|
||||
bx lr
|
||||
|
||||
|
||||
#ifdef FULL_LIBRARY
|
||||
.bss
|
||||
args:
|
||||
.space ARGSSPACE
|
||||
#endif
|
||||
|
||||
/* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
|
||||
.section .stack, "wa", %nobits
|
||||
.section .stack_process, "wa", %nobits
|
||||
.section .heap, "wa", %nobits
|
||||
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
MEMORY
|
||||
{
|
||||
UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x00004000
|
||||
RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00001800
|
||||
USB_CAN_RAM (wx) : ORIGIN = 0x40006000, LENGTH = 0x00000200
|
||||
CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__FLASH_segment_start__ = 0x08000000;
|
||||
__FLASH_segment_end__ = 0x08004000;
|
||||
__RAM_segment_start__ = 0x20000000;
|
||||
__RAM_segment_end__ = 0x20001800;
|
||||
__USB_CAN_RAM_segment_start__ = 0x40006000;
|
||||
__USB_CAN_RAM_segment_end__ = 0x40006200;
|
||||
__CM3_System_Control_Space_segment_start__ = 0xe000e000;
|
||||
__CM3_System_Control_Space_segment_end__ = 0xe000f000;
|
||||
|
||||
__STACKSIZE__ = 256;
|
||||
__STACKSIZE_PROCESS__ = 0;
|
||||
__STACKSIZE_IRQ__ = 0;
|
||||
__STACKSIZE_FIQ__ = 0;
|
||||
__STACKSIZE_SVC__ = 0;
|
||||
__STACKSIZE_ABT__ = 0;
|
||||
__STACKSIZE_UND__ = 0;
|
||||
__HEAPSIZE__ = 128;
|
||||
|
||||
__vectors_ram_load_start__ = ALIGN(__RAM_segment_start__ , 256);
|
||||
.vectors_ram ALIGN(__RAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__RAM_segment_start__ , 256))
|
||||
{
|
||||
__vectors_ram_start__ = .;
|
||||
*(.vectors_ram .vectors_ram.*)
|
||||
}
|
||||
__vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
|
||||
|
||||
__vectors_ram_load_end__ = __vectors_ram_end__;
|
||||
|
||||
. = ASSERT(__vectors_ram_end__ >= __RAM_segment_start__ && __vectors_ram_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .vectors_ram is too large to fit in RAM memory segment");
|
||||
|
||||
__vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
|
||||
.vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
|
||||
{
|
||||
__vectors_start__ = .;
|
||||
*(.vectors .vectors.*)
|
||||
}
|
||||
__vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
|
||||
|
||||
__vectors_load_end__ = __vectors_end__;
|
||||
|
||||
. = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .vectors is too large to fit in FLASH memory segment");
|
||||
|
||||
__init_load_start__ = ALIGN(__vectors_end__ , 4);
|
||||
.init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
|
||||
{
|
||||
__init_start__ = .;
|
||||
*(.init .init.*)
|
||||
}
|
||||
__init_end__ = __init_start__ + SIZEOF(.init);
|
||||
|
||||
__init_load_end__ = __init_end__;
|
||||
|
||||
. = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .init is too large to fit in FLASH memory segment");
|
||||
|
||||
__text_load_start__ = ALIGN(__init_end__ , 4);
|
||||
.text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
|
||||
{
|
||||
__text_start__ = .;
|
||||
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
|
||||
}
|
||||
__text_end__ = __text_start__ + SIZEOF(.text);
|
||||
|
||||
__text_load_end__ = __text_end__;
|
||||
|
||||
. = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .text is too large to fit in FLASH memory segment");
|
||||
|
||||
__dtors_load_start__ = ALIGN(__text_end__ , 4);
|
||||
.dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
|
||||
{
|
||||
__dtors_start__ = .;
|
||||
KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) KEEP (*(.fini_array .fini_array.*))
|
||||
}
|
||||
__dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
|
||||
|
||||
__dtors_load_end__ = __dtors_end__;
|
||||
|
||||
. = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .dtors is too large to fit in FLASH memory segment");
|
||||
|
||||
__ctors_load_start__ = ALIGN(__dtors_end__ , 4);
|
||||
.ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
|
||||
{
|
||||
__ctors_start__ = .;
|
||||
KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*(.init_array .init_array.*))
|
||||
}
|
||||
__ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
|
||||
|
||||
__ctors_load_end__ = __ctors_end__;
|
||||
|
||||
. = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ctors is too large to fit in FLASH memory segment");
|
||||
|
||||
__rodata_load_start__ = ALIGN(__ctors_end__ , 4);
|
||||
.rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
|
||||
{
|
||||
__rodata_start__ = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
}
|
||||
__rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
|
||||
|
||||
__rodata_load_end__ = __rodata_end__;
|
||||
|
||||
. = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .rodata is too large to fit in FLASH memory segment");
|
||||
|
||||
__ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
|
||||
.ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
|
||||
{
|
||||
__ARM.exidx_start__ = .;
|
||||
__exidx_start = __ARM.exidx_start__;
|
||||
*(.ARM.exidx .ARM.exidx.*)
|
||||
}
|
||||
__ARM.exidx_end__ = __ARM.exidx_start__ + SIZEOF(.ARM.exidx);
|
||||
|
||||
__exidx_end = __ARM.exidx_end__;
|
||||
__ARM.exidx_load_end__ = __ARM.exidx_end__;
|
||||
|
||||
. = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ARM.exidx is too large to fit in FLASH memory segment");
|
||||
|
||||
__fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
|
||||
.fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
|
||||
{
|
||||
__fast_start__ = .;
|
||||
*(.fast .fast.*)
|
||||
}
|
||||
__fast_end__ = __fast_start__ + SIZEOF(.fast);
|
||||
|
||||
__fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
|
||||
|
||||
. = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .fast is too large to fit in FLASH memory segment");
|
||||
|
||||
.fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__fast_run_start__ = .;
|
||||
. = MAX(__fast_run_start__ + SIZEOF(.fast), .);
|
||||
}
|
||||
__fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
|
||||
|
||||
__fast_run_load_end__ = __fast_run_end__;
|
||||
|
||||
. = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .fast_run is too large to fit in RAM memory segment");
|
||||
|
||||
__data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
|
||||
.data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
}
|
||||
__data_end__ = __data_start__ + SIZEOF(.data);
|
||||
|
||||
__data_load_end__ = __data_load_start__ + SIZEOF(.data);
|
||||
|
||||
. = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .data is too large to fit in FLASH memory segment");
|
||||
|
||||
.data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__data_run_start__ = .;
|
||||
. = MAX(__data_run_start__ + SIZEOF(.data), .);
|
||||
}
|
||||
__data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
|
||||
|
||||
__data_run_load_end__ = __data_run_end__;
|
||||
|
||||
. = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .data_run is too large to fit in RAM memory segment");
|
||||
|
||||
__bss_load_start__ = ALIGN(__data_run_end__ , 4);
|
||||
.bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
|
||||
}
|
||||
__bss_end__ = __bss_start__ + SIZEOF(.bss);
|
||||
|
||||
__bss_load_end__ = __bss_end__;
|
||||
|
||||
. = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .bss is too large to fit in RAM memory segment");
|
||||
|
||||
__non_init_load_start__ = ALIGN(__bss_end__ , 4);
|
||||
.non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
|
||||
{
|
||||
__non_init_start__ = .;
|
||||
*(.non_init .non_init.*)
|
||||
}
|
||||
__non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
|
||||
|
||||
__non_init_load_end__ = __non_init_end__;
|
||||
|
||||
. = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .non_init is too large to fit in RAM memory segment");
|
||||
|
||||
__heap_load_start__ = ALIGN(__non_init_end__ , 4);
|
||||
.heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
|
||||
{
|
||||
__heap_start__ = .;
|
||||
*(.heap .heap.*)
|
||||
. = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
|
||||
}
|
||||
__heap_end__ = __heap_start__ + SIZEOF(.heap);
|
||||
|
||||
__heap_load_end__ = __heap_end__;
|
||||
|
||||
. = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .heap is too large to fit in RAM memory segment");
|
||||
|
||||
__stack_load_start__ = ALIGN(__heap_end__ , 4);
|
||||
.stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
|
||||
{
|
||||
__stack_start__ = .;
|
||||
*(.stack .stack.*)
|
||||
. = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
|
||||
}
|
||||
__stack_end__ = __stack_start__ + SIZEOF(.stack);
|
||||
|
||||
__stack_load_end__ = __stack_end__;
|
||||
|
||||
. = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .stack is too large to fit in RAM memory segment");
|
||||
|
||||
__stack_process_load_start__ = ALIGN(__stack_end__ , 4);
|
||||
.stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
|
||||
{
|
||||
__stack_process_start__ = .;
|
||||
*(.stack_process .stack_process.*)
|
||||
. = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
|
||||
}
|
||||
__stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
|
||||
|
||||
__stack_process_load_end__ = __stack_process_end__;
|
||||
|
||||
. = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .stack_process is too large to fit in RAM memory segment");
|
||||
|
||||
__tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
|
||||
.tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
|
||||
{
|
||||
__tbss_start__ = .;
|
||||
*(.tbss .tbss.*)
|
||||
}
|
||||
__tbss_end__ = __tbss_start__ + SIZEOF(.tbss);
|
||||
|
||||
__tbss_load_end__ = __tbss_end__;
|
||||
|
||||
. = ASSERT(__tbss_end__ >= __RAM_segment_start__ && __tbss_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .tbss is too large to fit in RAM memory segment");
|
||||
|
||||
__tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
|
||||
.tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
|
||||
{
|
||||
__tdata_start__ = .;
|
||||
*(.tdata .tdata.*)
|
||||
}
|
||||
__tdata_end__ = __tdata_start__ + SIZEOF(.tdata);
|
||||
|
||||
__tdata_load_end__ = __tdata_load_start__ + SIZEOF(.tdata);
|
||||
|
||||
__FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
|
||||
|
||||
. = ASSERT((__tdata_load_start__ + SIZEOF(.tdata)) >= __FLASH_segment_start__ && (__tdata_load_start__ + SIZEOF(.tdata)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .tdata is too large to fit in FLASH memory segment");
|
||||
|
||||
.tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
|
||||
{
|
||||
__tdata_run_start__ = .;
|
||||
. = MAX(__tdata_run_start__ + SIZEOF(.tdata), .);
|
||||
}
|
||||
__tdata_run_end__ = __tdata_run_start__ + SIZEOF(.tdata_run);
|
||||
|
||||
__tdata_run_load_end__ = __tdata_run_end__;
|
||||
|
||||
__RAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
|
||||
|
||||
. = ASSERT(__tdata_run_end__ >= __RAM_segment_start__ && __tdata_run_end__ <= (__RAM_segment_start__ + 0x00005000) , "error: .tdata_run is too large to fit in RAM memory segment");
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader interrupt vector table source file
|
||||
| File Name: vectors.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void reset_handler(void); /* implemented in cstart.s */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External data declarations
|
||||
****************************************************************************************/
|
||||
extern blt_int32u __stack_end__; /* stack end address (memory.x) */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: UnusedISR
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Catch-all for unused interrrupt service routines.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void UnusedISR(void)
|
||||
{
|
||||
/* unexpected interrupt occured, so trigger an assertion to halt the system */
|
||||
ASSERT_RT(BLT_FALSE);
|
||||
} /*** end of UnusedISR ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* I N T E R R U P T V E C T O R T A B L E
|
||||
****************************************************************************************/
|
||||
typedef union
|
||||
{
|
||||
void (*func)(void); /* for ISR function pointers */
|
||||
blt_int32u ptr; /* for stack pointer entry */
|
||||
}tIsrFunc; /* type for vector table entries */
|
||||
|
||||
__attribute__ ((section(".vectors")))
|
||||
const tIsrFunc _vectors[] =
|
||||
{
|
||||
{ .ptr = (blt_int32u)&__stack_end__ }, /* the initial stack pointer */
|
||||
reset_handler, /* the reset handler */
|
||||
UnusedISR, /* NMI Handler */
|
||||
UnusedISR, /* Hard Fault Handler */
|
||||
UnusedISR, /* MPU Fault Handler */
|
||||
UnusedISR, /* Bus Fault Handler */
|
||||
UnusedISR, /* Usage Fault Handler */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* SVCall Handler */
|
||||
UnusedISR, /* Debug Monitor Handler */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* PendSV Handler */
|
||||
UnusedISR, /* SysTick Handler */
|
||||
UnusedISR, /* Window Watchdog */
|
||||
UnusedISR, /* PVD through EXTI Line detect */
|
||||
UnusedISR, /* Tamper */
|
||||
UnusedISR, /* RTC */
|
||||
UnusedISR, /* Flash */
|
||||
UnusedISR, /* RCC */
|
||||
UnusedISR, /* EXTI Line 0 */
|
||||
UnusedISR, /* EXTI Line 1 */
|
||||
UnusedISR, /* EXTI Line 2 */
|
||||
UnusedISR, /* EXTI Line 3 */
|
||||
UnusedISR, /* EXTI Line 4 */
|
||||
UnusedISR, /* DMA1 Channel 1 */
|
||||
UnusedISR, /* DMA1 Channel 2 */
|
||||
UnusedISR, /* DMA1 Channel 3 */
|
||||
UnusedISR, /* DMA1 Channel 4 */
|
||||
UnusedISR, /* DMA1 Channel 5 */
|
||||
UnusedISR, /* DMA1 Channel 6 */
|
||||
UnusedISR, /* DMA1 Channel 7 */
|
||||
UnusedISR, /* ADC1 and ADC2 */
|
||||
UnusedISR, /* CAN1 TX */
|
||||
UnusedISR, /* CAN1 RX0 */
|
||||
UnusedISR, /* CAN1 RX1 */
|
||||
UnusedISR, /* CAN1 SCE */
|
||||
UnusedISR, /* EXTI Line 9..5 */
|
||||
UnusedISR, /* TIM1 Break */
|
||||
UnusedISR, /* TIM1 Update */
|
||||
UnusedISR, /* TIM1 Trigger and Commutation */
|
||||
UnusedISR, /* TIM1 Capture Compare */
|
||||
UnusedISR, /* TIM2 */
|
||||
UnusedISR, /* TIM3 */
|
||||
UnusedISR, /* TIM4 */
|
||||
UnusedISR, /* I2C1 Event */
|
||||
UnusedISR, /* I2C1 Error */
|
||||
UnusedISR, /* I2C2 Event */
|
||||
UnusedISR, /* I2C1 Error */
|
||||
UnusedISR, /* SPI1 */
|
||||
UnusedISR, /* SPI2 */
|
||||
UnusedISR, /* USART1 */
|
||||
UnusedISR, /* USART2 */
|
||||
UnusedISR, /* USART3 */
|
||||
UnusedISR, /* EXTI Line 15..10 */
|
||||
UnusedISR, /* RTC alarm through EXTI line */
|
||||
UnusedISR, /* USB OTG FS Wakeup */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* Reserved */
|
||||
UnusedISR, /* TIM5 */
|
||||
UnusedISR, /* SPI3 */
|
||||
UnusedISR, /* UART4 */
|
||||
UnusedISR, /* UART5 */
|
||||
UnusedISR, /* TIM6 */
|
||||
UnusedISR, /* TIM7 */
|
||||
UnusedISR, /* DMA2 Channel1 */
|
||||
UnusedISR, /* DMA2 Channel2 */
|
||||
UnusedISR, /* DMA2 Channel3 */
|
||||
UnusedISR, /* DMA2 Channel4 */
|
||||
UnusedISR, /* DMA2 Channel5 */
|
||||
UnusedISR, /* Ethernet */
|
||||
UnusedISR, /* Ethernet Wakeup */
|
||||
UnusedISR, /* CAN2 TX */
|
||||
UnusedISR, /* CAN2 RX0 */
|
||||
UnusedISR, /* CAN2 RX1 */
|
||||
UnusedISR, /* CAN2 SCE */
|
||||
UnusedISR /* USB OTG FS */
|
||||
};
|
||||
|
||||
|
||||
/************************************ end of hw.c **************************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,351 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader CAN communication interface source file
|
||||
| File Name: can.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/* CAN transmission mailbox */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int32u TIR;
|
||||
volatile blt_int32u TDTR;
|
||||
volatile blt_int32u TDLR;
|
||||
volatile blt_int32u TDHR;
|
||||
} tCanTxMailBox;
|
||||
|
||||
/* CAN reception FIFO mailbox */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int32u RIR;
|
||||
volatile blt_int32u RDTR;
|
||||
volatile blt_int32u RDLR;
|
||||
volatile blt_int32u RDHR;
|
||||
} tCanRxFIFOMailBox;
|
||||
|
||||
/* CAN filter register layout */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int32u FR1;
|
||||
volatile blt_int32u FR2;
|
||||
} tCanFilter;
|
||||
|
||||
/* CAN controller register layout */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int32u MCR;
|
||||
volatile blt_int32u MSR;
|
||||
volatile blt_int32u TSR;
|
||||
volatile blt_int32u RF0R;
|
||||
volatile blt_int32u RF1R;
|
||||
volatile blt_int32u IER;
|
||||
volatile blt_int32u ESR;
|
||||
volatile blt_int32u BTR;
|
||||
blt_int32u RESERVED0[88];
|
||||
tCanTxMailBox sTxMailBox[3];
|
||||
tCanRxFIFOMailBox sFIFOMailBox[2];
|
||||
blt_int32u RESERVED1[12];
|
||||
volatile blt_int32u FMR;
|
||||
volatile blt_int32u FM1R;
|
||||
blt_int32u RESERVED2;
|
||||
volatile blt_int32u FS1R;
|
||||
blt_int32u RESERVED3;
|
||||
volatile blt_int32u FFA1R;
|
||||
blt_int32u RESERVED4;
|
||||
volatile blt_int32u FA1R;
|
||||
blt_int32u RESERVED5[8];
|
||||
tCanFilter sFilterRegister[14];
|
||||
} tCanRegs;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#define CAN_BIT_RESET ((blt_int32u)0x00008000) /* reset request bit */
|
||||
#define CAN_BIT_INRQ ((blt_int32u)0x00000001) /* initialization request bit */
|
||||
#define CAN_BIT_INAK ((blt_int32u)0x00000001) /* initialization acknowledge bit*/
|
||||
#define CAN_BIT_SLEEP ((blt_int32u)0x00000002) /* sleep mode request bit */
|
||||
#define CAN_BIT_FILTER0 ((blt_int32u)0x00000001) /* filter 0 selection bit */
|
||||
#define CAN_BIT_FINIT ((blt_int32u)0x00000001) /* filter init mode bit */
|
||||
#define CAN_BIT_TME0 ((blt_int32u)0x04000000) /* transmit mailbox 0 empty bit */
|
||||
#define CAN_BIT_TXRQ ((blt_int32u)0x00000001) /* transmit mailbox request bit */
|
||||
#define CAN_BIT_RFOM0 ((blt_int32u)0x00000020) /* release FIFO 0 mailbox bit */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Register definitions
|
||||
****************************************************************************************/
|
||||
#define CANx ((tCanRegs *) (blt_int32u)0x40006400)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
typedef struct t_can_bus_timing
|
||||
{
|
||||
blt_int8u tseg1; /* CAN time segment 1 */
|
||||
blt_int8u tseg2; /* CAN time segment 2 */
|
||||
} tCanBusTiming; /* bus timing structure type */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/* According to the CAN protocol 1 bit-time can be made up of between 8..25 time quanta
|
||||
* (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC always being 1.
|
||||
* The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) * 100%. This array contains
|
||||
* possible and valid time quanta configurations with a sample point between 68..78%.
|
||||
*/
|
||||
static const tCanBusTiming canTiming[] =
|
||||
{ /* TQ | TSEG1 | TSEG2 | SP */
|
||||
/* ------------------------- */
|
||||
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
|
||||
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
|
||||
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
|
||||
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
|
||||
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
|
||||
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
|
||||
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
|
||||
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
|
||||
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
|
||||
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
|
||||
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
|
||||
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
|
||||
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
|
||||
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
|
||||
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
|
||||
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
|
||||
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
|
||||
{ 16, 8 } /* 25 | 16 | 8 | 68% */
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CanGetSpeedConfig
|
||||
** PARAMETER: baud The desired baudrate in kbps. Valid values are 10..1000.
|
||||
** prescaler Pointer to where the value for the prescaler will be stored.
|
||||
** tseg1 Pointer to where the value for TSEG2 will be stored.
|
||||
** tseg2 Pointer to where the value for TSEG2 will be stored.
|
||||
** RETURN VALUE: BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
|
||||
** otherwise.
|
||||
** DESCRIPTION: Search algorithm to match the desired baudrate to a possible bus
|
||||
** timing configuration.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u *prescaler,
|
||||
blt_int8u *tseg1, blt_int8u *tseg2)
|
||||
{
|
||||
blt_int8u cnt;
|
||||
|
||||
/* loop through all possible time quanta configurations to find a match */
|
||||
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
|
||||
{
|
||||
if (((BOOT_CPU_SYSTEM_SPEED_KHZ/2) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
|
||||
{
|
||||
/* compute the prescaler that goes with this TQ configuration */
|
||||
*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/2)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
|
||||
|
||||
/* make sure the prescaler is valid */
|
||||
if ( (*prescaler > 0) && (*prescaler <= 1024) )
|
||||
{
|
||||
/* store the bustiming configuration */
|
||||
*tseg1 = canTiming[cnt].tseg1;
|
||||
*tseg2 = canTiming[cnt].tseg2;
|
||||
/* found a good bus timing configuration */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* could not find a good bus timing configuration */
|
||||
return BLT_FALSE;
|
||||
} /*** end of CanGetSpeedConfig ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CanInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the CAN controller and synchronizes it to the CAN bus.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CanInit(void)
|
||||
{
|
||||
blt_int16u prescaler;
|
||||
blt_int8u tseg1, tseg2;
|
||||
blt_bool result;
|
||||
|
||||
/* the current implementation supports CAN1. throw an assertion error in case a
|
||||
* different CAN channel is configured.
|
||||
*/
|
||||
ASSERT_CT(BOOT_COM_CAN_CHANNEL_INDEX == 0);
|
||||
/* obtain bittiming configuration information */
|
||||
result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
|
||||
ASSERT_RT(result == BLT_TRUE);
|
||||
/* disable all can interrupt. this driver works in polling mode */
|
||||
CANx->IER = (blt_int32u)0;
|
||||
/* set request to reset the can controller */
|
||||
CANx->MCR |= CAN_BIT_RESET ;
|
||||
/* wait for acknowledge that the can controller was reset */
|
||||
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* exit from sleep mode, which is the default mode after reset */
|
||||
CANx->MCR &= ~CAN_BIT_SLEEP;
|
||||
/* set request to enter initialisation mode */
|
||||
CANx->MCR |= CAN_BIT_INRQ ;
|
||||
/* wait for acknowledge that initialization mode was entered */
|
||||
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* configure the bittming */
|
||||
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
||||
(blt_int32u)((blt_int32u)(tseg2 - 1) << 20) | \
|
||||
(blt_int32u)(prescaler - 1);
|
||||
/* set request to leave initialisation mode */
|
||||
CANx->MCR &= ~CAN_BIT_INRQ;
|
||||
/* wait for acknowledge that initialization mode was exited */
|
||||
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* enter initialisation mode for the acceptance filter */
|
||||
CANx->FMR |= CAN_BIT_FINIT;
|
||||
/* deactivate filter 0 */
|
||||
CANx->FA1R &= ~CAN_BIT_FILTER0;
|
||||
/* 32-bit scale for the filter */
|
||||
CANx->FS1R |= CAN_BIT_FILTER0;
|
||||
/* open up the acceptance filter to receive all messages */
|
||||
CANx->sFilterRegister[0].FR1 = 0;
|
||||
CANx->sFilterRegister[0].FR2 = 0;
|
||||
/* select id/mask mode for the filter */
|
||||
CANx->FM1R &= ~CAN_BIT_FILTER0;
|
||||
/* FIFO 0 assignation for the filter */
|
||||
CANx->FFA1R &= ~CAN_BIT_FILTER0;
|
||||
/* filter activation */
|
||||
CANx->FA1R |= CAN_BIT_FILTER0;
|
||||
/* leave initialisation mode for the acceptance filter */
|
||||
CANx->FMR &= ~CAN_BIT_FINIT;
|
||||
} /*** end of CanInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CanTransmitPacket
|
||||
** PARAMETER: data pointer to byte array with data that it to be transmitted.
|
||||
** len number of bytes that are to be transmitted.
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Transmits a packet formatted for the communication interface.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||
{
|
||||
blt_int8u byte_count;
|
||||
blt_int8u mailbox;
|
||||
|
||||
/* make sure that transmit mailbox 0 is available */
|
||||
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
||||
/* store the 11-bit message identifier */
|
||||
CANx->sTxMailBox[0].TIR &= CAN_BIT_TXRQ;
|
||||
CANx->sTxMailBox[0].TIR |= ((blt_int32u)BOOT_COM_CAN_TX_MSG_ID << 21);
|
||||
/* store the message date length code (DLC) */
|
||||
CANx->sTxMailBox[0].TDTR = len;
|
||||
/* store the message data bytes */
|
||||
CANx->sTxMailBox[0].TDLR = (((blt_int32u)data[3] << 24) | \
|
||||
((blt_int32u)data[2] << 16) | \
|
||||
((blt_int32u)data[1] << 8) | \
|
||||
((blt_int32u)data[0]));
|
||||
CANx->sTxMailBox[0].TDHR = (((blt_int32u)data[7] << 24) | \
|
||||
((blt_int32u)data[6] << 16) | \
|
||||
((blt_int32u)data[5] << 8) | \
|
||||
((blt_int32u)data[4]));
|
||||
/* request the start of message transmission */
|
||||
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
||||
/* wait for transmit completion */
|
||||
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
} /*** end of CanTransmitPacket ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CanReceivePacket
|
||||
** PARAMETER: data pointer to byte array where the data is to be stored.
|
||||
** RETURN VALUE: BLT_TRUE is a packet was received, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Receives a communication interface packet if one is present.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool CanReceivePacket(blt_int8u *data)
|
||||
{
|
||||
blt_int8u byte_count;
|
||||
blt_int32u rxMsgId;
|
||||
blt_bool result = BLT_FALSE;
|
||||
|
||||
/* check if a new message was received */
|
||||
if ((CANx->RF0R&(blt_int32u)0x00000003) > 0)
|
||||
{
|
||||
/* read out the message identifier */
|
||||
rxMsgId = (blt_int32u)0x000007FF & (CANx->sFIFOMailBox[0].RIR >> 21);
|
||||
/* is this the packet identifier */
|
||||
if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
|
||||
{
|
||||
result = BLT_TRUE;
|
||||
/* store the received packet data */
|
||||
data[0] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDLR;
|
||||
data[1] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 8);
|
||||
data[2] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 16);
|
||||
data[3] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 24);
|
||||
data[4] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDHR;
|
||||
data[5] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 8);
|
||||
data[6] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 16);
|
||||
data[7] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 24);
|
||||
}
|
||||
/* release FIFO0 */
|
||||
CANx->RF0R |= CAN_BIT_RFOM0;
|
||||
}
|
||||
return result;
|
||||
} /*** end of CanReceivePacket ***/
|
||||
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of can.c **************************************/
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader CAN communication interface header file
|
||||
| File Name: can.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef CAN_H
|
||||
#define CAN_H
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void CanInit(void);
|
||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len);
|
||||
blt_bool CanReceivePacket(blt_int8u *data);
|
||||
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||
|
||||
|
||||
#endif /* CAN_H */
|
||||
/*********************************** end of can.h **************************************/
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader cpu module source file
|
||||
| File Name: cpu.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr) 0x08002004)
|
||||
#define CPU_USER_PROGRAM_VECTABLE_OFFSET ((blt_int32u)0x00002000)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Register definitions
|
||||
****************************************************************************************/
|
||||
/* vector table offset register */
|
||||
#define SCB_VTOR (*((volatile blt_int32u *) 0xE000ED08))
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void reset_handler(void); /* implemented in cstart.s */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CpuStartUserProgram
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Starts the user program, if one is present. In this case this function
|
||||
** does not return.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuStartUserProgram(void)
|
||||
{
|
||||
void (*pProgResetHandler)(void);
|
||||
|
||||
/* check if a user program is present by verifying the checksum */
|
||||
if (NvmVerifyChecksum() == BLT_FALSE)
|
||||
{
|
||||
/* not a valid user program so it cannot be started */
|
||||
return;
|
||||
}
|
||||
/* remap user program's vector table */
|
||||
SCB_VTOR = CPU_USER_PROGRAM_VECTABLE_OFFSET & (blt_int32u)0x1FFFFF80;
|
||||
/* set the address where the bootloader needs to jump to. this is the address of
|
||||
* the 2nd entry in the user program's vector table. this address points to the
|
||||
* user program's reset handler.
|
||||
*/
|
||||
pProgResetHandler = (void*)(*((blt_addr*)CPU_USER_PROGRAM_STARTADDR_PTR));
|
||||
/* start the user program by activating its reset interrupt service routine */
|
||||
pProgResetHandler();
|
||||
} /*** end of CpuStartUserProgram ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CpuMemCopy
|
||||
** PARAMETER: dest destination address for the data.
|
||||
** src source address of the data.
|
||||
** len length of the data in bytes.
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Copies data from the source to the destination address.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
|
||||
{
|
||||
blt_int8u *from, *to;
|
||||
|
||||
/* set casted pointers */
|
||||
from = (blt_int8u *)src;
|
||||
to = (blt_int8u *)dest;
|
||||
|
||||
/* copy all bytes from source address to destination address */
|
||||
while(len-- > 0)
|
||||
{
|
||||
/* store byte value from source to destination */
|
||||
*to++ = *from++;
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
} /*** end of CpuMemCopy ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: CpuReset
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Perform a soft reset of the microcontroller by starting from the reset
|
||||
** ISR.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuReset(void)
|
||||
{
|
||||
/* perform a software reset by calling the reset ISR routine */
|
||||
reset_handler();
|
||||
} /*** end of CpuReset ***/
|
||||
|
||||
|
||||
/*********************************** end of cpu.c **************************************/
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader cpu module header file
|
||||
| File Name: cpu.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef CPU_H
|
||||
#define CPU_H
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void CpuStartUserProgram(void);
|
||||
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len);
|
||||
void CpuReset(void);
|
||||
|
||||
|
||||
#endif /* CPU_H */
|
||||
/*********************************** end of cpu.h **************************************/
|
||||
|
|
@ -0,0 +1,813 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader flash driver source file
|
||||
| File Name: flash.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#define FLASH_INVALID_SECTOR (0xff)
|
||||
#define FLASH_INVALID_ADDRESS (0xffffffff)
|
||||
#define FLASH_WRITE_BLOCK_SIZE (512)
|
||||
#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
|
||||
#if (BOOT_NVM_SIZE_KB > 128)
|
||||
#define FLASH_ERASE_BLOCK_SIZE (0x800)
|
||||
#else
|
||||
#define FLASH_ERASE_BLOCK_SIZE (0x400)
|
||||
#endif
|
||||
#define FLASH ((tFlashRegs *) (blt_int32u)0x40022000)
|
||||
#define FLASH_KEY1 ((blt_int32u)0x45670123)
|
||||
#define FLASH_KEY2 ((blt_int32u)0xCDEF89AB)
|
||||
#define FLASH_LOCK_BIT ((blt_int32u)0x00000080)
|
||||
#define FLASH_EOP_BIT ((blt_int32u)0x00000020)
|
||||
#define FLASH_PGERR_BIT ((blt_int32u)0x00000004)
|
||||
#define FLASH_WRPRTERR_BIT ((blt_int32u)0x00000010)
|
||||
#define FLASH_BSY_BIT ((blt_int32u)0x00000001)
|
||||
#define FLASH_PER_BIT ((blt_int32u)0x00000002)
|
||||
#define FLASH_STRT_BIT ((blt_int32u)0x00000040)
|
||||
#define FLASH_PG_BIT ((blt_int32u)0x00000001)
|
||||
#define FLASH_VECTOR_TABLE_CS_OFFSET (0x150)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/* flash sector descriptor type */
|
||||
typedef struct
|
||||
{
|
||||
blt_addr sector_start; /* sector start address */
|
||||
blt_int32u sector_size; /* sector size in bytes */
|
||||
blt_int8u sector_num; /* sector number */
|
||||
} tFlashSector; /* flash sector description */
|
||||
|
||||
/* programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a flash block
|
||||
* manager is implemented in this driver. this flash block manager depends on this
|
||||
* flash block info structure. It holds the base address of the flash block and the
|
||||
* data that should be programmed into the flash block. The .base_addr must be a multiple
|
||||
* of FLASH_WRITE_BLOCK_SIZE.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
blt_addr base_addr;
|
||||
blt_int8u data[FLASH_WRITE_BLOCK_SIZE];
|
||||
} tFlashBlockInfo;
|
||||
|
||||
/* FLASH register layout type */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int32u ACR; /* flash access control register */
|
||||
volatile blt_int32u KEYR; /* FPEC key register */
|
||||
volatile blt_int32u OPTKEYR; /* flash OPTKEY register */
|
||||
volatile blt_int32u SR; /* flash status register */
|
||||
volatile blt_int32u CR; /* flash control register */
|
||||
volatile blt_int32u AR; /* flash address register */
|
||||
volatile blt_int32u RESERVED;
|
||||
volatile blt_int32u OBR; /* option byte register */
|
||||
volatile blt_int32u WRPR; /* write protection register */
|
||||
} tFlashRegs;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address);
|
||||
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
|
||||
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
|
||||
blt_int8u *data, blt_int16u len);
|
||||
static blt_bool FlashWriteBlock(tFlashBlockInfo *block);
|
||||
static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector);
|
||||
static void FlashUnlock(void);
|
||||
static void FlashLock(void);
|
||||
static blt_int8u FlashGetSector(blt_addr address);
|
||||
static blt_addr FlashGetSectorBaseAddr(blt_int8u sector);
|
||||
static blt_addr FlashGetSectorSize(blt_int8u sector);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/* The current flash layout does not reflect the minimum sector size of the physical
|
||||
* flash (1 - 2kb), because this would make the table quit long and a wast or ROM. The
|
||||
* minumum sector size is only really needed when erasing the flash. This can still be
|
||||
* done in combination with macro FLASH_ERASE_BLOCK_SIZE.
|
||||
*/
|
||||
static const tFlashSector flashLayout[] =
|
||||
{
|
||||
/* { 0x08000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
|
||||
{ 0x08002000, 0x02000, 1}, /* flash sector 1 - 8kb */
|
||||
{ 0x08004000, 0x02000, 2}, /* flash sector 2 - 8kb */
|
||||
{ 0x08006000, 0x02000, 3}, /* flash sector 3 - 8kb */
|
||||
#if (BOOT_NVM_SIZE_KB > 32)
|
||||
{ 0x08008000, 0x02000, 4}, /* flash sector 4 - 8kb */
|
||||
{ 0x0800A000, 0x02000, 5}, /* flash sector 5 - 8kb */
|
||||
{ 0x0800C000, 0x02000, 6}, /* flash sector 6 - 8kb */
|
||||
{ 0x0800E000, 0x02000, 7}, /* flash sector 7 - 8kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB > 64)
|
||||
{ 0x08010000, 0x02000, 8}, /* flash sector 8 - 8kb */
|
||||
{ 0x08012000, 0x02000, 9}, /* flash sector 9 - 8kb */
|
||||
{ 0x08014000, 0x02000, 10}, /* flash sector 10 - 8kb */
|
||||
{ 0x08016000, 0x02000, 11}, /* flash sector 11 - 8kb */
|
||||
{ 0x08018000, 0x02000, 12}, /* flash sector 12 - 8kb */
|
||||
{ 0x0801A000, 0x02000, 13}, /* flash sector 13 - 8kb */
|
||||
{ 0x0801C000, 0x02000, 14}, /* flash sector 14 - 8kb */
|
||||
{ 0x0801E000, 0x02000, 15}, /* flash sector 15 - 8kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB > 128)
|
||||
{ 0x08020000, 0x08000, 16}, /* flash sector 16 - 32kb */
|
||||
{ 0x08028000, 0x08000, 17}, /* flash sector 17 - 32kb */
|
||||
{ 0x08030000, 0x08000, 18}, /* flash sector 18 - 32kb */
|
||||
{ 0x08038000, 0x08000, 19}, /* flash sector 19 - 32kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB > 256)
|
||||
{ 0x08040000, 0x08000, 20}, /* flash sector 20 - 32kb */
|
||||
{ 0x08048000, 0x08000, 21}, /* flash sector 21 - 32kb */
|
||||
{ 0x08050000, 0x08000, 22}, /* flash sector 22 - 32kb */
|
||||
{ 0x08058000, 0x08000, 23}, /* flash sector 23 - 32kb */
|
||||
{ 0x08060000, 0x08000, 24}, /* flash sector 24 - 32kb */
|
||||
{ 0x08068000, 0x08000, 25}, /* flash sector 25 - 32kb */
|
||||
{ 0x08070000, 0x08000, 26}, /* flash sector 26 - 32kb */
|
||||
{ 0x08078000, 0x08000, 27}, /* flash sector 27 - 32kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB > 512)
|
||||
#error "BOOT_NVM_SIZE_KB > 512 is currently not supported."
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/* The smallest amount of flash that can be programmed is FLASH_WRITE_BLOCK_SIZE. A flash
|
||||
* block manager is implemented in this driver and stores info in this variable. Whenever
|
||||
* new data should be flashed, it is first added to a RAM buffer, which is part of this
|
||||
* variable. Whenever the RAM buffer, which has the size of a flash block, is full or
|
||||
* data needs to be written to a different block, the contents of the RAM buffer are
|
||||
* programmed to flash. The flash block manager requires some software overhead, yet
|
||||
* results is faster flash programming because data is first harvested, ideally until
|
||||
* there is enough to program an entire flash block, before the flash device is actually
|
||||
* operated on.
|
||||
*/
|
||||
static tFlashBlockInfo blockInfo;
|
||||
|
||||
/* The first block of the user program holds the vector table, which on the STM32 is
|
||||
* also the where the checksum is written to. Is it likely that the vector table is
|
||||
* first flashed and then, at the end of the programming sequence, the checksum. This
|
||||
* means that this flash block need to be written to twice. Normally this is not a
|
||||
* problem with flash memory, as long as you write the same values to those bytes that
|
||||
* are not supposed to be changed and the locations where you do write to are still in
|
||||
* the erased 0xFF state. Unfortunately, writing twice to flash this way, does not work
|
||||
* reliably on all micros. This is why we need to have an extra block, the bootblock,
|
||||
* placed under the management of the block manager. This way is it possible to implement
|
||||
* functionality so that the bootblock is only written to once at the end of the
|
||||
* programming sequency.
|
||||
*/
|
||||
static tFlashBlockInfo bootBlockInfo;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the flash driver.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FlashInit(void)
|
||||
{
|
||||
/* init the flash block info structs by setting the address to an invalid address */
|
||||
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
|
||||
bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
|
||||
} /*** end of FlashInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashWrite
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** data pointer to the data buffer.
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Writes the data to flash through a flash block manager. Note that this
|
||||
** function also checks that no data is programmed outside the flash
|
||||
** memory region, so the bootloader can never be overwritten.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
blt_addr base_addr;
|
||||
|
||||
/* make sure the addresses are within the flash device */
|
||||
if ( (FlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
|
||||
(FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
|
||||
/* if this is the bootblock, then let the boot block manager handle it */
|
||||
base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
|
||||
if (base_addr == flashLayout[0].sector_start)
|
||||
{
|
||||
/* let the boot block manager handle it */
|
||||
return FlashAddToBlock(&bootBlockInfo, addr, data, len);
|
||||
}
|
||||
/* let the block manager handle it */
|
||||
return FlashAddToBlock(&blockInfo, addr, data, len);
|
||||
} /*** end of FlashWrite ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashErase
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Erases the flash memory. Note that this function also checks that no
|
||||
** data is erased outside the flash memory region, so the bootloader can
|
||||
** never be erased.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashErase(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
blt_int8u first_sector;
|
||||
blt_int8u last_sector;
|
||||
|
||||
/* obtain the first and last sector number */
|
||||
first_sector = FlashGetSector(addr);
|
||||
last_sector = FlashGetSector(addr+len-1);
|
||||
/* check them */
|
||||
if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* erase the sectors */
|
||||
return FlashEraseSectors(first_sector, last_sector);
|
||||
} /*** end of FlashErase ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashWriteChecksum
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
|
||||
** DESCRIPTION: Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if the programming session
|
||||
** was completed, which indicates that a valid user programming is
|
||||
** present and can be started.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashWriteChecksum(void)
|
||||
{
|
||||
blt_int32u signature_checksum = 0;
|
||||
|
||||
/* for the STM32 target we defined the checksum as the Two's complement value of the
|
||||
* sum of the first 7 exception addresses.
|
||||
*
|
||||
* Layout of the vector table:
|
||||
* 0x08000000 Initial stack pointer
|
||||
* 0x08000004 Reset Handler
|
||||
* 0x08000008 NMI Handler
|
||||
* 0x0800000C Hard Fault Handler
|
||||
* 0x08000010 MPU Fault Handler
|
||||
* 0x08000014 Bus Fault Handler
|
||||
* 0x08000018 Usage Fault Handler
|
||||
*
|
||||
* signature_checksum = Two's complement of (SUM(exception address values))
|
||||
*
|
||||
* the bootloader writes this 32-bit checksum value right after the vector table
|
||||
* of the user program. note that this means one extra dummy entry must be added
|
||||
* at the end of the user program's vector table to reserve storage space for the
|
||||
* checksum.
|
||||
*/
|
||||
|
||||
/* compute the checksum. note that the user program's vectors are not yet written
|
||||
* to flash but are present in the bootblock data structure at this point.
|
||||
*/
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x00]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x04]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x08]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x0C]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x10]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x14]));
|
||||
signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x18]));
|
||||
signature_checksum = ~signature_checksum; /* one's complement */
|
||||
signature_checksum += 1; /* two's complement */
|
||||
|
||||
/* check that this value of the checksum is not already present, which means
|
||||
* the program area with the vector table was not programmed, so the checksum
|
||||
* also doesn't need to be written. this check is important because it allows
|
||||
* for additional data to be programmed, such as calibration parameters, in
|
||||
* which case the checksum doesn't not need to be rewritten
|
||||
*/
|
||||
if (signature_checksum == FlashVerifyChecksum())
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* write the checksum */
|
||||
return FlashWrite(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET,
|
||||
sizeof(blt_addr), (blt_int8u*)&signature_checksum);
|
||||
} /*** end of FlashWriteChecksum ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashVerifyChecksum
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
|
||||
** DESCRIPTION: Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashVerifyChecksum(void)
|
||||
{
|
||||
blt_int32u signature_checksum = 0;
|
||||
|
||||
/* verify the checksum based on how it was written by CpuWriteChecksum() */
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x04));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x08));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x0C));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x10));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x14));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x18));
|
||||
signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET));
|
||||
/* sum should add up to an unsigned 32-bit value of 0 */
|
||||
if (signature_checksum == 0)
|
||||
{
|
||||
/* checksum okay */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* checksum incorrect */
|
||||
return BLT_FALSE;
|
||||
} /*** end of FlashVerifyChecksum ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashDone
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Finilizes the flash driver operations. There could still be data in
|
||||
** the currently active block that needs to be flashed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashDone(void)
|
||||
{
|
||||
/* check if there is still data waiting to be programmed in the boot block */
|
||||
if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* check if there is still data waiting to be programmed */
|
||||
if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
if (FlashWriteBlock(&blockInfo) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
/* still here so all is okay */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashDone ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashInitBlock
|
||||
** PARAMETER: block pointer to flash block info structure to operate on.
|
||||
** address base address of the block data.
|
||||
** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Copies data currently in flash to the block->data and sets the
|
||||
** base address.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address)
|
||||
{
|
||||
/* check address alignment */
|
||||
if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* make sure that we are initializing a new block and not the same one */
|
||||
if (block->base_addr == address)
|
||||
{
|
||||
/* block already initialized, so nothing to do */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* set the base address and copies the current data from flash */
|
||||
block->base_addr = address;
|
||||
CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashInitBlock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashSwitchBlock
|
||||
** PARAMETER: block pointer to flash block info structure to operate on.
|
||||
** base_addr base address for the next block
|
||||
** RETURN VALUE: the pointer of the block info struct that is no being used, or a NULL
|
||||
** pointer in case of error.
|
||||
** DESCRIPTION: Switches blocks by programming the current one and initializing the
|
||||
** next.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
|
||||
{
|
||||
/* check if a switch needs to be made away from the boot block. in this case the boot
|
||||
* block shouldn't be written yet, because this is done at the end of the programming
|
||||
* session by FlashDone(), this is right after the checksum was written.
|
||||
*/
|
||||
if (block == &bootBlockInfo)
|
||||
{
|
||||
/* switch from the boot block to the generic block info structure */
|
||||
block = &blockInfo;
|
||||
}
|
||||
/* check if a switch back into the bootblock is needed. in this case the generic block
|
||||
* doesn't need to be written here yet.
|
||||
*/
|
||||
else if (base_addr == flashLayout[0].sector_start)
|
||||
{
|
||||
/* switch from the generic block to the boot block info structure */
|
||||
block = &bootBlockInfo;
|
||||
base_addr = flashLayout[0].sector_start;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
if (FlashWriteBlock(block) == BLT_FALSE)
|
||||
{
|
||||
return BLT_NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* initialize tne new block when necessary */
|
||||
if (FlashInitBlock(block, base_addr) == BLT_FALSE)
|
||||
{
|
||||
return BLT_NULL;
|
||||
}
|
||||
|
||||
/* still here to all is okay */
|
||||
return block;
|
||||
} /*** end of FlashSwitchBlock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashAddToBlock
|
||||
** PARAMETER: block pointer to flash block info structure to operate on.
|
||||
** address flash destination address
|
||||
** data pointer to the byte array with data
|
||||
** len number of bytes to add to the block
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Programming is done per block. This function adds data to the block
|
||||
** that is currently collecting data to be written to flash. If the
|
||||
** address is outside of the current block, the current block is written
|
||||
** to flash an a new block is initialized.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
|
||||
blt_int8u *data, blt_int16u len)
|
||||
{
|
||||
blt_addr current_base_addr;
|
||||
blt_int8u *dst;
|
||||
blt_int8u *src;
|
||||
|
||||
/* determine the current base address */
|
||||
current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
|
||||
|
||||
/* make sure the blockInfo is not uninitialized */
|
||||
if (block->base_addr == FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
/* initialize the blockInfo struct for the current block */
|
||||
if (FlashInitBlock(block, current_base_addr) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* check if the new data fits in the current block */
|
||||
if (block->base_addr != current_base_addr)
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
block = FlashSwitchBlock(block, current_base_addr);
|
||||
if (block == BLT_NULL)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* add the data to the current block, but check for block overflow */
|
||||
dst = &(block->data[address - block->base_addr]);
|
||||
src = data;
|
||||
do
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
/* buffer overflow? */
|
||||
if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
|
||||
if (block == BLT_NULL)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* reset destination pointer */
|
||||
dst = &(block->data[0]);
|
||||
}
|
||||
/* write the data to the buffer */
|
||||
*dst = *src;
|
||||
/* update pointers */
|
||||
dst++;
|
||||
src++;
|
||||
/* decrement byte counter */
|
||||
len--;
|
||||
}
|
||||
while (len > 0);
|
||||
/* still here so all is good */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashAddToBlock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashWriteBlock
|
||||
** PARAMETER: block pointer to flash block info structure to operate on.
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data
|
||||
** array.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
|
||||
{
|
||||
blt_int8u sector_num;
|
||||
blt_bool result = BLT_TRUE;
|
||||
blt_addr prog_addr;
|
||||
blt_int32u prog_data;
|
||||
blt_int32u word_cnt;
|
||||
|
||||
/* check that address is actually within flash */
|
||||
sector_num = FlashGetSector(block->base_addr);
|
||||
if (sector_num == FLASH_INVALID_SECTOR)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* unlock the flash array */
|
||||
FlashUnlock();
|
||||
/* check that the flash peripheral is not busy */
|
||||
if ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||
{
|
||||
/* lock the flash array again */
|
||||
FlashLock();
|
||||
/* could not perform erase operation */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* set the program bit to indicate that we are about to program data */
|
||||
FLASH->CR |= FLASH_PG_BIT;
|
||||
/* program all words in the block one by one */
|
||||
for (word_cnt=0; word_cnt<(FLASH_WRITE_BLOCK_SIZE/sizeof(blt_int32u)); word_cnt++)
|
||||
{
|
||||
prog_addr = block->base_addr + (word_cnt * sizeof(blt_int32u));
|
||||
prog_data = *(volatile blt_int32u*)(&block->data[word_cnt * sizeof(blt_int32u)]);
|
||||
/* program the first half word */
|
||||
*(volatile blt_int16u*)prog_addr = (blt_int16u)prog_data;
|
||||
/* wait for the program operation to complete */
|
||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* program the second half word */
|
||||
*(volatile blt_int16u*)(prog_addr+2) = (blt_int16u)(prog_data >> 16);
|
||||
/* wait for the program operation to complete */
|
||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* verify that the written data is actually there */
|
||||
if (*(volatile blt_int32u*)prog_addr != prog_data)
|
||||
{
|
||||
result = BLT_FALSE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* reset the program bit to indicate that we are done programming data */
|
||||
FLASH->CR &= ~FLASH_PG_BIT;
|
||||
/* lock the flash array */
|
||||
FlashLock();
|
||||
/* still here so all is okay */
|
||||
return result;
|
||||
} /*** end of FlashWriteBlock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashEraseSectors
|
||||
** PARAMETER: first_sector first flash sector number
|
||||
** last_sector last flash sector number
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Erases the flash sectors from first_sector up until last_sector
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
|
||||
{
|
||||
blt_int16u nr_of_blocks;
|
||||
blt_int16u block_cnt;
|
||||
blt_addr start_addr;
|
||||
blt_addr end_addr;
|
||||
|
||||
/* validate the sector numbers */
|
||||
if (first_sector > last_sector)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
if ( (first_sector < flashLayout[0].sector_num) || \
|
||||
(last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num) )
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* unlock the flash array */
|
||||
FlashUnlock();
|
||||
/* check that the flash peripheral is not busy */
|
||||
if ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||
{
|
||||
/* lock the flash array again */
|
||||
FlashLock();
|
||||
/* could not perform erase operation */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* set the page erase bit to indicate that we are about to erase a block */
|
||||
FLASH->CR |= FLASH_PER_BIT;
|
||||
|
||||
/* determine how many blocks need to be erased */
|
||||
start_addr = FlashGetSectorBaseAddr(first_sector);
|
||||
end_addr = FlashGetSectorBaseAddr(last_sector) + FlashGetSectorSize(last_sector) - 1;
|
||||
nr_of_blocks = (end_addr - start_addr + 1) / FLASH_ERASE_BLOCK_SIZE;
|
||||
|
||||
/* erase all blocks one by one */
|
||||
for (block_cnt=0; block_cnt<nr_of_blocks; block_cnt++)
|
||||
{
|
||||
/* store an address of the block that is to be erased to select the block */
|
||||
FLASH->AR = start_addr + (block_cnt * FLASH_ERASE_BLOCK_SIZE);
|
||||
/* start the block erase operation */
|
||||
FLASH->CR |= FLASH_STRT_BIT;
|
||||
/* wait for the erase operation to complete */
|
||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
}
|
||||
/* reset the page erase bit because we're all done erasing */
|
||||
FLASH->CR &= ~FLASH_PER_BIT;
|
||||
/* lock the flash array */
|
||||
FlashLock();
|
||||
/* still here so all went okay */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashEraseSectors ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashUnlock
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Unlocks the flash array so that erase and program operations can be
|
||||
** performed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void FlashUnlock(void)
|
||||
{
|
||||
/* authorize the FPEC to access bank 1 */
|
||||
FLASH->KEYR = FLASH_KEY1;
|
||||
FLASH->KEYR = FLASH_KEY2;
|
||||
/* clear all possibly pending status flags */
|
||||
FLASH->SR = (FLASH_EOP_BIT | FLASH_PGERR_BIT | FLASH_WRPRTERR_BIT);
|
||||
} /*** end of FlashUnlock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashLock
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Locks the flash array so that erase and program operations can no
|
||||
** longer be performed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void FlashLock(void)
|
||||
{
|
||||
/* set the lock bit to lock the FPEC */
|
||||
FLASH->CR |= FLASH_LOCK_BIT;
|
||||
} /*** end of FlashLock ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashGetSector
|
||||
** PARAMETER: address address in the flash sector
|
||||
** RETURN VALUE: flash sector number or FLASH_INVALID_SECTOR
|
||||
** DESCRIPTION: Determines the flash sector the address is in.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_int8u FlashGetSector(blt_addr address)
|
||||
{
|
||||
blt_int8u sectorIdx;
|
||||
|
||||
/* search through the sectors to find the right one */
|
||||
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
/* is the address in this sector? */
|
||||
if ( (address >= flashLayout[sectorIdx].sector_start) && \
|
||||
(address < (flashLayout[sectorIdx].sector_start + \
|
||||
flashLayout[sectorIdx].sector_size)) )
|
||||
{
|
||||
/* return the sector number */
|
||||
return flashLayout[sectorIdx].sector_num;
|
||||
}
|
||||
}
|
||||
/* still here so no valid sector found */
|
||||
return FLASH_INVALID_SECTOR;
|
||||
} /*** end of FlashGetSector ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashGetSectorBaseAddr
|
||||
** PARAMETER: sector sector to get the base address of.
|
||||
** RETURN VALUE: flash sector base address or FLASH_INVALID_ADDRESS
|
||||
** DESCRIPTION: Determines the flash sector base address.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_addr FlashGetSectorBaseAddr(blt_int8u sector)
|
||||
{
|
||||
blt_int8u sectorIdx;
|
||||
|
||||
/* search through the sectors to find the right one */
|
||||
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
if (flashLayout[sectorIdx].sector_num == sector)
|
||||
{
|
||||
return flashLayout[sectorIdx].sector_start;
|
||||
}
|
||||
}
|
||||
/* still here so no valid sector found */
|
||||
return FLASH_INVALID_ADDRESS;
|
||||
} /*** end of FlashGetSectorBaseAddr ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: FlashGetSectorSize
|
||||
** PARAMETER: sector sector to get the size of.
|
||||
** RETURN VALUE: flash sector size or 0
|
||||
** DESCRIPTION: Determines the flash sector size.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_addr FlashGetSectorSize(blt_int8u sector)
|
||||
{
|
||||
blt_int8u sectorIdx;
|
||||
|
||||
/* search through the sectors to find the right one */
|
||||
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
if (flashLayout[sectorIdx].sector_num == sector)
|
||||
{
|
||||
return flashLayout[sectorIdx].sector_size;
|
||||
}
|
||||
}
|
||||
/* still here so no valid sector found */
|
||||
return 0;
|
||||
} /*** end of FlashGetSectorSize ***/
|
||||
|
||||
|
||||
/*********************************** end of flash.c ************************************/
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader flash driver header file
|
||||
| File Name: flash.h
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
#ifndef FLASH_H
|
||||
#define FLASH_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void FlashInit(void);
|
||||
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||
blt_bool FlashErase(blt_addr addr, blt_int32u len);
|
||||
blt_bool FlashWriteChecksum(void);
|
||||
blt_bool FlashVerifyChecksum(void);
|
||||
blt_bool FlashDone(void);
|
||||
|
||||
|
||||
#endif /* FLASH_H */
|
||||
/*********************************** end of flash.h ************************************/
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
/****************************************************************************************
|
||||
| Description: bootloader non-volatile memory driver source file
|
||||
| File Name: nvm.c
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| C O P Y R I G H T
|
||||
|----------------------------------------------------------------------------------------
|
||||
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
||||
|
|
||||
|----------------------------------------------------------------------------------------
|
||||
| L I C E N S E
|
||||
|----------------------------------------------------------------------------------------
|
||||
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
| modify it under the terms of the GNU General Public License as published by the Free
|
||||
| Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
| version.
|
||||
|
|
||||
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
| PURPOSE. See the GNU General Public License for more details.
|
||||
|
|
||||
| You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
| If not, see <http://www.gnu.org/licenses/>.
|
||||
|
|
||||
| A special exception to the GPL is included to allow you to distribute a combined work
|
||||
| that includes OpenBLT without being obliged to provide the source code for any
|
||||
| proprietary components. The exception text is included at the bottom of the license
|
||||
| file <license.html>.
|
||||
|
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Hook functions
|
||||
****************************************************************************************/
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
extern void NvmInitHook(void);
|
||||
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
|
||||
extern blt_bool NvmDoneHook(void);
|
||||
#endif
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmInit
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Initializes the NVM driver.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInit(void)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to initialize a driver for operating on NVM
|
||||
* that is not by default supported by this driver.
|
||||
*/
|
||||
NvmInitHook();
|
||||
#endif
|
||||
|
||||
/* init the internal driver */
|
||||
FlashInit();
|
||||
} /*** end of NvmInit ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmWrite
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** data pointer to the data buffer.
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Programs the non-volatile memory.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
blt_int8u result = BTL_NVM_NOT_IN_RANGE;
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to operate on memory that is not by default supported
|
||||
* by this driver.
|
||||
*/
|
||||
result = NvmWriteHook(addr, len, data);
|
||||
|
||||
/* process the return code */
|
||||
if (result == BTL_NVM_OKAY)
|
||||
{
|
||||
/* data was within range of the additionally supported memory and succesfully
|
||||
* programmed, so we are all done.
|
||||
*/
|
||||
return BLT_TRUE;
|
||||
}
|
||||
else if (result == BTL_NVM_ERROR)
|
||||
{
|
||||
/* data was within range of the additionally supported memory and attempted to be
|
||||
* programmed, but an error occurred, so we can't continue.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* still here to the internal driver should try and perform the program operation */
|
||||
return FlashWrite(addr, len, data);
|
||||
} /*** end of NvmWrite ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmErase
|
||||
** PARAMETER: addr start address
|
||||
** len length in bytes
|
||||
** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Erases the non-volatile memory.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmErase(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
blt_int8u result = BTL_NVM_NOT_IN_RANGE;
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to operate on memory that is not by default supported
|
||||
* by this driver.
|
||||
*/
|
||||
result = NvmEraseHook(addr, len);
|
||||
|
||||
/* process the return code */
|
||||
if (result == BTL_NVM_OKAY)
|
||||
{
|
||||
/* address was within range of the additionally supported memory and succesfully
|
||||
* erased, so we are all done.
|
||||
*/
|
||||
return BLT_TRUE;
|
||||
}
|
||||
else if (result == BTL_NVM_ERROR)
|
||||
{
|
||||
/* address was within range of the additionally supported memory and attempted to be
|
||||
* erased, but an error occurred, so we can't continue.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* still here to the internal driver should try and perform the erase operation */
|
||||
return FlashErase(addr, len);
|
||||
} /*** end of NvmErase ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmVerifyChecksum
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
|
||||
** DESCRIPTION: Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmVerifyChecksum(void)
|
||||
{
|
||||
/* check checksum */
|
||||
return FlashVerifyChecksum();
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: NvmDone
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||
** DESCRIPTION: Once all erase and programming operations are completed, this
|
||||
** function is called, so at the end of the programming session and
|
||||
** right before a software reset is performed. It is used to calculate
|
||||
** a checksum and program this into flash. This checksum is later used
|
||||
** to determine if a valid user program is present in flash.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDone(void)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application's NVM driver a chance to finish up */
|
||||
if (NvmDoneHook() == BLT_FALSE)
|
||||
{
|
||||
/* error so no need to continue */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
/* compute and write checksum, which is programmed by the internal driver */
|
||||
if (FlashWriteChecksum() == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* finish up internal driver operations */
|
||||
return FlashDone();
|
||||
} /*** end of NvmDone ***/
|
||||
|
||||
|
||||
/*********************************** end of nvm.c **************************************/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue