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Refs #871. Deprecated the LPC2000 and Tricore TC1798 ports. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@710 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2019-08-06 15:44:12 +00:00
parent b3b43fed6f
commit acf99e9c2c
56 changed files with 0 additions and 10024 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openblt_olimex_lpc_l2294_20mhz.elf
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Binary file not shown.

439
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openblt_olimex_lpc_l2294_20mhz.map
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@ -1,439 +0,0 @@
bin/openblt_olimex_lpc_l2294_20mhz.elf: file format elf32-littlearm
bin/openblt_olimex_lpc_l2294_20mhz.elf
architecture: armv4t, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00000000
Program Header:
LOAD off 0x00010000 vaddr 0x00000000 paddr 0x00000000 align 2**16
filesz 0x00001dbc memsz 0x00001dbc flags r-x
LOAD off 0x00020200 vaddr 0x40000200 paddr 0x00001dbc align 2**16
filesz 0x00000001 memsz 0x00000001 flags rw-
LOAD off 0x00020204 vaddr 0x40000204 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x0000004c flags rw-
LOAD off 0x00020250 vaddr 0x40000250 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000040 flags rw-
LOAD off 0x00020290 vaddr 0x40000290 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x00020294 vaddr 0x40000294 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
LOAD off 0x00020298 vaddr 0x40000298 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000041 flags rw-
LOAD off 0x000202d9 vaddr 0x400002d9 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x000202da vaddr 0x400002da paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x000202dc vaddr 0x400002dc paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
LOAD off 0x000202e0 vaddr 0x400002e0 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000204 flags rw-
LOAD off 0x000204e4 vaddr 0x400004e4 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000204 flags rw-
LOAD off 0x000206e8 vaddr 0x400006e8 paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
LOAD off 0x000206ec vaddr 0x400006ec paddr 0x00001dbd align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
private flags = 5000200: [Version5 EABI] [soft-float ABI]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000368 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .init 0000000c 00000368 00000368 00010368 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .fini 0000000c 00000374 00000374 00010374 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .text.FIQ_ISR 00000028 00000380 00000380 00010380 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
4 .text.IRQ_ISR 00000028 000003a8 000003a8 000103a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
5 .text.UNDEF_ISR 00000024 000003d0 000003d0 000103d0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
6 .text.main 000000c4 000003f4 000003f4 000103f4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
7 .text.XcpSetCtoError 00000020 000004b8 000004b8 000104b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
8 .text.XcpInit 00000028 000004d8 000004d8 000104d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
9 .text.XcpIsConnected 00000018 00000500 00000500 00010500 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
10 .text.XcpPacketTransmitted 00000014 00000518 00000518 00010518 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
11 .text.XcpPacketReceived 00000678 0000052c 0000052c 0001052c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
12 .text.ComInit 00000054 00000ba4 00000ba4 00010ba4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
13 .text.ComTask 00000088 00000bf8 00000bf8 00010bf8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
14 .text.ComFree 00000004 00000c80 00000c80 00010c80 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
15 .text.ComTransmitPacket 0000006c 00000c84 00000c84 00010c84 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
16 .text.ComGetActiveInterfaceMaxRxLen 0000003c 00000cf0 00000cf0 00010cf0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
17 .text.ComGetActiveInterfaceMaxTxLen 0000003c 00000d2c 00000d2c 00010d2c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
18 .text.ComIsConnected 0000001c 00000d68 00000d68 00010d68 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
19 .text.BackDoorCheck 0000007c 00000d84 00000d84 00010d84 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
20 .text.BackDoorInit 00000048 00000e00 00000e00 00010e00 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
21 .text.BootInit 0000006c 00000e48 00000e48 00010e48 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
22 .text.BootTask 0000004c 00000eb4 00000eb4 00010eb4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
23 .text.CopInit 00000004 00000f00 00000f00 00010f00 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
24 .text.CopService 00000004 00000f04 00000f04 00010f04 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
25 .text.AssertFailure 00000018 00000f08 00000f08 00010f08 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
26 .text.UartTransmitByte 0000006c 00000f20 00000f20 00010f20 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
27 .text.UartInit 00000040 00000f8c 00000f8c 00010f8c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
28 .text.UartTransmitPacket 000000c0 00000fcc 00000fcc 00010fcc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
29 .text.UartReceivePacket 00000134 0000108c 0000108c 0001108c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
30 .text.NvmInit 0000001c 000011c0 000011c0 000111c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
31 .text.NvmWrite 0000001c 000011dc 000011dc 000111dc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
32 .text.NvmErase 0000001c 000011f8 000011f8 000111f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
33 .text.NvmVerifyChecksum 0000001c 00001214 00001214 00011214 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
34 .text.NvmGetUserProgBaseAddress 0000001c 00001230 00001230 00011230 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
35 .text.NvmDone 00000030 0000124c 0000124c 0001124c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
36 .text.CpuInit 0000001c 0000127c 0000127c 0001127c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
37 .text.CpuMemCopy 0000004c 00001298 00001298 00011298 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
38 .text.CpuStartUserProgram 0000008c 000012e4 000012e4 000112e4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
39 .text.FlashGetSector 00000070 00001370 00001370 00011370 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
40 .text.FlashWriteBlock 00000148 000013e0 000013e0 000113e0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
41 .text.FlashSwitchBlock 000000a0 00001528 00001528 00011528 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
42 .text.FlashAddToBlock 00000108 000015c8 000015c8 000115c8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
43 .text.FlashInit 00000020 000016d0 000016d0 000116d0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
44 .text.FlashWrite 0000008c 000016f0 000016f0 000116f0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
45 .text.FlashErase 0000016c 0000177c 0000177c 0001177c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
46 .text.FlashWriteChecksum 00000090 000018e8 000018e8 000118e8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
47 .text.FlashVerifyChecksum 00000048 00001978 00001978 00011978 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
48 .text.FlashDone 00000070 000019c0 000019c0 000119c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
49 .text.FlashGetUserProgBaseAddress 00000008 00001a30 00001a30 00011a30 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
50 .text.CanInit 00000120 00001a38 00001a38 00011a38 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
51 .text.CanTransmitPacket 000000d4 00001b58 00001b58 00011b58 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
52 .text.CanReceivePacket 000000b8 00001c2c 00001c2c 00011c2c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
53 .text.TimerInit 00000048 00001ce4 00001ce4 00011ce4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
54 .text.TimerReset 00000020 00001d2c 00001d2c 00011d2c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
55 .text.TimerUpdate 00000038 00001d4c 00001d4c 00011d4c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
56 .text.TimerGet 00000028 00001d84 00001d84 00011d84 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
57 .text.CpuIrqDisable 00000010 00001dac 00001dac 00011dac 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
58 .data.comActiveInterface 00000001 40000200 00001dbc 00020200 2**0
CONTENTS, ALLOC, LOAD, DATA
59 .bss.xcpInfo 0000004c 40000204 00001dbd 00020204 2**2
ALLOC
60 .bss.xcpCtoReqPacket.4275 00000040 40000250 00001dbd 00020250 2**2
ALLOC
61 .bss.backdoorOpen 00000001 40000290 00001dbd 00020290 2**0
ALLOC
62 .bss.backdoorOpenTime 00000004 40000294 00001dbd 00020294 2**2
ALLOC
63 .bss.xcpCtoReqPacket.4280 00000041 40000298 00001dbd 00020298 2**2
ALLOC
64 .bss.xcpCtoRxLength.4281 00000001 400002d9 00001dbd 000202d9 2**0
ALLOC
65 .bss.xcpCtoRxInProgress.4282 00000001 400002da 00001dbd 000202da 2**0
ALLOC
66 .bss.xcpCtoRxStartTime.4283 00000004 400002dc 00001dbd 000202dc 2**2
ALLOC
67 .bss.bootBlockInfo 00000204 400002e0 00001dbd 000202e0 2**2
ALLOC
68 .bss.blockInfo 00000204 400004e4 00001dbd 000204e4 2**2
ALLOC
69 .bss.millisecond_counter 00000004 400006e8 00001dbd 000206e8 2**2
ALLOC
70 .bss.free_running_counter_last 00000004 400006ec 00001dbd 000206ec 2**2
ALLOC
71 .ARM.attributes 0000002c 00000000 00000000 00020201 2**0
CONTENTS, READONLY
72 .comment 0000006e 00000000 00000000 0002022d 2**0
CONTENTS, READONLY
73 .debug_line 00001519 00000000 00000000 0002029b 2**0
CONTENTS, READONLY, DEBUGGING
74 .debug_info 00002154 00000000 00000000 000217b4 2**0
CONTENTS, READONLY, DEBUGGING
75 .debug_abbrev 00000edf 00000000 00000000 00023908 2**0
CONTENTS, READONLY, DEBUGGING
76 .debug_aranges 00000358 00000000 00000000 000247e8 2**3
CONTENTS, READONLY, DEBUGGING
77 .debug_ranges 00000298 00000000 00000000 00024b40 2**0
CONTENTS, READONLY, DEBUGGING
78 .debug_macro 00001d76 00000000 00000000 00024dd8 2**0
CONTENTS, READONLY, DEBUGGING
79 .debug_str 0000814b 00000000 00000000 00026b4e 2**0
CONTENTS, READONLY, DEBUGGING
80 .debug_frame 00000754 00000000 00000000 0002ec9c 2**2
CONTENTS, READONLY, DEBUGGING
81 .debug_loc 00000f54 00000000 00000000 0002f3f0 2**0
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000 l d .text 00000000 .text
00000368 l d .init 00000000 .init
00000374 l d .fini 00000000 .fini
00000380 l d .text.FIQ_ISR 00000000 .text.FIQ_ISR
000003a8 l d .text.IRQ_ISR 00000000 .text.IRQ_ISR
000003d0 l d .text.UNDEF_ISR 00000000 .text.UNDEF_ISR
000003f4 l d .text.main 00000000 .text.main
000004b8 l d .text.XcpSetCtoError 00000000 .text.XcpSetCtoError
000004d8 l d .text.XcpInit 00000000 .text.XcpInit
00000500 l d .text.XcpIsConnected 00000000 .text.XcpIsConnected
00000518 l d .text.XcpPacketTransmitted 00000000 .text.XcpPacketTransmitted
0000052c l d .text.XcpPacketReceived 00000000 .text.XcpPacketReceived
00000ba4 l d .text.ComInit 00000000 .text.ComInit
00000bf8 l d .text.ComTask 00000000 .text.ComTask
00000c80 l d .text.ComFree 00000000 .text.ComFree
00000c84 l d .text.ComTransmitPacket 00000000 .text.ComTransmitPacket
00000cf0 l d .text.ComGetActiveInterfaceMaxRxLen 00000000 .text.ComGetActiveInterfaceMaxRxLen
00000d2c l d .text.ComGetActiveInterfaceMaxTxLen 00000000 .text.ComGetActiveInterfaceMaxTxLen
00000d68 l d .text.ComIsConnected 00000000 .text.ComIsConnected
00000d84 l d .text.BackDoorCheck 00000000 .text.BackDoorCheck
00000e00 l d .text.BackDoorInit 00000000 .text.BackDoorInit
00000e48 l d .text.BootInit 00000000 .text.BootInit
00000eb4 l d .text.BootTask 00000000 .text.BootTask
00000f00 l d .text.CopInit 00000000 .text.CopInit
00000f04 l d .text.CopService 00000000 .text.CopService
00000f08 l d .text.AssertFailure 00000000 .text.AssertFailure
00000f20 l d .text.UartTransmitByte 00000000 .text.UartTransmitByte
00000f8c l d .text.UartInit 00000000 .text.UartInit
00000fcc l d .text.UartTransmitPacket 00000000 .text.UartTransmitPacket
0000108c l d .text.UartReceivePacket 00000000 .text.UartReceivePacket
000011c0 l d .text.NvmInit 00000000 .text.NvmInit
000011dc l d .text.NvmWrite 00000000 .text.NvmWrite
000011f8 l d .text.NvmErase 00000000 .text.NvmErase
00001214 l d .text.NvmVerifyChecksum 00000000 .text.NvmVerifyChecksum
00001230 l d .text.NvmGetUserProgBaseAddress 00000000 .text.NvmGetUserProgBaseAddress
0000124c l d .text.NvmDone 00000000 .text.NvmDone
0000127c l d .text.CpuInit 00000000 .text.CpuInit
00001298 l d .text.CpuMemCopy 00000000 .text.CpuMemCopy
000012e4 l d .text.CpuStartUserProgram 00000000 .text.CpuStartUserProgram
00001370 l d .text.FlashGetSector 00000000 .text.FlashGetSector
000013e0 l d .text.FlashWriteBlock 00000000 .text.FlashWriteBlock
00001528 l d .text.FlashSwitchBlock 00000000 .text.FlashSwitchBlock
000015c8 l d .text.FlashAddToBlock 00000000 .text.FlashAddToBlock
000016d0 l d .text.FlashInit 00000000 .text.FlashInit
000016f0 l d .text.FlashWrite 00000000 .text.FlashWrite
0000177c l d .text.FlashErase 00000000 .text.FlashErase
000018e8 l d .text.FlashWriteChecksum 00000000 .text.FlashWriteChecksum
00001978 l d .text.FlashVerifyChecksum 00000000 .text.FlashVerifyChecksum
000019c0 l d .text.FlashDone 00000000 .text.FlashDone
00001a30 l d .text.FlashGetUserProgBaseAddress 00000000 .text.FlashGetUserProgBaseAddress
00001a38 l d .text.CanInit 00000000 .text.CanInit
00001b58 l d .text.CanTransmitPacket 00000000 .text.CanTransmitPacket
00001c2c l d .text.CanReceivePacket 00000000 .text.CanReceivePacket
00001ce4 l d .text.TimerInit 00000000 .text.TimerInit
00001d2c l d .text.TimerReset 00000000 .text.TimerReset
00001d4c l d .text.TimerUpdate 00000000 .text.TimerUpdate
00001d84 l d .text.TimerGet 00000000 .text.TimerGet
00001dac l d .text.CpuIrqDisable 00000000 .text.CpuIrqDisable
40000200 l d .data.comActiveInterface 00000000 .data.comActiveInterface
40000204 l d .bss.xcpInfo 00000000 .bss.xcpInfo
40000250 l d .bss.xcpCtoReqPacket.4275 00000000 .bss.xcpCtoReqPacket.4275
40000290 l d .bss.backdoorOpen 00000000 .bss.backdoorOpen
40000294 l d .bss.backdoorOpenTime 00000000 .bss.backdoorOpenTime
40000298 l d .bss.xcpCtoReqPacket.4280 00000000 .bss.xcpCtoReqPacket.4280
400002d9 l d .bss.xcpCtoRxLength.4281 00000000 .bss.xcpCtoRxLength.4281
400002da l d .bss.xcpCtoRxInProgress.4282 00000000 .bss.xcpCtoRxInProgress.4282
400002dc l d .bss.xcpCtoRxStartTime.4283 00000000 .bss.xcpCtoRxStartTime.4283
400002e0 l d .bss.bootBlockInfo 00000000 .bss.bootBlockInfo
400004e4 l d .bss.blockInfo 00000000 .bss.blockInfo
400006e8 l d .bss.millisecond_counter 00000000 .bss.millisecond_counter
400006ec l d .bss.free_running_counter_last 00000000 .bss.free_running_counter_last
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .comment 00000000 .comment
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_macro 00000000 .debug_macro
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l df *ABS* 00000000 obj/cstart.o
00000004 l *ABS* 00000000 UND_STACK_SIZE
00000004 l *ABS* 00000000 ABT_STACK_SIZE
00000004 l *ABS* 00000000 FIQ_STACK_SIZE
00000004 l *ABS* 00000000 IRQ_STACK_SIZE
00000004 l *ABS* 00000000 SVC_STACK_SIZE
00000010 l *ABS* 00000000 MODE_USR
00000011 l *ABS* 00000000 MODE_FIQ
00000012 l *ABS* 00000000 MODE_IRQ
00000013 l *ABS* 00000000 MODE_SVC
00000017 l *ABS* 00000000 MODE_ABT
0000001b l *ABS* 00000000 MODE_UND
0000001f l *ABS* 00000000 MODE_SYS
00000080 l *ABS* 00000000 I_BIT
00000040 l *ABS* 00000000 F_BIT
e01fc040 l *ABS* 00000000 MEMMAP
00000000 l .text 00000000 _vectors
00000020 l .text 00000000 Reset_Addr
00000024 l .text 00000000 Undef_Addr
00000028 l .text 00000000 PAbt_Addr
0000002c l .text 00000000 DAbt_Addr
00000034 l .text 00000000 IRQ_Addr
00000030 l .text 00000000 FIQ_Addr
00000000 l df *ABS* 00000000 _divsi3.o
000000e4 l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
00000000 l df *ABS* 00000000 vectors.c
00000000 l df *ABS* 00000000 xcp.c
000004b8 l F .text.XcpSetCtoError 00000020 XcpSetCtoError
00000234 l O .text 00000008 xcpStationId
40000204 l O .bss.xcpInfo 0000004c xcpInfo
00000000 l df *ABS* 00000000 uart.c
00000f20 l F .text.UartTransmitByte 0000006c UartTransmitByte
40000298 l O .bss.xcpCtoReqPacket.4280 00000041 xcpCtoReqPacket.4280
400002d9 l O .bss.xcpCtoRxLength.4281 00000001 xcpCtoRxLength.4281
400002da l O .bss.xcpCtoRxInProgress.4282 00000001 xcpCtoRxInProgress.4282
400002dc l O .bss.xcpCtoRxStartTime.4283 00000004 xcpCtoRxStartTime.4283
00000000 l df *ABS* 00000000 flash.c
00001370 l F .text.FlashGetSector 00000070 FlashGetSector
000013e0 l F .text.FlashWriteBlock 00000148 FlashWriteBlock
00001528 l F .text.FlashSwitchBlock 000000a0 FlashSwitchBlock
000015c8 l F .text.FlashAddToBlock 00000108 FlashAddToBlock
00000260 l O .text 000000c0 flashLayout
400002e0 l O .bss.bootBlockInfo 00000204 bootBlockInfo
400004e4 l O .bss.blockInfo 00000204 blockInfo
00000000 l df *ABS* 00000000 can.c
00000344 l O .text 00000024 canTiming
00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/crti.o
00000000 l df *ABS* 00000000 main.c
00000000 l df *ABS* 00000000 com.c
40000250 l O .bss.xcpCtoReqPacket.4275 00000040 xcpCtoReqPacket.4275
40000200 l O .data.comActiveInterface 00000001 comActiveInterface
00000000 l df *ABS* 00000000 backdoor.c
40000290 l O .bss.backdoorOpen 00000001 backdoorOpen
40000294 l O .bss.backdoorOpenTime 00000004 backdoorOpenTime
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 cop.c
00000000 l df *ABS* 00000000 assert.c
00000000 l df *ABS* 00000000 nvm.c
00000000 l df *ABS* 00000000 cpu.c
00000000 l df *ABS* 00000000 timer.c
400006e8 l O .bss.millisecond_counter 00000004 millisecond_counter
400006ec l O .bss.free_running_counter_last 00000004 free_running_counter_last
00000000 l df *ABS* 00000000 cpu_comp.c
00000000 l df *ABS* 00000000
00000000 l *UND* 00000000 __bss_start__
00000000 l *UND* 00000000 __libc_fini_array
00000000 l *UND* 00000000 __sf_fake_stderr
00000000 l *UND* 00000000 __deregister_frame_info
00000000 l *UND* 00000000 __bss_end__
00000000 l *UND* 00000000 __call_exitprocs
00000000 l *UND* 00000000 software_init_hook
00000000 l *UND* 00000000 __sf_fake_stdin
00000000 l *UND* 00000000 __init_array_end
00000000 l *UND* 00000000 hardware_init_hook
00000000 l *UND* 00000000 atexit
00000000 l *UND* 00000000 __preinit_array_end
00000000 l *UND* 00000000 __stack
00000000 l *UND* 00000000 __sf_fake_stdout
00000000 l *UND* 00000000 __init_array_start
00000000 l *UND* 00000000 _exit
00000000 l *UND* 00000000 _Jv_RegisterClasses
00000000 l *UND* 00000000 __preinit_array_start
00000000 l *UND* 00000000 __register_frame_info
00000ba4 g F .text.ComInit 00000054 ComInit
000016f0 g F .text.FlashWrite 0000008c FlashWrite
00000f08 g F .text.AssertFailure 00000018 AssertFailure
00001c2c g F .text.CanReceivePacket 000000b8 CanReceivePacket
000003a8 g F .text.IRQ_ISR 00000028 IRQ_ISR
00001d4c g F .text.TimerUpdate 00000038 TimerUpdate
00000518 g F .text.XcpPacketTransmitted 00000014 XcpPacketTransmitted
00000bf8 g F .text.ComTask 00000088 ComTask
00000e48 g F .text.BootInit 0000006c BootInit
00000e00 g F .text.BackDoorInit 00000048 BackDoorInit
00000f04 g F .text.CopService 00000004 CopService
00000368 g .text 00000000 _etext
00001dac g F .text.CpuIrqDisable 00000010 CpuIrqDisable
00001a30 g F .text.FlashGetUserProgBaseAddress 00000008 FlashGetUserProgBaseAddress
00001d2c g F .text.TimerReset 00000020 TimerReset
00000eb4 g F .text.BootTask 0000004c BootTask
000018e8 g F .text.FlashWriteChecksum 00000090 FlashWriteChecksum
40000201 g .data.comActiveInterface 00000000 _bss_start
00000c84 g F .text.ComTransmitPacket 0000006c ComTransmitPacket
00000000 g .text 00000000 _startup
00000500 g F .text.XcpIsConnected 00000018 XcpIsConnected
00000368 g F .init 00000000 _init
000011c0 g F .text.NvmInit 0000001c NvmInit
000016d0 g F .text.FlashInit 00000020 FlashInit
00001230 g F .text.NvmGetUserProgBaseAddress 0000001c NvmGetUserProgBaseAddress
40000204 g .data.comActiveInterface 00000000 _bss_end
0000003c g .text 00000000 Reset_Handler
00000c80 g F .text.ComFree 00000004 ComFree
000000dc g F .text 00000000 .hidden __aeabi_idiv
00000f8c g F .text.UartInit 00000040 UartInit
000011f8 g F .text.NvmErase 0000001c NvmErase
0000052c g F .text.XcpPacketReceived 00000678 XcpPacketReceived
0000127c g F .text.CpuInit 0000001c CpuInit
000019c0 g F .text.FlashDone 00000070 FlashDone
00001b58 g F .text.CanTransmitPacket 000000d4 CanTransmitPacket
00000224 w F .text 00000004 .hidden __aeabi_ldiv0
000004d8 g F .text.XcpInit 00000028 XcpInit
0000177c g F .text.FlashErase 0000016c FlashErase
000003f4 g F .text.main 000000c4 main
0000124c g F .text.NvmDone 00000030 NvmDone
00000fcc g F .text.UartTransmitPacket 000000c0 UartTransmitPacket
00001214 g F .text.NvmVerifyChecksum 0000001c NvmVerifyChecksum
00001298 g F .text.CpuMemCopy 0000004c CpuMemCopy
40001edc g *ABS* 00000000 _stack_end
000000dc g F .text 00000128 .hidden __divsi3
00000380 g F .text.FIQ_ISR 00000028 FIQ_ISR
00000374 g F .fini 00000000 _fini
00000d2c g F .text.ComGetActiveInterfaceMaxTxLen 0000003c ComGetActiveInterfaceMaxTxLen
0000108c g F .text.UartReceivePacket 00000134 UartReceivePacket
40000200 g .data.comActiveInterface 00000000 _data
00000f00 g F .text.CopInit 00000004 CopInit
0000008c g .text 00000000 SetupRAM
00001a38 g F .text.CanInit 00000120 CanInit
000011dc g F .text.NvmWrite 0000001c NvmWrite
000012e4 g F .text.CpuStartUserProgram 0000008c CpuStartUserProgram
00001978 g F .text.FlashVerifyChecksum 00000048 FlashVerifyChecksum
40000200 g .data.comActiveInterface 00000000 _edata
40000204 g .data.comActiveInterface 00000000 _end
000003d0 g F .text.UNDEF_ISR 00000024 UNDEF_ISR
00000d68 g F .text.ComIsConnected 0000001c ComIsConnected
00000224 w F .text 00000004 .hidden __aeabi_idiv0
00000cf0 g F .text.ComGetActiveInterfaceMaxRxLen 0000003c ComGetActiveInterfaceMaxRxLen
00000d84 g F .text.BackDoorCheck 0000007c BackDoorCheck
00001d84 g F .text.TimerGet 00000028 TimerGet
00000204 g F .text 00000020 .hidden __aeabi_idivmod
00001ce4 g F .text.TimerInit 00000048 TimerInit

499
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openblt_olimex_lpc_l2294_20mhz.srec
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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_UART_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_UART_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_UART_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_UART_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_UART_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (256)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (0)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

7
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/boot.dox
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@ -1,7 +0,0 @@
/**
\defgroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC Bootloader
\brief Bootloader.
\ingroup ARM7_LPC2000_Olimex_LPC_L2294_GCC
*/

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/************************************************************************************//**
* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_GCC\Boot\cstart.s
* \brief Bootloader C-startup assembly file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* stack Sizes */
.set UND_STACK_SIZE, 0x00000004 /* stack for "undef" interrupts is 4 bytes */
.set ABT_STACK_SIZE, 0x00000004 /* stack for "abort" interrupts is 4 bytes */
.set FIQ_STACK_SIZE, 0x00000004 /* stack for "FIQ" interrupts is 4 bytes */
.set IRQ_STACK_SIZE, 0X00000004 /* stack for "IRQ" normal interrupts is 4 bytes */
.set SVC_STACK_SIZE, 0x00000004 /* stack for "SVC" supervisor mode is 4 bytes */
/* mode bits and Interrupt (I & F) flags in program status registers (PSRs) */
.set MODE_USR, 0x10 /* Normal User Mode */
.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
.set MODE_SYS, 0x1F /* System Running Priviledged OS Tasks Mode */
.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
/* microcontroller registers */
.set MEMMAP, 0xE01FC040 /* MEMMAP register */
.text
.arm
.global Reset_Handler
.global SetupRAM
.global _startup
.func _startup
_startup:
/****************************************************************************************
* Interrupt vector table
****************************************************************************************/
_vectors: ldr PC, Reset_Addr /* point to Reset_Handler address */
ldr PC, Undef_Addr /* point to UNDEF_ISR address */
ldr PC, Undef_Addr /* point to SWI_ISR address */
ldr PC, PAbt_Addr /* point to UNDEF_ISR address */
ldr PC, DAbt_Addr /* point to UNDEF_ISR address */
nop /* reserved for Philips ISP checksum */
ldr PC, IRQ_Addr /* point to IRQ_ISR address */
ldr PC, FIQ_Addr /* point to FIQ_ISR address */
Reset_Addr: .word Reset_Handler /* defined in this module below */
Undef_Addr: .word UNDEF_ISR /* defined in vectors.c */
PAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
DAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
FIQ_Addr: .word FIQ_ISR /* defined in vectors.c */
IRQ_Addr: .word IRQ_ISR /* defined in vectors.c */
.word 0 /* rounds vectors and ISR addresses to */
/* 64 bytes */
/************************************************************************************//**
** \brief Reset interrupt service routine. Configures the stack for each mode,
** disables the IRQ and FIQ interrupts, initializes RAM and jumps to
** function main.
** \return none.
**
****************************************************************************************/
Reset_Handler:
/* setup a stack and disable interrupts for each mode */
ldr r0, =_stack_end
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
mov sp, r0
/* copy .data section from ROM to RAM and zero out .bss section */
bl SetupRAM
/* start bootloader program by jumping to main() */
b main
/*** end of Reset_Handler ***/
/************************************************************************************//**
** \brief Initializes RAM by copying .data section from ROM to RAM and zero-ing
** out .bss section.
** \return none.
**
****************************************************************************************/
SetupRAM:
/* copy .data section (Copy from ROM to RAM) */
ldr R1, =_etext
ldr R2, =_data
ldr R3, =_edata
1: cmp R2, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo 1b
/* clear .bss section (Zero init) */
mov R0, #0
ldr R1, =_bss_start
ldr R2, =_bss_end
2: cmp R1, R2
strlo R0, [R1], #4
blo 2b
/* return */
bx lr
/*** end of SetupRAM ***/
.endfunc
.end
/*********************************** end of cstart.s ***********************************/

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@ -1,653 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/extflash.c
* \brief Bootloader external flash driver source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Value for an invalid flash sector. */
#define FLASH_INVALID_SECTOR (0xff)
/** \brief Value for an invalid flash address. */
#define FLASH_INVALID_ADDRESS (0xffffffff)
/** \brief Standard size of a flash block for writing. */
#define FLASH_WRITE_BLOCK_SIZE (512)
/** \brief Total numbers of sectors in array flashLayout[]. */
#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
/** \brief C3 Intel flash read array command. */
#define FLASH_CMD_READ_ARRAY_MODE (0xFF)
/** \brief C3 Intel flash read id command. */
#define FLASH_CMD_READ_ID_MODE (0x90)
/** \brief C3 Intel flash erase command. */
#define FLASH_CMD_ERASE_MODE (0x20)
/** \brief C3 Intel flash read status command. */
#define FLASH_CMD_READ_STATUS_MODE (0x70)
/** \brief C3 Intel flash change lock command. */
#define FLASH_CMD_CHANGE_LOCK_MODE (0x60)
/** \brief C3 Intel flash unlock sector command. */
#define FLASH_CMD_UNLOCK_SECTOR (0xD0)
/** \brief C3 Intel flash lock sector command. */
#define FLASH_CMD_LOCK_SECTOR (0x01)
/** \brief C3 Intel flash program command. */
#define FLASH_CMD_PROGRAM_MODE (0x40)
/** \brief C3 Intel flash erase confirm command. */
#define FLASH_CMD_ERASE_CONFIRM (0xD0)
/** \brief C3 Intel flash clear status command. */
#define FLASH_CMD_CLEAR_STATUS (0x50)
/** \brief C3 Intel flash lock bit. */
#define FLASH_LOCK_BIT (0x01)
/** \brief C3 Intel flash status ready bit. */
#define FLASH_STATUS_READY_BIT (0x80)
/** \brief C3 Intel flash locked error code. */
#define FLASH_ERR_LOCKED (0x02)
/** \brief C3 Intel flash Vpp range error code. */
#define FLASH_ERR_VPP_RANGE (0x08)
/** \brief C3 Intel flash program error code. */
#define FLASH_ERR_PROGRAM (0x10)
/** \brief C3 Intel flash command sequence error code. */
#define FLASH_ERR_CMD_SEQ (0x10)
/** \brief C3 Intel flash erase error code. */
#define FLASH_ERR_ERASE (0x20)
/** \brief Flash erase timeout value. */
#define FLASH_ERASE_TIMEOUT ((blt_int32u)5000000)
/** \brief Flash program timeout value. */
#define FLASH_PROGRAM_TIMEOUT ((blt_int32u)1000000)
/** \brief Supported Intel C3 flash manufacturer ID. */
#define FLASH_DEV_MAN_ID ((blt_int16u)0x0089)
/** \brief Supported Intel C3 flash device ID. */
#define FLASH_DEV_ID ((blt_int16u)0x88c3)
/** \brief Offset for reading manufacturer ID. */
#define FLASH_DEVINFO_MAN_ID ((blt_int16u)0x0000)
/** \brief Offset for reading device ID. */
#define FLASH_DEVINFO_DEV_ID ((blt_int16u)0x0001)
/** \brief Offset for reading lock status. */
#define FLASH_DEVINFO_LOCK_STATUS ((blt_int16u)0x0002)
/** \brief Runtime efficient macro for obtaining the manufacturer ID. */
#define ExtFlashGetManID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
FLASH_DEVINFO_MAN_ID))
/** \brief Runtime efficient macro for obtaining the device ID. */
#define ExtFlashGetDevID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
FLASH_DEVINFO_DEV_ID))
/** \brief Runtime efficient macro for obtaining the lock status. */
#define ExtFlashGetLockStatus(base) (ExtFlashGetDeviceInfo(base, \
FLASH_DEVINFO_LOCK_STATUS))
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Flash sector descriptor type. */
typedef struct
{
blt_addr sector_start; /**< sector start address */
blt_int32u sector_size; /**< sector size in bytes */
blt_int8u sector_num; /**< sector number */
} tFlashSector;
/** \brief Structure type for grouping flash block information.
* \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a
* flash block manager is implemented in this driver. this flash block manager
* depends on this flash block info structure. It holds the base address of
* the flash block and the data that should be programmed into the flash
* block.
*/
typedef struct
{
blt_addr base_addr; /**< Base address for the flash operation.*/
blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; /**< Data array. */
} tFlashBlockInfo;
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address);
static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len);
static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block);
static blt_bool ExtFlashEraseSector(blt_addr sector_base);
static blt_int16u ExtFlashGetDeviceInfo(blt_addr block_base, blt_int16u info);
static void ExtFlashLockSector(blt_addr sector_base);
static void ExtFlashUnlockSector(blt_addr sector_base);
static blt_int8u ExtFlashGetSector(blt_addr address);
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief Array wit the layout of the flash memory.
* \details The current layout supports the 2MB external C3 Intel flash:
* - manufacturer id = 0x0089
* - device id = 0x88c3 (16 Mbit bottom boot device)
* Note that what Intel calls a block in the user manual, is called a sector in this
* driver.
*/
static const tFlashSector flashLayout[] =
{
{ 0x80000000, 0x02000, 0}, /* flash sector 0 - 8 kbyte */
{ 0x80002000, 0x02000, 1}, /* flash sector 1 - 8 kbyte */
{ 0x80004000, 0x02000, 2}, /* flash sector 2 - 8 kbyte */
{ 0x80006000, 0x02000, 3}, /* flash sector 3 - 8 kbyte */
{ 0x80008000, 0x02000, 4}, /* flash sector 4 - 8 kbyte */
{ 0x8000A000, 0x02000, 5}, /* flash sector 5 - 8 kbyte */
{ 0x8000C000, 0x02000, 6}, /* flash sector 6 - 8 kbyte */
{ 0x8000E000, 0x02000, 7}, /* flash sector 7 - 8 kbyte */
{ 0x80010000, 0x10000, 8}, /* flash sector 8 - 64 kbyte */
{ 0x80020000, 0x10000, 9}, /* flash sector 9 - 64 kbyte */
{ 0x80030000, 0x10000, 10}, /* flash sector 10 - 64 kbyte */
{ 0x80040000, 0x10000, 11}, /* flash sector 11 - 64 kbyte */
{ 0x80050000, 0x10000, 12}, /* flash sector 12 - 64 kbyte */
{ 0x80060000, 0x10000, 13}, /* flash sector 13 - 64 kbyte */
{ 0x80070000, 0x10000, 14}, /* flash sector 14 - 64 kbyte */
{ 0x80080000, 0x10000, 15}, /* flash sector 15 - 64 kbyte */
{ 0x80090000, 0x10000, 16}, /* flash sector 16 - 64 kbyte */
{ 0x800A0000, 0x10000, 17}, /* flash sector 17 - 64 kbyte */
{ 0x800B0000, 0x10000, 18}, /* flash sector 18 - 64 kbyte */
{ 0x800C0000, 0x10000, 19}, /* flash sector 19 - 64 kbyte */
{ 0x800D0000, 0x10000, 20}, /* flash sector 20 - 64 kbyte */
{ 0x800E0000, 0x10000, 21}, /* flash sector 21 - 64 kbyte */
{ 0x800F0000, 0x10000, 22}, /* flash sector 22 - 64 kbyte */
{ 0x80100000, 0x10000, 23}, /* flash sector 23 - 64 kbyte */
{ 0x80110000, 0x10000, 24}, /* flash sector 24 - 64 kbyte */
{ 0x80120000, 0x10000, 25}, /* flash sector 25 - 64 kbyte */
{ 0x80130000, 0x10000, 26}, /* flash sector 26 - 64 kbyte */
{ 0x80140000, 0x10000, 27}, /* flash sector 27 - 64 kbyte */
{ 0x80150000, 0x10000, 28}, /* flash sector 28 - 64 kbyte */
{ 0x80160000, 0x10000, 29}, /* flash sector 29 - 64 kbyte */
{ 0x80170000, 0x10000, 30}, /* flash sector 30 - 64 kbyte */
{ 0x80180000, 0x10000, 31}, /* flash sector 31 - 64 kbyte */
{ 0x80190000, 0x10000, 32}, /* flash sector 32 - 64 kbyte */
{ 0x801A0000, 0x10000, 33}, /* flash sector 33 - 64 kbyte */
{ 0x801B0000, 0x10000, 34}, /* flash sector 34 - 64 kbyte */
{ 0x801C0000, 0x10000, 35}, /* flash sector 35 - 64 kbyte */
{ 0x801D0000, 0x10000, 36}, /* flash sector 36 - 64 kbyte */
{ 0x801E0000, 0x10000, 37}, /* flash sector 37 - 64 kbyte */
{ 0x801F0000, 0x10000, 38} /* flash sector 38 - 64 kbyte */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable with information about the flash block that is currently
* being operated on.
* \details The smallest amount of flash that can be programmed is
* FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver
* and stores info in this variable. Whenever new data should be flashed, it
* is first added to a RAM buffer, which is part of this variable. Whenever
* the RAM buffer, which has the size of a flash block, is full or data needs
* to be written to a different block, the contents of the RAM buffer are
* programmed to flash. The flash block manager requires some software
* overhead, yet results is faster flash programming because data is first
* harvested, ideally until there is enough to program an entire flash block,
* before the flash device is actually operated on.
*/
static tFlashBlockInfo blockInfo;
/************************************************************************************//**
** \brief Initializes the flash driver.
** \return none.
**
****************************************************************************************/
void ExtFlashInit(void)
{
/* init the flash block info struct by setting the address to an invalid address */
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
/* check the flash device identification */
if ((ExtFlashGetManID() != FLASH_DEV_MAN_ID) || (ExtFlashGetDevID() != FLASH_DEV_ID))
{
ASSERT_RT(BLT_FALSE);
}
} /*** end of ExtFlashInit ***/
/************************************************************************************//**
** \brief Writes the data to flash.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
/* make sure the addresses are within the flash device */
if ( (ExtFlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
(ExtFlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
{
return BLT_NVM_NOT_IN_RANGE;
}
/* let the block manager handle it */
if (ExtFlashAddToBlock(&blockInfo, addr, data, len) == BLT_FALSE)
{
return BLT_NVM_ERROR;
}
return BLT_NVM_OKAY;
} /*** end of FlashWrite ***/
/************************************************************************************//**
** \brief Erases the flash memory. Note that this function also checks that no
** data is erased outside the flash memory region.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len)
{
blt_int8u first_sector;
blt_int8u last_sector;
blt_int8u sectorIdx;
/* obtain the first and last sector number */
first_sector = ExtFlashGetSector(addr);
last_sector = ExtFlashGetSector(addr+len-1);
/* check them */
if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
{
return BLT_NVM_NOT_IN_RANGE;
}
/* erase the sectors one-by-one */
for (sectorIdx = first_sector; sectorIdx <= last_sector; sectorIdx++)
{
/* keep the watchdog happy */
CopService();
/* erase the sector */
if (ExtFlashEraseSector(flashLayout[sectorIdx].sector_start) == BLT_FALSE)
{
return BLT_NVM_ERROR;
}
}
/* done so return the result of the operation */
return BLT_NVM_OKAY;
} /*** end of ExtFlashErase ***/
/************************************************************************************//**
** \brief Finalizes the flash driver operations.
** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool ExtFlashDone(void)
{
/* check if there is still data waiting to be programmed */
if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
{
if (ExtFlashWriteBlock(&blockInfo) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* still here so all is okay */
return BLT_TRUE;
} /*** end of ExtFlashDone ***/
/************************************************************************************//**
** \brief Copies data currently in flash to the block->data and sets the
** base address.
** \param block Pointer to flash block info structure to operate on.
** \param address Base address of the block data.
** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address)
{
/* check address alignment */
if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
{
return BLT_FALSE;
}
/* make sure that we are initializing a new block and not the same one */
if (block->base_addr == address)
{
/* block already initialized, so nothing to do */
return BLT_TRUE;
}
/* set the base address and copies the current data from flash */
block->base_addr = address;
CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
return BLT_TRUE;
} /*** end of ExtFlashInitBlock ***/
/************************************************************************************//**
** \brief Switches blocks by programming the current one and initializing the next.
** \param block Pointer to flash block info structure to operate on.
** \param base_addr Base address for the next block.
** \return The pointer of the block info struct that is no being used, or a NULL
** pointer in case of error.
**
****************************************************************************************/
static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
{
/* need to switch to a new block, so program the current one and init the next */
if (ExtFlashWriteBlock(block) == BLT_FALSE)
{
return BLT_NULL;
}
/* initialize the new block when necessary */
if (ExtFlashInitBlock(block, base_addr) == BLT_FALSE)
{
return BLT_NULL;
}
/* still here to all is okay */
return block;
} /*** end of ExtFlashSwitchBlock ***/
/************************************************************************************//**
** \brief Programming is done per block. This function adds data to the block
** that is currently collecting data to be written to flash. If the
** address is outside of the current block, the current block is written
** to flash an a new block is initialized.
** \param block Pointer to flash block info structure to operate on.
** \param address Flash destination address.
** \param data Pointer to the byte array with data.
** \param len Number of bytes to add to the block.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len)
{
blt_addr current_base_addr;
blt_int8u *dst;
blt_int8u *src;
/* determine the current base address */
current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
/* make sure the blockInfo is not uninitialized */
if (block->base_addr == FLASH_INVALID_ADDRESS)
{
/* initialize the blockInfo struct for the current block */
if (ExtFlashInitBlock(block, current_base_addr) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* check if the new data fits in the current block */
if (block->base_addr != current_base_addr)
{
/* need to switch to a new block, so program the current one and init the next */
block = ExtFlashSwitchBlock(block, current_base_addr);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
}
/* add the data to the current block, but check for block overflow */
dst = &(block->data[address - block->base_addr]);
src = data;
do
{
/* keep the watchdog happy */
CopService();
/* buffer overflow? */
if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
{
/* need to switch to a new block, so program the current one and init the next */
block = ExtFlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
/* reset destination pointer */
dst = &(block->data[0]);
}
/* write the data to the buffer */
*dst = *src;
/* update pointers */
dst++;
src++;
/* decrement byte counter */
len--;
}
while (len > 0);
/* still here so all is good */
return BLT_TRUE;
} /*** end of ExtFlashAddToBlock ***/
/************************************************************************************//**
** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data array.
** \param block Pointer to flash block info structure to operate on.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block)
{
volatile blt_int16u *pAddr;
volatile blt_int16u *pData;
blt_bool result = BLT_TRUE;
volatile blt_int32u timeout = 0;
/* unlock the sector */
ExtFlashUnlockSector(block->base_addr);
/* init pointer to valid address in the flash block */
pAddr = (blt_int16u *)block->base_addr;
/* init pointer to start of block data */
pData = (blt_int16u *)block->data;
/* program all block data 16-bits at a time */
while ((blt_addr)pAddr < (block->base_addr+FLASH_WRITE_BLOCK_SIZE))
{
/* keep the watchdog happy */
CopService();
/* issue program setup command */
*pAddr = FLASH_CMD_PROGRAM_MODE;
/* write 16-bit data that is to be programmed to start programming operation */
*pAddr = *pData;
/* check status register for completion */
*pAddr = FLASH_CMD_READ_STATUS_MODE;
/* wait for completion or timeout */
while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_PROGRAM_TIMEOUT) )
{
timeout++;
}
/* check for possible errors */
if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_PROGRAM))!= 0) )
{
result = BLT_FALSE;
}
/* clear the status register */
*pAddr = FLASH_CMD_CLEAR_STATUS;
/* increment address and data pointers */
pAddr++;
pData++;
}
/* lock the sector. this also switches back to read array mode */
ExtFlashLockSector(block->base_addr);
/* inform the caller about the result */
return result;
} /*** end of ExtFlashWriteBlock ***/
/************************************************************************************//**
** \brief Erases the flash sector.
** \param sector_base Base address of the sector to erase.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool ExtFlashEraseSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
blt_bool result = BLT_TRUE;
volatile blt_int32u timeout = 0;
/* unlock the sector */
ExtFlashUnlockSector(sector_base);
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* issue erase setup command */
*pAddr = FLASH_CMD_ERASE_MODE;
/* issue erase confirm command */
*pAddr = FLASH_CMD_ERASE_CONFIRM;
/* check status register for completion */
*pAddr = FLASH_CMD_READ_STATUS_MODE;
/* wait for completion or timeout */
while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_ERASE_TIMEOUT) )
{
timeout++;
}
/* check for possible errors */
if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_ERASE))!= 0) )
{
result = BLT_FALSE;
}
/* clear the status register */
*pAddr = FLASH_CMD_CLEAR_STATUS;
/* lock the sector. this also switches back to read array mode */
ExtFlashLockSector(sector_base);
/* inform the caller about the result */
return result;
} /*** end of ExtFlashEraseSector ***/
/************************************************************************************//**
** \brief Locks the flash sector.
** \param sector_base Base address of the sector to lock.
** \return none.
**
****************************************************************************************/
static void ExtFlashLockSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
/* no need to lock a sector that is already locked */
if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0)
{
return;
}
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* switch to change lock mode */
*pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
/* unlock the sector */
*pAddr = FLASH_CMD_LOCK_SECTOR;
/* check that the sector is now actually locked */
ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0);
} /*** end of ExtFlashLockSector ***/
/************************************************************************************//**
** \brief Unlocks the flash sector.
** \param sector_base Base address of the sector to unlock.
** \return none.
**
****************************************************************************************/
static void ExtFlashUnlockSector(blt_addr sector_base)
{
volatile blt_int16u *pAddr;
/* no need to unlock a sector that is already unlocked */
if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0)
{
return;
}
/* init pointer to valid address in the flash sector */
pAddr = (blt_int16u *)sector_base;
/* switch to change lock mode */
*pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
/* unlock the sector */
*pAddr = FLASH_CMD_UNLOCK_SECTOR;
/* check that the sector is now actually unlocked */
ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0);
} /*** end of ExtFlashUnlockSector ***/
/************************************************************************************//**
** \brief Obtains device information from the flash device.
** \param sector_base Base address of the sector to get the info from.
** \param info Identifier to the type of info to obtain.
** \return Device info.
**
****************************************************************************************/
static blt_int16u ExtFlashGetDeviceInfo(blt_addr sector_base, blt_int16u info)
{
volatile blt_int16u *pAddr;
blt_int16u readData;
/* init pointer to any valid address in the flash device */
pAddr = (blt_int16u *)sector_base + info;
/* switch to read identifier mode */
*pAddr = FLASH_CMD_READ_ID_MODE;
/* read the info */
readData = *pAddr;
/* switch back to reading mode */
*pAddr = FLASH_CMD_READ_ARRAY_MODE;
/* return the result */
return readData;
} /*** end of ExtFlashGetDeviceInfo ***/
/************************************************************************************//**
** \brief Determines the flash sector the address is in.
** \param address Address in the flash sector.
** \return Flash sector number or FLASH_INVALID_SECTOR
**
****************************************************************************************/
static blt_int8u ExtFlashGetSector(blt_addr address)
{
blt_int8u sectorIdx;
/* search through the sectors to find the right one */
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
{
/* keep the watchdog happy */
CopService();
/* is the address in this sector? */
if ( (address >= flashLayout[sectorIdx].sector_start) && \
(address < (flashLayout[sectorIdx].sector_start + \
flashLayout[sectorIdx].sector_size)) )
{
/* return the sector number */
return flashLayout[sectorIdx].sector_num;
}
}
/* still here so no valid sector found */
return FLASH_INVALID_SECTOR;
} /*** end of ExtFlashGetSector ***/
#endif
/*********************************** end of extflash.c *********************************/

42
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/extflash.h
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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/extflash.h
* \brief Bootloader external flash driver header file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef EXTFLASH_H
#define EXTFLASH_H
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void ExtFlashInit(void);
blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len);
blt_bool ExtFlashDone(void);
#endif
#endif /* EXTFLASH_H */
/*********************************** end of extflash.h *********************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "lpc2294.h" /* CPU register definitions */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
/* configure the button connected to P0.16 as a digital input */
IO0DIR &= ~(1<<16);
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* button P0.16 has a pullup, so will read high by default. enter backdoor only when
* this button is pressed. this is the case when it reads low */
if ((IO0PIN & (1<<16)) == 0)
{
return BLT_TRUE;
}
return BLT_FALSE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
#include "extflash.h"
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
/* init the external flash driver */
ExtFlashInit();
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
/* attempt to write with the external flash driver */
return ExtFlashWrite(addr, len, data);
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
/* attempt to erase with the external flash driver */
return ExtFlashErase(addr, len);
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
/* finish up the operations of the external flash driver */
return ExtFlashDone();
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "libseednkey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

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/****************************************************************************************
| Description: NXP LPC2294 register definitions
| File Name: lpc2294.h
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
#ifndef LPC2294_H
#define LPC2294_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* EXTERNAL MEMORY CONTROLLER (EMC) */
#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
/* External Interrupts */
#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
/* SMemory mapping control. */
#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
/* Phase Locked Loop (PLL) */
#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
/* Power Control */
#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
/* VPB Divider */
#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
/* Memory Accelerator Module (MAM) */
#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
/* Vectored Interrupt Controller (VIC) */
#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
/* Pin Connect Block */
#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
/* General Purpose Input/Output (GPIO) */
#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define U0RBR (*((volatile unsigned char *) 0xE000C000))
#define U0THR (*((volatile unsigned char *) 0xE000C000))
#define U0IER (*((volatile unsigned char *) 0xE000C004))
#define U0IIR (*((volatile unsigned char *) 0xE000C008))
#define U0FCR (*((volatile unsigned char *) 0xE000C008))
#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
#define U0LSR (*((volatile unsigned char *) 0xE000C014))
#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
#define U0DLL (*((volatile unsigned char *) 0xE000C000))
#define U0DLM (*((volatile unsigned char *) 0xE000C004))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define U1RBR (*((volatile unsigned char *) 0xE0010000))
#define U1THR (*((volatile unsigned char *) 0xE0010000))
#define U1IER (*((volatile unsigned char *) 0xE0010004))
#define U1IIR (*((volatile unsigned char *) 0xE0010008))
#define U1FCR (*((volatile unsigned char *) 0xE0010008))
#define U1LCR (*((volatile unsigned char *) 0xE001000C))
#define U1MCR (*((volatile unsigned char *) 0xE0010010))
#define U1LSR (*((volatile unsigned char *) 0xE0010014))
#define U1MSR (*((volatile unsigned char *) 0xE0010018))
#define U1SCR (*((volatile unsigned char *) 0xE001001C))
#define U1DLL (*((volatile unsigned char *) 0xE0010000))
#define U1DLM (*((volatile unsigned char *) 0xE0010004))
/* I2C (8/16 bit data bus) */
#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
#define I2STAT (*((volatile unsigned long *) 0xE001C004))
#define I2DAT (*((volatile unsigned long *) 0xE001C008))
#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
/* SPI (Serial Peripheral Interface) */
/* only for lpc210x*/
#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
/* Timer 0 */
#define T0IR (*((volatile unsigned long *) 0xE0004000))
#define T0TCR (*((volatile unsigned long *) 0xE0004004))
#define T0TC (*((volatile unsigned long *) 0xE0004008))
#define T0PR (*((volatile unsigned long *) 0xE000400C))
#define T0PC (*((volatile unsigned long *) 0xE0004010))
#define T0MCR (*((volatile unsigned long *) 0xE0004014))
#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
#define T0CCR (*((volatile unsigned long *) 0xE0004028))
#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
#define T0EMR (*((volatile unsigned long *) 0xE000403C))
/* Timer 1 */
#define T1IR (*((volatile unsigned long *) 0xE0008000))
#define T1TCR (*((volatile unsigned long *) 0xE0008004))
#define T1TC (*((volatile unsigned long *) 0xE0008008))
#define T1PR (*((volatile unsigned long *) 0xE000800C))
#define T1PC (*((volatile unsigned long *) 0xE0008010))
#define T1MCR (*((volatile unsigned long *) 0xE0008014))
#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
#define T1CCR (*((volatile unsigned long *) 0xE0008028))
#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
#define T1EMR (*((volatile unsigned long *) 0xE000803C))
/* Pulse Width Modulator (PWM) */
#define PWMIR (*((volatile unsigned long *) 0xE0014000))
#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
#define PWMTC (*((volatile unsigned long *) 0xE0014008))
#define PWMPR (*((volatile unsigned long *) 0xE001400C))
#define PWMPC (*((volatile unsigned long *) 0xE0014010))
#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
#define PWMLER (*((volatile unsigned long *) 0xE0014050))
/* A/D CONVERTER */
#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
/* Real Time Clock */
#define ILR (*((volatile unsigned char *) 0xE0024000))
#define CTC (*((volatile unsigned short*) 0xE0024004))
#define CCR (*((volatile unsigned char *) 0xE0024008))
#define CIIR (*((volatile unsigned char *) 0xE002400C))
#define AMR (*((volatile unsigned char *) 0xE0024010))
#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
#define SEC (*((volatile unsigned char *) 0xE0024020))
#define MIN (*((volatile unsigned char *) 0xE0024024))
#define HOUR (*((volatile unsigned char *) 0xE0024028))
#define DOM (*((volatile unsigned char *) 0xE002402C))
#define DOW (*((volatile unsigned char *) 0xE0024030))
#define DOY (*((volatile unsigned short*) 0xE0024034))
#define MONTH (*((volatile unsigned char *) 0xE0024038))
#define YEAR (*((volatile unsigned short*) 0xE002403C))
#define ALSEC (*((volatile unsigned char *) 0xE0024060))
#define ALMIN (*((volatile unsigned char *) 0xE0024064))
#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
#define ALDOM (*((volatile unsigned char *) 0xE002406C))
#define ALDOW (*((volatile unsigned char *) 0xE0024070))
#define ALDOY (*((volatile unsigned short*) 0xE0024074))
#define ALMON (*((volatile unsigned char *) 0xE0024078))
#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
#define PREINT (*((volatile unsigned short*) 0xE0024080))
#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
/* Watchdog */
#define WDMOD (*((volatile unsigned char *) 0xE0000000))
#define WDTC (*((volatile unsigned long *) 0xE0000004))
#define WDFEED (*((volatile unsigned char *) 0xE0000008))
#define WDTV (*((volatile unsigned long *) 0xE000000C))
#endif /* LPC2294_H */
/*********************************** end of lpc2294.h **********************************/

174
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/main.c
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@ -1,174 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "lpc2294.h" /* CPU register definitions */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* initialize the microcontroller */
Init();
/* initialize the bootloader */
BootInit();
/* start the infinite program loop */
while (1)
{
/* run the bootloader task */
BootTask();
}
/* program should never get here */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
** configured equal to Fpll. The GPIO pin of the status LED is configured
** as digital output.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
blt_int8u m_sel; /* pll multiplier register value */
static blt_int8u pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
blt_int8u p_sel_cnt; /* loop counter to find p_sel */
blt_int32u f_cco; /* current controller oscillator */
/* check that pll multiplier value will be in the range 1..32 */
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ >= 1);
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ <= 32);
/* calculate MSEL: M = round(Fcclk / Fosc) */
m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ;
/* value for the PLLCFG register is -1 */
m_sel--;
/* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
for (p_sel_cnt=0; p_sel_cnt<sizeof(pll_dividers)/sizeof(pll_dividers[0]); p_sel_cnt++)
{
/* check f_cco with this pll divider */
f_cco = BOOT_CPU_SYSTEM_SPEED_KHZ * 2 * pll_dividers[p_sel_cnt];
if ( (f_cco >= 156000) && (f_cco <= 320000) )
{
/* found a valid pll divider value */
break;
}
}
/* check that a valid value was found */
ASSERT_RT(p_sel_cnt < (sizeof(pll_dividers)/sizeof(pll_dividers[0])));
/* set multiplier and divider values */
PLLCFG = (p_sel_cnt << 5) | m_sel;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable the PLL */
PLLCON = 0x1;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* wait for the PLL to lock to set frequency */
while(!(PLLSTAT & 0x400)) { ; }
/* connect the PLL as the clock source */
PLLCON = 0x3;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
* Fcclk >= 60 MHz: 4 clock cycles
* Fcclk >= 40 MHz: 3 clock cycles
* Fcclk >= 20 MHz: 2 clock cycles
* Fcclk < 20 MHz: 1 clock cycle
*/
MAMCR = 0x0;
#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
MAMTIM = 4;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
MAMTIM = 3;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
MAMTIM = 2;
#else
MAMTIM = 1;
#endif
MAMCR = 0x2;
/* setting peripheral Clock (pclk) to System Clock (cclk) */
VPBDIV = 0x1;
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* in this the external memory on the Olimex LPC-L2294 board is used so configure
* the memory banks for the external flash EEPROM and RAM
*/
/* external flash EEPROM:
* IDCY=3 (idle timing)
* WST1=4 (read timing)
* RBLE=1
* WST2=6 (write timing)
* MW=1 (16-bit data bus)
*/
BCFG0 = (0x3 << 0) | (0x4 << 5) | (0x1 << 10) | (0x6 << 11) | (0x1 << 28);
/* external RAM:
* IDCY=0 (idle timing)
* WST1=0 (read timing)
* RBLE=1
* WST2=0 (write timing)
* MW=2 (32-bit data bus)
*/
BCFG1 = (0x0 << 0) | (0x0 << 5) | (0x1 << 10) | (0x0 << 11) | (0x2 << 28);
/* configure use of data bus and strobe pins for the external memory */
PINSEL2 = 0x0F000924;
#endif
#if (BOOT_COM_UART_ENABLE > 0)
/* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
PINSEL0 |= 0x05;
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* configure P0.25 for CAN1 Rx functionality */
PINSEL1 |= 0x00040000L;
#endif
} /*** end of Init ***/
/*********************************** end of main.c *************************************/

172
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#****************************************************************************************
#| Description: Makefile for GNU ARM Embedded toolchain.
#| File Name: makefile
#|
#|---------------------------------------------------------------------------------------
#| C O P Y R I G H T
#|---------------------------------------------------------------------------------------
#| Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
#|
#|---------------------------------------------------------------------------------------
#| L I C E N S E
#|---------------------------------------------------------------------------------------
#| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
#| modify it under the terms of the GNU General Public License as published by the Free
#| Software Foundation, either version 3 of the License, or (at your option) any later
#| version.
#|
#| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
#| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
#| PURPOSE. See the GNU General Public License for more details.
#|
#| You have received a copy of the GNU General Public License along with OpenBLT. It
#| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
#|
#****************************************************************************************
SHELL = sh
#|--------------------------------------------------------------------------------------|
#| Configure project name |
#|--------------------------------------------------------------------------------------|
PROJ_NAME=openblt_olimex_lpc_l2294_20mhz
#|--------------------------------------------------------------------------------------|
#| Configure tool path |
#|--------------------------------------------------------------------------------------|
TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/
#|--------------------------------------------------------------------------------------|
#| Collect project files |
#|--------------------------------------------------------------------------------------|
# Recursive wildcard function implementation. Example usages:
# $(call rwildcard, , *.c *.h)
# --> Returns all *.c and *.h files in the current directory and below
# $(call rwildcard, /lib/, *.c)
# --> Returns all *.c files in the /lib directory and below
rwildcard = $(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)))
# Collect all application files in the current directory and its subdirectories, but
# exclude flash-layout.c as this one is directly included in a source file, when used.
PROJ_FILES = $(filter-out flash_layout.c, $(call rwildcard, , *.c *.h *.s))
# Collect bootloader core files
PROJ_FILES += $(wildcard ../../../Source/*.c)
PROJ_FILES += $(wildcard ../../../Source/*.h)
# Collect bootloader port files
PROJ_FILES += $(wildcard ../../../Source/ARM7_LPC2000/*.c)
PROJ_FILES += $(wildcard ../../../Source/ARM7_LPC2000/*.h)
# Collect bootloader port compiler specific files
PROJ_FILES += $(wildcard ../../../Source/ARM7_LPC2000/GCC/*.c)
PROJ_FILES += $(wildcard ../../../Source/ARM7_LPC2000/GCC/*.h)
#|--------------------------------------------------------------------------------------|
#| Toolchain binaries |
#|--------------------------------------------------------------------------------------|
RM = rm
CC = $(TOOL_PATH)arm-none-eabi-gcc
LN = $(TOOL_PATH)arm-none-eabi-gcc
OC = $(TOOL_PATH)arm-none-eabi-objcopy
OD = $(TOOL_PATH)arm-none-eabi-objdump
AS = $(TOOL_PATH)arm-none-eabi-gcc
SZ = $(TOOL_PATH)arm-none-eabi-size
#|--------------------------------------------------------------------------------------|
#| Filter project files
#|--------------------------------------------------------------------------------------|
PROJ_ASRCS = $(filter %.s,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
#|--------------------------------------------------------------------------------------|
#| Set important path variables |
#|--------------------------------------------------------------------------------------|
VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :)
OBJ_PATH = obj
BIN_PATH = bin
INC_PATH = $(patsubst %/,%,$(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file))))))
INC_PATH += -I./lib
LIB_PATH =
#|--------------------------------------------------------------------------------------|
#| Options for toolchain binaries |
#|--------------------------------------------------------------------------------------|
STDFLAGS = -mcpu=arm7tdmi-s -mlong-calls -fno-strict-aliasing
STDFLAGS += -Wno-unused-but-set-variable
STDFLAGS += -fdata-sections -ffunction-sections -Wall -g3
OPTFLAGS = -O1
CFLAGS = $(STDFLAGS) $(OPTFLAGS)
CFLAGS += -DDEBUG -Dgcc
CFLAGS += $(INC_PATH)
AFLAGS = $(CFLAGS)
LFLAGS = $(STDFLAGS) $(OPTFLAGS)
LFLAGS += -Wl,-script="memory.x" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map
LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH)
OFLAGS = -O srec
ODFLAGS = -x
SZFLAGS = -B -d
RMFLAGS = -f
#|--------------------------------------------------------------------------------------|
#| Specify library files |
#|--------------------------------------------------------------------------------------|
LIBS =
#|--------------------------------------------------------------------------------------|
#| Define targets |
#|--------------------------------------------------------------------------------------|
AOBJS = $(patsubst %.s,%.o,$(PROJ_ASRCS))
COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS))
#|--------------------------------------------------------------------------------------|
#| Make ALL |
#|--------------------------------------------------------------------------------------|
.PHONY: all
all: $(BIN_PATH)/$(PROJ_NAME).srec
$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf
@$(OC) $< $(OFLAGS) $@
@$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map
@echo +++ Summary of memory consumption:
@$(SZ) $(SZFLAGS) $<
@echo +++ Build complete [$(notdir $@)]
$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS)
@echo +++ Linking [$(notdir $@)]
@$(LN) $(LFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS)
#|--------------------------------------------------------------------------------------|
#| Compile and assemble |
#|--------------------------------------------------------------------------------------|
$(AOBJS): %.o: %.s $(PROJ_CHDRS)
@echo +++ Assembling [$(notdir $<)]
@$(AS) $(AFLAGS) -c $< -o $(OBJ_PATH)/$(@F)
$(COBJS): %.o: %.c $(PROJ_CHDRS)
@echo +++ Compiling [$(notdir $<)]
@$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F)
#|--------------------------------------------------------------------------------------|
#| Make CLEAN |
#|--------------------------------------------------------------------------------------|
.PHONY: clean
clean:
@echo +++ Cleaning build environment
@$(RM) $(RMFLAGS) $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file))
@$(RM) $(RMFLAGS) $(foreach file,$(COBJS),$(OBJ_PATH)/$(file))
@$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file)))
@$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map
@$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).srec
@echo +++ Clean complete

54
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/memory.x
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@ -1,54 +0,0 @@
/* identify the Entry Point */
ENTRY(_startup)
/* specify the LPC2xxx memory areas. note that the RAM is configured to be only 8kb. this is
* the smallest in the LPC2xxx series, making this memory layout compatible with all devices
* in this serie of microcontrollers.
*/
MEMORY
{
flash : ORIGIN = 0x00000000, LENGTH = 8K /* FLASH ROM reserved for the bootloader */
ram_vectors(A) : ORIGIN = 0x40000000, LENGTH = 64 /* RAM vectors of the user program */
ram_monitor(A) : ORIGIN = 0x40000040, LENGTH = 224 /* variables used by Philips RealMonitor */
ram_isp_low(A) : ORIGIN = 0x40000120, LENGTH = 224 /* variables used by Philips ISP bootloader */
ram : ORIGIN = 0x40000200, LENGTH = 7392 /* free RAM area */
ram_isp_high(A) : ORIGIN = 0x40001EE0, LENGTH = 288 /* variables used by Philips ISP bootloader */
}
/* define a global symbol _stack_end, placed at the very end of unused RAM */
_stack_end = 0x40001EE0 - 4;
/* now define the output sections */
SECTIONS
{
. = 0; /* set location counter to address zero */
startup : { *(.startup)} >flash /* the startup code goes into FLASH */
.text : /* collect all sections that should go into FLASH after startup */
{
*(.text) /* all .text sections (code) */
*(.rodata) /* all .rodata sections (constants, strings, etc.) */
*(.rodata*) /* all .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* all .glue_7 sections (no idea what these are) */
*(.glue_7t) /* all .glue_7t sections (no idea what these are) */
_etext = .; /* define a global symbol _etext just after the last code byte */
} >flash /* put all the above into FLASH */
.data : /* collect all initialized .data sections that go into RAM */
{
_data = .; /* create a global symbol marking the start of the .data section */
*(.data) /* all .data sections */
_edata = .; /* define a global symbol marking the end of the .data section */
} >ram AT >flash /* put all the above into RAM (but load the LMA copy into FLASH) */
.bss : /* collect all uninitialized .bss sections that go into RAM */
{
_bss_start = .; /* define a global symbol marking the start of the .bss section */
*(.bss) /* all .bss sections */
} >ram /* put all the above in RAM (it will be cleared in the startup code */
. = ALIGN(4); /* advance location counter to the next 32-bit boundary */
_bss_end = . ; /* define a global symbol marking the end of the .bss section */
}
_end = .; /* define a global symbol marking the end of application RAM */

4
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/obj/.gitignore vendored
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@ -1,4 +0,0 @@
# Ignore everything in this directory
*
# Except this file
!.gitignore

80
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/vectors.c
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@ -1,80 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/vectors.c
* \brief Bootloader interrupt vectors source file.
* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void __attribute__((interrupt("FIQ"))) FIQ_ISR(void);
void __attribute__((interrupt("IRQ"))) IRQ_ISR(void);
void __attribute__((interrupt("UNDEF"))) UNDEF_ISR(void);
/************************************************************************************//**
** \brief FIQ exception routine.
** \return none.
**
****************************************************************************************/
void FIQ_ISR(void)
{
/* unexpected interrupt so trigger assertion */
ASSERT_RT(BLT_FALSE);
} /*** end of FIQ_ISR ***/
/************************************************************************************//**
** \brief IRQ exception routine.
** \return none.
**
****************************************************************************************/
void IRQ_ISR(void)
{
/* unexpected interrupt so trigger assertion */
ASSERT_RT(BLT_FALSE);
} /*** end of IRQ_ISR ***/
/************************************************************************************//**
** \brief UNDEF exception routine.
** \return none.
**
****************************************************************************************/
void UNDEF_ISR(void)
{
/* unexpected interrupt so trigger assertion */
ASSERT_RT(BLT_FALSE);
} /*** end of UNDEF_ISR ***/
/*********************************** end of vectors.c **********************************/

BIN
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf
View File

Binary file not shown.

232
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
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@ -1,232 +0,0 @@
bin/demoprog_olimex_lpc_l2294_20mhz.elf: file format elf32-littlearm
bin/demoprog_olimex_lpc_l2294_20mhz.elf
architecture: armv4t, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00002000
Program Header:
LOAD off 0x00000000 vaddr 0x00000000 paddr 0x00000000 align 2**16
filesz 0x000028cc memsz 0x000028cc flags r-x
LOAD off 0x00010200 vaddr 0x40000200 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000041 flags rw-
LOAD off 0x00010241 vaddr 0x40000241 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x00010242 vaddr 0x40000242 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x00010244 vaddr 0x40000244 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
LOAD off 0x00010248 vaddr 0x40000248 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
LOAD off 0x0001024c vaddr 0x4000024c paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000001 flags rw-
LOAD off 0x00010250 vaddr 0x40000250 paddr 0x000028cc align 2**16
filesz 0x00000000 memsz 0x00000004 flags rw-
private flags = 5000200: [Version5 EABI] [soft-float ABI]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000024c 00002000 00002000 00002000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .init 0000000c 0000224c 0000224c 0000224c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .fini 0000000c 00002258 00002258 00002258 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .text.IrqInterruptEnable 00000010 00002264 00002264 00002264 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
4 .text.BootComInit 00000140 00002274 00002274 00002274 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
5 .text.BootActivate 00000034 000023b4 000023b4 000023b4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
6 .text.BootComCheckActivationRequest 000001d4 000023e8 000023e8 000023e8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
7 .text.TIMER0_ISR 00000038 000025bc 000025bc 000025bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
8 .text.SWI_ISR 00000004 000025f4 000025f4 000025f4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
9 .text.FIQ_ISR 00000004 000025f8 000025f8 000025f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
10 .text.UNDEF_ISR 00000004 000025fc 000025fc 000025fc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
11 .text.main 00000188 00002600 00002600 00002600 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
12 .text.LedInit 00000020 00002788 00002788 00002788 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
13 .text.LedToggle 00000088 000027a8 000027a8 000027a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
14 .text.TimerInit 00000058 00002830 00002830 00002830 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
15 .text.TimerUpdate 00000018 00002888 00002888 00002888 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
16 .text.TimerGet 00000010 000028a0 000028a0 000028a0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
17 .text.memcpy 0000001c 000028b0 000028b0 000028b0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
18 .bss.xcpCtoReqPacket.4213 00000041 40000200 000028cc 00010200 2**2
ALLOC
19 .bss.xcpCtoRxLength.4214 00000001 40000241 000028cc 00010241 2**0
ALLOC
20 .bss.xcpCtoRxInProgress.4215 00000001 40000242 000028cc 00010242 2**0
ALLOC
21 .bss.xcpCtoRxStartTime.4216 00000004 40000244 000028cc 00010244 2**2
ALLOC
22 .bss.timer_counter_last.4194 00000004 40000248 000028cc 00010248 2**2
ALLOC
23 .bss.led_toggle_state.4193 00000001 4000024c 000028cc 0001024c 2**0
ALLOC
24 .bss.millisecond_counter 00000004 40000250 000028cc 00010250 2**2
ALLOC
25 .ARM.attributes 0000002c 00000000 00000000 000028cc 2**0
CONTENTS, READONLY
26 .comment 0000006e 00000000 00000000 000028f8 2**0
CONTENTS, READONLY
27 .debug_line 00000541 00000000 00000000 00002966 2**0
CONTENTS, READONLY, DEBUGGING
28 .debug_info 0000087a 00000000 00000000 00002ea7 2**0
CONTENTS, READONLY, DEBUGGING
29 .debug_abbrev 00000537 00000000 00000000 00003721 2**0
CONTENTS, READONLY, DEBUGGING
30 .debug_aranges 00000138 00000000 00000000 00003c58 2**3
CONTENTS, READONLY, DEBUGGING
31 .debug_loc 00000249 00000000 00000000 00003d90 2**0
CONTENTS, READONLY, DEBUGGING
32 .debug_ranges 00000118 00000000 00000000 00003fd9 2**0
CONTENTS, READONLY, DEBUGGING
33 .debug_macro 00001368 00000000 00000000 000040f1 2**0
CONTENTS, READONLY, DEBUGGING
34 .debug_str 000068f2 00000000 00000000 00005459 2**0
CONTENTS, READONLY, DEBUGGING
35 .debug_frame 0000020c 00000000 00000000 0000bd4c 2**2
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00002000 l d .text 00000000 .text
0000224c l d .init 00000000 .init
00002258 l d .fini 00000000 .fini
00002264 l d .text.IrqInterruptEnable 00000000 .text.IrqInterruptEnable
00002274 l d .text.BootComInit 00000000 .text.BootComInit
000023b4 l d .text.BootActivate 00000000 .text.BootActivate
000023e8 l d .text.BootComCheckActivationRequest 00000000 .text.BootComCheckActivationRequest
000025bc l d .text.TIMER0_ISR 00000000 .text.TIMER0_ISR
000025f4 l d .text.SWI_ISR 00000000 .text.SWI_ISR
000025f8 l d .text.FIQ_ISR 00000000 .text.FIQ_ISR
000025fc l d .text.UNDEF_ISR 00000000 .text.UNDEF_ISR
00002600 l d .text.main 00000000 .text.main
00002788 l d .text.LedInit 00000000 .text.LedInit
000027a8 l d .text.LedToggle 00000000 .text.LedToggle
00002830 l d .text.TimerInit 00000000 .text.TimerInit
00002888 l d .text.TimerUpdate 00000000 .text.TimerUpdate
000028a0 l d .text.TimerGet 00000000 .text.TimerGet
000028b0 l d .text.memcpy 00000000 .text.memcpy
40000200 l d .bss.xcpCtoReqPacket.4213 00000000 .bss.xcpCtoReqPacket.4213
40000241 l d .bss.xcpCtoRxLength.4214 00000000 .bss.xcpCtoRxLength.4214
40000242 l d .bss.xcpCtoRxInProgress.4215 00000000 .bss.xcpCtoRxInProgress.4215
40000244 l d .bss.xcpCtoRxStartTime.4216 00000000 .bss.xcpCtoRxStartTime.4216
40000248 l d .bss.timer_counter_last.4194 00000000 .bss.timer_counter_last.4194
4000024c l d .bss.led_toggle_state.4193 00000000 .bss.led_toggle_state.4193
40000250 l d .bss.millisecond_counter 00000000 .bss.millisecond_counter
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .comment 00000000 .comment
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_macro 00000000 .debug_macro
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 obj/cstart.o
00000100 l *ABS* 00000000 UND_STACK_SIZE
00000100 l *ABS* 00000000 ABT_STACK_SIZE
00000100 l *ABS* 00000000 FIQ_STACK_SIZE
00000100 l *ABS* 00000000 IRQ_STACK_SIZE
00000100 l *ABS* 00000000 SVC_STACK_SIZE
00000010 l *ABS* 00000000 MODE_USR
00000011 l *ABS* 00000000 MODE_FIQ
00000012 l *ABS* 00000000 MODE_IRQ
00000013 l *ABS* 00000000 MODE_SVC
00000017 l *ABS* 00000000 MODE_ABT
0000001b l *ABS* 00000000 MODE_UND
0000001f l *ABS* 00000000 MODE_SYS
00000080 l *ABS* 00000000 I_BIT
00000040 l *ABS* 00000000 F_BIT
00002000 l .text 00000000 _vectors
00002020 l .text 00000000 Reset_Addr
00002024 l .text 00000000 Undef_Addr
00002028 l .text 00000000 SWI_Addr
0000202c l .text 00000000 PAbt_Addr
00002030 l .text 00000000 DAbt_Addr
0000203c l .text 00000000 FIQ_Addr
00002038 l .text 00000000 IRQ_Addr
00000000 l df *ABS* 00000000 _divsi3.o
000020e0 l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
00000000 l df *ABS* 00000000 main.c
00000000 l df *ABS* 00000000 boot.c
40000200 l O .bss.xcpCtoReqPacket.4213 00000041 xcpCtoReqPacket.4213
40000241 l O .bss.xcpCtoRxLength.4214 00000001 xcpCtoRxLength.4214
40000242 l O .bss.xcpCtoRxInProgress.4215 00000001 xcpCtoRxInProgress.4215
40000244 l O .bss.xcpCtoRxStartTime.4216 00000004 xcpCtoRxStartTime.4216
00002228 l O .text 00000024 canTiming
00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/crti.o
00000000 l df *ABS* 00000000 irq.c
00000000 l df *ABS* 00000000 vectors.c
00000000 l df *ABS* 00000000 led.c
40000248 l O .bss.timer_counter_last.4194 00000004 timer_counter_last.4194
4000024c l O .bss.led_toggle_state.4193 00000001 led_toggle_state.4193
00000000 l df *ABS* 00000000 timer.c
40000250 l O .bss.millisecond_counter 00000004 millisecond_counter
00000000 l df *ABS* 00000000 memcpy-stub.c
00000000 l df *ABS* 00000000
00000000 l *UND* 00000000 __bss_start__
00000000 l *UND* 00000000 __libc_fini_array
00000000 l *UND* 00000000 __sf_fake_stderr
00000000 l *UND* 00000000 __deregister_frame_info
00000000 l *UND* 00000000 __bss_end__
00000000 l *UND* 00000000 __call_exitprocs
00000000 l *UND* 00000000 software_init_hook
00000000 l *UND* 00000000 __sf_fake_stdin
00000000 l *UND* 00000000 __init_array_end
00000000 l *UND* 00000000 hardware_init_hook
00000000 l *UND* 00000000 atexit
00000000 l *UND* 00000000 __preinit_array_end
00000000 l *UND* 00000000 __stack
00000000 l *UND* 00000000 __sf_fake_stdout
00000000 l *UND* 00000000 __init_array_start
00000000 l *UND* 00000000 _exit
00000000 l *UND* 00000000 _Jv_RegisterClasses
00000000 l *UND* 00000000 __preinit_array_start
00000000 l *UND* 00000000 __register_frame_info
00002888 g F .text.TimerUpdate 00000018 TimerUpdate
00002264 g F .text.IrqInterruptEnable 00000010 IrqInterruptEnable
000025bc g F .text.TIMER0_ISR 00000038 TIMER0_ISR
0000224c g .text 00000000 _etext
000028b0 g F .text.memcpy 0000001c memcpy
40000200 g .text.memcpy 00000000 _bss_start
00002000 g .text 00000000 _startup
0000224c g F .init 00000000 _init
000023b4 g F .text.BootActivate 00000034 BootActivate
40000200 g .text.memcpy 00000000 _bss_end
00002040 g .text 00000000 Reset_Handler
00002788 g F .text.LedInit 00000020 LedInit
000020d8 g F .text 00000000 .hidden __aeabi_idiv
00002220 w F .text 00000004 .hidden __aeabi_ldiv0
00002600 g F .text.main 00000188 main
40003edc g *ABS* 00000000 _stack_end
000020d8 g F .text 00000128 .hidden __divsi3
00002274 g F .text.BootComInit 00000140 BootComInit
000025f8 g F .text.FIQ_ISR 00000004 FIQ_ISR
00002258 g F .fini 00000000 _fini
40000200 g .text.memcpy 00000000 _data
000027a8 g F .text.LedToggle 00000088 LedToggle
40000200 g .text.memcpy 00000000 _edata
40000200 g .text.memcpy 00000000 _end
000025fc g F .text.UNDEF_ISR 00000004 UNDEF_ISR
000025f4 g F .text.SWI_ISR 00000004 SWI_ISR
000023e8 g F .text.BootComCheckActivationRequest 000001d4 BootComCheckActivationRequest
00002220 w F .text 00000004 .hidden __aeabi_idiv0
000028a0 g F .text.TimerGet 00000010 TimerGet
00002200 g F .text 00000020 .hidden __aeabi_idivmod
00002830 g F .text.TimerInit 00000058 TimerInit

150
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.srec
View File

@ -1,150 +0,0 @@
S02B000062696E2F64656D6F70726F675F6F6C696D65785F6C70635F6C323239345F32306D687A2E73726563FD
S113200018F09FE518F09FE518F09FE518F09FE59C
S113201018F09FE50000A0E1F0FF1FE518F09FE530
S113202040200000FC250000F4250000FC250000F1
S1132030FC2500000000000000000000F82500005E
S113204078009FE5DBF021E300D0A0E1010C40E241
S1132050D7F021E300D0A0E1010C40E2D1F021E36C
S113206000D0A0E1010C40E2D2F021E300D0A0E1D5
S1132070010C40E2D3F021E300D0A0E1010C40E2E6
S1132080DFF021E300D0A0E134109FE534209FE588
S113209034309FE5030052E104009134040082349B
S11320A0FBFFFF3A0000A0E320109FE520209FE5FE
S11320B0020051E104008134FCFFFF3A4F0100EAC1
S11320C0DC3E00404C2200000002004000020040C0
S11320D00002004000020040000051E34300000AF7
S11320E001C020E000106142012051E22700000AF3
S11320F00030B0E100306042010053E12600009A54
S1132100020011E12800000A0E0211E38111A0016E
S11321100820A0030120A013010251E30300513160
S11321200112A0310222A031FAFFFF3A020151E369
S1132130030051318110A0318220A031FAFFFF3A0F
S11321400000A0E3010053E101304320020080219C
S1132150A10053E1A1304320A2008021210153E1D9
S11321602131432022018021A10153E1A1314320E7
S1132170A2018021000053E32222B0112112A011F8
S1132180EFFFFF1A00005CE3000060421EFF2FE136
S113219000003CE1000060421EFF2FE10000A0337C
S11321A0CC0FA001010080031EFF2FE1010851E3C1
S11321B02118A0211020A0230020A033010C51E3FA
S11321C02114A02108208222100051E32112A02111
S11321D004208222040051E303208282A120829001
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S1132374025085E2090055E1DCFFFF1A0020A0E3C6
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S113239400C002E000C000E0282200000022000087
S11323A4D8200000FF03000060EA0000004004E0BD
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Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/boot.c
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@ -1,443 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/boot.c
* \brief Demo program bootloader interface source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
#if (BOOT_COM_UART_ENABLE > 0)
static void BootComUartInit(void);
static void BootComUartCheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
** \return none.
**
****************************************************************************************/
void BootComInit(void)
{
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartInit();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
void BootComCheckActivationRequest(void)
{
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartCheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
/************************************************************************************//**
** \brief Bootloader activation function. Performs a software reset by configuring
** and triggering the watchdog.
** \return none.
**
****************************************************************************************/
void BootActivate(void)
{
#define WDEN_BIT (0x01) /* watchdog enable bit (set only) */
#define WDRESET_BIT (0x02) /* watchdog reset enable bit */
/* configure a short timeout. not really interesting as we won't be using it */
WDTC = 1024;
/* enable the watchdog and configure it such that a watchdog timeout causes a reset */
WDMOD = WDEN_BIT | WDRESET_BIT;
/* start the watchdog */
WDFEED = 0xAA;
WDFEED = 0x55;
/* write invalid feed sequence to cause an instant reset */
WDFEED = 0xAA;
WDFEED = 0x00;
} /*** end of BootActivate ***/
#if (BOOT_COM_UART_ENABLE > 0)
/****************************************************************************************
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Divisor latch access bit. */
#define UART_DLAB (0x80)
/** \brief 8 data and 1 stop bit, no parity. */
#define UART_MODE_8N1 (0x03)
/** \brief FIFO reset and RX FIFO 1 deep. */
#define UART_FIFO_RX1 (0x07)
/** \brief Receiver data ready. */
#define UART_RDR (0x01)
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static unsigned char UartReceiveByte(unsigned char *data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
static void BootComUartInit(void)
{
unsigned long baud_reg_value; /* baudrate register value */
/* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
PINSEL0 |= 0x05;
/* disable UART related interrupt generation. this driver works in polling mode */
U0IER = 0;
/* clear interrupt id register */
U0IIR = 0;
/* clear line status register */
U0LSR = 0;
/* set divisor latch DLAB = 1 so buadrate can be configured */
U0LCR = UART_DLAB;
/* Baudrate calculation:
* y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
* smartness to automatically round the value up/down using the following trick:
* y = x/n can round with y = (x + (n + 1)/2 ) / n
*/
baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
/* write the calculated baudrate selector value to the registers */
U0DLL = (unsigned char)baud_reg_value;
U0DLM = (unsigned char)(baud_reg_value >> 8);
/* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
U0LCR = UART_MODE_8N1;
/* enable and reset transmit and receive FIFO. necessary for UART operation */
U0FCR = UART_FIFO_RX1;
} /*** end of BootComUartInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComUartCheckActivationRequest(void)
{
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
static unsigned char xcpCtoRxLength;
static unsigned char xcpCtoRxInProgress = 0;
static unsigned long xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == 0)
{
/* store the message length when received */
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
{
/* check that the length has a valid value. it should not be 0 */
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_UART_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = 1;
/* reset packet data count */
xcpCtoRxLength = 0;
}
}
}
else
{
/* store the next packet byte */
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* done with cto packet reception */
xcpCtoRxInProgress = 0;
/* check if this was an XCP CONNECT command */
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + UART_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that this automatically
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = 0;
}
}
}
} /*** end of BootComUartCheckActivationRequest ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return 1 if a byte was received, 0 otherwise.
**
****************************************************************************************/
static unsigned char UartReceiveByte(unsigned char *data)
{
/* check if a new byte was received by means of the RDR-bit */
if((U0LSR & UART_RDR) != 0)
{
/* store the received byte */
data[0] = U0RBR;
/* inform caller of the newly received byte */
return 1;
}
/* inform caller that no new data was received */
return 0;
} /*** end of UartReceiveByte ***/
#endif /* BOOT_COM_UART_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Transmit buffer 1 idle. */
#define CAN_TBS1 (0x00000004)
/** \brief Transmit buffer 1 complete. */
#define CAN_TCS1 (0x00000008)
/** \brief Receive buffer release. */
#define CAN_RRB (0x04)
/** \brief Receive buffer status. */
#define CAN_RBS (0x01)
/** \brief Transmission request. */
#define CAN_TR (0x01)
/** \brief Select tx buffer 1 for transmit. */
#define CAN_STB1 (0x20)
/** \brief Frame format bit. 0 for 11-bit and 1 for 29-bit CAN identifiers. */
#define CAN_FF (0x80000000)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char tseg1; /**< CAN time segment 1 */
unsigned char tseg2; /**< CAN time segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
* 100%. This array contains possible and valid time quanta configurations with
* a sample point between 68..78%.
*/
static const tCanBusTiming canTiming[] =
{ /* TQ | TSEG1 | TSEG2 | SP */
/* ------------------------- */
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
{ 16, 8 } /* 25 | 16 | 8 | 68% */
};
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param btr Pointer to where the value for register CANxBTR will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned long *btr)
{
unsigned short prescaler;
unsigned char cnt;
/* loop through all possible time quanta configurations to find a match */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((BOOT_CPU_SYSTEM_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
{
/* compute the prescaler that goes with this TQ configuration */
prescaler = BOOT_CPU_SYSTEM_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
/* make sure the prescaler is valid */
if ( (prescaler > 0) && (prescaler <= 1024) )
{
/* store the prescaler and bustiming register value */
*btr = prescaler - 1;
*btr |= ((canTiming[cnt].tseg2 - 1) << 20) | ((canTiming[cnt].tseg1 - 1) << 16);
/* found a good bus timing configuration */
return 1;
}
}
}
/* could not find a good bus timing configuration */
return 0;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
unsigned long btr_reg_value;
/* configure acceptance filter for bypass mode so it receives all messages */
CANAFMR = 0x00000002L;
/* take CAN controller offline and go into reset mode */
CAN1MOD = 1;
/* disable all interrupts. driver only needs to work in polling mode */
CAN1IER = 0;
/* reset CAN controller status */
CAN1GSR = 0;
/* configure the bittiming */
if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btr_reg_value) == 1)
{
/* write the bittiming configuration to the register */
CAN1BTR = btr_reg_value;
}
/* enter normal operating mode and synchronize to the CAN bus */
CAN1MOD = 0;
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
unsigned long rxMsgId;
unsigned char data[2];
unsigned char idMatchFound = 0;
/* check if a new message was received */
if ((CAN1SR & CAN_RBS) == 0)
{
return;
}
/* read out the CAN message identifier */
rxMsgId = CAN1RID;
/* was is a 29-bit extended CAN identifier? */
if ((CAN1RFS & CAN_FF) != 0)
{
/* set mask bit. */
rxMsgId |= 0x80000000;
}
/* see if this is the message identifier that we are interested in */
if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
{
/* store the message data */
data[0] = (unsigned char)CAN1RDA;
data[1] = (unsigned char)(CAN1RDA >> 8);
/* set matched flag. */
idMatchFound = 1;
}
/* release the receive buffer */
CAN1CMR = CAN_RRB;
/* check if a match was found. */
if (idMatchFound == 1)
{
/* check if this was an XCP CONNECT command */
if ((data[0] == 0xff) && (data[1] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

40
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/boot.h
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@ -1,40 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/boot.h
* \brief Demo program bootloader interface header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BOOT_H
#define BOOT_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void BootComInit(void);
void BootComCheckActivationRequest(void);
void BootActivate(void);
#endif /* BOOT_H */
/*********************************** end of boot.h *************************************/

131
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/cstart.s
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/****************************************************************************************
| Description: demo program C-startup assembly file
| File Name: cstart.s
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* stack Sizes */
.set UND_STACK_SIZE, 0x00000100 /* stack for "undef" interrupts is 4 bytes */
.set ABT_STACK_SIZE, 0x00000100 /* stack for "abort" interrupts is 4 bytes */
.set FIQ_STACK_SIZE, 0x00000100 /* stack for "FIQ" interrupts is 4 bytes */
.set IRQ_STACK_SIZE, 0X00000100 /* stack for "IRQ" normal interrupts is 4 bytes */
.set SVC_STACK_SIZE, 0x00000100 /* stack for "SVC" supervisor mode is 4 bytes */
/* mode bits and Interrupt (I & F) flags in program status registers (PSRs) */
.set MODE_USR, 0x10 /* Normal User Mode */
.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
.set MODE_SYS, 0x1F /* System Running Priviledged OS Tasks Mode */
.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
.text
.arm
.global Reset_Handler
.global _startup
.func _startup
_startup:
/****************************************************************************************
* Interrupt vector table
****************************************************************************************/
_vectors: ldr PC, Reset_Addr /* point to Reset_Handler address */
ldr PC, Undef_Addr /* point to UNDEF_ISR address */
ldr PC, SWI_Addr /* point to SWI_ISR address */
ldr PC, PAbt_Addr /* point to UNDEF_ISR address */
ldr PC, DAbt_Addr /* point to UNDEF_ISR address */
nop /* reserved for OpenBLT checksum */
ldr PC, [PC,#-0xFF0] /* point to VIC table */
ldr PC, FIQ_Addr /* point to FIQ_ISR address */
Reset_Addr: .word Reset_Handler /* defined in this module below */
Undef_Addr: .word UNDEF_ISR /* defined in vectors.c */
SWI_Addr: .word SWI_ISR /* defined in vectors.c */
PAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
DAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
.word 0
IRQ_Addr: .word 0
FIQ_Addr: .word FIQ_ISR /* defined in vectors.c */
/****************************************************************************************
** NAME: Reset_Handler
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Reset interrupt service routine. Configures the stack for each mode,
** disables the IRQ and FIQ interrupts, initializes RAM and jumps to
** function main.
**
****************************************************************************************/
Reset_Handler:
/* setup a stack and disable interrupts for each mode */
ldr r0, =_stack_end
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
mov sp, r0
/* copy .data section (Copy from ROM to RAM) */
ldr R1, =_etext
ldr R2, =_data
ldr R3, =_edata
1: cmp R2, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo 1b
/* clear .bss section (Zero init) */
mov R0, #0
ldr R1, =_bss_start
ldr R2, =_bss_end
2: cmp R1, R2
strlo R0, [R1], #4
blo 2b
/* start bootloader program by jumping to main() */
b main
/*** end of Reset_Handler ***/
.endfunc
.end
/*********************************** end of cstart.s ***********************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/header.h
* \brief Generic header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef HEADER_H
#define HEADER_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include "../Boot/blt_conf.h" /* bootloader configuration */
#include "lpc2294.h" /* CPU register definitions */
#include "boot.h" /* bootloader interface driver */
#include "irq.h" /* IRQ driver */
#include "led.h" /* LED driver */
#include "timer.h" /* Timer driver */
#endif /* HEADER_H */
/*********************************** end of header.h ***********************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/irq.c
* \brief IRQ driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data definitions
****************************************************************************************/
/** \brief Interrupt status before disabling. Used for global interrupt en/disable. */
static unsigned long oldInterruptStatus;
/** \brief Interrupt nesting counter. Used for global interrupt en/disable. */
static unsigned char interruptNesting = 0;
/************************************************************************************//**
** \brief Obtains current value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \return CPSR value.
**
****************************************************************************************/
static unsigned long IrqGetCPSR(void)
{
unsigned long retval;
asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
return retval;
} /*** end of IrqGetCPSR ***/
/************************************************************************************//**
** \brief Update value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \param val CPSR value.
** \return none.
**
****************************************************************************************/
static void IrqSetCPSR(unsigned long val)
{
asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
} /*** end of IrqSetCPSR ***/
/************************************************************************************//**
** \brief Enables the generation IRQ interrupts. Typically called once during
** software startup after completion of the initialization.
** \return none.
**
****************************************************************************************/
void IrqInterruptEnable(void)
{
unsigned _cpsr;
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr & ~0x00000080);
} /*** end of IrqInterruptEnable ***/
/************************************************************************************//**
** \brief Disables the generation IRQ interrupts and stores information on
** whether or not the interrupts were already disabled before explicitly
** disabling them with this function. Normally used as a pair together
** with IrqInterruptRestore during a critical section.
** \return none.
**
****************************************************************************************/
void IrqInterruptDisable(void)
{
unsigned long _cpsr;
if (interruptNesting == 0)
{
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr | 0x00000080);
oldInterruptStatus = _cpsr;
}
interruptNesting++;
} /*** end of IrqInterruptDisable ***/
/************************************************************************************//**
** \brief Restore the generation IRQ interrupts to the setting it had prior to
** calling IrqInterruptDisable. Normally used as a pair together with
** IrqInterruptDisable during a critical section.
** \return none.
**
****************************************************************************************/
void IrqInterruptRestore(void)
{
unsigned _cpsr;
interruptNesting--;
if (interruptNesting == 0)
{
_cpsr = IrqGetCPSR();
IrqSetCPSR((_cpsr & ~0x00000080) | (oldInterruptStatus & 0x00000080));
}
} /*** end of IrqInterruptRestore ***/
/*********************************** end of irq.c **************************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/irq.h
* \brief IRQ driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef IRQ_H
#define IRQ_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void IrqInterruptEnable(void);
void IrqInterruptDisable(void);
void IrqInterruptRestore(void);
#endif /* IRQ_H */
/*********************************** end of irq.h **************************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/led.c
* \brief LED driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Toggle interval time in milliseconds. */
#define LED_TOGGLE_MS (500)
/************************************************************************************//**
** \brief Initializes the LED.
** \return none.
**
****************************************************************************************/
void LedInit(void)
{
/* set io pins for led P1.23 */
IO1DIR |= 0x00800000;
/* turn the led off */
IO1SET = 0x00800000;
} /*** end of LedInit ***/
/************************************************************************************//**
** \brief Toggles the LED at a fixed time interval.
** \return none.
**
****************************************************************************************/
void LedToggle(void)
{
static unsigned char led_toggle_state = 0;
static unsigned long timer_counter_last = 0;
unsigned long timer_counter_now;
/* check if toggle interval time passed */
timer_counter_now = TimerGet();
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
{
/* not yet time to toggle */
return;
}
/* determine toggle action */
if (led_toggle_state == 0)
{
led_toggle_state = 1;
/* turn the LED on */
IO1CLR = 0x00800000;
}
else
{
led_toggle_state = 0;
/* turn the LED off */
IO1SET = 0x00800000;
}
/* store toggle time to determine next toggle interval */
timer_counter_last = timer_counter_now;
} /*** end of LedToggle ***/
/*********************************** end of led.c **************************************/

39
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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/led.h
* \brief LED driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedInit(void);
void LedToggle(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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/****************************************************************************************
| Description: NXP LPC2294 register definitions
| File Name: lpc2294.h
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
#ifndef LPC2294_H
#define LPC2294_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/* EXTERNAL MEMORY CONTROLLER (EMC) */
#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
/* External Interrupts */
#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
/* SMemory mapping control. */
#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
/* Phase Locked Loop (PLL) */
#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
/* Power Control */
#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
/* VPB Divider */
#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
/* Memory Accelerator Module (MAM) */
#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
/* Vectored Interrupt Controller (VIC) */
#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
/* Pin Connect Block */
#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
/* General Purpose Input/Output (GPIO) */
#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define U0RBR (*((volatile unsigned char *) 0xE000C000))
#define U0THR (*((volatile unsigned char *) 0xE000C000))
#define U0IER (*((volatile unsigned char *) 0xE000C004))
#define U0IIR (*((volatile unsigned char *) 0xE000C008))
#define U0FCR (*((volatile unsigned char *) 0xE000C008))
#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
#define U0LSR (*((volatile unsigned char *) 0xE000C014))
#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
#define U0DLL (*((volatile unsigned char *) 0xE000C000))
#define U0DLM (*((volatile unsigned char *) 0xE000C004))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define U1RBR (*((volatile unsigned char *) 0xE0010000))
#define U1THR (*((volatile unsigned char *) 0xE0010000))
#define U1IER (*((volatile unsigned char *) 0xE0010004))
#define U1IIR (*((volatile unsigned char *) 0xE0010008))
#define U1FCR (*((volatile unsigned char *) 0xE0010008))
#define U1LCR (*((volatile unsigned char *) 0xE001000C))
#define U1MCR (*((volatile unsigned char *) 0xE0010010))
#define U1LSR (*((volatile unsigned char *) 0xE0010014))
#define U1MSR (*((volatile unsigned char *) 0xE0010018))
#define U1SCR (*((volatile unsigned char *) 0xE001001C))
#define U1DLL (*((volatile unsigned char *) 0xE0010000))
#define U1DLM (*((volatile unsigned char *) 0xE0010004))
/* I2C (8/16 bit data bus) */
#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
#define I2STAT (*((volatile unsigned long *) 0xE001C004))
#define I2DAT (*((volatile unsigned long *) 0xE001C008))
#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
/* SPI (Serial Peripheral Interface) */
/* only for lpc210x*/
#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
/* Timer 0 */
#define T0IR (*((volatile unsigned long *) 0xE0004000))
#define T0TCR (*((volatile unsigned long *) 0xE0004004))
#define T0TC (*((volatile unsigned long *) 0xE0004008))
#define T0PR (*((volatile unsigned long *) 0xE000400C))
#define T0PC (*((volatile unsigned long *) 0xE0004010))
#define T0MCR (*((volatile unsigned long *) 0xE0004014))
#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
#define T0CCR (*((volatile unsigned long *) 0xE0004028))
#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
#define T0EMR (*((volatile unsigned long *) 0xE000403C))
/* Timer 1 */
#define T1IR (*((volatile unsigned long *) 0xE0008000))
#define T1TCR (*((volatile unsigned long *) 0xE0008004))
#define T1TC (*((volatile unsigned long *) 0xE0008008))
#define T1PR (*((volatile unsigned long *) 0xE000800C))
#define T1PC (*((volatile unsigned long *) 0xE0008010))
#define T1MCR (*((volatile unsigned long *) 0xE0008014))
#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
#define T1CCR (*((volatile unsigned long *) 0xE0008028))
#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
#define T1EMR (*((volatile unsigned long *) 0xE000803C))
/* Pulse Width Modulator (PWM) */
#define PWMIR (*((volatile unsigned long *) 0xE0014000))
#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
#define PWMTC (*((volatile unsigned long *) 0xE0014008))
#define PWMPR (*((volatile unsigned long *) 0xE001400C))
#define PWMPC (*((volatile unsigned long *) 0xE0014010))
#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
#define PWMLER (*((volatile unsigned long *) 0xE0014050))
/* A/D CONVERTER */
#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
/* Real Time Clock */
#define ILR (*((volatile unsigned char *) 0xE0024000))
#define CTC (*((volatile unsigned short*) 0xE0024004))
#define CCR (*((volatile unsigned char *) 0xE0024008))
#define CIIR (*((volatile unsigned char *) 0xE002400C))
#define AMR (*((volatile unsigned char *) 0xE0024010))
#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
#define SEC (*((volatile unsigned char *) 0xE0024020))
#define MIN (*((volatile unsigned char *) 0xE0024024))
#define HOUR (*((volatile unsigned char *) 0xE0024028))
#define DOM (*((volatile unsigned char *) 0xE002402C))
#define DOW (*((volatile unsigned char *) 0xE0024030))
#define DOY (*((volatile unsigned short*) 0xE0024034))
#define MONTH (*((volatile unsigned char *) 0xE0024038))
#define YEAR (*((volatile unsigned short*) 0xE002403C))
#define ALSEC (*((volatile unsigned char *) 0xE0024060))
#define ALMIN (*((volatile unsigned char *) 0xE0024064))
#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
#define ALDOM (*((volatile unsigned char *) 0xE002406C))
#define ALDOW (*((volatile unsigned char *) 0xE0024070))
#define ALDOY (*((volatile unsigned short*) 0xE0024074))
#define ALMON (*((volatile unsigned char *) 0xE0024078))
#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
#define PREINT (*((volatile unsigned short*) 0xE0024080))
#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
/* Watchdog */
#define WDMOD (*((volatile unsigned char *) 0xE0000000))
#define WDTC (*((volatile unsigned long *) 0xE0000004))
#define WDFEED (*((volatile unsigned char *) 0xE0000008))
#define WDTV (*((volatile unsigned long *) 0xE000000C))
#endif /* LPC2294_H */
/*********************************** end of lpc2294.h **********************************/

144
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/main.c
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@ -1,144 +0,0 @@
/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/main.c
* \brief Demo program application source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* initialize the microcontroller */
Init();
/* initialize the bootloader interface */
BootComInit();
/* start the infinite program loop */
while (1)
{
/* toggle LED with a fixed frequency */
LedToggle();
/* check for bootloader activation request */
BootComCheckActivationRequest();
}
/* program should never get here */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
** configured equal to Fpll. The GPIO pin of the status LED is configured
** as digital output.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
unsigned char m_sel; /* pll multiplier register value */
unsigned char pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
unsigned char p_sel_cnt; /* loop counter to find p_sel */
unsigned long f_cco; /* current controller oscillator */
/* calculate MSEL: M = round(Fcclk / Fosc) */
m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
BOOT_CPU_XTAL_SPEED_KHZ;
/* value for the PLLCFG register is -1 */
m_sel--;
/* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
for (p_sel_cnt=0; p_sel_cnt<sizeof(pll_dividers)/sizeof(pll_dividers[0]); p_sel_cnt++)
{
/* check f_cco with this pll divider */
f_cco = BOOT_CPU_SYSTEM_SPEED_KHZ * 2 * pll_dividers[p_sel_cnt];
if ( (f_cco >= 156000) && (f_cco <= 320000) )
{
/* found a valid pll divider value */
break;
}
}
/* set multiplier and divider values */
PLLCFG = (p_sel_cnt << 5) | m_sel;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable the PLL */
PLLCON = 0x1;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* wait for the PLL to lock to set frequency */
while(!(PLLSTAT & 0x400)) { ; }
/* connect the PLL as the clock source */
PLLCON = 0x3;
PLLFEED = 0xAA;
PLLFEED = 0x55;
/* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
* Fcclk >= 60 MHz: 4 clock cycles
* Fcclk >= 40 MHz: 3 clock cycles
* Fcclk >= 20 MHz: 2 clock cycles
* Fcclk < 20 MHz: 1 clock cycle
*/
MAMCR = 0x0;
#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
MAMTIM = 4;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
MAMTIM = 3;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
MAMTIM = 2;
#else
MAMTIM = 1;
#endif
MAMCR = 0x2;
/* setting peripheral Clock (pclk) to System Clock (cclk) */
VPBDIV = 0x1;
/* init the led driver */
LedInit();
/* init the timer driver */
TimerInit();
/* enable IRQ's */
IrqInterruptEnable();
} /*** end of Init ***/
/*********************************** end of main.c *************************************/

162
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/makefile
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@ -1,162 +0,0 @@
#****************************************************************************************
#| Description: Makefile for GNU ARM Embedded toolchain.
#| File Name: makefile
#|
#|---------------------------------------------------------------------------------------
#| C O P Y R I G H T
#|---------------------------------------------------------------------------------------
#| Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
#|
#|---------------------------------------------------------------------------------------
#| L I C E N S E
#|---------------------------------------------------------------------------------------
#| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
#| modify it under the terms of the GNU General Public License as published by the Free
#| Software Foundation, either version 3 of the License, or (at your option) any later
#| version.
#|
#| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
#| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
#| PURPOSE. See the GNU General Public License for more details.
#|
#| You have received a copy of the GNU General Public License along with OpenBLT. It
#| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
#|
#****************************************************************************************
SHELL = sh
#|--------------------------------------------------------------------------------------|
#| Configure project name |
#|--------------------------------------------------------------------------------------|
PROJ_NAME=demoprog_olimex_lpc_l2294_20mhz
#|--------------------------------------------------------------------------------------|
#| Configure tool path |
#|--------------------------------------------------------------------------------------|
TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/
#|--------------------------------------------------------------------------------------|
#| Collect project files |
#|--------------------------------------------------------------------------------------|
# Recursive wildcard function implementation. Example usages:
# $(call rwildcard, , *.c *.h)
# --> Returns all *.c and *.h files in the current directory and below
# $(call rwildcard, /lib/, *.c)
# --> Returns all *.c files in the /lib directory and below
rwildcard = $(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)))
# Collect all application files in the current directory and its subdirectories
PROJ_FILES = $(call rwildcard, , *.c *.h *.s)
#|--------------------------------------------------------------------------------------|
#| Toolchain binaries |
#|--------------------------------------------------------------------------------------|
RM = rm
CC = $(TOOL_PATH)arm-none-eabi-gcc
LN = $(TOOL_PATH)arm-none-eabi-gcc
OC = $(TOOL_PATH)arm-none-eabi-objcopy
OD = $(TOOL_PATH)arm-none-eabi-objdump
AS = $(TOOL_PATH)arm-none-eabi-gcc
SZ = $(TOOL_PATH)arm-none-eabi-size
#|--------------------------------------------------------------------------------------|
#| Filter project files
#|--------------------------------------------------------------------------------------|
PROJ_ASRCS = $(filter %.s,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file))))
#|--------------------------------------------------------------------------------------|
#| Set important path variables |
#|--------------------------------------------------------------------------------------|
VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :)
OBJ_PATH = obj
BIN_PATH = bin
INC_PATH = $(patsubst %/,%,$(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file))))))
INC_PATH += -I./lib
LIB_PATH =
#|--------------------------------------------------------------------------------------|
#| Options for toolchain binaries |
#|--------------------------------------------------------------------------------------|
STDFLAGS = -mcpu=arm7tdmi-s -mlong-calls -fno-strict-aliasing
STDFLAGS += -Wno-unused-but-set-variable
STDFLAGS += -fdata-sections -ffunction-sections -Wall -g3
OPTFLAGS = -O1
CFLAGS = $(STDFLAGS) $(OPTFLAGS)
CFLAGS += -DDEBUG -Dgcc
CFLAGS += $(INC_PATH)
AFLAGS = $(CFLAGS)
LFLAGS = $(STDFLAGS) $(OPTFLAGS)
LFLAGS += -Wl,-script="memory.x" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map
LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH)
OFLAGS = -O srec
ODFLAGS = -x
SZFLAGS = -B -d
RMFLAGS = -f
#|--------------------------------------------------------------------------------------|
#| Specify library files |
#|--------------------------------------------------------------------------------------|
LIBS =
#|--------------------------------------------------------------------------------------|
#| Define targets |
#|--------------------------------------------------------------------------------------|
AOBJS = $(patsubst %.s,%.o,$(PROJ_ASRCS))
COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS))
#|--------------------------------------------------------------------------------------|
#| Make ALL |
#|--------------------------------------------------------------------------------------|
.PHONY: all
all: $(BIN_PATH)/$(PROJ_NAME).srec
$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf
@$(OC) $< $(OFLAGS) $@
@$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map
@echo +++ Summary of memory consumption:
@$(SZ) $(SZFLAGS) $<
@echo +++ Build complete [$(notdir $@)]
$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS)
@echo +++ Linking [$(notdir $@)]
@$(LN) $(LFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS)
#|--------------------------------------------------------------------------------------|
#| Compile and assemble |
#|--------------------------------------------------------------------------------------|
$(AOBJS): %.o: %.s $(PROJ_CHDRS)
@echo +++ Assembling [$(notdir $<)]
@$(AS) $(AFLAGS) -c $< -o $(OBJ_PATH)/$(@F)
$(COBJS): %.o: %.c $(PROJ_CHDRS)
@echo +++ Compiling [$(notdir $<)]
@$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F)
#|--------------------------------------------------------------------------------------|
#| Make CLEAN |
#|--------------------------------------------------------------------------------------|
.PHONY: clean
clean:
@echo +++ Cleaning build environment
@$(RM) $(RMFLAGS) $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file))
@$(RM) $(RMFLAGS) $(foreach file,$(COBJS),$(OBJ_PATH)/$(file))
@$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file)))
@$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map
@$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).srec
@echo +++ Clean complete

51
Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/memory.x
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@ -1,51 +0,0 @@
/* identify the Entry Point */
ENTRY(_startup)
/* specify the LPC2294 memory areas */
MEMORY
{
flash : ORIGIN = 0x00002000, LENGTH = 240K /* FLASH ROM for the user program */
ram_vectors(A) : ORIGIN = 0x40000000, LENGTH = 64 /* RAM vectors of the user program */
ram_monitor(A) : ORIGIN = 0x40000040, LENGTH = 224 /* variables used by Philips RealMonitor */
ram_isp_low(A) : ORIGIN = 0x40000120, LENGTH = 224 /* variables used by Philips ISP bootloader */
ram : ORIGIN = 0x40000200, LENGTH = 15584 /* free RAM area */
ram_isp_high(A) : ORIGIN = 0x40003EE0, LENGTH = 288 /* variables used by Philips ISP bootloader */
}
/* define a global symbol _stack_end, placed at the very end of unused RAM */
_stack_end = 0x40003EE0 - 4;
/* now define the output sections */
SECTIONS
{
. = 0; /* set location counter to address zero */
startup : { *(.startup)} >flash /* the startup code goes into FLASH */
.text : /* collect all sections that should go into FLASH after startup */
{
*(.text) /* all .text sections (code) */
*(.rodata) /* all .rodata sections (constants, strings, etc.) */
*(.rodata*) /* all .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* all .glue_7 sections (no idea what these are) */
*(.glue_7t) /* all .glue_7t sections (no idea what these are) */
_etext = .; /* define a global symbol _etext just after the last code byte */
} >flash /* put all the above into FLASH */
.data : /* collect all initialized .data sections that go into RAM */
{
_data = .; /* create a global symbol marking the start of the .data section */
*(.data) /* all .data sections */
_edata = .; /* define a global symbol marking the end of the .data section */
} >ram AT >flash /* put all the above into RAM (but load the LMA copy into FLASH) */
.bss : /* collect all uninitialized .bss sections that go into RAM */
{
_bss_start = .; /* define a global symbol marking the start of the .bss section */
*(.bss) /* all .bss sections */
} >ram /* put all the above in RAM (it will be cleared in the startup code */
. = ALIGN(4); /* advance location counter to the next 32-bit boundary */
_bss_end = . ; /* define a global symbol marking the end of the .bss section */
}
_end = .; /* define a global symbol marking the end of application RAM */

4
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# Ignore everything in this directory
*
# Except this file
!.gitignore

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/**
\defgroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC User Program
\ingroup ARM7_LPC2000_Olimex_LPC_L2294_GCC
\brief User Program.
\details The intention of the demo user program is two-fold. (1) To test the
bootloader, you need some sort of firmware to see if you can perform a
firmware update with the bootloader. This program can be used for this
purpose. (2) To make firmware programmable by the bootloader, a few
adjustments to the firmware are required. The demo user program serves as an
example for how these adjustments can be implemented. Additional details on
this subject can be found in the port specifics documentation, which is
available at:
https://www.feaser.com/openblt/doku.php?id=manual:ports:arm7_lpc2000.
*/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/timer.c
* \brief Timer driver source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static unsigned long millisecond_counter;
/****************************************************************************************
* External functions
****************************************************************************************/
extern void TIMER0_ISR(void);
/************************************************************************************//**
** \brief Initializes the timer.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* configure timer0 as 1 ms software output compare */
T0MR0 = BOOT_CPU_SYSTEM_SPEED_KHZ-1;
/* enable interrupt and automatic reset upon compare */
T0MCR = 0x01 | 0x02;
/* enable the output compare */
T0TCR = 0x01;
/* set the interrupt service routine for the output compare event */
VICVectAddr0 = (unsigned long)TIMER0_ISR;
/* connect vectored IRQ slot 0 to Timer0's channel 4 */
VICVectCntl0 = 0x20 | 4;
/* enable the timer0 interrupt */
VICIntEnable = 0x10;
/* reset the millisecond counter */
TimerSet(0);
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Updates the millisecond timer. Should be called every millisecond by
** the timer interrupt service routine.
** \return none.
**
****************************************************************************************/
void TimerUpdate(void)
{
/* increment the millisecond counter */
millisecond_counter++;
} /*** end of TimerUpdate ***/
/************************************************************************************//**
** \brief Sets the initial counter value of the millisecond timer.
** \param timer_value initialize value of the millisecond timer.
** \return none.
**
****************************************************************************************/
void TimerSet(unsigned long timer_value)
{
/* set the millisecond counter */
millisecond_counter = timer_value;
} /*** end of TimerSet ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
unsigned long TimerGet(void)
{
/* read and return the millisecond counter value */
return millisecond_counter;
} /*** end of TimerGet ***/
/*********************************** end of timer.c ************************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/timer.h
* \brief Timer driver header file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TIMER_H
#define TIMER_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void TimerInit(void);
void TimerUpdate(void);
void TimerSet(unsigned long timer_value);
unsigned long TimerGet(void);
#endif /* TIMER_H */
/*********************************** end of timer.h ************************************/

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/************************************************************************************//**
* \file Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Prog/vectors.c
* \brief Demo program interrupt vectors source file.
* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void __attribute__ ((interrupt("IRQ"))) TIMER0_ISR(void);
void __attribute__ ((interrupt("SWI"))) SWI_ISR(void);
void __attribute__ ((interrupt("FIQ"))) FIQ_ISR(void);
void __attribute__ ((interrupt("UNDEF"))) UNDEF_ISR(void);
/************************************************************************************//**
** \brief Timer0 exception routine.
** \return none.
**
****************************************************************************************/
void TIMER0_ISR(void)
{
/* clear the interrupt flag */
T0IR = 0x01;
/* acknowledge interrupt */
VICVectAddr = 0;
/* process time tick */
TimerUpdate();
} /*** end of TIMER0_ISR ***/
/************************************************************************************//**
** \brief SWI exception routine.
** \return none.
**
****************************************************************************************/
void SWI_ISR(void)
{
/* unexpected interrupt so halt program */
for (;;) { ; }
} /*** end of SWI_ISR ***/
/************************************************************************************//**
** \brief FIQ exception routine.
** \return none.
**
****************************************************************************************/
void FIQ_ISR(void)
{
/* unexpected interrupt so halt program */
for (;;) { ; }
} /*** end of FIQ_ISR ***/
/************************************************************************************//**
** \brief UNDEF exception routine.
** \return none.
**
****************************************************************************************/
void UNDEF_ISR(void)
{
/* unexpected interrupt so halt program */
for (;;) { ; }
} /*** end of UNDEF_ISR ***/
/*********************************** end of vectors.c **********************************/

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/**
\defgroup ARM7_LPC2000_Olimex_LPC_L2294_GCC Demo for Olimex LPC-L2294/GCC
\ingroup Demos
\brief Preconfigured programs for the Olimex LPC-L2294 and the GCC compiler.
\details For detailed getting started instructions, refer to:
https://feaser.com/openblt/doku.php?id=manual:demos:olimex_lpc_l2294_gcc.
*/

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/************************************************************************************//**
* \file Source/ARM7_LPC2000/GCC/cpu_comp.c
* \brief Bootloader cpu module source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/************************************************************************************//**
** \brief Obtains current value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \return CPSR value.
**
****************************************************************************************/
static blt_int32u IrqGetCPSR(void)
{
blt_int32u retval;
asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
return retval;
} /*** end of IrqGetCPSR ***/
/************************************************************************************//**
** \brief Update value of CPSR CPU register. Derived from a sample by R O
** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
** or commercial purposes.
** \param val CPSR value.
** \return none.
**
****************************************************************************************/
static void IrqSetCPSR(blt_int32u val)
{
asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
} /*** end of IrqSetCPSR ***/
/************************************************************************************//**
** \brief Disable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqDisable(void)
{
blt_int32u _cpsr;
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr | 0x00000080);
} /*** end of CpuIrqDisable ***/
/************************************************************************************//**
** \brief Enable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqEnable(void)
{
blt_int32u _cpsr;
_cpsr = IrqGetCPSR();
IrqSetCPSR(_cpsr & ~0x00000080);
} /*** end of CpuIrqEnable ***/
/*********************************** end of cpu_comp.c *********************************/

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/************************************************************************************//**
* \file Source/ARM7_LPC2000/can.c
* \brief Bootloader CAN communication interface source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout for transmitting a CAN message in milliseconds. */
#define CAN_MSG_TX_TIMEOUT_MS (50u)
/** \brief Transmit buffer 1 idle bit. */
#define CAN_TBS1 (0x00000004)
/** \brief Transmit buffer 1 complete bit. */
#define CAN_TCS1 (0x00000008)
/** \brief Receive buffer release bit. */
#define CAN_RRB (0x04)
/** \brief Receive buffer status bit. */
#define CAN_RBS (0x01)
/** \brief Transmission request bit. */
#define CAN_TR (0x01)
/** \brief Select tx buffer 1 for transmit bit. */
#define CAN_STB1 (0x20)
/** \brief Frame format bit. 0 for 11-bit and 1 for 29-bit CAN identifiers. */
#define CAN_FF (0x80000000)
/****************************************************************************************
* Register definitions
****************************************************************************************/
/** \brief CANAFMR CAN controller register. */
#define CANAFMR (*((volatile blt_int8u *) 0xE003C000))
/** \brief CAN1MOD CAN controller register. */
#define CAN1MOD (*((volatile blt_int32u *) 0xE0044000))
/** \brief CAN1IER CAN controller register. */
#define CAN1IER (*((volatile blt_int32u *) 0xE0044010))
/** \brief CAN1GSR CAN controller register. */
#define CAN1GSR (*((volatile blt_int32u *) 0xE0044008))
/** \brief CAN1BTR CAN controller register. */
#define CAN1BTR (*((volatile blt_int32u *) 0xE0044014))
/** \brief CAN1TFI1 CAN controller register. */
#define CAN1TFI1 (*((volatile blt_int32u *) 0xE0044030))
/** \brief CAN1TID1 CAN controller register. */
#define CAN1TID1 (*((volatile blt_int32u *) 0xE0044034))
/** \brief CAN1TDA1 CAN controller register. */
#define CAN1TDA1 (*((volatile blt_int32u *) 0xE0044038))
/** \brief CAN1TDB1 CAN controller register. */
#define CAN1TDB1 (*((volatile blt_int32u *) 0xE004403C))
/** \brief CAN1CMR CAN controller register. */
#define CAN1CMR (*((volatile blt_int32u *) 0xE0044004))
/** \brief CAN1SR CAN controller register. */
#define CAN1SR (*((volatile blt_int32u *) 0xE004401C))
/** \brief CAN1RFS CAN controller register. */
#define CAN1RFS (*((volatile blt_int32u *) 0xE0044020))
/** \brief CAN1RID CAN controller register. */
#define CAN1RID (*((volatile blt_int32u *) 0xE0044024))
/** \brief CAN1RDA CAN controller register. */
#define CAN1RDA (*((volatile blt_int32u *) 0xE0044028))
/** \brief CAN1RDB CAN controller register. */
#define CAN1RDB (*((volatile blt_int32u *) 0xE004402C))
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
blt_int8u tseg1; /**< CAN time segment 1 */
blt_int8u tseg2; /**< CAN time segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
* 100%. This array contains possible and valid time quanta configurations with
* a sample point between 68..78%.
*/
static const tCanBusTiming canTiming[] =
{
/* TQ | TSEG1 | TSEG2 | SP */
/* ------------------------- */
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
{ 16, 8 } /* 25 | 16 | 8 | 68% */
};
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param btr Pointer to where the value for register CANxBTR will be stored.
** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
** otherwise.
**
****************************************************************************************/
static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int32u *btr)
{
blt_int16u prescaler;
blt_int8u cnt;
/* loop through all possible time quanta configurations to find a match */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((BOOT_CPU_SYSTEM_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
{
/* compute the prescaler that goes with this TQ configuration */
prescaler = BOOT_CPU_SYSTEM_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
/* make sure the prescaler is valid */
if ((prescaler > 0) && (prescaler <= 1024))
{
/* store the prescaler and bustiming register value */
*btr = prescaler - 1;
*btr |= ((canTiming[cnt].tseg2 - 1) << 20) | ((canTiming[cnt].tseg1 - 1) << 16);
/* found a good bus timing configuration */
return BLT_TRUE;
}
}
}
/* could not find a good bus timing configuration */
return BLT_FALSE;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
** \return none.
**
****************************************************************************************/
void CanInit(void)
{
blt_bool result;
blt_int32u btr_reg_value=0;
/* the current implementation supports CAN1, which has channel index 0. throw an
* assertion error in case a different CAN channel is configured.
*/
ASSERT_CT(BOOT_COM_CAN_CHANNEL_INDEX == 0);
/* configure acceptance filter for bypass mode so it receives all messages */
CANAFMR = 0x00000002L;
/* take CAN controller offline and go into reset mode */
CAN1MOD = 1;
/* disable all interrupts. driver only needs to work in polling mode */
CAN1IER = 0;
/* reset CAN controller status */
CAN1GSR = 0;
/* configure the bittiming */
result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btr_reg_value);
/* check that a valid baudrate configuration was found */
ASSERT_RT(result == BLT_TRUE);
/* write the bittiming configuration to the register */
CAN1BTR = btr_reg_value;
/* enter normal operating mode and synchronize to the CAN bus */
CAN1MOD = 0;
} /*** end of CanInit ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
{
blt_int32u timeout;
/* check that transmit buffer 1 is ready to accept a new message */
ASSERT_RT((CAN1SR & CAN_TBS1) != 0);
/* write dlc and configure message as a standard message with 11-bit identifier */
CAN1TFI1 = (len << 16);
/* write the message identifier */
CAN1TID1 = BOOT_COM_CAN_TX_MSG_ID;
/* is it a 29-bit CAN identifier? */
if ( (BOOT_COM_CAN_TX_MSG_ID & 0x80000000) != 0)
{
/* configure identifier as 29-bit extended. */
CAN1TFI1 |= CAN_FF;
/* Reset the mask bit. */
CAN1TID1 &= ~0x80000000;
}
/* write the first set of 4 data bytes */
CAN1TDA1 = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
/* write the second set of 4 data bytes */
CAN1TDB1 = (data[7] << 24) + (data[6] << 16) + (data[5] << 8) + data[4];
/* write transmission request for transmit buffer 1 */
CAN1CMR = CAN_TR | CAN_STB1;
/* set timeout time to wait for transmission completion */
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
/* wait for transmit completion */
while ((CAN1SR & CAN_TCS1) == 0)
{
/* keep the watchdog happy */
CopService();
/* break loop upon timeout. this would indicate a hardware failure or no other
* nodes connected to the bus.
*/
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanTransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \param len Pointer where the length of the packet is to be stored.
** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool CanReceivePacket(blt_int8u *data, blt_int8u *len)
{
blt_int32u rxMsgId;
blt_int8u rxMsgDlc;
blt_bool result = BLT_FALSE;
/* check if a new message was received */
if ((CAN1SR & CAN_RBS) != 0)
{
/* read out the CAN message identifier */
rxMsgId = CAN1RID;
/* was is a 29-bit extended CAN identifier? */
if ((CAN1RFS & CAN_FF) != 0)
{
/* set mask bit. */
rxMsgId |= 0x80000000;
}
/* see if this is the message identifier that we are interested in */
if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
{
/* store the message data length */
rxMsgDlc = ((blt_int8u)(CAN1RFS >> 16)) & 0x0Fu;
if (rxMsgDlc > 8)
{
rxMsgDlc = 8;
}
*len = rxMsgDlc;
/* store the message data */
data[0] = (blt_int8u)CAN1RDA;
data[1] = (blt_int8u)(CAN1RDA >> 8);
data[2] = (blt_int8u)(CAN1RDA >> 16);
data[3] = (blt_int8u)(CAN1RDA >> 24);
data[4] = (blt_int8u)CAN1RDB;
data[5] = (blt_int8u)(CAN1RDB >> 8);
data[6] = (blt_int8u)(CAN1RDB >> 16);
data[7] = (blt_int8u)(CAN1RDB >> 24);
/* update the result. */
result = BLT_TRUE;
}
/* release the receive buffer */
CAN1CMR = CAN_RRB;
}
/* give the result back to the caller. */
return result;
} /*** end of CanReceivePacket ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of can.c **************************************/

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/************************************************************************************//**
* \file Source/ARM7_LPC2000/cpu.c
* \brief Bootloader cpu module source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Start address of the user program vector table. */
#define CPU_USER_PROG_VECTORS_START_ADDR ((blt_addr)NvmGetUserProgBaseAddress())
/** \brief Start address of the RAM vector table. */
#define CPU_RAM_VECTORS_START_ADDR ((blt_addr)0x40000000)
/** \brief Size of the vector table in bytes. */
#define CPU_VECTORS_TABLE_SIZE (64)
/****************************************************************************************
* Register definitions
****************************************************************************************/
/** \brief MEMMAP microcontroller register. */
#define MEMMAP (*((volatile blt_int32u *) 0xE01FC040))
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
extern blt_bool CpuUserProgramStartHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the CPU module.
** \return none.
**
****************************************************************************************/
void CpuInit(void)
{
/* bootloader runs in polling mode so disable the global interrupts. this is done for
* safety reasons. if the bootloader was started from a running user program, it could
* be that the user program did not properly disable the interrupt generation of
* peripherals. */
CpuIrqDisable();
} /*** end of CpuInit ***/
/************************************************************************************//**
** \brief Starts the user program, if one is present. In this case this function
** does not return.
** \return none.
**
****************************************************************************************/
void CpuStartUserProgram(void)
{
void (*pProgResetHandler)(void);
/* check if a user program is present by verifying the checksum */
if (NvmVerifyChecksum() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* not a valid user program so it cannot be started */
return;
}
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/* invoke callback */
if (CpuUserProgramStartHook() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* callback requests the user program to not be started */
return;
}
#endif
#if (BOOT_COM_ENABLE > 0)
/* release the communication interface */
ComFree();
#endif
/* reset the timer */
TimerReset();
/* copy the user program's interrupt vector table to RAM */
CpuMemCopy(CPU_RAM_VECTORS_START_ADDR, CPU_USER_PROG_VECTORS_START_ADDR, \
CPU_VECTORS_TABLE_SIZE);
/* select RAM vector table */
MEMMAP = 0x02;
/* set the address where the bootloader needs to jump to */
pProgResetHandler = (void *)CPU_RAM_VECTORS_START_ADDR;
/* start the user program by activating its reset interrupt service routine */
pProgResetHandler();
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* theoretically, the code never gets here because the user program should now be
* running and the previous function call should not return. In case it did return
* for whatever reason, make sure all communication interfaces are initialized so that
* firmware updates can be started.
*/
ComDeferredInit();
#endif
} /*** end of CpuStartUserProgram ***/
/************************************************************************************//**
** \brief Copies data from the source to the destination address.
** \param dest Destination address for the data.
** \param src Source address of the data.
** \param len length of the data in bytes.
** \return none.
**
****************************************************************************************/
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
{
blt_int8u *from, *to;
/* set casted pointers */
from = (blt_int8u *)src;
to = (blt_int8u *)dest;
/* copy all bytes from source address to destination address */
while (len-- > 0)
{
/* store byte value from source to destination */
*to++ = *from++;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemCopy ***/
/************************************************************************************//**
** \brief Sets the bytes at the destination address to the specified value.
** \param dest Destination address for the data.
** \param value Value to write.
** \param len Number of bytes to write.
** \return none.
**
****************************************************************************************/
void CpuMemSet(blt_addr dest, blt_int8u value, blt_int16u len)
{
blt_int8u *to;
/* set casted pointer */
to = (blt_int8u *)dest;
/* set all bytes at the destination address to the specified value */
while (len-- > 0)
{
/* set byte value */
*to++ = value;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemSet ***/
/*********************************** end of cpu.c **************************************/

810
Target/Source/ARM7_LPC2000/flash.c
View File

@ -1,810 +0,0 @@
/************************************************************************************//**
* \file Source/ARM7_LPC2000/GCC/flash.c
* \brief Bootloader flash driver source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Value for an invalid flash sector. */
#define FLASH_INVALID_SECTOR (0xff)
/** \brief Value for an invalid flash address. */
#define FLASH_INVALID_ADDRESS (0xffffffff)
/** \brief Standard size of a flash block for writing. */
#define FLASH_WRITE_BLOCK_SIZE (512)
/** \brief Total numbers of sectors in array flashLayout[]. */
#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
/** \brief End address of the bootloader programmable flash. */
#define FLASH_END_ADDRESS (flashLayout[FLASH_TOTAL_SECTORS-1].sector_start + \
flashLayout[FLASH_TOTAL_SECTORS-1].sector_size - 1)
/** \brief Entry address for the IAP algorithms, enabling a switch to thumb mode. */
#define IAP_ENTRY_ADDRESS (0x7ffffff1)
/** \brief IAP prepare sectos command code. */
#define IAP_CMD_PREPARE_SECTORS (50)
/** \brief IAP copy ram to flash command code. */
#define IAP_CMD_COPY_RAM_TO_FLASH (51)
/** \brief IAP erase sectors command code. */
#define IAP_CMD_ERASE_SECTORS (52)
/** \brief IAP black check sectors command code. */
#define IAP_CMD_BLANK_CHECK_SECTORS (53)
/** \brief IAP compare command code. */
#define IAP_CMD_COMPARE (56)
/** \brief IAP result code for success. */
#define IAP_CMD_SUCCESS (0)
/****************************************************************************************
* Plausibility checks
****************************************************************************************/
#ifndef BOOT_FLASH_CUSTOM_LAYOUT_ENABLE
#define BOOT_FLASH_CUSTOM_LAYOUT_ENABLE (0u)
#endif
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Function pointer type that is needed to call IAP functions of the
* NXP LPC2xxx.
*/
typedef void (*pIapHandler)(blt_int32u command[], blt_int32u result[]);
/** \brief Flash sector descriptor type. */
typedef struct
{
blt_addr sector_start; /**< sector start address */
blt_int32u sector_size; /**< sector size in bytes */
blt_int8u sector_num; /**< sector number */
} tFlashSector;
/** \brief Structure type for grouping flash block information.
* \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a
* flash block manager is implemented in this driver. this flash block manager
* depends on this flash block info structure. It holds the base address of
* the flash block and the data that should be programmed into the flash
* block. Note that the .data member must be 32-bit aligned by the linker.
* the .base_addr must be a multiple of FLASH_WRITE_BLOCK_SIZE.
*/
typedef struct
{
blt_addr base_addr; /**< Base address for the flash operation.*/
blt_int8u data[FLASH_WRITE_BLOCK_SIZE] __attribute__((aligned(4))); /**< Data array. */
} tFlashBlockInfo;
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0)
extern blt_bool FlashCryptoDecryptDataHook(blt_int8u * data, blt_int32u size);
#endif
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address);
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len);
static blt_bool FlashWriteBlock(tFlashBlockInfo *block);
static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector);
static blt_int8u FlashGetSector(blt_addr address);
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief If desired, it is possible to set BOOT_FLASH_CUSTOM_LAYOUT_ENABLE to > 0
* in blt_conf.h and then implement your own version of the flashLayout[] table
* in a source-file with the name flash_layout.c. This way you customize the
* flash memory size reserved for the bootloader, without having to modify
* the flashLayout[] table in this file directly. This file will then include
* flash_layout.c so there is no need to compile it additionally with your
* project.
*/
#if (BOOT_FLASH_CUSTOM_LAYOUT_ENABLE == 0)
/** \brief Array wit the layout of the flash memory.
* \details Also controls what part of the flash memory is reserved for the bootloader.
* If the bootloader size changes, the reserved sectors for the bootloader
* might need adjustment to make sure the bootloader doesn't get overwritten.
* The current flash layout supports the NXP LPC21xx and LPC22xx targets.
* LPC23xx has a slightly different layout. To support the LPC23xx, simply
* update this flash layout.
*/
static const tFlashSector flashLayout[] =
{
#if (BOOT_NVM_SIZE_KB == 64)
/* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
{ 0x00002000, 0x02000, 1}, /* flash sector 1 */
{ 0x00004000, 0x02000, 2}, /* flash sector 2 */
{ 0x00006000, 0x02000, 3}, /* flash sector 3 */
{ 0x00008000, 0x02000, 4}, /* flash sector 4 */
{ 0x0000A000, 0x02000, 5}, /* flash sector 5 */
{ 0x0000C000, 0x02000, 6}, /* flash sector 6 */
/* { 0x0000E000, 0x02000, 7}, flash sector 7 - used by NXP bootcode */
#endif
#if (BOOT_NVM_SIZE_KB == 128)
/* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
{ 0x00002000, 0x02000, 1}, /* flash sector 1 */
{ 0x00004000, 0x02000, 2}, /* flash sector 2 */
{ 0x00006000, 0x02000, 3}, /* flash sector 3 */
{ 0x00008000, 0x02000, 4}, /* flash sector 4 */
{ 0x0000A000, 0x02000, 5}, /* flash sector 5 */
{ 0x0000C000, 0x02000, 6}, /* flash sector 6 */
{ 0x0000E000, 0x02000, 7}, /* flash sector 7 */
{ 0x00010000, 0x02000, 8}, /* flash sector 8 */
{ 0x00012000, 0x02000, 9}, /* flash sector 9 */
{ 0x00014000, 0x02000, 10}, /* flash sector 10 */
{ 0x00016000, 0x02000, 11}, /* flash sector 11 */
{ 0x00018000, 0x02000, 12}, /* flash sector 12 */
{ 0x0001A000, 0x02000, 13}, /* flash sector 13 */
{ 0x0001C000, 0x02000, 14}, /* flash sector 14 */
/* { 0x0001E000, 0x02000, 15}, flash sector 15 - used by NXP bootcode */
#endif
#if (BOOT_NVM_SIZE_KB == 256)
/* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
{ 0x00002000, 0x02000, 1}, /* flash sector 1 */
{ 0x00004000, 0x02000, 2}, /* flash sector 2 */
{ 0x00006000, 0x02000, 3}, /* flash sector 3 */
{ 0x00008000, 0x02000, 4}, /* flash sector 4 */
{ 0x0000A000, 0x02000, 5}, /* flash sector 5 */
{ 0x0000C000, 0x02000, 6}, /* flash sector 6 */
{ 0x0000E000, 0x02000, 7}, /* flash sector 7 */
{ 0x00010000, 0x10000, 8}, /* flash sector 8 */
{ 0x00020000, 0x10000, 9}, /* flash sector 9 */
{ 0x00030000, 0x02000, 10}, /* flash sector 10 */
{ 0x00032000, 0x02000, 11}, /* flash sector 11 */
{ 0x00034000, 0x02000, 12}, /* flash sector 12 */
{ 0x00036000, 0x02000, 13}, /* flash sector 13 */
{ 0x00038000, 0x02000, 14}, /* flash sector 14 */
{ 0x0003A000, 0x02000, 15}, /* flash sector 15 */
{ 0x0003C000, 0x02000, 16}, /* flash sector 16 */
/* { 0x0003E000, 0x02000, 17}, flash sector 17 - used by NXP bootcode */
#endif
};
#else
#include "flash_layout.c"
#endif /* BOOT_FLASH_CUSTOM_LAYOUT_ENABLE == 0 */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable with information about the flash block that is currently
* being operated on.
* \details The smallest amount of flash that can be programmed is
* FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver
* and stores info in this variable. Whenever new data should be flashed, it
* is first added to a RAM buffer, which is part of this variable. Whenever
* the RAM buffer, which has the size of a flash block, is full or data needs
* to be written to a different block, the contents of the RAM buffer are
* programmed to flash. The flash block manager requires some software
* overhead, yet results is faster flash programming because data is first
* harvested, ideally until there is enough to program an entire flash block,
* before the flash device is actually operated on.
*/
static tFlashBlockInfo blockInfo;
/** \brief Local variable with information about the flash boot block.
* \details The first block of the user program holds the vector table, which on the
* LPC2000 is also the where the checksum is written to. Is it likely that the
* vector table is first flashed and then, at the end of the programming
* sequence, the checksum. This means that this flash block need to be written
* to twice. Normally this is not a problem with flash memory, as long as you
* write the same values to those bytes that are not supposed to be changed and
* the locations where you do write to are still in the erased 0xFF state.
* Unfortunately, writing twice to flash this way, does not work reliably on
* the LPC2000. This is why we need to have an extra block, the bootblock,
* placed under the management of the block manager. This way is it possible
* to implement functionality so that the bootblock is only written to once at
* the end of the programming sequence.
*/
static tFlashBlockInfo bootBlockInfo;
/************************************************************************************//**
** \brief Initializes the flash driver.
** \return none.
**
****************************************************************************************/
void FlashInit(void)
{
/* check the flash block data buffer alignments */
if ((((blt_addr)blockInfo.data % 4) != 0) || (((blt_addr)bootBlockInfo.data % 4) != 0))
{
/* incorrect alignment */
ASSERT_RT(BLT_FALSE);
}
/* init the flash block info structs by setting the address to an invalid address */
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
} /*** end of FlashInit ***/
/************************************************************************************//**
** \brief Reinitializes the flash driver.
** \return none.
**
****************************************************************************************/
void FlashReinit(void)
{
/* init the flash block info structs by setting the address to an invalid address */
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
} /*** end of FlashReinit ***/
/************************************************************************************//**
** \brief Writes the data to flash through a flash block manager. Note that this
** function also checks that no data is programmed outside the flash
** memory region, so the bootloader can never be overwritten.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
blt_addr base_addr;
/* validate the len parameter */
if ((len - 1) > (FLASH_END_ADDRESS - addr))
{
return BLT_FALSE;
}
/* make sure the addresses are within the flash device */
if ((FlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
(FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR))
{
return BLT_FALSE;
}
/* if this is the bootblock, then let the boot block manager handle it */
base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
if (base_addr == flashLayout[0].sector_start)
{
/* let the boot block manager handle it */
return FlashAddToBlock(&bootBlockInfo, addr, data, len);
}
/* let the block manager handle it */
return FlashAddToBlock(&blockInfo, addr, data, len);
} /*** end of FlashWrite ***/
/************************************************************************************//**
** \brief Erases the flash memory. Note that this function also checks that no
** data is erased outside the flash memory region, so the bootloader can
** never be erased.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool FlashErase(blt_addr addr, blt_int32u len)
{
blt_int8u first_sector;
blt_int8u last_sector;
/* validate the len parameter */
if ((len - 1) > (FLASH_END_ADDRESS - addr))
{
return BLT_FALSE;
}
/* obtain the first and last sector number */
first_sector = FlashGetSector(addr);
last_sector = FlashGetSector(addr+len-1);
/* check them */
if ((first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR))
{
return BLT_FALSE;
}
/* erase the sectors */
return FlashEraseSectors(first_sector, last_sector);
} /*** end of FlashErase ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if the programming session
** was completed, which indicates that a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool FlashWriteChecksum(void)
{
blt_int32u signature_checksum = 0;
/* The ARM7 core already has a spot reserved for a checksum that the bootloader can
* store at the end of a programming session.
*
* Layout of the vector table (* = don't care)
* 0x******00 Reset Exception
* 0x******04 Undefined Instruction Exception
* 0x******08 Software Interrupt Exception
* 0x******0C Prefetch Exception
* 0x******10 Abort Exception
* 0x******14 [reserved for signature checksum]
* 0x******18 IRQ Exception
* 0x******1C FIQ Exception
*
* signature_checksum = Two's complement of (SUM(exception address values))
*/
/* first check that the bootblock contains valid data. if not, this means the
* bootblock is not part of the reprogramming this time and therefore no
* new checksum needs to be written
*/
if (bootBlockInfo.base_addr == FLASH_INVALID_ADDRESS)
{
return BLT_TRUE;
}
#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0)
/* perform decryption of the bootblock, before calculating the checksum and writing it
* to flash memory.
*/
if (FlashCryptoDecryptDataHook(bootBlockInfo.data, FLASH_WRITE_BLOCK_SIZE) == BLT_FALSE)
{
return BLT_FALSE;
}
#endif
/* compute the checksum. note that the user program's vectors are not yet written
* to flash but are present in the bootblock data structure at this point.
*/
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x00]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x04]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x08]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x0C]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x10]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x18]));
signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x1C]));
signature_checksum = ~signature_checksum; /* one's complement */
signature_checksum += 1; /* two's complement */
/* write the checksum */
return FlashWrite(flashLayout[0].sector_start+0x14, sizeof(blt_addr),
(blt_int8u *)&signature_checksum);
} /*** end of FlashWriteChecksum ***/
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool FlashVerifyChecksum(void)
{
blt_int32u signature_checksum = 0;
/* verify the checksum based on how it was written by CpuWriteChecksum() */
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x04));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x08));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x0C));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x10));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x14));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x18));
signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x1C));
/* sum should add up to an unsigned 32-bit value of 0 */
if (signature_checksum == 0)
{
/* checksum okay */
return BLT_TRUE;
}
/* checksum incorrect */
return BLT_FALSE;
} /*** end of FlashVerifyChecksum ***/
/************************************************************************************//**
** \brief Finalizes the flash driver operations. There could still be data in
** the currently active block that needs to be flashed.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool FlashDone(void)
{
/* check if there is still data waiting to be programmed in the boot block */
if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS)
{
if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* check if there is still data waiting to be programmed */
if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
{
if (FlashWriteBlock(&blockInfo) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* still here so all is okay */
return BLT_TRUE;
} /*** end of FlashDone ***/
/************************************************************************************//**
** \brief Obtains the base address of the flash memory available to the user program.
** This is basically the first address in the flashLayout table.
** \return Base address.
**
****************************************************************************************/
blt_addr FlashGetUserProgBaseAddress(void)
{
return flashLayout[0].sector_start;
} /*** end of FlashGetUserProgBaseAddress ***/
/************************************************************************************//**
** \brief Copies data currently in flash to the block->data and sets the
** base address.
** \param block Pointer to flash block info structure to operate on.
** \param address Base address of the block data.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address)
{
/* check address alignment */
if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
{
return BLT_FALSE;
}
/* make sure that we are initializing a new block and not the same one */
if (block->base_addr == address)
{
/* block already initialized, so nothing to do */
return BLT_TRUE;
}
/* set the base address and copies the current data from flash */
block->base_addr = address;
CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
return BLT_TRUE;
} /*** end of FlashInitBlock ***/
/************************************************************************************//**
** \brief Switches blocks by programming the current one and initializing the
** next.
** \param block Pointer to flash block info structure to operate on.
** \param base_addr Base address of the next block.
** \return The pointer of the block info struct that is no being used, or a NULL
** pointer in case of error.
**
****************************************************************************************/
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
{
/* check if a switch needs to be made away from the boot block. in this case the boot
* block shouldn't be written yet, because this is done at the end of the programming
* session by FlashDone(), this is right after the checksum was written.
*/
if (block == &bootBlockInfo)
{
/* switch from the boot block to the generic block info structure */
block = &blockInfo;
}
/* check if a switch back into the bootblock is needed. in this case the generic block
* doesn't need to be written here yet.
*/
else if (base_addr == flashLayout[0].sector_start)
{
/* switch from the generic block to the boot block info structure */
block = &bootBlockInfo;
base_addr = flashLayout[0].sector_start;
}
else
{
/* need to switch to a new block, so program the current one and init the next */
if (FlashWriteBlock(block) == BLT_FALSE)
{
return BLT_NULL;
}
}
/* initialize tne new block when necessary */
if (FlashInitBlock(block, base_addr) == BLT_FALSE)
{
return BLT_NULL;
}
/* still here to all is okay */
return block;
} /*** end of FlashSwitchBlock ***/
/************************************************************************************//**
** \brief Programming is done per block. This function adds data to the block
** that is currently collecting data to be written to flash. If the
** address is outside of the current block, the current block is written
** to flash an a new block is initialized.
** \param block Pointer to flash block info structure to operate on.
** \param address Flash destination address.
** \param data Pointer to the byte array with data.
** \param len Number of bytes to add to the block.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
blt_int8u *data, blt_int32u len)
{
blt_addr current_base_addr;
blt_int8u *dst;
blt_int8u *src;
/* determine the current base address */
current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
/* make sure the blockInfo is not uninitialized */
if (block->base_addr == FLASH_INVALID_ADDRESS)
{
/* initialize the blockInfo struct for the current block */
if (FlashInitBlock(block, current_base_addr) == BLT_FALSE)
{
return BLT_FALSE;
}
}
/* check if the new data fits in the current block */
if (block->base_addr != current_base_addr)
{
/* need to switch to a new block, so program the current one and init the next */
block = FlashSwitchBlock(block, current_base_addr);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
}
/* add the data to the current block, but check for block overflow */
dst = &(block->data[address - block->base_addr]);
src = data;
do
{
/* keep the watchdog happy */
CopService();
/* buffer overflow? */
if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
{
/* need to switch to a new block, so program the current one and init the next */
block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
if (block == BLT_NULL)
{
return BLT_FALSE;
}
/* reset destination pointer */
dst = &(block->data[0]);
}
/* write the data to the buffer */
*dst = *src;
/* update pointers */
dst++;
src++;
/* decrement byte counter */
len--;
}
while (len > 0);
/* still here so all is good */
return BLT_TRUE;
} /*** end of FlashAddToBlock ***/
/************************************************************************************//**
** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data
** array.
** \param block Pointer to flash block info structure to operate on.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
{
blt_int32u iap_command[5];
blt_int32u iap_result[3];
blt_int8u sector_num;
pIapHandler iapHandler = (void *)IAP_ENTRY_ADDRESS;
/* check that address is actually within flash */
sector_num = FlashGetSector(block->base_addr);
if (sector_num == FLASH_INVALID_SECTOR)
{
return BLT_FALSE;
}
#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0)
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE == 0)
/* note that the bootblock is already decrypted in FlashWriteChecksum(), if the
* internal checksum mechanism is used. Therefore don't decrypt it again.
*/
if (block != &bootBlockInfo)
#endif
{
/* perform decryption of the program data before writing it to flash memory. */
if (FlashCryptoDecryptDataHook(block->data, FLASH_WRITE_BLOCK_SIZE) == BLT_FALSE)
{
return BLT_FALSE;
}
}
#endif
/* send the prepare sector command for just this one sector */
iap_command[0] = IAP_CMD_PREPARE_SECTORS;
iap_command[1] = sector_num;
iap_command[2] = sector_num;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* send the erase sector command */
iap_command[0] = IAP_CMD_COPY_RAM_TO_FLASH;
iap_command[1] = (blt_int32u)block->base_addr;
iap_command[2] = (blt_int32u)block->data;
iap_command[3] = FLASH_WRITE_BLOCK_SIZE;
iap_command[4] = BOOT_CPU_SYSTEM_SPEED_KHZ;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* perform a comparison for verification purposes */
iap_command[0] = IAP_CMD_COMPARE;
iap_command[1] = (blt_int32u)block->base_addr;
iap_command[2] = (blt_int32u)block->data;
iap_command[3] = FLASH_WRITE_BLOCK_SIZE;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* still here so all is okay */
return BLT_TRUE;
} /*** end of FlashWriteBlock ***/
/************************************************************************************//**
** \brief Erases the flash sectors from first_sector up until last_sector.
** \param first_sector First flash sector number.
** \param last_sector Last flash sector number.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
{
blt_int32u iap_command[5];
blt_int32u iap_result[3];
pIapHandler iapHandler = (void *)IAP_ENTRY_ADDRESS;
/* validate the sector numbers */
if (first_sector > last_sector)
{
return BLT_FALSE;
}
if ((first_sector < flashLayout[0].sector_num) || \
(last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num))
{
return BLT_FALSE;
}
/* send the prepare sector command for just this one sector */
iap_command[0] = IAP_CMD_PREPARE_SECTORS;
iap_command[1] = first_sector;
iap_command[2] = last_sector;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* send the erase sector command */
iap_command[0] = IAP_CMD_ERASE_SECTORS;
iap_command[1] = first_sector;
iap_command[2] = last_sector;
iap_command[3] = BOOT_CPU_SYSTEM_SPEED_KHZ;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* perform a blank check for verification purposes */
iap_command[0] = IAP_CMD_BLANK_CHECK_SECTORS ;
iap_command[1] = first_sector;
iap_command[2] = last_sector;
iap_result[0] = !IAP_CMD_SUCCESS;
/* service the watchdog before calling the IAP handler */
CopService();
iapHandler(iap_command, iap_result);
if (iap_result[0] != IAP_CMD_SUCCESS)
{
return BLT_FALSE;
}
/* still here so all went okay */
return BLT_TRUE;
} /*** end of FlashEraseSectors ***/
/************************************************************************************//**
** \brief Determines the flash sector the address is in.
** \param address Address in the flash sector.
** \return Flash sector number or FLASH_INVALID_SECTOR.
**
****************************************************************************************/
static blt_int8u FlashGetSector(blt_addr address)
{
blt_int8u sectorIdx;
/* search through the sectors to find the right one */
for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
{
/* keep the watchdog happy */
CopService();
/* is the address in this sector? */
if ((address >= flashLayout[sectorIdx].sector_start) && \
(address < (flashLayout[sectorIdx].sector_start + \
flashLayout[sectorIdx].sector_size)))
{
/* return the sector number */
return flashLayout[sectorIdx].sector_num;
}
}
/* still here so no valid sector found */
return FLASH_INVALID_SECTOR;
} /*** end of FlashGetSector ***/
/*********************************** end of flash.c ************************************/

45
Target/Source/ARM7_LPC2000/flash.h
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@ -1,45 +0,0 @@
/************************************************************************************//**
* \file Source/ARM7_LPC2000/GCC/flash.h
* \brief Bootloader flash driver header file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef FLASH_H
#define FLASH_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void FlashInit(void);
void FlashReinit(void);
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
blt_bool FlashErase(blt_addr addr, blt_int32u len);
blt_bool FlashWriteChecksum(void);
blt_bool FlashVerifyChecksum(void);
blt_bool FlashDone(void);
blt_addr FlashGetUserProgBaseAddress(void);
#endif /* FLASH_H */
/*********************************** end of flash.h ************************************/

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Target/Source/ARM7_LPC2000/nvm.c
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@ -1,246 +0,0 @@
/************************************************************************************//**
* \file Source/ARM7_LPC2000/nvm.c
* \brief Bootloader non-volatile memory driver source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "flash.h"
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
extern void NvmInitHook(void);
extern void NvmReinitHook(void);
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
extern blt_bool NvmDoneHook(void);
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
extern blt_bool NvmWriteChecksumHook(void);
extern blt_bool NvmVerifyChecksumHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmInit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmInitHook();
#endif
/* init the internal driver */
FlashInit();
} /*** end of NvmInit ***/
/************************************************************************************//**
** \brief Reinitializes the NVM driver. This function is called at the start of each
** firmware update as opposed to NvmInit, which is only called once during
** power on.
** \return none.
**
****************************************************************************************/
void NvmReinit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to re-initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmReinitHook();
#endif
/* reinitialize the internal driver */
FlashReinit();
} /*** end of NvmReinit ***/
/************************************************************************************//**
** \brief Programs the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmWriteHook(addr, len, data);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* data was within range of the additionally supported memory and succesfully
* programmed, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* data was within range of the additionally supported memory and attempted to be
* programmed, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the program operation */
return FlashWrite(addr, len, data);
} /*** end of NvmWrite ***/
/************************************************************************************//**
** \brief Erases the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmErase(blt_addr addr, blt_int32u len)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmEraseHook(addr, len);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* address was within range of the additionally supported memory and succesfully
* erased, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* address was within range of the additionally supported memory and attempted to be
* erased, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the erase operation */
return FlashErase(addr, len);
} /*** end of NvmErase ***/
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksum(void)
{
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* check checksum using the application specific method. */
return NvmVerifyChecksumHook();
#else
/* check checksum using the interally supported method. */
return FlashVerifyChecksum();
#endif
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Obtains the base address of the non-volatile memory available to the user
** program. This is typically that start of the vector table.
** \return Base address.
**
****************************************************************************************/
blt_addr NvmGetUserProgBaseAddress(void)
{
return FlashGetUserProgBaseAddress();
} /*** end of NvmGetUserProgBaseAddress ***/
/************************************************************************************//**
** \brief Once all erase and programming operations are completed, this
** function is called, so at the end of the programming session and
** right before a software reset is performed. It is used to calculate
** a checksum and program this into flash. This checksum is later used
** to determine if a valid user program is present in flash.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDone(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application's NVM driver a chance to finish up */
if (NvmDoneHook() == BLT_FALSE)
{
/* error so no need to continue */
return BLT_FALSE;
}
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* compute and write checksum, using the application specific method. */
if (NvmWriteChecksumHook() == BLT_FALSE)
{
return BLT_FALSE;
}
#else
/* compute and write checksum, which is programmed by the internal driver. */
if (FlashWriteChecksum() == BLT_FALSE)
{
return BLT_FALSE;
}
#endif
/* finish up internal driver operations */
return FlashDone();
} /*** end of NvmDone ***/
/*********************************** end of nvm.c **************************************/

9
Target/Source/ARM7_LPC2000/target.dox
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@ -1,9 +0,0 @@
/**
\defgroup Target_ARM7_LPC2000 Target ARM7 LPC2000
\ingroup Ports
\brief Target dependent code for the ARM7 LPC2000 microcontroller family.
\details This module implements the bootloader's target dependent part for the
ARM7 LPC2000 microcontroller family.
*/

137
Target/Source/ARM7_LPC2000/timer.c
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/************************************************************************************//**
* \file Source/ARM7_LPC2000/timer.c
* \brief Bootloader timer driver source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable that holds the last value of the free running counter. */
static blt_int32u free_running_counter_last;
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static blt_int32u millisecond_counter;
/****************************************************************************************
* Register definitions
****************************************************************************************/
/** \brief T0MCR timer register. */
#define T0MCR (*((volatile blt_int32u *) 0xE0004014))
/** \brief T0CCR timer register. */
#define T0CCR (*((volatile blt_int32u *) 0xE0004028))
/** \brief T0PR timer register. */
#define T0PR (*((volatile blt_int32u *) 0xE000400C))
/** \brief T0PC timer register. */
#define T0PC (*((volatile blt_int32u *) 0xE0004010))
/** \brief T0TCR timer register. */
#define T0TCR (*((volatile blt_int32u *) 0xE0004004))
/** \brief T0TC timer register. */
#define T0TC (*((volatile blt_int32u *) 0xE0004008))
/************************************************************************************//**
** \brief Initializes the polling based millisecond timer driver.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* disable timer 0 interrupts */
T0MCR = 0x00;
T0CCR = 0x00;
/* set prescaler so that free running counter runs at 1 kHz */
T0PR = BOOT_CPU_SYSTEM_SPEED_KHZ - 1;
/* start free running counter for timer 0 */
T0TCR = 0x01;
/* store the start value of the free running counter */
free_running_counter_last = T0TC;
/* reset the millisecond counter value */
millisecond_counter = 0;
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Reset the timer by placing the timer back into it's default reset
** configuration.
** \return none.
**
****************************************************************************************/
void TimerReset(void)
{
/* reset the timer */
T0TCR = 0;
/* reset the prescaler */
T0PR = 0;
/* reset the timer counter */
T0TC = 0;
/* reset the prescaled counter */
T0PC = 0;
} /* TimerReset */
/************************************************************************************//**
** \brief Updates the millisecond timer.
** \return none.
**
****************************************************************************************/
void TimerUpdate(void)
{
blt_int32u free_running_counter_now;
/* update the millisecond counter */
free_running_counter_now = T0TC;
millisecond_counter += (free_running_counter_now - free_running_counter_last);
/* store current free running counter value for next time around */
free_running_counter_last = free_running_counter_now;
} /*** end of TimerUpdate ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
blt_int32u TimerGet(void)
{
/* updating timer here allows this function to be called in a loop with timeout
* detection.
*/
TimerUpdate();
/* read and return the amount of milliseconds that passed since initialization */
return millisecond_counter;
} /*** end of TimerGet ***/
/*********************************** end of timer.c ************************************/

58
Target/Source/ARM7_LPC2000/types.h
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@ -1,58 +0,0 @@
/************************************************************************************//**
* \file Source/ARM7_LPC2000/types.h
* \brief Bootloader types header file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TYPES_H
#define TYPES_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Boolean true value. */
#define BLT_TRUE (1)
/** \brief Boolean false value. */
#define BLT_FALSE (0)
/** \brief NULL pointer value. */
#define BLT_NULL ((void *)0)
/****************************************************************************************
* Type definitions
****************************************************************************************/
typedef unsigned char blt_bool; /**< boolean type */
typedef char blt_char; /**< character type */
typedef unsigned long blt_addr; /**< memory address type */
typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */
typedef signed char blt_int8s; /**< 8-bit signed integer */
typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */
typedef signed short blt_int16s; /**< 16-bit signed integer */
typedef unsigned int blt_int32u; /**< 32-bit unsigned integer */
typedef signed int blt_int32s; /**< 32-bit signed integer */
#endif /* TYPES_H */
/*********************************** end of types.h ************************************/

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Target/Source/ARM7_LPC2000/uart.c
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/************************************************************************************//**
* \file Source/ARM7_LPC2000/uart.c
* \brief Bootloader UART communication interface source file.
* \ingroup Target_ARM7_LPC2000
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_COM_UART_ENABLE > 0)
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
/** \brief Timeout for transmitting a byte in milliseconds. */
#define UART_BYTE_TX_TIMEOUT_MS (10u)
/** \brief Divisor latch access bit. */
#define UART_DLAB (0x80)
/** \brief 8 data and 1 stop bit, no parity. */
#define UART_MODE_8N1 (0x03)
/** \brief FIFO reset and RX FIFO 1 deep. */
#define UART_FIFO_RX1 (0x07)
/** \brief Receiver data ready. */
#define UART_RDR (0x01)
/** \brief Transmitter holding register empty. */
#define UART_THRE (0x20)
/****************************************************************************************
* Register definitions
****************************************************************************************/
/** \brief U0RBR UART register. */
#define U0RBR (*((volatile blt_int8u *) 0xE000C000))
/** \brief U0THR UART register. */
#define U0THR (*((volatile blt_int8u *) 0xE000C000))
/** \brief U0IER UART register. */
#define U0IER (*((volatile blt_int8u *) 0xE000C004))
/** \brief U0IIR UART register. */
#define U0IIR (*((volatile blt_int8u *) 0xE000C008))
/** \brief U0FCR UART register. */
#define U0FCR (*((volatile blt_int8u *) 0xE000C008))
/** \brief U0LCR UART register. */
#define U0LCR (*((volatile blt_int8u *) 0xE000C00C))
/** \brief U0LSR UART register. */
#define U0LSR (*((volatile blt_int8u *) 0xE000C014))
/** \brief U0SCR UART register. */
#define U0SCR (*((volatile blt_int8u *) 0xE000C01C))
/** \brief U0DLL UART register. */
#define U0DLL (*((volatile blt_int8u *) 0xE000C000))
/** \brief U0DLM UART register. */
#define U0DLM (*((volatile blt_int8u *) 0xE000C004))
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool UartReceiveByte(blt_int8u *data);
static blt_bool UartTransmitByte(blt_int8u data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
void UartInit(void)
{
blt_int32u baud_reg_value; /* baudrate register value */
/* the current implementation supports UART0. throw an assertion error in case
* a different UART channel is configured.
*/
ASSERT_CT(BOOT_COM_UART_CHANNEL_INDEX == 0);
/* disable UART related interrupt generation. this driver works in polling mode */
U0IER = 0;
/* clear interrupt id register */
U0IIR = 0;
/* clear line status register */
U0LSR = 0;
/* set divisor latch DLAB = 1 so buadrate can be configured */
U0LCR = UART_DLAB;
/* Baudrate calculation:
* y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
* smartness to automatically round the value up/down using the following trick:
* y = x/n can round with y = (x + (n + 1)/2 ) / n
*/
/* check that baudrate register value is not 0 */
ASSERT_CT((((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+((BOOT_COM_UART_BAUDRATE+1)/2))/ \
BOOT_COM_UART_BAUDRATE) > 0);
/* check that baudrate register value is not greater than max 16-bit unsigned value */
ASSERT_CT((((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+((BOOT_COM_UART_BAUDRATE+1)/2))/ \
BOOT_COM_UART_BAUDRATE) <= 65535);
baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
/* write the calculated baudrate selector value to the registers */
U0DLL = (blt_int8u)baud_reg_value;
U0DLM = (blt_int8u)(baud_reg_value >> 8);
/* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
U0LCR = UART_MODE_8N1;
/* enable and reset transmit and receive FIFO. necessary for UART operation */
U0FCR = UART_FIFO_RX1;
} /*** end of UartInit ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void UartTransmitPacket(blt_int8u *data, blt_int8u len)
{
blt_int16u data_index;
blt_bool result;
/* verify validity of the len-paramenter */
ASSERT_RT(len <= BOOT_COM_UART_TX_MAX_DATA);
/* first transmit the length of the packet */
result = UartTransmitByte(len);
ASSERT_RT(result == BLT_TRUE);
/* transmit all the packet bytes one-by-one */
for (data_index = 0; data_index < len; data_index++)
{
/* keep the watchdog happy */
CopService();
/* write byte */
result = UartTransmitByte(data[data_index]);
ASSERT_RT(result == BLT_TRUE);
}
} /*** end of UartTransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \param len Pointer where the length of the packet is to be stored.
** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool UartReceivePacket(blt_int8u *data, blt_int8u *len)
{
static blt_int8u xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1]; /* one extra for length */
static blt_int8u xcpCtoRxLength;
static blt_bool xcpCtoRxInProgress = BLT_FALSE;
static blt_int32u xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == BLT_FALSE)
{
/* store the message length when received */
if (UartReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
{
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_UART_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* reset packet data count */
xcpCtoRxLength = 0;
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = BLT_TRUE;
}
}
}
else
{
/* store the next packet byte */
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* copy the packet data */
CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
/* done with cto packet reception */
xcpCtoRxInProgress = BLT_FALSE;
/* set the packet length */
*len = xcpCtoRxLength;
/* packet reception complete */
return BLT_TRUE;
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + UART_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that that automaticaly
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = BLT_FALSE;
}
}
}
/* packet reception not yet complete */
return BLT_FALSE;
} /*** end of UartReceivePacket ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool UartReceiveByte(blt_int8u *data)
{
/* check if a new byte was received by means of the RDR-bit */
if ((U0LSR & UART_RDR) != 0)
{
/* store the received byte */
data[0] = U0RBR;
/* inform caller of the newly received byte */
return BLT_TRUE;
}
/* inform caller that no new data was received */
return BLT_FALSE;
} /*** end of UartReceiveByte ***/
/************************************************************************************//**
** \brief Transmits a communication interface byte.
** \param data Value of byte that is to be transmitted.
** \return BLT_TRUE if the byte was transmitted, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool UartTransmitByte(blt_int8u data)
{
blt_int32u timeout;
blt_bool result = BLT_TRUE;
/* check if tx holding register can accept new data */
if ((U0LSR & UART_THRE) == 0)
{
/* UART not ready. should not happen */
return BLT_FALSE;
}
/* write byte to transmit holding register */
U0THR = data;
/* set timeout time to wait for transmit completion. */
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
/* wait for tx holding register to be empty */
while ((U0LSR & UART_THRE) == 0)
{
/* keep the watchdog happy */
CopService();
/* break loop upon timeout. this would indicate a hardware failure. */
if (TimerGet() > timeout)
{
result = BLT_FALSE;
break;
}
}
/* give the result back to the caller */
return result;
} /*** end of UartTransmitByte ***/
#endif /* BOOT_COM_UART_ENABLE > 0 */
/*********************************** end of uart.c *************************************/

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/************************************************************************************//**
* \file Source/TRICORE_TC1798/GCC/cpu_comp.c
* \brief Bootloader compiler specific cpu module source file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "cpu_comp.h" /* compiler specific CPU definitions */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
#define CPU_INIT_MODE_TIMEOUT_MS (250u)
/****************************************************************************************
* Local function prototypes
****************************************************************************************/
static void CpuWriteWDTCON0(blt_int32u uwValue);
/************************************************************************************//**
** \brief Disable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqDisable(void)
{
_disable();
} /*** end of CpuIrqDisable ***/
/************************************************************************************//**
** \brief Enable global interrupts.
** \return none.
**
****************************************************************************************/
void CpuIrqEnable(void)
{
_enable();
} /*** end of CpuIrqEnable ***/
/************************************************************************************//**
** \brief This macro clears the EndInit bit, which controls access to system critical
** registers. Clearing the EndInit bit unlocks all EndInit protectedd
** registers. Modifications of the EndInit bit are monitored by the watchdog
** timer such that after clearing the EndInit, the watchdog timer enters a
** defined time-out mode; EndInit must be set again before the time-out
** expires.
** \return none.
**
****************************************************************************************/
void CpuEnterInitMode(void)
{
blt_int32u timeout;
/* request clearing of the EndInit bit */
CpuWriteWDTCON0(WDT_CON0.reg & ~0x00000001);
/* set timeout to wait for hardware handshake */
timeout = TimerGet() + CPU_INIT_MODE_TIMEOUT_MS;
/* wait for hardware handshake */
while (WDT_CON0.bits.ENDINIT != 0)
{
/* keep the watchdog happy */
CopService();
/* break loop if timeout occurred */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CpuEnterInitMode ***/
/************************************************************************************//**
** \brief This macro sets the EndInit bit, which controls access to system critical
** registers. Setting the EndInit bit locks all EndInit protected registers.
** \return none.
**
****************************************************************************************/
void CpuLeaveInitMode(void)
{
/* set the EndInit bit */
CpuWriteWDTCON0(WDT_CON0.reg | 0x00000001);
} /*** end of CpuLeaveInitMode ***/
/************************************************************************************//**
** \brief Write a new value to the WDTCON0 register.
** \param value New value for the WDTCON0 register.
** \return none.
**
****************************************************************************************/
static void CpuWriteWDTCON0(blt_int32u value)
{
blt_int32u dummy;
/* load current value of the WDTCON0 register */
dummy = WDT_CON0.reg;
/* set HWPW1 = 1111b */
dummy |= 0x000000F0;
/* set HWPW0 = WDTDR */
if (WDT_CON1.bits.DR)
{
dummy |= 0x00000008;
}
else
{
dummy &= ~0x00000008;
}
/* set HWPW0 = WDTIR */
if (WDT_CON1.bits.IR)
{
dummy |= 0x00000004;
}
else
{
dummy &= ~0x00000004;
}
/* set WDTLCK = 0 */
dummy &= ~0x00000002;
/* unlock access */
WDT_CON0.reg = dummy;
/* set HWPW1 = 1111b and WDTLCK = 1 */
value |= 0x000000F2;
/* set HWPW0 = 00b */
value &= ~0x0000000C;
/* write access and lock */
WDT_CON0.reg = value;
} /*** end of CpuWriteWDTCON0 ***/
/*********************************** end of cpu_comp.c *********************************/

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/************************************************************************************//**
* \file Source/TRICORE_TC1798/GCC/cpu_comp.h
* \brief Bootloader compiler specific cpu module header file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef CPU_COMP_H
#define CPU_COMP_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include <TC1798.h>
#include <machine/intrinsics.h>
#include <machine/cint.h>
#include <sys/types.h>
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Macro for performing a processor specific desync. This part is located in the
* compiler specific part because it uses an inline assembly call.
*/
#define CpuSetDSYNC() asm("DSYNC")
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void CpuEnterInitMode(void);
void CpuLeaveInitMode(void);
#endif /* CPU_COMP_H */
/*********************************** end of cpu_comp.h *********************************/

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/************************************************************************************//**
* \file Source/TRICORE_TC1798/cpu.c
* \brief Bootloader cpu module source file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Pointer to the user program's reset vector. */
#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr)(NvmGetUserProgBaseAddress()))
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
extern blt_bool CpuUserProgramStartHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the CPU module.
** \return none.
**
****************************************************************************************/
void CpuInit(void)
{
/* bootloader runs in polling mode so disable the global interrupts. this is done for
* safety reasons. if the bootloader was started from a running user program, it could
* be that the user program did not properly disable the interrupt generation of
* peripherals. */
CpuIrqDisable();
} /*** end of CpuInit ***/
/************************************************************************************//**
** \brief Starts the user program, if one is present. In this case this function
** does not return.
** \return none.
**
****************************************************************************************/
void CpuStartUserProgram(void)
{
void (*pProgResetHandler)(void);
/* check if a user program is present by verifying the checksum */
if (NvmVerifyChecksum() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* not a valid user program so it cannot be started */
return;
}
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/* invoke callback */
if (CpuUserProgramStartHook() == BLT_FALSE)
{
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* bootloader will stay active so perform deferred initialization to make sure
* the communication interface that were not yet initialized are now initialized.
* this is needed to make sure firmware updates via these communication interfaces
* will be possible.
*/
ComDeferredInit();
#endif
/* callback requests the user program to not be started */
return;
}
#endif
#if (BOOT_COM_ENABLE > 0)
/* release the communication interface */
ComFree();
#endif
/* reset the timer */
TimerReset();
/* set the address where the bootloader needs to jump to. the user program entry,
* typically called _start, is expected to be located at the start of the user program
* flash.
*/
pProgResetHandler = (void(*)(void))((blt_addr *)CPU_USER_PROGRAM_STARTADDR_PTR);
/* start the user program by activating its reset interrupt service routine */
pProgResetHandler();
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
/* theoretically, the code never gets here because the user program should now be
* running and the previous function call should not return. In case it did return
* for whatever reason, make sure all communication interfaces are initialized so that
* firmware updates can be started.
*/
ComDeferredInit();
#endif
} /*** end of CpuStartUserProgram ***/
/************************************************************************************//**
** \brief Copies data from the source to the destination address.
** \param dest Destination address for the data.
** \param src Source address of the data.
** \param len length of the data in bytes.
** \return none.
**
****************************************************************************************/
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
{
blt_int8u *from, *to;
/* set casted pointers */
from = (blt_int8u *)src;
to = (blt_int8u *)dest;
/* copy all bytes from source address to destination address */
while (len-- > 0)
{
/* store byte value from source to destination */
*to++ = *from++;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemCopy ***/
/************************************************************************************//**
** \brief Sets the bytes at the destination address to the specified value.
** \param dest Destination address for the data.
** \param value Value to write.
** \param len Number of bytes to write.
** \return none.
**
****************************************************************************************/
void CpuMemSet(blt_addr dest, blt_int8u value, blt_int16u len)
{
blt_int8u *to;
/* set casted pointer */
to = (blt_int8u *)dest;
/* set all bytes at the destination address to the specified value */
while (len-- > 0)
{
/* set byte value */
*to++ = value;
/* keep the watchdog happy */
CopService();
}
} /*** end of CpuMemSet ***/
/*********************************** end of cpu.c **************************************/

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Target/Source/TRICORE_TC1798/flash.c
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Target/Source/TRICORE_TC1798/flash.h
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/************************************************************************************//**
* \file Source/TRICORE_TC1798/flash.h
* \brief Bootloader flash driver header file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef FLASH_H
#define FLASH_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void FlashInit(void);
void FlashReinit(void);
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
blt_bool FlashErase(blt_addr addr, blt_int32u len);
blt_bool FlashWriteChecksum(void);
blt_bool FlashVerifyChecksum(void);
blt_bool FlashDone(void);
blt_addr FlashGetUserProgBaseAddress(void);
#endif /* FLASH_H */
/*********************************** end of flash.h ************************************/

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/************************************************************************************//**
* \file Source/TRICORE_TC1798/nvm.c
* \brief Bootloader non-volatile memory driver source file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "flash.h"
/****************************************************************************************
* Hook functions
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
extern void NvmInitHook(void);
extern void NvmReinitHook(void);
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
extern blt_bool NvmDoneHook(void);
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
extern blt_bool NvmWriteChecksumHook(void);
extern blt_bool NvmVerifyChecksumHook(void);
#endif
/************************************************************************************//**
** \brief Initializes the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmInit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmInitHook();
#endif
/* init the internal driver */
FlashInit();
} /*** end of NvmInit ***/
/************************************************************************************//**
** \brief Reinitializes the NVM driver. This function is called at the start of each
** firmware update as opposed to NvmInit, which is only called once during
** power on.
** \return none.
**
****************************************************************************************/
void NvmReinit(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to re-initialize a driver for operating on NVM
* that is not by default supported by this driver.
*/
NvmReinitHook();
#endif
/* reinitialize the internal driver */
FlashReinit();
} /*** end of NvmReinit ***/
/************************************************************************************//**
** \brief Programs the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmWriteHook(addr, len, data);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* data was within range of the additionally supported memory and succesfully
* programmed, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* data was within range of the additionally supported memory and attempted to be
* programmed, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the program operation */
return FlashWrite(addr, len, data);
} /*** end of NvmWrite ***/
/************************************************************************************//**
** \brief Erases the non-volatile memory.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmErase(blt_addr addr, blt_int32u len)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
#endif
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application a chance to operate on memory that is not by default supported
* by this driver.
*/
result = NvmEraseHook(addr, len);
/* process the return code */
if (result == BLT_NVM_OKAY)
{
/* address was within range of the additionally supported memory and succesfully
* erased, so we are all done.
*/
return BLT_TRUE;
}
else if (result == BLT_NVM_ERROR)
{
/* address was within range of the additionally supported memory and attempted to be
* erased, but an error occurred, so we can't continue.
*/
return BLT_FALSE;
}
#endif
/* still here so the internal driver should try and perform the erase operation */
return FlashErase(addr, len);
} /*** end of NvmErase ***/
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksum(void)
{
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* check checksum using the application specific method. */
return NvmVerifyChecksumHook();
#else
/* check checksum using the interally supported method. */
return FlashVerifyChecksum();
#endif
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Obtains the base address of the non-volatile memory available to the user
** program. This is typically that start of the vector table.
** \return Base address.
**
****************************************************************************************/
blt_addr NvmGetUserProgBaseAddress(void)
{
return FlashGetUserProgBaseAddress();
} /*** end of NvmGetUserProgBaseAddress ***/
/************************************************************************************//**
** \brief Once all erase and programming operations are completed, this
** function is called, so at the end of the programming session and
** right before a software reset is performed. It is used to calculate
** a checksum and program this into flash. This checksum is later used
** to determine if a valid user program is present in flash.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDone(void)
{
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/* give the application's NVM driver a chance to finish up */
if (NvmDoneHook() == BLT_FALSE)
{
/* error so no need to continue */
return BLT_FALSE;
}
#endif
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/* compute and write checksum, using the application specific method. */
if (NvmWriteChecksumHook() == BLT_FALSE)
{
return BLT_FALSE;
}
#else
/* compute and write checksum, which is programmed by the internal driver. */
if (FlashWriteChecksum() == BLT_FALSE)
{
return BLT_FALSE;
}
#endif
/* finish up internal driver operations */
return FlashDone();
} /*** end of NvmDone ***/
/*********************************** end of nvm.c **************************************/

9
Target/Source/TRICORE_TC1798/target.dox
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@ -1,9 +0,0 @@
/**
\defgroup Target_TRICORE_TC1798 Target Tricore TC1798
\ingroup Ports
\brief Target dependent code for the Tricore TC1798 microcontroller family.
\details This module implements the bootloader's target dependent part for the
Tricore TC1798 microcontroller family.
*/

144
Target/Source/TRICORE_TC1798/timer.c
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@ -1,144 +0,0 @@
/************************************************************************************//**
* \file Source/TRICORE_TC1798/timer.c
* \brief Bootloader timer driver source file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "cpu_comp.h" /* compiler specific CPU definitions */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static blt_int32u millisecond_counter;
/** \brief Holds the timer tick count for 1 millisecond. */
static blt_int16u millisecond_ticks;
/************************************************************************************//**
** \brief Initializes the polling based millisecond timer driver.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
blt_int32u dummy;
/* reset the timer configuration */
TimerReset();
/* obtain "E" access rights */
CpuEnterInitMode();
/* enable the GPT12 timer module */
GPT120_CLC.reg = 0x00000000;
/* dummy read to avoid pipeline effects */
dummy = GPT120_CLC.reg;
/* release "E" access rights */
CpuLeaveInitMode();
/* core timer 3 is used for polling millisecond events. its configuration is:
* - timer 3 works in timer mode
* - external up/down control is disabled
* - prescaler factor is 128 (Ftimer3 = BOOT_CPU_SYSTEM_SPEED_KHZ / 128)
* - up/down control bit is reset
* - alternate output function T3OUT is disabled
* - timer 3 output toggle latch (T3OTL) is set to 0
* - timer 3 run bit is set
*/
GPT120_T3CON.reg = 0x00000845;
/* reset the timer 3 register so that counter starts at 0 */
GPT120_T3.reg = 0x00000000;
/* calculate the number of timer ticks in 1 millisecond */
millisecond_ticks = ((blt_int32u)BOOT_CPU_SYSTEM_SPEED_KHZ / 128);
/* reset the millisecond counter value */
millisecond_counter = 0;
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Reset the timer by placing the timer back into it's default reset
** configuration.
** \return none.
**
****************************************************************************************/
void TimerReset(void)
{
blt_int32u dummy;
/* revert back to timer 3 configuration reset value */
GPT120_T3CON.reg = 0x00000000;
/* revert back to timer 3 reset value */
GPT120_T3.reg = 0x00000000;
/* obtain "E" access rights */
CpuEnterInitMode();
/* disable the GPT12 timer module */
GPT120_CLC.reg = 0x00000003;
/* dummy read to avoid pipeline effects */
dummy = GPT120_CLC.reg;
/* release "E" access rights */
CpuLeaveInitMode();
} /* end of TimerReset */
/************************************************************************************//**
** \brief Updates the millisecond timer.
** \return none.
**
****************************************************************************************/
void TimerUpdate(void)
{
/* check if the millisecond event occurred */
if (GPT120_T3.reg >= millisecond_ticks)
{
GPT120_T3.reg = 0;
/* reset timer 3 register for detecting the next millisecond */
/* increment the millisecond counter */
millisecond_counter++;
}
} /*** end of TimerUpdate ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
blt_int32u TimerGet(void)
{
/* updating timer here allows this function to be called in a loop with timeout
* detection.
*/
TimerUpdate();
/* read and return the amount of milliseconds that passed since initialization */
return millisecond_counter;
} /*** end of TimerGet ***/
/*********************************** end of timer.c ************************************/

58
Target/Source/TRICORE_TC1798/types.h
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@ -1,58 +0,0 @@
/************************************************************************************//**
* \file Source/TRICORE_TC1798/types.h
* \brief Bootloader types header file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TYPES_H
#define TYPES_H
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Boolean true value. */
#define BLT_TRUE (1)
/** \brief Boolean false value. */
#define BLT_FALSE (0)
/** \brief NULL pointer value. */
#define BLT_NULL ((void *)0)
/****************************************************************************************
* Type definitions
****************************************************************************************/
typedef unsigned char blt_bool; /**< boolean type */
typedef char blt_char; /**< character type */
typedef unsigned long blt_addr; /**< memory address type */
typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */
typedef signed char blt_int8s; /**< 8-bit signed integer */
typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */
typedef signed short blt_int16s; /**< 16-bit signed integer */
typedef unsigned int blt_int32u; /**< 32-bit unsigned integer */
typedef signed int blt_int32s; /**< 32-bit signed integer */
#endif /* TYPES_H */
/*********************************** end of types.h ************************************/

296
Target/Source/TRICORE_TC1798/uart.c
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@ -1,296 +0,0 @@
/************************************************************************************//**
* \file Source/TRICORE_TC1798/uart.c
* \brief Bootloader UART communication interface source file.
* \ingroup Target_TRICORE_TC1798
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "cpu_comp.h" /* compiler specific CPU definitions */
#if (BOOT_COM_UART_ENABLE > 0)
/****************************************************************************************
* Type definitions
****************************************************************************************/
typedef struct
{
blt_int32u reserved0[0x1]; /* 0x0 */
ASCn_PISEL_t PISEL; /* 0x4 */
ASCn_ID_t ID; /* 0x8 */
blt_int32u reserved3[0x1]; /* 0xc */
ASCn_CON_t CON; /* 0x10 */
ASCn_BG_t BG; /* 0x14 */
ASCn_FDV_t FDV; /* 0x18 */
blt_int32u reserved7[0x1]; /* 0x1c */
ASCn_TBUF_t TBUF; /* 0x20 */
ASCn_RBUF_t RBUF; /* 0x24 */
blt_int32u reserved10[0xa]; /* 0x28 */
ASCn_WHBCON_t WHBCON; /* 0x50 */
blt_int32u reserved12[0x27]; /* 0x54 */
ASCn_TSRC_t TSRC; /* 0xf0 */
ASCn_RSRC_t RSRC; /* 0xf4 */
ASCn_ESRC_t ESRC; /* 0xf8 */
ASCn_TBSRC_t TBSRC; /* 0xfc */
} tUartRegs;
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
/** \brief Timeout for transmitting a byte in milliseconds. */
#define UART_BYTE_TX_TIMEOUT_MS (10u)
/****************************************************************************************
* Register definitions
****************************************************************************************/
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
/** \brief Set UART base address to ASC0. */
#define UARTx ((tUartRegs *) (blt_int32u)0xf0000a00)
#elif (BOOT_COM_UART_CHANNEL_INDEX == 1)
/** \brief Set UART base address to ASC1. */
#define UARTx ((tUartRegs *) (blt_int32u)0xf0000b00)
#else
/** \brief Set UART base address to ASC0 by default. */
#define UARTx ((tUartRegs *) (blt_int32u)0xf0000a00)
#endif
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static blt_bool UartReceiveByte(blt_int8u *data);
static blt_bool UartTransmitByte(blt_int8u data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
void UartInit(void)
{
blt_int32u frequency, reload_value, fdv, dfreq;
/* Compute system frequency and reload value for ASC */
frequency = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000;
/* reload_value = fdv/512 * freq/16/baudrate -1 ==>
* reload_value = (512*freq)/(baudrate * 512*16) - 1
* fdv = (reload_value + 1) * (baudrate*512*16/freq)
* reload_value = (frequency / 32) / baudrate - 1;
*/
reload_value = (frequency / ((blt_int32u)BOOT_COM_UART_BAUDRATE * 16)) - 1;
dfreq = frequency / (16*512);
fdv = (reload_value + 1) * (blt_int32u)BOOT_COM_UART_BAUDRATE / dfreq;
/* enable ASC module */
CpuEnterInitMode();
ASC0_CLC.bits.RMC = 1;
ASC0_CLC.bits.DISR = 0;
CpuLeaveInitMode();
/* configure the ASC module for 8,n,1 */
UARTx->CON.reg = 0;
UARTx->BG.reg = reload_value;
UARTx->FDV.reg = fdv;
UARTx->CON.bits.M = 0x01;
UARTx->CON.bits.R = 1;
UARTx->CON.bits.REN = 1;
UARTx->CON.bits.FDE = 1;
} /*** end of UartInit ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void UartTransmitPacket(blt_int8u *data, blt_int8u len)
{
blt_int16u data_index;
blt_bool result;
/* verify validity of the len-paramenter */
ASSERT_RT(len <= BOOT_COM_UART_TX_MAX_DATA);
/* first transmit the length of the packet */
result = UartTransmitByte(len);
ASSERT_RT(result == BLT_TRUE);
/* transmit all the packet bytes one-by-one */
for (data_index = 0; data_index < len; data_index++)
{
/* keep the watchdog happy */
CopService();
/* write byte */
result = UartTransmitByte(data[data_index]);
ASSERT_RT(result == BLT_TRUE);
}
} /*** end of UartTransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \param len Pointer where the length of the packet is to be stored.
** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool UartReceivePacket(blt_int8u *data, blt_int8u *len)
{
static blt_int8u xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1]; /* one extra for length */
static blt_int8u xcpCtoRxLength;
static blt_bool xcpCtoRxInProgress = BLT_FALSE;
static blt_int32u xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == BLT_FALSE)
{
/* store the message length when received */
if (UartReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
{
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_UART_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* reset packet data count */
xcpCtoRxLength = 0;
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = BLT_TRUE;
}
}
}
else
{
/* store the next packet byte */
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* copy the packet data */
CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
/* done with cto packet reception */
xcpCtoRxInProgress = BLT_FALSE;
/* set the packet length */
*len = xcpCtoRxLength;
/* packet reception complete */
return BLT_TRUE;
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + UART_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that that automaticaly
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = BLT_FALSE;
}
}
}
/* packet reception not yet complete */
return BLT_FALSE;
} /*** end of UartReceivePacket ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool UartReceiveByte(blt_int8u *data)
{
blt_bool result = BLT_FALSE;
/* reception event pending? */
if (UARTx->RSRC.bits.SRR != 0)
{
/* read out the newly received byte */
*data = UARTx->RBUF.bits.RD_VALUE;
/* reset the reception event flag */
UARTx->RSRC.bits.CLRR = 1;
/* set result to indicate that a new byte was received */
result = BLT_TRUE;
}
/* inform caller about the result */
return result;
} /*** end of UartReceiveByte ***/
/************************************************************************************//**
** \brief Transmits a communication interface byte.
** \param data Value of byte that is to be transmitted.
** \return BLT_TRUE if the byte was transmitted, BLT_FALSE otherwise.
**
****************************************************************************************/
static blt_bool UartTransmitByte(blt_int8u data)
{
blt_int32u timeout;
blt_bool result = BLT_TRUE;
/* reset transmit buffer interrupt request */
UARTx->TBSRC.bits.CLRR = 1;
/* write byte to transmit buffer register */
UARTx->TBUF.reg = data;
/* set timeout time to wait for transmit completion. */
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
/* wait for transmit buffer register to be empty */
while (UARTx->TBSRC.bits.SRR == 0)
{
/* keep the watchdog happy */
CopService();
/* break loop upon timeout. this would indicate a hardware failure. */
if (TimerGet() > timeout)
{
result = BLT_FALSE;
break;
}
}
/* give the result back to the caller */
return result;
} /*** end of UartTransmitByte ***/
#endif /* BOOT_COM_UART_ENABLE > 0 */
/*********************************** end of uart.c *************************************/