913 lines
28 KiB
C
913 lines
28 KiB
C
//*****************************************************************************
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//
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// flash.c - Driver for programming the on-chip flash.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup flash_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_flash.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/flashlib.h"
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#include "driverlib/interrupt.h"
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//*****************************************************************************
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//
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// An array that maps the specified memory bank to the appropriate Flash
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// Memory Protection Program Enable (FMPPE) register.
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//
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//*****************************************************************************
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static const unsigned long g_pulFMPPERegs[] =
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{
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FLASH_FMPPE,
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FLASH_FMPPE1,
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FLASH_FMPPE2,
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FLASH_FMPPE3
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};
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//*****************************************************************************
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//
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// An array that maps the specified memory bank to the appropriate Flash
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// Memory Protection Read Enable (FMPRE) register.
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//
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//*****************************************************************************
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static const unsigned long g_pulFMPRERegs[] =
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{
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FLASH_FMPRE,
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FLASH_FMPRE1,
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FLASH_FMPRE2,
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FLASH_FMPRE3
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};
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//*****************************************************************************
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//
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//! Gets the number of processor clocks per micro-second.
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//!
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//! This function returns the number of clocks per micro-second, as presently
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//! known by the flash controller.
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//!
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//! \return Returns the number of processor clocks per micro-second.
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//
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//*****************************************************************************
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unsigned long
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FlashUsecGet(void)
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{
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//
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// Return the number of clocks per micro-second.
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//
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return(HWREG(FLASH_USECRL) + 1);
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}
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//*****************************************************************************
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//
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//! Sets the number of processor clocks per micro-second.
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//!
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//! \param ulClocks is the number of processor clocks per micro-second.
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//!
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//! This function is used to tell the flash controller the number of processor
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//! clocks per micro-second. This value must be programmed correctly or the
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//! flash most likely will not program correctly; it has no affect on reading
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//! flash.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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FlashUsecSet(unsigned long ulClocks)
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{
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//
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// Set the number of clocks per micro-second.
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//
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HWREG(FLASH_USECRL) = ulClocks - 1;
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}
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//*****************************************************************************
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//
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//! Erases a block of flash.
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//!
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//! \param ulAddress is the start address of the flash block to be erased.
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//!
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//! This function will erase a 1 kB block of the on-chip flash. After erasing,
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//! the block will be filled with 0xFF bytes. Read-only and execute-only
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//! blocks cannot be erased.
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//!
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//! This function will not return until the block has been erased.
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//!
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//! \return Returns 0 on success, or -1 if an invalid block address was
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//! specified or the block is write-protected.
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//
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//*****************************************************************************
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long
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FlashClear(unsigned long ulAddress)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
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//
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// Clear the flash access interrupt.
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//
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HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
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//
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// Erase the block.
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//
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HWREG(FLASH_FMA) = ulAddress;
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HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
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//
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// Wait until the block has been erased.
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//
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while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
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{
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}
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//
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// Return an error if an access violation occurred.
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//
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if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
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{
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return(-1);
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}
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//
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// Success.
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//
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return(0);
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}
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//*****************************************************************************
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//
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//! Programs flash.
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//!
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//! \param pulData is a pointer to the data to be programmed.
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//! \param ulAddress is the starting address in flash to be programmed. Must
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//! be a multiple of four.
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//! \param ulCount is the number of bytes to be programmed. Must be a multiple
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//! of four.
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//!
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//! This function will program a sequence of words into the on-chip flash.
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//! Programming each location consists of the result of an AND operation
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//! of the new data and the existing data; in other words bits that contain
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//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
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//! to 1. Therefore, a word can be programmed multiple times as long as these
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//! rules are followed; if a program operation attempts to change a 0 bit to
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//! a 1 bit, that bit will not have its value changed.
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//!
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//! Since the flash is programmed one word at a time, the starting address and
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//! byte count must both be multiples of four. It is up to the caller to
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//! verify the programmed contents, if such verification is required.
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//!
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//! This function will not return until the data has been programmed.
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//!
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//! \return Returns 0 on success, or -1 if a programming error is encountered.
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//
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//*****************************************************************************
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long
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FlashProgram(unsigned long *pulData, unsigned long ulAddress,
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unsigned long ulCount)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & 3));
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ASSERT(!(ulCount & 3));
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//
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// Clear the flash access interrupt.
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//
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HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
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//
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// See if this device has a write buffer.
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//
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if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
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{
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//
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// Loop over the words to be programmed.
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//
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while(ulCount)
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{
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//
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// Set the address of this block of words.
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//
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HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
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//
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// Loop over the words in this 32-word block.
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//
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while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
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(ulCount != 0))
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{
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//
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// Write this word into the write buffer.
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//
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HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
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ulAddress += 4;
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ulCount -= 4;
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}
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//
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// Program the contents of the write buffer into flash.
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//
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HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
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//
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// Wait until the write buffer has been programmed.
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//
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while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
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{
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}
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}
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}
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else
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{
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//
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// Loop over the words to be programmed.
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//
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while(ulCount)
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{
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//
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// Program the next word.
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//
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HWREG(FLASH_FMA) = ulAddress;
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HWREG(FLASH_FMD) = *pulData;
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HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
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//
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// Wait until the word has been programmed.
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//
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while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
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{
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}
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//
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// Increment to the next word.
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//
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pulData++;
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ulAddress += 4;
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ulCount -= 4;
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}
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}
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//
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// Return an error if an access violation occurred.
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//
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if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
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{
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return(-1);
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}
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//
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// Success.
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//
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return(0);
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}
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//*****************************************************************************
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//
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//! Gets the protection setting for a block of flash.
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//!
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//! \param ulAddress is the start address of the flash block to be queried.
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//!
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//! This function will get the current protection for the specified 2 kB block
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//! of flash. Each block can be read/write, read-only, or execute-only.
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//! Read/write blocks can be read, executed, erased, and programmed. Read-only
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//! blocks can be read and executed. Execute-only blocks can only be executed;
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//! processor and debugger data reads are not allowed.
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//!
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//! \return Returns the protection setting for this block. See
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//! FlashProtectSet() for possible values.
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//
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//*****************************************************************************
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tFlashProtection
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FlashProtectGet(unsigned long ulAddress)
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{
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unsigned long ulFMPRE, ulFMPPE;
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unsigned long ulBank;
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//
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// Check the argument.
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//
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ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
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//
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// Calculate the Flash Bank from Base Address, and mask off the Bank
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// from ulAddress for subsequent reference.
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//
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ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
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ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
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//
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// Read the appropriate flash protection registers for the specified
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// flash bank.
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//
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ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
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ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
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//
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// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
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// bits of the FMPPE register are used for JTAG protect options, and are
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// not available for the FLASH protection scheme. When Querying Block
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// Protection, assume these bits are 1.
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//
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if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
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{
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ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
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}
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//
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// Check the appropriate protection bits for the block of memory that
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// is specified by the address.
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//
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switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
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FLASH_FMP_BLOCK_0) << 1) |
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((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
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{
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//
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// This block is marked as execute only (that is, it can not be erased
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// or programmed, and the only reads allowed are via the instruction
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// fetch interface).
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//
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case 0:
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case 1:
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{
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return(FlashExecuteOnly);
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}
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//
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// This block is marked as read only (that is, it can not be erased or
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// programmed).
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//
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case 2:
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{
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return(FlashReadOnly);
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}
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//
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// This block is read/write; it can be read, erased, and programmed.
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//
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case 3:
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default:
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{
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return(FlashReadWrite);
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}
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}
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}
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//*****************************************************************************
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//
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//! Sets the protection setting for a block of flash.
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//!
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//! \param ulAddress is the start address of the flash block to be protected.
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//! \param eProtect is the protection to be applied to the block. Can be one
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//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
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//!
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//! This function will set the protection for the specified 2 kB block of
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//! flash. Blocks which are read/write can be made read-only or execute-only.
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//! Blocks which are read-only can be made execute-only. Blocks which are
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//! execute-only cannot have their protection modified. Attempts to make the
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//! block protection less stringent (that is, read-only to read/write) will
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//! result in a failure (and be prevented by the hardware).
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//!
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//! Changes to the flash protection are maintained only until the next reset.
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//! This allows the application to be executed in the desired flash protection
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//! environment to check for inappropriate flash access (via the flash
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//! interrupt). To make the flash protection permanent, use the
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//! FlashProtectSave() function.
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//!
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//! \return Returns 0 on success, or -1 if an invalid address or an invalid
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//! protection was specified.
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//
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//*****************************************************************************
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long
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FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
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{
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unsigned long ulProtectRE, ulProtectPE;
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unsigned long ulBank;
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//
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// Check the argument.
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//
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ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
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ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
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(eProtect == FlashExecuteOnly));
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//
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// Convert the address into a block number.
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//
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ulAddress /= FLASH_PROTECT_SIZE;
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//
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// ulAddress contains a "raw" block number. Derive the Flash Bank from
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// the "raw" block number, and convert ulAddress to a "relative"
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// block number.
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//
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ulBank = ((ulAddress / 32) % 4);
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ulAddress %= 32;
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//
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// Get the current protection for the specified flash bank.
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//
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ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
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ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
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//
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// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
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// bits of the FMPPE register are used for JTAG protect options, and are
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// not available for the FLASH protection scheme. When setting protection,
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// check to see if block 30 or 31 and protection is FlashExecuteOnly. If
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// so, return an error condition.
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//
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if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
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{
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if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
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{
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return(-1);
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}
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}
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//
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// Set the protection based on the requested proection.
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//
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switch(eProtect)
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{
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//
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// Make this block execute only.
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//
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case FlashExecuteOnly:
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{
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//
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// Turn off the read and program bits for this block.
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//
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ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
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ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
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//
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// We're done handling this protection.
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//
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break;
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}
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//
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// Make this block read only.
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//
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case FlashReadOnly:
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{
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//
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// The block can not be made read only if it is execute only.
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//
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if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
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FLASH_FMP_BLOCK_0)
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{
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return(-1);
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}
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|
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//
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// Make this block read only.
|
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//
|
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ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
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|
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//
|
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// We're done handling this protection.
|
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//
|
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break;
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}
|
|
|
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//
|
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// Make this block read/write.
|
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//
|
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case FlashReadWrite:
|
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default:
|
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{
|
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//
|
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// The block can not be made read/write if it is not already
|
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// read/write.
|
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//
|
|
if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
|
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FLASH_FMP_BLOCK_0) ||
|
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(((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
|
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FLASH_FMP_BLOCK_0))
|
|
{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// The block is already read/write, so there is nothing to do.
|
|
//
|
|
return(0);
|
|
}
|
|
}
|
|
|
|
//
|
|
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
|
|
// bits of the FMPPE register are used for JTAG options, and are not
|
|
// available for the FLASH protection scheme. When setting block
|
|
// protection, ensure that these bits are not altered.
|
|
//
|
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if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
|
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{
|
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ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
|
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ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
|
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(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
|
|
}
|
|
|
|
//
|
|
// Set the new protection for the specified flash bank.
|
|
//
|
|
HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
|
|
HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
|
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|
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//
|
|
// Success.
|
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//
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Saves the flash protection settings.
|
|
//!
|
|
//! This function will make the currently programmed flash protection settings
|
|
//! permanent. This is a non-reversible operation; a chip reset or power cycle
|
|
//! will not change the flash protection.
|
|
//!
|
|
//! This function will not return until the protection has been saved.
|
|
//!
|
|
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
FlashProtectSave(void)
|
|
{
|
|
int ulTemp, ulLimit;
|
|
|
|
//
|
|
// If running on a Sandstorm-class device, only trigger a save of the first
|
|
// two protection registers (FMPRE and FMPPE). Otherwise, save the
|
|
// entire bank of flash protection registers.
|
|
//
|
|
ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
|
|
for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
|
|
{
|
|
//
|
|
// Tell the flash controller to write the flash protection register.
|
|
//
|
|
HWREG(FLASH_FMA) = ulTemp;
|
|
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
|
|
|
//
|
|
// Wait until the write has completed.
|
|
//
|
|
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
|
{
|
|
}
|
|
}
|
|
|
|
//
|
|
// Success.
|
|
//
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the user registers.
|
|
//!
|
|
//! \param pulUser0 is a pointer to the location to store USER Register 0.
|
|
//! \param pulUser1 is a pointer to the location to store USER Register 1.
|
|
//!
|
|
//! This function will read the contents of user registers (0 and 1), and
|
|
//! store them in the specified locations.
|
|
//!
|
|
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
|
|
{
|
|
//
|
|
// Verify that the pointers are valid.
|
|
//
|
|
ASSERT(pulUser0 != 0);
|
|
ASSERT(pulUser1 != 0);
|
|
|
|
//
|
|
// Verify that hardware supports user registers.
|
|
//
|
|
if(CLASS_IS_SANDSTORM)
|
|
{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// Get and store the current value of the user registers.
|
|
//
|
|
*pulUser0 = HWREG(FLASH_USERREG0);
|
|
*pulUser1 = HWREG(FLASH_USERREG1);
|
|
|
|
//
|
|
// Success.
|
|
//
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the user registers.
|
|
//!
|
|
//! \param ulUser0 is the value to store in USER Register 0.
|
|
//! \param ulUser1 is the value to store in USER Register 1.
|
|
//!
|
|
//! This function will set the contents of the user registers (0 and 1) to
|
|
//! the specified values.
|
|
//!
|
|
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
|
|
{
|
|
//
|
|
// Verify that hardware supports user registers.
|
|
//
|
|
if(CLASS_IS_SANDSTORM)
|
|
{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// Save the new values into the user registers.
|
|
//
|
|
HWREG(FLASH_USERREG0) = ulUser0;
|
|
HWREG(FLASH_USERREG1) = ulUser1;
|
|
|
|
//
|
|
// Success.
|
|
//
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Saves the user registers.
|
|
//!
|
|
//! This function will make the currently programmed user register settings
|
|
//! permanent. This is a non-reversible operation; a chip reset or power cycle
|
|
//! will not change this setting.
|
|
//!
|
|
//! This function will not return until the protection has been saved.
|
|
//!
|
|
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
FlashUserSave(void)
|
|
{
|
|
//
|
|
// Verify that hardware supports user registers.
|
|
//
|
|
if(CLASS_IS_SANDSTORM)
|
|
{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// Setting the MSB of FMA will trigger a permanent save of a USER
|
|
// register. Bit 0 will indicate User 0 (0) or User 1 (1).
|
|
//
|
|
HWREG(FLASH_FMA) = 0x80000000;
|
|
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
|
|
|
//
|
|
// Wait until the write has completed.
|
|
//
|
|
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Tell the flash controller to write the USER1 Register.
|
|
//
|
|
HWREG(FLASH_FMA) = 0x80000001;
|
|
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
|
|
|
//
|
|
// Wait until the write has completed.
|
|
//
|
|
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Success.
|
|
//
|
|
return(0);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for the flash interrupt.
|
|
//!
|
|
//! \param pfnHandler is a pointer to the function to be called when the flash
|
|
//! interrupt occurs.
|
|
//!
|
|
//! This sets the handler to be called when the flash interrupt occurs. The
|
|
//! flash controller can generate an interrupt when an invalid flash access
|
|
//! occurs, such as trying to program or erase a read-only block, or trying to
|
|
//! read from an execute-only block. It can also generate an interrupt when a
|
|
//! program or erase operation has completed. The interrupt will be
|
|
//! automatically enabled when the handler is registered.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntRegister(void (*pfnHandler)(void))
|
|
{
|
|
//
|
|
// Register the interrupt handler, returning an error if an error occurs.
|
|
//
|
|
IntRegister(INT_FLASH, pfnHandler);
|
|
|
|
//
|
|
// Enable the flash interrupt.
|
|
//
|
|
IntEnable(INT_FLASH);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters the interrupt handler for the flash interrupt.
|
|
//!
|
|
//! This function will clear the handler to be called when the flash interrupt
|
|
//! occurs. This will also mask off the interrupt in the interrupt controller
|
|
//! so that the interrupt handler is no longer called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntUnregister(void)
|
|
{
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
IntDisable(INT_FLASH);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(INT_FLASH);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
|
|
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
|
|
//!
|
|
//! Enables the indicated flash controller interrupt sources. Only the sources
|
|
//! that are enabled can be reflected to the processor interrupt; disabled
|
|
//! sources have no effect on the processor.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntEnable(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Enable the specified interrupts.
|
|
//
|
|
HWREG(FLASH_FCIM) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
|
|
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
|
|
//!
|
|
//! Disables the indicated flash controller interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntDisable(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(FLASH_FCIM) &= ~(ulIntFlags);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param bMasked is false if the raw interrupt status is required and true if
|
|
//! the masked interrupt status is required.
|
|
//!
|
|
//! This returns the interrupt status for the flash controller. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return The current interrupt status, enumerated as a bit field of
|
|
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
FlashIntStatus(tBoolean bMasked)
|
|
{
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return(HWREG(FLASH_FCMISC));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(FLASH_FCRIS));
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
|
|
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
|
|
//!
|
|
//! The specified flash controller interrupt sources are cleared, so that they
|
|
//! no longer assert. This must be done in the interrupt handler to keep it
|
|
//! from being called again immediately upon exit.
|
|
//!
|
|
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
|
|
//! take several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (because the interrupt controller still sees
|
|
//! the interrupt source asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntClear(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Clear the flash interrupt.
|
|
//
|
|
HWREG(FLASH_FCMISC) = ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|