2012-06-15 21:51:23 +00:00
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#include "stm32f0xx_conf.h"
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2012-06-16 17:37:50 +00:00
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void SysTick_Handler(void) {
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static uint16_t tick = 0;
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2012-06-16 18:47:01 +00:00
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2012-06-16 17:37:50 +00:00
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switch (tick++) {
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case 100:
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tick = 0;
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GPIOC->ODR ^= (1 << 8);
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break;
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}
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}
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2012-06-15 20:10:19 +00:00
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int main(void)
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{
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2012-06-16 18:47:01 +00:00
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RCC->AHBENR |= RCC_AHBENR_GPIOCEN; // enable the clock to GPIOC
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2012-06-15 21:51:23 +00:00
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//(RM0091 lists this as IOPCEN, not GPIOCEN)
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // enable TIM2 clock
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2012-06-15 21:17:36 +00:00
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2012-06-15 20:10:19 +00:00
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GPIOC->MODER = (1 << 16);
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2012-06-16 18:47:01 +00:00
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2012-06-16 17:37:50 +00:00
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SysTick_Config(SystemCoreClock/100);
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2012-06-16 18:47:01 +00:00
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2012-06-15 21:51:23 +00:00
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TIM2->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock
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TIM2->DIER |= TIM_DIER_UIE; // enable update interrupt
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TIM2->ARR = 0x01; // count to 1 (autoreload value 1)
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TIM2->CR1 |= TIM_CR1_ARPE | TIM_CR1_CEN; // autoreload on, counter enabled
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TIM2->EGR = 1; // trigger update event to reload timer registers
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2012-06-16 18:47:01 +00:00
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2012-06-15 21:51:23 +00:00
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while(1);
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2012-06-16 18:47:01 +00:00
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2012-06-15 20:10:19 +00:00
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}
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