2008-10-27 16:20:26 +00:00
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/*
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*
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* (c) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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2010-08-04 01:33:15 +00:00
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#include <linux/clk.h>
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2008-10-27 16:20:26 +00:00
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#include <errno.h>
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2011-09-22 17:02:57 +00:00
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#include <io.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/gpio.h>
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2012-03-30 04:58:47 +00:00
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#include <mach/io.h>
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#include <mach/cpu.h>
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2008-10-27 16:20:26 +00:00
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#include <gpio.h>
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static int gpio_banks;
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2012-03-30 04:58:47 +00:00
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static int cpu_has_pio3;
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2008-10-27 16:20:26 +00:00
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static struct at91_gpio_bank *gpio;
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2012-03-30 04:58:47 +00:00
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/*
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* Functionnality can change with newer chips
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*/
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2008-10-27 16:20:26 +00:00
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static inline void __iomem *pin_to_controller(unsigned pin)
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{
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2009-10-03 23:20:22 +00:00
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pin -= PIN_BASE;
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2008-10-27 16:20:26 +00:00
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pin /= 32;
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if (likely(pin < gpio_banks))
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return gpio[pin].regbase;
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return NULL;
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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2009-10-03 23:20:22 +00:00
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pin -= PIN_BASE;
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2008-10-27 16:20:26 +00:00
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return 1 << (pin % 32);
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}
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2009-10-03 23:20:22 +00:00
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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int at91_set_GPIO_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_GPIO_periph);
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int at91_set_A_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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2012-03-30 04:58:47 +00:00
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if (cpu_has_pio3) {
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__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
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pio + PIO_ABCDSR1);
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__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
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pio + PIO_ABCDSR2);
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} else {
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__raw_writel(mask, pio + PIO_ASR);
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}
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_A_periph);
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int at91_set_B_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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2012-03-30 04:58:47 +00:00
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if (cpu_has_pio3) {
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__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
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pio + PIO_ABCDSR1);
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__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
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pio + PIO_ABCDSR2);
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} else {
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__raw_writel(mask, pio + PIO_BSR);
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}
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_B_periph);
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2012-03-30 04:58:47 +00:00
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/*
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* mux the pin to the "C" internal peripheral role.
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*/
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int at91_set_C_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !cpu_has_pio3)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
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__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_C_periph);
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/*
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* mux the pin to the "C" internal peripheral role.
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*/
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int at91_set_D_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !cpu_has_pio3)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
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__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_D_periph);
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2008-10-27 16:20:26 +00:00
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ODR);
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__raw_writel(mask, pio + PIO_PER);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_gpio_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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__raw_writel(mask, pio + PIO_PER);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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2009-10-03 23:20:22 +00:00
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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int at91_set_deglitch(unsigned pin, int is_on)
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2008-10-27 16:20:26 +00:00
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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2009-10-03 23:20:22 +00:00
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if (!pio)
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2008-10-27 16:20:26 +00:00
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return -EINVAL;
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2012-03-30 04:58:47 +00:00
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if (cpu_has_pio3 && is_on)
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__raw_writel(mask, pio + PIO_IFSCDR);
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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2009-10-03 23:20:22 +00:00
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EXPORT_SYMBOL(at91_set_deglitch);
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2008-10-27 16:20:26 +00:00
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2012-03-30 04:58:47 +00:00
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/*
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* enable/disable the debounce filter;
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*/
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int at91_set_debounce(unsigned pin, int is_on, int div)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !cpu_has_pio3)
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return -EINVAL;
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if (is_on) {
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__raw_writel(mask, pio + PIO_IFSCER);
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__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
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__raw_writel(mask, pio + PIO_IFER);
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} else {
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__raw_writel(mask, pio + PIO_IFDR);
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}
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return 0;
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}
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EXPORT_SYMBOL(at91_set_debounce);
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2009-10-03 23:20:22 +00:00
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int at91_set_multi_drive(unsigned pin, int is_on)
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2008-10-27 16:20:26 +00:00
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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2009-10-03 23:20:22 +00:00
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if (!pio)
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2008-10-27 16:20:26 +00:00
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return -EINVAL;
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2009-10-03 23:20:22 +00:00
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__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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2009-10-03 23:20:22 +00:00
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EXPORT_SYMBOL(at91_set_multi_drive);
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2008-10-27 16:20:26 +00:00
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2012-03-30 04:58:47 +00:00
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/*
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* enable/disable the pull-down.
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* If pull-up already enabled while calling the function, we disable it.
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*/
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int at91_set_pulldown(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !cpu_has_pio3)
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return -EINVAL;
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/* Disable pull-up anyway */
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_pulldown);
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/*
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* disable Schmitt trigger
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*/
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int at91_disable_schmitt_trig(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !cpu_has_pio3)
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return -EINVAL;
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__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
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return 0;
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}
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EXPORT_SYMBOL(at91_disable_schmitt_trig);
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2008-10-27 16:20:26 +00:00
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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2009-10-03 23:20:22 +00:00
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int at91_set_gpio_value(unsigned pin, int value)
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2008-10-27 16:20:26 +00:00
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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2009-10-03 23:20:22 +00:00
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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return 0;
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2008-10-27 16:20:26 +00:00
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}
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2009-10-03 23:20:22 +00:00
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EXPORT_SYMBOL(at91_set_gpio_value);
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2008-10-27 16:20:26 +00:00
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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2009-10-03 23:20:22 +00:00
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int at91_get_gpio_value(unsigned pin)
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2008-10-27 16:20:26 +00:00
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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if (!pio)
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return -EINVAL;
|
2009-10-03 23:20:22 +00:00
|
|
|
pdsr = __raw_readl(pio + PIO_PDSR);
|
2008-10-27 16:20:26 +00:00
|
|
|
return (pdsr & mask) != 0;
|
|
|
|
}
|
2009-10-03 23:20:22 +00:00
|
|
|
EXPORT_SYMBOL(at91_get_gpio_value);
|
|
|
|
|
|
|
|
int gpio_direction_input(unsigned pin)
|
|
|
|
{
|
|
|
|
void __iomem *pio = pin_to_controller(pin);
|
|
|
|
unsigned mask = pin_to_mask(pin);
|
|
|
|
|
|
|
|
if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
|
|
|
|
return -EINVAL;
|
|
|
|
__raw_writel(mask, pio + PIO_ODR);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(gpio_direction_input);
|
|
|
|
|
|
|
|
int gpio_direction_output(unsigned pin, int value)
|
|
|
|
{
|
|
|
|
void __iomem *pio = pin_to_controller(pin);
|
|
|
|
unsigned mask = pin_to_mask(pin);
|
|
|
|
|
|
|
|
if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
|
|
|
|
return -EINVAL;
|
|
|
|
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
|
|
|
|
__raw_writel(mask, pio + PIO_OER);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(gpio_direction_output);
|
|
|
|
|
|
|
|
/*--------------------------------------------------------------------------*/
|
2008-10-27 16:20:26 +00:00
|
|
|
|
|
|
|
int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
|
|
|
|
{
|
2011-12-31 15:21:34 +00:00
|
|
|
unsigned i;
|
2008-10-27 16:20:26 +00:00
|
|
|
|
|
|
|
gpio = data;
|
|
|
|
gpio_banks = nr_banks;
|
|
|
|
|
2011-12-31 15:21:34 +00:00
|
|
|
for (i = 0; i < nr_banks; i++, data++) {
|
2010-08-04 01:33:15 +00:00
|
|
|
/* enable PIO controller's clock */
|
|
|
|
clk_enable(data->clock);
|
2008-10-27 16:20:26 +00:00
|
|
|
}
|
|
|
|
|
2012-03-30 04:58:47 +00:00
|
|
|
cpu_has_pio3 = cpu_is_at91sam9x5();
|
|
|
|
|
2008-10-27 16:20:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|