2007-07-05 16:01:24 +00:00
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/*
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* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*
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*/
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#include <asm/arch/imx-regs.h>
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2007-10-16 12:45:58 +00:00
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#define CPU200
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#ifdef CPU200
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#define CFG_MPCTL0_VAL 0x00321431
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#else
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#define CFG_MPCTL0_VAL 0x040e200e
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#endif
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#define BUS72
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#ifdef BUS72
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#define CFG_SPCTL0_VAL 0x04002400
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#endif
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#ifdef BUS96
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#define CFG_SPCTL0_VAL 0x04001800
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#endif
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#ifdef BUS64
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#define CFG_SPCTL0_VAL 0x08001800
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#endif
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/* Das ist der BCLK Divider, der aus der System PLL
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BCLK und HCLK erzeugt:
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31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
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0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
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0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
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0x2f001003 : 192MHz/5=38,4MHz
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0x2f000003 : 64MHz/1
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Bit 22: SPLL Restart
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Bit 21: MPLL Restart */
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#ifdef BUS64
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#define CFG_CSCR_VAL 0x2f030003
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#endif
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#ifdef BUS72
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#define CFG_CSCR_VAL 0x2f030403
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#endif
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/* Bit[0:3] contain PERCLK1DIV for UART 1
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0x000b00b ->b<- -> 192MHz/12=16MHz
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0x000b00b ->8<- -> 144MHz/09=16MHz
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0x000b00b ->3<- -> 64MHz/4=16MHz */
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#ifdef BUS96
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#define CFG_PCDR_VAL 0x000b00b5
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#endif
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#ifdef BUS64
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#define CFG_PCDR_VAL 0x000b00b3
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#endif
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#ifdef BUS72
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#define CFG_PCDR_VAL 0x000b00b8
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#endif
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2007-10-16 09:31:13 +00:00
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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2007-07-05 16:01:33 +00:00
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2007-10-16 09:31:13 +00:00
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.globl board_init_lowlevel
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board_init_lowlevel:
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2007-07-05 16:01:24 +00:00
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mov r10, lr
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2007-10-16 12:45:58 +00:00
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/* Change PERCLK1DIV to 14 ie 14+1 */
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2007-10-16 09:31:13 +00:00
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writel(CFG_PCDR_VAL, PCDR)
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2007-07-05 16:01:24 +00:00
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2007-10-16 12:45:58 +00:00
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/* set MCU PLL Control Register 0 */
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2007-10-16 09:31:13 +00:00
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writel(CFG_MPCTL0_VAL, MPCTL0)
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2007-07-05 16:01:24 +00:00
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2007-10-16 12:45:58 +00:00
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/* set mpll restart bit */
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2007-07-05 16:01:24 +00:00
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<21)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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2007-10-16 12:45:58 +00:00
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/* set System PLL Control Register 0 */
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2007-10-16 09:31:13 +00:00
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writel(CFG_SPCTL0_VAL, SPCTL0)
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2007-07-05 16:01:24 +00:00
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2007-10-16 12:45:58 +00:00
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/* set spll restart bit */
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2007-07-05 16:01:24 +00:00
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<22)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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2007-10-16 09:31:13 +00:00
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writel(CFG_CSCR_VAL, CSCR)
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2007-07-05 16:01:24 +00:00
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/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
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*this.....
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*
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* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
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* register 1, this stops it using the output of the PLL and thus runs at the
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* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
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* use the value set in the CM_OSC registers...regardless of what you set it
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* too! Thus, although i thought i was running at 140MHz, i'm actually running
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* at 40!..
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* Slapping this into my bootloader does the trick...
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* MRC p15,0,r0,c1,c0,0 ; read core configuration register
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* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
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* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
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* register
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*/
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MRC p15,0,r0,c1,c0,0
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ORR r0,r0,#0xC0000000
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MCR p15,0,r0,c1,c0,0
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2007-10-16 09:31:13 +00:00
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x08000000
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bls 1f
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cmp pc, #0x09000000
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bhi 1f
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2007-07-05 16:01:24 +00:00
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2007-10-16 09:31:13 +00:00
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mov pc,r10
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2007-07-05 16:01:24 +00:00
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2007-10-16 09:31:13 +00:00
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1:
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2007-07-05 16:01:24 +00:00
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/* SDRAM Setup */
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2007-10-16 09:31:13 +00:00
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writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */
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writel(0x0, 0x08200000) /* Issue Precharge all Command */
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writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */
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2007-07-05 16:01:24 +00:00
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ldr r0, =0x08000000
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ldr r1, =0x0 /* Issue AutoRefresh Command */
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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2007-10-16 09:31:13 +00:00
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writel(0xb10a8300, SDCTL0)
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writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
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writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */
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2007-07-05 16:01:24 +00:00
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mov pc,r10
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