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barebox
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Merge branch 'for-next/imx'

This commit is contained in:
Sascha Hauer 2013-02-04 15:48:53 +01:00
parent 22e2544809 13b0a5a271
commit 265e6da19d
42 changed files with 341 additions and 592 deletions
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54
arch/arm/boards/ccxmx51/ccxmx51.c
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@ -50,26 +50,26 @@
#include "ccxmx51.h"
static struct ccxmx51_ident ccxmx51_ids[] = {
/* 0x00 */ { "Unknown", 0, 0, 0, 0, 0 },
/* 0x01 */ { "Not supported", 0, 0, 0, 0, 0 },
/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1 },
/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0 },
/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1 },
/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 0 },
/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 0, 1, 0, 1 },
/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", SZ_256M, 0, 1, 0, 0 },
/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 1, 1, 0, 1 },
/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", SZ_256M, 1, 1, 0, 0 },
/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 0, 1, 0, 1 },
/* 0x0d */ { "i.MX512@800MHz", SZ_128M, 0, 0, 0, 0 },
/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", SZ_128M, 1, 1, 0, 0 },
/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 1, 1, 0, 1 },
/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", SZ_128M, 0, 1, 0, 0 },
/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1 },
/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
/* 0x00 */ { "Unknown", 0, 0, 0, 0 },
/* 0x01 */ { "Not supported", 0, 0, 0, 0 },
/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", 0, 1, 1, 1 },
/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", 0, 1, 1, 0 },
/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", 1, 1, 1, 1 },
/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", 1, 1, 1, 0 },
/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x0d */ { "i.MX512@800MHz", 0, 0, 0, 0 },
/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
};
struct ccxmx51_ident *ccxmx51_id;
@ -363,12 +363,12 @@ static int ccxmx51_power_init(void)
/* De-assert reset of external devices on GP01, GPO2, GPO3 and GPO4 */
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val);
/* GPO1 - External */
/* GP02 - LAN9221 */
/* GP03 - FEC */
/* GP04 - Wireless */
if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth0)
/* GP02 - LAN9221 Power */
/* GP03 - FEC Reset */
/* GP04 - Wireless Power */
if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth1)
val |= (1 << 8);
if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth1)
if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth0)
val |= (1 << 10);
if (ccxmx51_id->wless)
val |= (1 << 12);
@ -408,8 +408,6 @@ static int ccxmx51_devices_init(void)
break;
}
printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
}
imx51_add_uart1();
@ -435,8 +433,8 @@ static int ccxmx51_devices_init(void)
#ifdef CONFIG_DRIVER_NET_FEC_IMX
if (ccxmx51_id->eth0 && !pwr) {
imx51_add_fec(&fec_info);
eth_register_ethaddr(0, hwid);
imx51_add_fec(&fec_info);
}
#endif

1
arch/arm/boards/ccxmx51/ccxmx51.h
View File

@ -23,7 +23,6 @@ struct ccxmx51_hwid {
struct ccxmx51_ident {
const char *id_string;
const int mem_sz;
const char industrial;
const char eth0;
const char eth1;

1
arch/arm/boards/ccxmx51/ccxmx51js.c
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@ -59,6 +59,7 @@ static iomux_v3_cfg_t ccxmx51js_pads[] = {
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
MX51_PAD_DISPB2_SER_RS__GPIO3_8, /* Reset */
};
static struct esdhc_platform_data sdhc1_pdata = {

14
arch/arm/boards/efika-mx-smartbook/board.c
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@ -198,7 +198,7 @@ static int efikamx_mem_init(void)
{
arm_add_mem_device("ram0", 0x90000000, SZ_512M);
return 0;
return 0;
}
mem_initcall(efikamx_mem_init);
@ -220,7 +220,7 @@ static const struct spi_board_info efikamx_spi_board_info[] = {
.chip_select = 1,
.max_speed_hz = 20 * 1000 * 1000,
.bus_num = 0,
},
},
};
static void efikamx_power_init(void)
@ -294,11 +294,11 @@ static void efikamx_power_init(void)
/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
mc13xxx_reg_read(mc, MC13892_REG_SETTING_0, &val);
val &= ~(MC13892_SETTING_0_VCAM_MASK |
MC13892_SETTING_0_VGEN3_MASK |
MC13892_SETTING_0_VDIG_MASK);
MC13892_SETTING_0_VGEN3_MASK |
MC13892_SETTING_0_VDIG_MASK);
val |= MC13892_SETTING_0_VDIG_1_8 |
MC13892_SETTING_0_VGEN3_1_8 |
MC13892_SETTING_0_VCAM_2_6;
MC13892_SETTING_0_VGEN3_1_8 |
MC13892_SETTING_0_VCAM_2_6;
mc13xxx_reg_write(mc, MC13892_REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
@ -455,7 +455,7 @@ static int efikamx_devices_init(void)
imx51_add_mmc1(&efikasb_sd2_data);
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
led_gpio_register(&leds[i]);
imx51_add_i2c1(NULL);

7
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
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@ -235,10 +235,3 @@ static int eukrea_cpuimx25_console_init(void)
}
console_initcall(eukrea_cpuimx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
}
#endif

35
arch/arm/boards/eukrea_cpuimx25/lowlevel.c
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@ -30,27 +30,9 @@
#include <asm-generic/memory_layout.h>
#include <asm/system.h>
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
void __bare_init __naked reset(void)
{
uint32_t r;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
register uint32_t loops = 0x20000;
common_reset();
@ -146,21 +128,10 @@ void __bare_init __naked reset(void)
writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
src = (unsigned int *)MX25_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx25_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif

9
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
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@ -248,12 +248,3 @@ static int eukrea_cpuimx27_late_init(void)
}
late_initcall(eukrea_cpuimx27_late_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

23
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
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@ -126,28 +126,7 @@ reset:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret
cmp pc, r2
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
b nand_boot /* Load barebox from NAND Flash */
/* to SDRAM */
b imx27_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
ret:

46
arch/arm/boards/eukrea_cpuimx35/lowlevel.c
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@ -35,34 +35,10 @@
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
void __bare_init __naked reset(void)
{
uint32_t r, s;
unsigned long ccm_base = MX35_CCM_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
register uint32_t loops = 0x20000;
common_reset();
@ -155,23 +131,17 @@ void __bare_init __naked reset(void)
writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx35_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif
}

9
arch/arm/boards/freescale-mx25-3-stack/3stack.c
View File

@ -274,14 +274,6 @@ static int imx25_console_init(void)
console_initcall(imx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
static int imx25_core_setup(void)
{
writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
@ -289,4 +281,3 @@ static int imx25_core_setup(void)
}
core_initcall(imx25_core_setup);

23
arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
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@ -100,28 +100,7 @@ reset:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =MX25_NFC_BASE_ADDR /* start of NFC SRAM */
ldr r2, =MX25_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret
cmp pc, r2
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
b nand_boot /* Load barebox from NAND Flash */
b imx25_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
ret:

12
arch/arm/boards/freescale-mx35-3-stack/3stack.c
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@ -427,15 +427,3 @@ static int f3s_pmic_init(void)
}
late_initcall(f3s_pmic_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
/*
* The driver is able to detect NAND's pagesize by CPU internal
* fuses or external pull ups. But not the blocksize...
*/
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

23
arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
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@ -157,28 +157,7 @@ reset:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =MX35_NFC_BASE_ADDR /* start of NFC SRAM */
ldr r2, =MX35_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
blo ret
cmp pc, r2
bhs ret
/* Move ourselves out of NFC SRAM */
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
b nand_boot /* Load barebox from NAND Flash */
ret:
b imx35_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
b board_init_lowlevel_return

45
arch/arm/boards/guf-cupid/lowlevel.c
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@ -42,26 +42,6 @@
#define SDRAM_COMPARE_CONST1 0x55555555
#define SDRAM_COMPARE_CONST2 0xaaaaaaaa
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr)
{
volatile int loop;
@ -188,9 +168,6 @@ void __bare_init __naked reset(void)
u32 r0, r1;
void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR;
int i;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
#endif
common_reset();
@ -330,23 +307,17 @@ void __bare_init __naked reset(void)
setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r0 = get_pc();
if (r0 < MX35_NFC_BASE_ADDR || r0 > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* Speed up NAND controller by adjusting the NFC divider */
r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r0 &= ~(0xf << 28);
r0 |= 0x1 << 28;
writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r0 = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r0));
imx35_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif
}

33
arch/arm/boards/guf-neso/lowlevel.c
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@ -30,27 +30,12 @@
#include <asm-generic/sections.h>
#include <asm-generic/memory_layout.h>
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
void __bare_init __naked reset(void)
{
uint32_t r;
int i;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
#endif
common_reset();
@ -102,23 +87,11 @@ void __bare_init __naked reset(void)
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* setup a stack to be able to call imx27_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
src = (unsigned int *)MX27_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx27_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif
}

8
arch/arm/boards/guf-vincell/env/init/bootargs-base vendored
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@ -1,8 +0,0 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "Base bootargs"
exit
fi
global.linux.bootargs.base="console=ttymxc0,115200"

7
arch/arm/boards/guf-vincell/env/init/config-board vendored Normal file
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@ -0,0 +1,7 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=vincell
global.linux.bootargs.base="console=ttymxc0,115200"

8
arch/arm/boards/guf-vincell/env/init/hostname vendored
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@ -1,8 +0,0 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "hostname"
exit
fi
global.hostname=vincell

9
arch/arm/boards/imx21ads/imx21ads.c
View File

@ -189,12 +189,3 @@ static int mx21ads_console_init(void)
}
console_initcall(mx21ads_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

23
arch/arm/boards/imx21ads/lowlevel_init.S
View File

@ -120,28 +120,7 @@ reset:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =MX21_NFC_BASE_ADDR /* start of NFC SRAM */
ldr r2, =MX21_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret
cmp pc, r2
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
b nand_boot /* Load barebox from NAND Flash */
/* SRAM to SDRAM */
b imx21_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
ret:

12
arch/arm/boards/karo-tx25/board.c
View File

@ -20,6 +20,7 @@
#include <common.h>
#include <init.h>
#include <driver.h>
#include <sizes.h>
#include <environment.h>
#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
@ -102,10 +103,10 @@ static int tx25_devices_init(void)
imx25_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
add_mem_device("sram0", 0x78000000, 128 * 1024,
@ -154,13 +155,6 @@ static int tx25_console_init(void)
console_initcall(tx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
}
#endif
static iomux_v3_cfg_t tx25_lcdc_gpios[] = {
MX25_PAD_A18__GPIO_2_4, /* LCD Reset (active LOW) */
MX25_PAD_PWM__GPIO_1_26, /* LCD Backlight brightness 0: full 1: off */

6
arch/arm/boards/karo-tx25/env/bin/init_board vendored
View File

@ -1,6 +0,0 @@
if [ -e /dev/fb0 -a -e /env/splash.bmp ]; then
splash /env/splash.bmp
fb0.enable=1
fi

10
arch/arm/boards/karo-tx25/env/boot/nand-ubi vendored Normal file
View File

@ -0,0 +1,10 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "nand (UBI)"
exit
fi
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"

48
arch/arm/boards/karo-tx25/env/config vendored
View File

@ -1,48 +0,0 @@
global.hostname=tx25
baseboard=tx28stk5
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.ethaddr=de:ad:be:ef:00:00
#eth0.netmask=a.b.c.d
#eth0.serverip=a.b.c.d
#eth0.gateway=a.b.c.d
# can be either 'nfs' or 'tftp'
kernel_loc=tftp
# can be either 'net' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-${global.hostname}.$rootfs_type
kernelimage=zImage-${global.hostname}
#kernelimage=uImage-${global.hostname}
#kernelimage=Image-${global.hostname}
#kernelimage=Image-${global.hostname}.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200 tx25_base=$baseboard"
nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
nand_device=mxc_nand
rootfs_mtdblock_nand=3
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

7
arch/arm/boards/karo-tx25/env/init/config-board vendored Normal file
View File

@ -0,0 +1,7 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=tx25
global.linux.bootargs.base="console=ttymxc0,115200"

11
arch/arm/boards/karo-tx25/env/init/mtdparts-nand vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NAND partitions"
exit
fi
mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

33
arch/arm/boards/karo-tx25/lowlevel.c
View File

@ -28,18 +28,6 @@
#include <asm-generic/sections.h>
#include <asm-generic/memory_layout.h>
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
uint32_t esdcfg)
{
@ -67,10 +55,6 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
void __bare_init __naked reset(void)
{
uint32_t r;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
common_reset();
@ -149,21 +133,10 @@ void __bare_init __naked reset(void)
setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
src = (unsigned int *)MX25_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx25_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif

34
arch/arm/boards/pcm037/lowlevel.c
View File

@ -30,28 +30,13 @@
#include <asm/barebox-arm-head.h>
#include <mach/esdctl.h>
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
void __bare_init __naked reset(void)
{
uint32_t r;
volatile int v;
#ifdef CONFIG_NAND_IMX_BOOT
int i;
unsigned int *trg, *src;
#endif
common_reset();
writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
@ -141,21 +126,10 @@ void __bare_init __naked reset(void)
#endif
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX31_NFC_BASE_ADDR || r > MX31_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* setup a stack to be able to call imx31_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
src = (unsigned int *)MX31_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx31_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif

8
arch/arm/boards/pcm037/pcm037.c
View File

@ -253,11 +253,3 @@ static int imx31_console_init(void)
}
console_initcall(imx31_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

34
arch/arm/boards/pcm038/lowlevel.c
View File

@ -31,27 +31,13 @@
#include "pll.h"
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
void __bare_init __naked reset(void)
{
uint32_t r;
int i;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
#endif
common_reset();
/* ahb lite ip interface */
@ -108,23 +94,11 @@ void __bare_init __naked reset(void)
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* setup a stack to be able to call mx27_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
src = (unsigned int *)MX27_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx27_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif
}

47
arch/arm/boards/pcm043/lowlevel.c
View File

@ -40,36 +40,13 @@
#define CCM_PDR0_399 0x00011000
#define CCM_PDR0_532 0x00001000
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif
void __bare_init __naked reset(void)
{
uint32_t r, s;
unsigned long ccm_base = MX35_CCM_BASE_ADDR;
unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
common_reset();
r = get_cr();
@ -206,23 +183,17 @@ void __bare_init __naked reset(void)
writel(0x00002000, esdctl_base + IMX_ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800)
board_init_lowlevel_return();
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
src = (unsigned int *)MX35_NFC_BASE_ADDR;
trg = (unsigned int *)_text;
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
imx35_barebox_boot_nand_external();
#else
board_init_lowlevel_return();
#endif
}

26
arch/arm/boards/phycard-i.MX27/lowlevel_init.S
View File

@ -111,31 +111,7 @@ reset:
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret
cmp pc, r2
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
ldr r0,=_text
ldr r1,=_barebox_image_size
bl imx_nand_load_image
b board_init_lowlevel_return
b imx27_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
ret:

24
arch/arm/configs/ccmx51_defconfig
View File

@ -2,54 +2,60 @@ CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX51=y
CONFIG_MACH_CCMX51=y
CONFIG_AEABI=y
CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/ccxmx51/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_NANDTEST=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
CONFIG_CMD_CLK=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_NET_SMC911X=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_USB=y
CONFIG_USB_IMX_CHIPIDEA=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
# CONFIG_MCI_WRITE is not set
CONFIG_MCI_IMX_ESDHC=y
CONFIG_FS_CRAMFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_LZO_DECOMPRESS=y

42
arch/arm/configs/tx25stk5_defconfig
View File

@ -1,58 +1,71 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX25=y
CONFIG_MACH_TX25=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x91d00000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx25/env"
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_DIRNAME=y
CONFIG_CMD_LN=y
CONFIG_CMD_READLINK=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OFTREE_PROBE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_CMD_TFTP=y
CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
@ -62,5 +75,14 @@ CONFIG_NAND_IMX=y
CONFIG_UBI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y

1
arch/arm/mach-imx/Kconfig
View File

@ -259,6 +259,7 @@ config MACH_FREESCALE_MX25_3STACK
config MACH_TX25
bool "Ka-Ro TX25"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say Y here if you are using the Ka-Ro tx25 board

67
arch/arm/mach-imx/clk-imx21.c
View File

@ -45,9 +45,52 @@
#define CCM_PMCOUNT 0x30
#define CCM_WKGDCTL 0x34
#define PCCR0_UART1_EN (1 << 0)
#define PCCR0_UART2_EN (1 << 1)
#define PCCR0_UART3_EN (1 << 2)
#define PCCR0_UART4_EN (1 << 3)
#define PCCR0_CSPI1_EN (1 << 4)
#define PCCR0_CSPI2_EN (1 << 5)
#define PCCR0_SSI1_EN (1 << 6)
#define PCCR0_SSI2_EN (1 << 7)
#define PCCR0_FIRI_EN (1 << 8)
#define PCCR0_SDHC1_EN (1 << 9)
#define PCCR0_SDHC2_EN (1 << 10)
#define PCCR0_GPIO_EN (1 << 11)
#define PCCR0_I2C_EN (1 << 12)
#define PCCR0_DMA_EN (1 << 13)
#define PCCR0_USBOTG_EN (1 << 14)
#define PCCR0_EMMA_EN (1 << 15)
#define PCCR0_SSI2_BAUD_EN (1 << 16)
#define PCCR0_SSI1_BAUD_EN (1 << 17)
#define PCCR0_PERCLK3_EN (1 << 18)
#define PCCR0_NFC_EN (1 << 19)
#define PCCR0_FRI_BAUD_EN (1 << 20)
#define PCCR0_SLDC_EN (1 << 21)
#define PCCR0_PERCLK4_EN (1 << 22)
#define PCCR0_HCLK_BMI_EN (1 << 23)
#define PCCR0_HCLK_USBOTG_EN (1 << 24)
#define PCCR0_HCLK_SLCDC_EN (1 << 25)
#define PCCR0_HCLK_LCDC_EN (1 << 26)
#define PCCR0_HCLK_EMMA_EN (1 << 27)
#define PCCR0_HCLK_BROM_EN (1 << 28)
#define PCCR0_HCLK_DMA_EN (1 << 30)
#define PCCR0_HCLK_CSI_EN (1 << 31)
#define PCCR1_CSPI3_EN (1 << 23)
#define PCCR1_WDT_EN (1 << 24)
#define PCCR1_GPT1_EN (1 << 25)
#define PCCR1_GPT2_EN (1 << 26)
#define PCCR1_GPT3_EN (1 << 27)
#define PCCR1_PWM_EN (1 << 28)
#define PCCR1_RTC_EN (1 << 29)
#define PCCR1_KPP_EN (1 << 30)
#define PCCR1_OWIRE_EN (1 << 31)
enum imx21_clks {
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, clk_max
per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, lcdc_ahb_gate,
lcdc_ipg_gate, clk_max
};
static struct clk *clks[clk_max];
@ -70,14 +113,16 @@ static int imx21_ccm_probe(struct device_d *dev)
base = dev_request_mem_region(dev, 0);
writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
(1 << 13) | (1 << 14) | (1 << 19) | (1 << 22) |
(1 << 24) | (1 << 26) | (1 << 30),
writel(PCCR0_UART1_EN | PCCR0_UART2_EN | PCCR0_UART3_EN | PCCR0_UART4_EN |
PCCR0_CSPI1_EN | PCCR0_CSPI2_EN | PCCR0_SDHC1_EN |
PCCR0_SDHC2_EN | PCCR0_GPIO_EN | PCCR0_I2C_EN | PCCR0_DMA_EN |
PCCR0_USBOTG_EN | PCCR0_NFC_EN | PCCR0_PERCLK4_EN |
PCCR0_HCLK_USBOTG_EN | PCCR0_HCLK_DMA_EN,
base + CCM_PCCR0);
writel((1 << 23) | (1 << 24) | (1 << 25) | (1 << 26) | (1 << 27) |
(1 << 28) | (1 << 29) | (1 << 30) | (1 << 31),
writel(PCCR1_CSPI3_EN | PCCR1_WDT_EN | PCCR1_GPT1_EN | PCCR1_GPT2_EN |
PCCR1_GPT3_EN | PCCR1_PWM_EN | PCCR1_RTC_EN | PCCR1_KPP_EN |
PCCR1_OWIRE_EN,
base + CCM_PCCR1);
clks[ckil] = clk_fixed("ckil", lref);
@ -99,6 +144,12 @@ static int imx21_ccm_probe(struct device_d *dev)
clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3);
clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4);
clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR0, 26);
/*
* i.MX21 doesn't have an IPG clock for the LCD. To avoid even more conditionals
* in the framebuffer code, provide a dummy clock.
*/
clks[lcdc_ipg_gate] = clk_fixed("dummy", 0);
clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL);
@ -114,6 +165,8 @@ static int imx21_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ahb_gate], MX21_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX21_LCDC_BASE_ADDR, "ipg");
return 0;
}

2
arch/arm/mach-imx/clk-imx25.c
View File

@ -150,6 +150,8 @@ static int imx25_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ahb");
return 0;
}

16
arch/arm/mach-imx/clk-imx27.c
View File

@ -93,7 +93,7 @@
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
clko_en, lcdc_per_gate, clk_max
clko_en, lcdc_per_gate, lcdc_ahb_gate, lcdc_ipg_gate, clk_max
};
static struct clk *clks[clk_max];
@ -136,7 +136,7 @@ static int imx27_ccm_probe(struct device_d *dev)
base = dev_request_mem_region(dev, 0);
writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_LCDC_EN | PCCR0_IIM_EN |
PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN |
PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN |
PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN |
PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN |
@ -144,9 +144,9 @@ static int imx27_ccm_probe(struct device_d *dev)
base + CCM_PCCR0);
writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN |
PCCR1_HCLK_USB | PCCR1_HCLK_LCDC | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI |
PCCR1_WDT_EN | PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN |
PCCR1_UART4_EN | PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
PCCR1_HCLK_USB | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN |
PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
base + CCM_PCCR1);
clks[dummy] = clk_fixed("dummy", 0);
@ -179,7 +179,9 @@ static int imx27_ccm_probe(struct device_d *dev)
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 7);
clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 8);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15);
clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14);
clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL);
@ -202,6 +204,8 @@ static int imx27_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
return 0;

75
arch/arm/mach-imx/external-nand-boot.c
View File

@ -15,6 +15,8 @@
#include <init.h>
#include <io.h>
#include <linux/mtd/nand.h>
#include <asm/sections.h>
#include <asm/barebox-arm.h>
#include <mach/imx-nand.h>
#include <mach/generic.h>
#include <mach/imx21-regs.h>
@ -256,6 +258,79 @@ void __bare_init imx_nand_load_image(void *dest, int size)
}
}
/*
* We are now running at the address we are linked at. Now load the image from
* NAND to SDRAM and continue booting.
*/
static void __bare_init __naked insdram(void)
{
imx_nand_load_image((void *)_text, barebox_image_size);
board_init_lowlevel_return();
}
/*
* Load and start barebox from NAND. This function also checks if we are really
* running inside the NFC address space. If not, barebox is started from the
* currently running address without loading anything from NAND.
*/
void __bare_init __noreturn imx_barebox_boot_nand_external(unsigned long nfc_base)
{
u32 r;
u32 *src, *trg;
int i;
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < nfc_base || r > nfc_base + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)nfc_base;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
/* not reached */
while (1);
}
/*
* SoC specific entries for booting in external NAND mode. To be called from
* the board specific entry code. This is safe to call even if not booting from
* NAND. In this case the booting is continued without loading an image from
* NAND. This function needs a stack to be set up.
*/
void __bare_init __noreturn imx21_barebox_boot_nand_external(void)
{
imx_barebox_boot_nand_external(MX21_NFC_BASE_ADDR);
}
void __bare_init __noreturn imx25_barebox_boot_nand_external(void)
{
imx_barebox_boot_nand_external(MX25_NFC_BASE_ADDR);
}
void __bare_init __noreturn imx27_barebox_boot_nand_external(void)
{
imx_barebox_boot_nand_external(MX27_NFC_BASE_ADDR);
}
void __bare_init __noreturn imx31_barebox_boot_nand_external(void)
{
imx_barebox_boot_nand_external(MX31_NFC_BASE_ADDR);
}
void __bare_init __noreturn imx35_barebox_boot_nand_external(void)
{
imx_barebox_boot_nand_external(MX35_NFC_BASE_ADDR);
}
#define CONFIG_NAND_IMX_BOOT_DEBUG
#ifdef CONFIG_NAND_IMX_BOOT_DEBUG
#include <command.h>

5
arch/arm/mach-imx/include/mach/imx-nand.h
View File

@ -4,6 +4,11 @@
#include <linux/mtd/mtd.h>
void imx_nand_load_image(void *dest, int size);
void imx21_barebox_boot_nand_external(void);
void imx25_barebox_boot_nand_external(void);
void imx27_barebox_boot_nand_external(void);
void imx31_barebox_boot_nand_external(void);
void imx35_barebox_boot_nand_external(void);
void imx_nand_set_layout(int writesize, int datawidth);
struct imx_nand_platform_data {

6
arch/arm/mach-imx/include/mach/imx21-regs.h
View File

@ -129,12 +129,6 @@
#define MX21_MPCTL1_BRMO (1 << 6)
#define MX21_MPCTL1_LF (1 << 15)
#define MX21_PCCR0_PERCLK3_EN (1 << 18)
#define MX21_PCCR0_NFC_EN (1 << 19)
#define MX21_PCCR0_HCLK_LCDC_EN (1 << 26)
#define MX21_PCCR1_GPT1_EN (1 << 25)
#define MX21_CCSR_32K_SR (1 << 15)
#endif /* _IMX21_REGS_H */

29
drivers/video/imx.c
View File

@ -138,7 +138,10 @@ struct imxfb_rgb {
struct imxfb_info {
void __iomem *regs;
struct clk *clk;
struct clk *ahb_clk;
struct clk *ipg_clk;
struct clk *per_clk;
u_int pcr;
u_int pwmr;
@ -252,7 +255,9 @@ static void imxfb_enable_controller(struct fb_info *info)
writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
clk_enable(fbi->clk);
clk_enable(fbi->ahb_clk);
clk_enable(fbi->ipg_clk);
clk_enable(fbi->per_clk);
if (fbi->enable)
fbi->enable(1);
@ -267,7 +272,9 @@ static void imxfb_disable_controller(struct fb_info *info)
writel(0, fbi->regs + LCDC_RMCR);
clk_disable(fbi->clk);
clk_disable(fbi->per_clk);
clk_disable(fbi->ipg_clk);
clk_disable(fbi->ahb_clk);
}
/*
@ -321,7 +328,7 @@ static int imxfb_activate_var(struct fb_info *info)
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
fbi->regs + LCDC_CPOS);
lcd_clk = clk_get_rate(fbi->clk);
lcd_clk = clk_get_rate(fbi->per_clk);
tmp = mode->pixclock * (unsigned long long)lcd_clk;
@ -531,9 +538,17 @@ static int imxfb_probe(struct device_d *dev)
fbi = xzalloc(sizeof(*fbi));
info = &fbi->info;
fbi->clk = clk_get(dev, NULL);
if (IS_ERR(fbi->clk))
return PTR_ERR(fbi->clk);
fbi->per_clk = clk_get(dev, NULL);
if (IS_ERR(fbi->per_clk))
return PTR_ERR(fbi->per_clk);
fbi->ahb_clk = clk_get(dev, "ahb");
if (IS_ERR(fbi->ahb_clk))
return PTR_ERR(fbi->ahb_clk);
fbi->ipg_clk = clk_get(dev, "ipg");
if (IS_ERR(fbi->ipg_clk))
return PTR_ERR(fbi->ipg_clk);
fbi->mode = pdata->mode;
fbi->regs = dev_request_mem_region(dev, 0);