ARM: i.MX31: Add support for mx31moboard board
The mx31moboard is used on the marXbot, Eyebot and Footbot robot. Signed-off-by: Philippe Rétornaz <philippe.retornaz@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Philippe Rétornaz
Sascha Hauer
parent
82e69edac7
commit
325d844aaa
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@ -51,6 +51,7 @@ obj-$(CONFIG_MACH_MIOA701) += mioa701/
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obj-$(CONFIG_MACH_MMCCPU) += mmccpu/
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obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/
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obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/
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obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/
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obj-$(CONFIG_MACH_MX6Q_ARM2) += freescale-mx6-arm2/
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obj-$(CONFIG_MACH_NESO) += guf-neso/
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obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/
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@ -0,0 +1,20 @@
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#
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# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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#
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lwl-y += lowlevel.o
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obj-y += mx31moboard.o
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@ -0,0 +1,9 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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boot-menu-add-entry "$0" "NOR Flash"
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exit
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fi
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global.bootm.image="/dev/nor0.kernel"
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global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro"
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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boot-menu-add-entry "$0" "SD Boot"
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exit
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fi
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boot mci0
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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boot-menu-add-entry "$0" "USB Boot"
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exit
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fi
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boot ehci0
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@ -0,0 +1,7 @@
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#!/bin/sh
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# board defaults, do not change in running system. Change /env/config
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# instead
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global.boot.default="usbmsd sd nor"
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global.linux.bootargs.base="console=ttymxc0,921600"
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@ -0,0 +1,11 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "NOR partitions"
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exit
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fi
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mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
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kernelname="physmap-flash.0"
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mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
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@ -0,0 +1,114 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm.h>
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#include <asm/system.h>
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#include <asm-generic/memory_layout.h>
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#include <asm-generic/sections.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx31-regs.h>
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#include <mach/imx-pll.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/esdctl.h>
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static noinline __noreturn void mx31moboard_startup(void)
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{
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uint32_t r;
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volatile int c;
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/* Enable IPU Display interface */
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writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
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writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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for (c = 0; c < 0x4000; c++) ;
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writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
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MX31_CCM_CCMR);
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writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
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MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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writel(MX31_PDR0_CSI_PODF(0x1ff) | \
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MX31_PDR0_PER_PODF(7) | \
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MX31_PDR0_HSP_PODF(3) | \
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MX31_PDR0_NFC_PODF(5) | \
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MX31_PDR0_IPG_PODF(1) | \
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MX31_PDR0_MAX_PODF(3) | \
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MX31_PDR0_MCU_PODF(0), \
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MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) |
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IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C),
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MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
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IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
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MX31_CCM_SPCTL);
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/*
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* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0,
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* except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000)
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* and 0x43fa_c280 (untouched)
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* (behaviour copied by sha, source unknown)
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*/
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writel(0, 0x43fac26c); /* SDCLK */
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writel(0, 0x43fac270); /* CAS */
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writel(0, 0x43fac274); /* RAS */
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writel(0x1000, 0x43fac27c); /* CSD0 */
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/* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */
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for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
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writel(0, r);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0xa0000000)
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imx31_barebox_entry(0);
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writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
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writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
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writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
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writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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imx31_barebox_entry(0);
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}
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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arm_cpu_lowlevel_init();
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/* Temporary stack location in internal SRAM */
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arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8);
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mx31moboard_startup();
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}
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@ -0,0 +1,259 @@
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/*
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* (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* Board support for EPFL's, i.MX31 based CPU card
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*
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* Based on:
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* Board support for Phytec's, i.MX31 based CPU card, called: PCM037
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <fs.h>
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#include <gpio.h>
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#include <led.h>
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#include <environment.h>
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#include <usb/ulpi.h>
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#include <mach/imx31-regs.h>
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#include <mach/iomux-mx31.h>
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#include <asm/armlinux.h>
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#include <asm/sections.h>
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#include <mach/weim.h>
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#include <io.h>
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#include <asm/mmu.h>
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#include <partition.h>
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#include <generated/mach-types.h>
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#include <asm/barebox-arm.h>
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#include <mach/devices-imx31.h>
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#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
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#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
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static void mx31moboard_usb_init(void)
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{
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u32 tmp;
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if (!IS_ENABLED(CONFIG_USB))
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return;
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/* enable clock */
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tmp = readl(0x53f80000);
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tmp |= (1 << 9);
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writel(tmp, 0x53f80000);
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/* Host 2 */
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tmp = readl(MX31_IOMUXC_GPR);
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tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */
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writel(tmp, MX31_IOMUXC_GPR);
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
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#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
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| PAD_CTL_ODE_CMOS)
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imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG | PAD_CTL_100K_PU);
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imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG | PAD_CTL_100K_PU);
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imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG | PAD_CTL_100K_PU);
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imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG | PAD_CTL_100K_PU);
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imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
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imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
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imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
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imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
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imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
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imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
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imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
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imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
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gpio_request(USB_RESET_B, "usb-reset");
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gpio_direction_output(USB_RESET_B, 0);
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mdelay(5);
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gpio_set_value(USB_RESET_B, 1);
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mdelay(10);
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gpio_request(USBH2_EN_B, "usbh2-en");
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gpio_direction_output(USBH2_EN_B, 0);
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udelay(900);
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gpio_set_value(USBH2_EN_B, 1);
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udelay(200);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp &= ~((3 << 21) | 1);
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tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
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tmp &= ~(3 << 30);
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tmp |= 2 << 30;
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
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gpio_set_value(USBH2_EN_B, 0);
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mdelay(50);
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ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
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/* Set to Host mode */
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
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writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
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}
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static struct gpio_led mx31moboard_leds[] = {
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{
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.led = {
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.name = "coreboard-led-0:red:running"
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},
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.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
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}, {
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.led = {
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.name = "coreboard-led-1:red",
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},
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.gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
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}, {
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.led = {
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.name = "coreboard-led-2:red",
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},
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.gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
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}, {
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.led = {
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.name = "coreboard-led-3:red",
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},
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.gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
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},
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};
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static void mx31moboard_add_leds(void)
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{
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int i;
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if (!IS_ENABLED(CONFIG_LED_GPIO))
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return;
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for (i = 0; i < ARRAY_SIZE(mx31moboard_leds); i++) {
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led_gpio_register(&mx31moboard_leds[i]);
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led_set(&mx31moboard_leds[i].led, 0);
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}
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led_set_trigger(LED_TRIGGER_HEARTBEAT, &mx31moboard_leds[0].led);
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}
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static int mx31moboard_mmu_init(void)
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{
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l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
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return 0;
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}
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postmmu_initcall(mx31moboard_mmu_init);
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static const struct devfs_partition mx31moboard_nor0_partitions[] = {
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{
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.offset = 0,
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.size = SZ_512K,
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.flags = DEVFS_PARTITION_FIXED,
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.name = "self0",
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}, {
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.offset = DEVFS_PARTITION_APPEND,
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.size = SZ_256K,
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.name = "env0",
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}, {
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/* Sentinel */
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}
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};
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static int mx31moboard_devices_init(void)
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{
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/* CS0: Nor Flash */
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imx31_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800);
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/*
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* Up to 32MiB NOR type flash, connected to
|
||||
* CS line 0, data width is 16 bit
|
||||
*/
|
||||
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, SZ_32M, 0);
|
||||
|
||||
imx31_add_mmc0(NULL);
|
||||
|
||||
/*
|
||||
* Create partitions that should be
|
||||
* not touched by any regular user
|
||||
*/
|
||||
devfs_create_partitions("nor0", mx31moboard_nor0_partitions);
|
||||
protect_file("/dev/env0", 1);
|
||||
|
||||
mx31moboard_usb_init();
|
||||
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC,
|
||||
MX31_USB_HS2_BASE_ADDR, NULL);
|
||||
|
||||
mx31moboard_add_leds();
|
||||
|
||||
armlinux_set_architecture(MACH_TYPE_MX31MOBOARD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(mx31moboard_devices_init);
|
||||
|
||||
static unsigned int mx31moboard_iomux[] = {
|
||||
/* UART1 */
|
||||
MX31_PIN_RXD1__RXD1,
|
||||
MX31_PIN_TXD1__TXD1,
|
||||
MX31_PIN_CTS1__GPIO2_7,
|
||||
/* SDHC1 */
|
||||
MX31_PIN_SD1_DATA3__SD1_DATA3,
|
||||
MX31_PIN_SD1_DATA2__SD1_DATA2,
|
||||
MX31_PIN_SD1_DATA1__SD1_DATA1,
|
||||
MX31_PIN_SD1_DATA0__SD1_DATA0,
|
||||
MX31_PIN_SD1_CLK__SD1_CLK,
|
||||
MX31_PIN_SD1_CMD__SD1_CMD,
|
||||
MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
|
||||
/* LEDS */
|
||||
MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
|
||||
MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
|
||||
};
|
||||
|
||||
static int imx31_console_init(void)
|
||||
{
|
||||
imx_iomux_setup_multiple_pins(mx31moboard_iomux,
|
||||
ARRAY_SIZE(mx31moboard_iomux));
|
||||
|
||||
gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
|
||||
gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
|
||||
|
||||
barebox_set_model("EPFL mx31moboard");
|
||||
barebox_set_hostname("mx31moboard");
|
||||
|
||||
imx31_add_uart0();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(imx31_console_init);
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/** @page mx31moboard EPFL mx31moboard
|
||||
|
||||
This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with:
|
||||
|
||||
- 32MiB NOR type Flash Memory
|
||||
- 128MiB LPDDR
|
||||
- A least one SD slot
|
||||
- A least one USB host (H2)
|
||||
|
||||
*/
|
||||
|
|
@ -14,6 +14,7 @@ config ARCH_TEXT_BASE
|
|||
default 0xa7f00000 if MACH_PCA100
|
||||
default 0xa0000000 if MACH_PCM038
|
||||
default 0x87f00000 if MACH_PCM037
|
||||
default 0x87f00000 if MACH_MX31MOBOARD
|
||||
default 0x87f00000 if MACH_PCM043
|
||||
default 0x08f80000 if MACH_SCB9328
|
||||
default 0xa7e00000 if MACH_NESO
|
||||
|
|
@ -359,6 +360,16 @@ config MACH_PCM037
|
|||
Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
|
||||
with a Freescale i.MX31 Processor
|
||||
|
||||
config MACH_MX31MOBOARD
|
||||
bool "mx31moboard-i.MX31"
|
||||
select ARCH_IMX31
|
||||
select USB_ULPI if USB
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
select ARCH_HAS_L2X0
|
||||
help
|
||||
Say Y here if you are using EPFL mx31moboard board equipped
|
||||
with a Freescale i.MX31 Processor
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
comment "i.MX35 Boards"
|
||||
|
|
|
|||
Loading…
Reference in New Issue