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* Patches by Xianghua Xiao, 15 Oct 2003: 

- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
This commit is contained in:
wdenk 2003-10-15 23:53:47 +00:00
parent 2d5b561e2b
commit 42d1f0394b
174 changed files with 14773 additions and 3497 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
CHANGELOG
View File

@ -2,6 +2,14 @@
Changes for U-Boot 1.0.0:
======================================================================
* Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Fix flash timings on TRAB board
* Make sure HUSH is initialized for running auto-update scripts
* Make 5200 reset command _really_ reset the board, without running

25
CREDITS
View File

@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
E: bruno@exet-ag.de
D: Support for NetBSD (both as host and target system)
N: Swen Anderson
E: sand@peppercon.de
D: ERIC Support
N: Guillaume Alexandre
E: guillaume.alexandre@gespac.ch
D: Add PCIPPC6 configuration
N: Swen Anderson
E: sand@peppercon.de
D: ERIC Support
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
@ -190,6 +190,11 @@ N: Thomas Koeller
E: tkoeller@gmx.net
D: Port to Motorola Sandpoint 3 (MPC8240)
N: Raghu Krishnaprasad
E: Raghu.Krishnaprasad@fci.com
D: Support for Adder-II MPC852T evaluation board
W: http://www.forcecomputers.com
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
@ -307,12 +312,6 @@ E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
N: Raghu Krishnaprasad
E: Raghu.Krishnaprasad@fci.com
D: Support for Adder-II MPC852T evaluation board
W: http://www.forcecomputers.com
N: Xianghua Xiao
E: x.xiao@motorola.com
D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

13
MAINTAINERS
View File

@ -112,10 +112,6 @@ Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx
Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
ADDERII MPC852T
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
@ -158,6 +154,10 @@ Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
ADDERII MPC852T
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
@ -240,6 +240,11 @@ John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
Xianghua Xiao <x.xiao@motorola.com>
MPC8540ADS MPC8540
MPC8560ADS MPC8560
-------------------------------------------------------------------------
Unknown / orphaned boards:

11
MAKEALL
View File

@ -86,6 +86,14 @@ LIST_8260=" \
TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
"
#########################################################################
## MPC85xx Systems (includes 8540, 8560 etc.)
#########################################################################
LIST_85xx=" \
MPC8540ADS MPC8560ADS \
"
#########################################################################
## 74xx/7xx Systems
#########################################################################
@ -102,6 +110,7 @@ LIST_7xx=" \
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8xx} \
${LIST_824x} ${LIST_8260} \
${LIST_85xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
@ -180,7 +189,7 @@ build_target() {
for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx| \
ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|pxa|ixp| \
mips| \
x86|I486)

13
Makefile
View File

@ -106,6 +106,9 @@ endif
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
LIBS = board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
@ -774,6 +777,16 @@ TQM8265_AA_config: unconfig
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
#########################################################################
## MPC85xx Systems
#########################################################################
MPC8540ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
MPC8560ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
#########################################################################
## 74xx/7xx Systems
#########################################################################

12
README
View File

@ -146,6 +146,7 @@ Directory Hierarchy:
- cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
- cpu/mpc824x Files specific to Motorola MPC824x CPUs
- cpu/mpc8260 Files specific to Motorola MPC8260 CPU
- cpu/mpc85xx Files specific to Motorola MPC85xx CPUs
- cpu/ppc4xx Files specific to IBM 4xx CPUs
@ -199,6 +200,10 @@ Directory Hierarchy:
- board/mbx8xx Files specific to MBX boards
- board/mpc8260ads
Files specific to MPC8260ADS and PQ2FADS-ZU boards
- board/mpc8540ads
Files specific to MPC8540ADS boards
- board/mpc8560ads
Files specific to MPC8560ADS boards
- board/mpl/ Files specific to boards manufactured by MPL
- board/mpl/common Common files for MPL boards
- board/mpl/pip405 Files specific to PIP405 boards
@ -306,6 +311,7 @@ The following options need to be configured:
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
or CONFIG_MPC5xx
or CONFIG_MPC824X, CONFIG_MPC8260
or CONFIG_MPC85xx
or CONFIG_IOP480
or CONFIG_405GP
or CONFIG_405EP
@ -356,7 +362,8 @@ The following options need to be configured:
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900,
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS
ARM based boards:
-----------------
@ -1950,7 +1957,8 @@ configurations; the following names are supported:
GEN860T_config EBONY_config FPS860L_config
ELPT860_config cmi_mpc5xx_config NETVIA_config
at91rm9200dk_config omap1510inn_config MPC8260ADS_config
omap1610inn_config ZPC1900_config
omap1610inn_config ZPC1900_config MPC8540ADS_config
MPC8560ADS_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for

2
board/adderII/adderII.h
View File

@ -41,5 +41,3 @@
* | |
* | ... |
*****************************************************************************/

1
board/adderII/config.mk
View File

@ -26,4 +26,3 @@
#
TEXT_BASE = 0xFE000000

1
board/adderII/u-boot.lds
View File

@ -144,4 +144,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}

1
board/dk1c20/config.mk
View File

@ -27,4 +27,3 @@ TEXT_BASE = 0x018c0000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

1
board/dk1c20/u-boot.lds
View File

@ -67,4 +67,3 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}

2
board/dk1c20/vectors.S
View File

@ -120,5 +120,3 @@ _vectors:
.long _def_xhandler@h /* Vector 61 */
.long _def_xhandler@h /* Vector 62 */
.long _def_xhandler@h /* Vector 63 */

6
board/esd/common/xilinx_jtag/micro.c
View File

@ -385,10 +385,10 @@ char* xsvf_pzTapState[] =
};
#endif /* DEBUG_MODE */
//#ifdef DEBUG_MODE
// FILE* in; /* Legacy DEBUG_MODE file pointer */
/*#ifdef DEBUG_MODE */
/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
int xsvf_iDebugLevel;
//#endif /* DEBUG_MODE */
/*#endif /XXX* DEBUG_MODE */
/*============================================================================
* Utility Functions

1
board/mpc8266ads/mpc8266ads.c
View File

@ -584,4 +584,3 @@ void pci_init_board(void)
pci_mpc8250_init(&hose);
}
#endif

48
board/mpc8540ads/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o
SOBJS := init.o
#SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

32
board/mpc8540ads/config.mk Normal file
View File

@ -0,0 +1,32 @@
# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,Motorola Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# mpc8540ads board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1

539
board/mpc8540ads/flash.c Normal file
View File

@ -0,0 +1,539 @@
/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao,(X.Xiao@motorola.com)
*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Add support the Sharp chips on the mpc8260ads.
* I started with board/ip860/flash.c and made changes I found in
* the MTD project by David Schleef.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if !defined(CFG_NO_FLASH)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
#undef DEBUG
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size;
int i;
/* Init: enable write,
* or we cannot even write flash commands
*/
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
}
/* Static FLASH Bank configuration here - FIXME XXX */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
}
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
&flash_info[0]);
#endif
#endif
return (size);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("Intel "); break;
case FLASH_MAN_SHARP: printf ("Sharp "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
break;
case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
break;
case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
break;
case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
break;
case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
ulong sector_offset;
#ifdef DEBUG
printf("Check flash at 0x%08x\n",(uint)addr);
#endif
/* Write "Intelligent Identifier" command: read Manufacturer ID */
*addr = 0x90909090;
udelay(20);
asm("sync");
value = addr[0] & 0x00FF00FF;
#ifdef DEBUG
printf("manufacturer=0x%x\n",(uint)value);
#endif
switch (value) {
case MT_MANUFACT: /* SHARP, MT or => Intel */
case INTEL_ALT_MANU:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf("unknown manufacturer: %x\n", (unsigned int)value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1] & 0x00FF00FF; /* device ID */
#ifdef DEBUG
printf("deviceID=0x%x\n",(uint)value);
#endif
switch (value) {
case (INTEL_ID_28F016S):
info->flash_id += FLASH_28F016SV;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F160S3):
info->flash_id += FLASH_28F160S3;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F320S3):
info->flash_id += FLASH_28F320S3;
info->sector_count = 64;
info->size = 0x00800000;
sector_offset = 0x20000;
break; /* => 2x4 MB */
case (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
sector_offset = 0x40000;
break; /* => 2x8 MB */
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
info->sector_count = 32;
info->size = 0x00800000;
sector_offset = 0x40000;
break; /* => 4x2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += sector_offset;
/* don't know how to check sector protection */
info->protect[i] = 0;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
*addr = 0xFFFFFF; /* reset bank to read array mode */
asm("sync");
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
#ifdef DEBUG
printf("\nFlash Erase:\n");
#endif
/* Make Sure Block Lock Bit is not set. */
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
return 1;
}
/* Start erase on unprotected sectors */
#if defined(DEBUG)
printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
#endif
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
asm("sync");
last = start = get_timer (0);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
/* Single Block Erase Command */
*addr = 0x20202020;
asm("sync");
/* Confirm */
*addr = 0xD0D0D0D0;
asm("sync");
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
/* Resume Command, as per errata update */
*addr = 0xD0D0D0D0;
asm("sync");
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x00800080) != 0x00800080) {
if(*addr & 0x00200020){
printf("Error in Block Erase - Lock Bit may be set!\n");
printf("Status Register = 0x%X\n", (uint)*addr);
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
/* reset to read mode */
*addr = 0xFFFFFFFF;
asm("sync");
}
}
printf ("flash erase done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong start, csr;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = 0x10101010;
asm("sync");
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x00800080) != 0x00800080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
}
if (csr & 0x40404040) {
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
}
/* Clear Status Registers Command */
*addr = 0x50505050;
asm("sync");
/* Reset to read array mode */
*addr = 0xFFFFFFFF;
asm("sync");
return (flag);
}
/*-----------------------------------------------------------------------
* Clear Block Lock Bit, returns:
* 0 - OK
* 1 - Timeout
*/
static int clear_block_lock_bit(vu_long * addr)
{
ulong start, now;
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
*addr = 0x60606060;
asm("sync");
*addr = 0xd0d0d0d0;
asm("sync");
start = get_timer (0);
while((*addr & 0x00800080) != 0x00800080){
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
}
return 0;
}
#endif /* !CFG_NO_FLASH */

178
board/mpc8540ads/init.S Normal file
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@ -0,0 +1,178 @@
/*
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
.long 0x0a /* the following data table uses a few of 16 TLB entries */
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(128M) -or- larger
* f000_0000-f3ff_ffff: PCI(256M)
* f400_0000-f7ff_ffff: RapidIO(128M)
* f800_0000-ffff_ffff: localbus(128M)
* f800_0000-fbff_ffff: LBC SDRAM(64M)
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
* fdf0_0000-fdff_ffff: CCSRBAR(1M)
* fe00_0000-ffff_ffff: Flash(32M)
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
entry_end

265
board/mpc8540ads/mpc8540ads.c Normal file
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/*
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
long int fixed_sdram (void);
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
return 0;
}
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: Motorola MPC8540ADS Board\n");
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */

148
board/mpc8540ads/u-boot.lds Normal file
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/*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/mpc8540ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
board/mpc8540ads/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

48
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o
SOBJS := init.o
#SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

32
board/mpc8560ads/config.mk Normal file
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,2003 Motorola Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# mpc8560ads board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1

539
board/mpc8560ads/flash.c Normal file
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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao,(X.Xiao@motorola.com)
*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Add support the Sharp chips on the mpc8260ads.
* I started with board/ip860/flash.c and made changes I found in
* the MTD project by David Schleef.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if !defined(CFG_NO_FLASH)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
#undef DEBUG
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size;
int i;
/* Init: enable write,
* or we cannot even write flash commands
*/
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
/* set the default sector offset */
}
/* Static FLASH Bank configuration here - FIXME XXX */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
}
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size;
#if !defined(CONFIG_RAM_AS_FLASH)
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
&flash_info[0]);
#endif
#endif
return (size);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("Intel "); break;
case FLASH_MAN_SHARP: printf ("Sharp "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
break;
case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
break;
case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
break;
case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
break;
case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
ulong sector_offset;
#ifdef DEBUG
printf("Check flash at 0x%08x\n",(uint)addr);
#endif
/* Write "Intelligent Identifier" command: read Manufacturer ID */
*addr = 0x90909090;
udelay(20);
asm("sync");
value = addr[0] & 0x00FF00FF;
#ifdef DEBUG
printf("manufacturer=0x%x\n",(uint)value);
#endif
switch (value) {
case MT_MANUFACT: /* SHARP, MT or => Intel */
case INTEL_ALT_MANU:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf("unknown manufacturer: %x\n", (unsigned int)value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1] & 0x00FF00FF; /* device ID */
#ifdef DEBUG
printf("deviceID=0x%x\n",(uint)value);
#endif
switch (value) {
case (INTEL_ID_28F016S):
info->flash_id += FLASH_28F016SV;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F160S3):
info->flash_id += FLASH_28F160S3;
info->sector_count = 32;
info->size = 0x00400000;
sector_offset = 0x20000;
break; /* => 2x2 MB */
case (INTEL_ID_28F320S3):
info->flash_id += FLASH_28F320S3;
info->sector_count = 64;
info->size = 0x00800000;
sector_offset = 0x20000;
break; /* => 2x4 MB */
case (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
sector_offset = 0x40000;
break; /* => 8 MB */
case SHARP_ID_28F016SCL:
case SHARP_ID_28F016SCZ:
info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
info->sector_count = 32;
info->size = 0x00800000;
sector_offset = 0x40000;
break; /* => 4x2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += sector_offset;
/* don't know how to check sector protection */
info->protect[i] = 0;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (vu_long *)info->start[0];
*addr = 0xFFFFFF; /* reset bank to read array mode */
asm("sync");
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
#ifdef DEBUG
printf("\nFlash Erase:\n");
#endif
/* Make Sure Block Lock Bit is not set. */
if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
return 1;
}
/* Start erase on unprotected sectors */
#if defined(DEBUG)
printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
#endif
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
asm("sync");
last = start = get_timer (0);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
/* Single Block Erase Command */
*addr = 0x20202020;
asm("sync");
/* Confirm */
*addr = 0xD0D0D0D0;
asm("sync");
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
/* Resume Command, as per errata update */
*addr = 0xD0D0D0D0;
asm("sync");
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x00800080) != 0x00800080) {
if(*addr & 0x00200020){
printf("Error in Block Erase - Lock Bit may be set!\n");
printf("Status Register = 0x%X\n", (uint)*addr);
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
/* reset to read mode */
*addr = 0xFFFFFFFF;
asm("sync");
}
}
printf ("flash erase done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)dest;
ulong start, csr;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Write Command */
*addr = 0x10101010;
asm("sync");
/* Write Data */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
flag = 0;
while (((csr = *addr) & 0x00800080) != 0x00800080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
flag = 1;
break;
}
}
if (csr & 0x40404040) {
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
}
/* Clear Status Registers Command */
*addr = 0x50505050;
asm("sync");
/* Reset to read array mode */
*addr = 0xFFFFFFFF;
asm("sync");
return (flag);
}
/*-----------------------------------------------------------------------
* Clear Block Lock Bit, returns:
* 0 - OK
* 1 - Timeout
*/
static int clear_block_lock_bit(vu_long * addr)
{
ulong start, now;
/* Reset Array */
*addr = 0xffffffff;
asm("sync");
/* Clear Status Register */
*addr = 0x50505050;
asm("sync");
*addr = 0x60606060;
asm("sync");
*addr = 0xd0d0d0d0;
asm("sync");
start = get_timer (0);
while((*addr & 0x00800080) != 0x00800080){
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout on clearing Block Lock Bit\n");
*addr = 0xFFFFFFFF; /* reset bank */
asm("sync");
return 1;
}
}
return 0;
}
#endif /* !CFG_NO_FLASH */

178
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/*
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
.long 0x0a /* the following data table uses a few of 16 TLB entries */
.long TLB1_MAS0(1,1,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if defined(CFG_FLASH_PORT_WIDTH_16)
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,2,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,3,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
#if !defined(CONFIG_SPD_EEPROM)
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,4,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,5,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
.long TLB1_MAS0(1,6,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
#if defined(CONFIG_RAM_AS_FLASH)
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
#else
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,7,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
#else
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
#endif
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,8,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1,9,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
#else
.long TLB1_MAS0(1,15,0)
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/* LAW(Local Access Window) configuration:
* 0000_0000-0800_0000: DDR(128M) -or- larger
* f000_0000-f3ff_ffff: PCI(256M)
* f400_0000-f7ff_ffff: RapidIO(128M)
* f800_0000-ffff_ffff: localbus(128M)
* f800_0000-fbff_ffff: LBC SDRAM(64M)
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
* fdf0_0000-fdff_ffff: CCSRBAR(1M)
* fe00_0000-ffff_ffff: Flash(32M)
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
* Window.
* Note: If flash is 8M at default position(last 8M),no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
#if !defined(CONFIG_RAM_AS_FLASH)
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR2 0
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x03
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
entry_end

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/*
* (C) Copyright 2003,Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
#include <miiphy.h>
long int fixed_sdram (void);
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* MPC8560ADS Board Status & Control Registers */
typedef struct bscr_ {
volatile unsigned char bcsr0;
volatile unsigned char bcsr1;
volatile unsigned char bcsr2;
volatile unsigned char bcsr3;
volatile unsigned char bcsr4;
volatile unsigned char bcsr5;
} bcsr_t;
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
return 0;
}
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
#endif
/* reset Giga bit Ethernet port if needed here */
/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
bcsr->bcsr2 &= ~FETH2_RST;
udelay(2);
bcsr->bcsr2 |= FETH2_RST;
udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
bcsr->bcsr3 &= ~FETH3_RST;
udelay(2);
bcsr->bcsr3 |= FETH3_RST;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
miiphy_reset(0x0); /* reset PHY */
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: Motorola MPC8560ADS Board\n");
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
long int initdram (int board_type)
{
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
return ( CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */

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/*
* (C) Copyright 2002,2003,Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/mpc8560ads/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
board/mpc8560ads/init.o (.text)
cpu/mpc85xx/commproc.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/serial_scc.o (.text)
cpu/mpc85xx/ether_fcc.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1
board/mpl/common/flash.c
View File

@ -152,7 +152,6 @@ void setup_cs_reloc(void)
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1,flashcr, size_reg;

1
board/mpl/vcma9/cmd_vcma9.c
View File

@ -178,4 +178,3 @@ U_BOOT_CMD(
"vcma9 - VCMA9 specific commands\n",
"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
);

5
board/omap1610inn/flash.c
View File

@ -54,7 +54,6 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define mb() __asm__ __volatile__ ("" : : : "memory")
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
@ -240,8 +239,6 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
}
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
@ -298,8 +295,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
}
start = get_timer (0);
last = start;

2
board/omap1610inn/platform.S
View File

@ -132,8 +132,6 @@ watch2Wait:
bne watch2Wait
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location

1
board/sl8245/sl8245.c
View File

@ -92,4 +92,3 @@ void pci_init_board(void)
{
pci_mpc824x_init(&hose);
}

4
board/trab/memsetup.S
View File

@ -48,8 +48,8 @@
#define BWSCON 0x14000000
/* Bank0 */
#define B0_Tacs 0x0 /* 0 clk */
#define B0_Tcos 0x0 /* 0 clk */
#define B0_Tacs 0x3 /* 4 clk */
#define B0_Tcos 0x3 /* 4 clk */
#define B0_Tacc 0x7 /* 14 clk */
#define B0_Tcoh 0x0 /* 0 clk */
#define B0_Tah 0x0 /* 0 clk */

2
board/trab/trab_fkt.c
View File

@ -885,7 +885,6 @@ int do_thermo (char **argv)
}
int do_touch (char **argv)
{
int x, y;
@ -1039,7 +1038,6 @@ static void touch_read_x_y (int *px, int *py)
}
int do_rs485 (char **argv)
{
int timeout;

15
common/cmd_bdinfo.c
View File

@ -55,7 +55,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("flashoffset", bd->bi_flashoffset );
print_num ("sramstart", bd->bi_sramstart );
print_num ("sramsize", bd->bi_sramsize );
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
print_num ("immr_base", bd->bi_immr_base );
#endif
print_num ("bootflags", bd->bi_bootflags );
@ -66,13 +66,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP */
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq));
#endif
print_str ("intfreq", strmhz(buf, bd->bi_intfreq));
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
@ -81,12 +81,19 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
|| (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
printf ("\neth1addr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
}
#endif /* CONFIG_PN62 */
#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
printf ("\neth2addr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
}
#endif
#ifdef CONFIG_HERMES
print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
#endif

5
common/cmd_bootm.c
View File

@ -558,7 +558,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
/* convert all clock information to MHz */
kbd->bi_intfreq /= 1000000L;
kbd->bi_busfreq /= 1000000L;
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
kbd->bi_cpmfreq /= 1000000L;
kbd->bi_brgfreq /= 1000000L;
kbd->bi_sccfreq /= 1000000L;
@ -758,7 +758,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
SHOW_BOOT_PROGRESS (15);
#ifdef CFG_INIT_RAM_LOCK
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
/*
@ -1341,4 +1341,3 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag,
}
#endif /* CONFIG_LYNXKDI */

4
common/cmd_fat.c
View File

@ -37,8 +37,6 @@
#include <fat.h>
block_dev_desc_t *get_dev (char* ifname, int dev)
{
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
@ -121,8 +119,6 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
fatload, 6, 0, do_fat_fsload,
"fatload - load binary file from a dos filesystem\n",

1
common/lynxkdi.c
View File

@ -67,4 +67,3 @@ void lynxkdi_boot ( image_header_t *hdr )
#endif
#endif /* CONFIG_LYNXKDI */

1
cpu/arm920t/usb_ohci.h
View File

@ -224,7 +224,6 @@ struct ohci_regs {
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */

1
cpu/arm926ejs/interrupts.c
View File

@ -79,7 +79,6 @@ int disable_interrupts (void)
#endif
void bad_mode (void)
{
panic ("Resetting CPU ...\n");

4
cpu/arm926ejs/start.S
View File

@ -31,7 +31,6 @@
*/
#include <config.h>
#include <version.h>
@ -154,9 +153,6 @@ reset:
strh r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/

1
cpu/ixp/interrupts.c
View File

@ -60,7 +60,6 @@ int disable_interrupts (void)
#endif
void bad_mode (void)
{
panic ("Resetting CPU ...\n");

30
cpu/ixp/start.S
View File

@ -31,32 +31,32 @@
#include <version.h>
#include <asm/arch/ixp425.h>
#define MMU_Control_M 0x001 // Enable MMU
#define MMU_Control_A 0x002 // Enable address alignment faults
#define MMU_Control_C 0x004 // Enable cache
#define MMU_Control_W 0x008 // Enable write-buffer
#define MMU_Control_P 0x010 // Compatability: 32 bit code
#define MMU_Control_D 0x020 // Compatability: 32 bit data
#define MMU_Control_L 0x040 // Compatability:
#define MMU_Control_B 0x080 // Enable Big-Endian
#define MMU_Control_S 0x100 // Enable system protection
#define MMU_Control_R 0x200 // Enable ROM protection
#define MMU_Control_I 0x1000 // Enable Instruction cache
#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000
#define MMU_Control_M 0x001 /* Enable MMU */
#define MMU_Control_A 0x002 /* Enable address alignment faults */
#define MMU_Control_C 0x004 /* Enable cache */
#define MMU_Control_W 0x008 /* Enable write-buffer */
#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
#define MMU_Control_L 0x040 /* Compatability: */
#define MMU_Control_B 0x080 /* Enable Big-Endian */
#define MMU_Control_S 0x100 /* Enable system protection */
#define MMU_Control_R 0x200 /* Enable ROM protection */
#define MMU_Control_I 0x1000 /* Enable Instruction cache */
#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
/*
* Macro definitions
*/
// Delay a bit
/* Delay a bit */
.macro DELAY_FOR cycles, reg0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
.endm
// wait for coprocessor write complete
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
@ -331,8 +331,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_start_armboot: .word start_armboot
/****************************************************************************/
/* */
/* Interrupt handling */

45
cpu/mpc85xx/Makefile Normal file
View File

@ -0,0 +1,45 @@
#
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,X.Xiao@motorola.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tsec.o \
pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
OBJS = $(COBJS)
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
sinclude .depend
#########################################################################

214
cpu/mpc85xx/commproc.c Normal file
View File

@ -0,0 +1,214 @@
/*
* Adapted for Motorola MPC8560 chips
* Xianghua Xiao <x.xiao@motorola.com>
*
* This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
* 8220 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
* 2.3.99 Updates
* Copyright (c) 2003 Motorola,Inc.
*
* In addition to the individual control of the communication
* channels, there are a few functions that globally affect the
* communication processor.
*
* Buffer descriptors must be allocated from the dual ported memory
* space. The allocator for that is here. When the communication
* process is reset, we reclaim the memory available. There is
* currently no deallocator for this memory.
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#if defined(CONFIG_MPC8560)
/*
* because we have stack and init data in dual port ram
* we must reduce the size
*/
#undef CPM_DATAONLY_SIZE
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
void
m8560_cpm_reset(void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ulong count;
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Reclaim the DP memory for our use.
*/
gd->dp_alloc_base = CPM_DATAONLY_BASE;
gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
/*
* Reset CPM
*/
immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
} while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}
/* Allocate some memory from the dual ported ram.
* To help protocols with object alignment restrictions, we do that
* if they ask.
*/
uint
m8560_cpm_dpalloc(uint size, uint align)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
uint retloc;
uint align_mask, off;
uint savebase;
align_mask = align - 1;
savebase = gd->dp_alloc_base;
if ((off = (gd->dp_alloc_base & align_mask)) != 0)
gd->dp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
size += align - off;
if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
gd->dp_alloc_base = savebase;
panic("m8560_cpm_dpalloc: ran out of dual port ram!");
}
retloc = gd->dp_alloc_base;
gd->dp_alloc_base += size;
memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
return(retloc);
}
/* We also own one page of host buffer space for the allocation of
* UART "fifos" and the like.
*/
uint
m8560_cpm_hostalloc(uint size, uint align)
{
/* the host might not even have RAM yet - just use dual port RAM */
return (m8560_cpm_dpalloc(size, align));
}
/* Set a baud rate generator. This needs lots of work. There are
* eight BRGs, which can be connected to the CPM channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
* The baud rate clock is the system clock divided by something.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
/* This function is used by UARTS, or anything else that uses a 16x
* oversampled clock.
*/
void
m8560_cpm_setbrg(uint brg, uint rate)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
}
/* This function is used to set high speed synchronous baud rate
* clocks.
*/
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (div16)
*bp |= CPM_BRG_DIV16;
}
/* This function is used to set baud rate generators using an external
* clock source and 16x oversampling.
*/
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
if (brg < 4) {
bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
}
else {
bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
if (pinsel == 0)
*bp |= CPM_BRG_EXTC_CLK3_9;
else
*bp |= CPM_BRG_EXTC_CLK5_15;
}
#ifdef CONFIG_POST
void post_word_store (ulong a)
{
volatile ulong *save_addr =
(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
*save_addr = a;
}
ulong post_word_load (void)
{
volatile ulong *save_addr =
(volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
return *save_addr;
}
#endif /* CONFIG_POST */
#endif /* CONFIG_MPC8560 */

26
cpu/mpc85xx/config.mk Normal file
View File

@ -0,0 +1,26 @@
#
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao, X.Xiao@motorola.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float

151
cpu/mpc85xx/cpu.c Normal file
View File

@ -0,0 +1,151 @@
/*
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
/* ------------------------------------------------------------------------- */
int checkcpu (void)
{
uint pir = get_pir();
uint pvr = get_pvr();
printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir);
switch(pvr) {
default:
printf("PVR=%08x", pvr);
break;
}
printf("\n");
return 0;
}
/* ------------------------------------------------------------------------- */
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
/*
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
__asm__ __volatile__("lis 3, 0x7000" ::: "r3");
mtspr(DBCR0,3);
return 1;
}
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk (void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
return ((sys_info.freqSystemBus + 3L) / 4L);
}
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable) enable_interrupts();
}
void
reset_85xx_watchdog(void)
{
/*
* Clear TSR(WIS) bit by writing 1
*/
unsigned long val;
val = mfspr(tsr);
val |= 0x40000000;
mtspr(tsr, val);
}
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_DDR_ECC)
__inline__ void dcbz(const void* addr)
{
__asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
}
__inline__ void dcbf(const void* addr)
{
__asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
}
void dma_init(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
asm("sync; isync; msync");
return;
}
uint dma_check(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
while((status & 4) == 4) {
status = dma->sr0;
}
if (status != 0) {
printf ("DMA Error: status = %x\n", status);
}
return status;
}
int dma_xfer(void *dest, uint count, void *src) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
dma->bcr0 = count;
dma->mr0 = 0xf000004;
asm("sync;isync;msync");
dma->mr0 = 0xf000005;
asm("sync;isync;msync");
return dma_check();
}
#endif

205
cpu/mpc85xx/cpu_init.c Normal file
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/*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <asm/io.h>
#ifdef CONFIG_MPC8560
static void config_8560_ioports (volatile immap_t * immr)
{
int portnum;
for (portnum = 0; portnum < 4; portnum++) {
uint pmsk = 0,
ppar = 0,
psor = 0,
pdir = 0,
podr = 0,
pdat = 0;
iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
iop_conf_t *eiopc = iopc + 32;
uint msk = 1;
/*
* NOTE:
* index 0 refers to pin 31,
* index 31 refers to pin 0
*/
while (iopc < eiopc) {
if (iopc->conf) {
pmsk |= msk;
if (iopc->ppar)
ppar |= msk;
if (iopc->psor)
psor |= msk;
if (iopc->pdir)
pdir |= msk;
if (iopc->podr)
podr |= msk;
if (iopc->pdat)
pdat |= msk;
}
msk <<= 1;
iopc++;
}
if (pmsk != 0) {
volatile ioport_t *iop = ioport_addr (immr, portnum);
uint tpmsk = ~pmsk;
/*
* the (somewhat confused) paragraph at the
* bottom of page 35-5 warns that there might
* be "unknown behaviour" when programming
* PSORx and PDIRx, if PPARx = 1, so I
* decided this meant I had to disable the
* dedicated function first, and enable it
* last.
*/
iop->ppar &= tpmsk;
iop->psor = (iop->psor & tpmsk) | psor;
iop->podr = (iop->podr & tpmsk) | podr;
iop->pdat = (iop->pdat & tpmsk) | pdat;
iop->pdir = (iop->pdir & tpmsk) | pdir;
iop->ppar |= ppar;
}
}
}
#endif
/*
* Breathe some life into the CPU...
*
* Set up the memory map
* initialize a bunch of registers
*/
void cpu_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_MPC8560
config_8560_ioports(immap);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CFG_OR0_REMAP)
memctl->or0 = CFG_OR0_REMAP;
#endif
#if defined(CFG_OR1_REMAP)
memctl->or1 = CFG_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
memctl->br0 = CFG_BR0_PRELIM;
memctl->or0 = CFG_OR0_PRELIM;
#endif
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
memctl->or1 = CFG_OR1_PRELIM;
memctl->br1 = CFG_BR1_PRELIM;
#endif
#if !defined(CONFIG_MPC85xx)
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
memctl->br2 = CFG_BR2_PRELIM;
#endif
#endif
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
memctl->or3 = CFG_OR3_PRELIM;
memctl->br3 = CFG_BR3_PRELIM;
#endif
#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
memctl->or4 = CFG_OR4_PRELIM;
memctl->br4 = CFG_BR4_PRELIM;
#endif
#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
memctl->or5 = CFG_OR5_PRELIM;
memctl->br5 = CFG_BR5_PRELIM;
#endif
#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
memctl->or6 = CFG_OR6_PRELIM;
memctl->br6 = CFG_BR6_PRELIM;
#endif
#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
memctl->or7 = CFG_OR7_PRELIM;
memctl->br7 = CFG_BR7_PRELIM;
#endif
#if defined(CONFIG_MPC8560)
m8560_cpm_reset();
#endif
}
/*
* We initialize L2 as cache here.
*/
int cpu_init_r (void)
{
#if defined(CONFIG_L2_CACHE)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
volatile uint temp;
asm("msync;isync");
l2cache->l2ctl = 0x68000000; /* invalidate */
temp = l2cache->l2ctl;
asm("msync;isync");
l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
temp = l2cache->l2ctl;
asm("msync;isync");
printf("L2 cache enabled: 256KB\n");
#else
printf("L2 cache disabled.\n");
#endif
return 0;
}

461
cpu/mpc85xx/ether_fcc.c Normal file
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/*
* MPC8560 FCC Fast Ethernet
* Copyright (c) 2003 Motorola,Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
*
* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* MPC8560 FCC Fast Ethernet
* Basic ET HW initialization and packet RX/TX routines
*
* This code will not perform the IO port configuration. This should be
* done in the iop_conf_t structure specific for the board.
*
* TODO:
* add a PHY driver to do the negotiation
* reflect negotiation results in FPSMR
* look for ways to configure the board specific stuff elsewhere, eg.
* config_xxx.h or the board directory
*/
#include <common.h>
#include <malloc.h>
#include <asm/cpm_85xx.h>
#include <command.h>
#include <config.h>
#include <net.h>
#if defined(CONFIG_MPC8560)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
static struct ether_fcc_info_s
{
int ether_index;
int proff_enet;
ulong cpm_cr_enet_sblock;
ulong cpm_cr_enet_page;
ulong cmxfcr_mask;
ulong cmxfcr_value;
}
ether_fcc_info[] =
{
#ifdef CONFIG_ETHER_ON_FCC1
{
0,
PROFF_FCC1,
CPM_CR_FCC1_SBLOCK,
CPM_CR_FCC1_PAGE,
CFG_CMXFCR_MASK1,
CFG_CMXFCR_VALUE1
},
#endif
#ifdef CONFIG_ETHER_ON_FCC2
{
1,
PROFF_FCC2,
CPM_CR_FCC2_SBLOCK,
CPM_CR_FCC2_PAGE,
CFG_CMXFCR_MASK2,
CFG_CMXFCR_VALUE2
},
#endif
#ifdef CONFIG_ETHER_ON_FCC3
{
2,
PROFF_FCC3,
CPM_CR_FCC3_SBLOCK,
CPM_CR_FCC3_PAGE,
CFG_CMXFCR_MASK3,
CFG_CMXFCR_VALUE3
},
#endif
};
/*---------------------------------------------------------------------*/
/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
#define PKT_MAXDMA_SIZE 1520
/* The FCC stores dest/src/type, data, and checksum for receive packets. */
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
/* Maximum input buffer size. Must be a multiple of 32. */
#define PKT_MAXBLR_SIZE 1536
#define TOUT_LOOP 1000000
#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
/*
* FCC Ethernet Tx and Rx buffer descriptors.
* Provide for Double Buffering
* Note: PKTBUFSRX is defined in net.h
*/
typedef volatile struct rtxbd {
cbd_t rxbd[PKTBUFSRX];
cbd_t txbd[TX_BUF_CNT];
} RTXBD;
/* Good news: the FCC supports external BDs! */
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
#else
#error "rtx must be 64-bit aligned"
#endif
#define ET_DEBUG
static int fec_send(struct eth_device* dev, volatile void *packet, int length)
{
int i = 0;
int result = 0;
if (length <= 0) {
printf("fec: bad packet size: %d\n", length);
goto out;
}
for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= TOUT_LOOP) {
printf("fec: tx buffer not ready\n");
goto out;
}
}
rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx.txbd[txIdx].cbd_datlen = length;
rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
BD_ENET_TX_TC );
for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= TOUT_LOOP) {
printf("fec: tx error\n");
goto out;
}
}
#ifdef ET_DEBUG
printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
for(i=0;i<(length/16 + 1);i++) {
printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
}
#endif
/* return only status bits */
result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
txIdx = (txIdx + 1) % TX_BUF_CNT;
out:
return result;
}
static int fec_recv(struct eth_device* dev)
{
int length;
for (;;)
{
if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = rtx.rxbd[rxIdx].cbd_datlen;
if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
}
else {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[rxIdx], length - 4);
}
/* Give the buffer back to the FCC. */
rtx.rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
}
else {
rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
return length;
}
static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
#if 0
mii_discover_phy();
#endif
/* 28.9 - (1-2): ioports have been set up already */
/* 28.9 - (3): connect FCC's tx and rx clocks */
immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
}
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
}
/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
rxIdx = 0;
txIdx = 0;
/* Setup Receiver Buffer Descriptors */
for (i = 0; i < PKTBUFSRX; i++)
{
rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx.rxbd[i].cbd_datlen = 0;
rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/* Setup Ethernet Transmitter Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++)
{
rtx.txbd[i].cbd_sc = 0;
rtx.txbd[i].cbd_datlen = 0;
rtx.txbd[i].cbd_bufaddr = 0;
}
rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* 28.9 - (7): initialize parameter ram */
pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
/* clear whole structure to make sure all reserved fields are zero */
memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
/*
* common Parameter RAM area
*
* Allocate space in the reserved FCC area of DPRAM for the
* internal buffers. No one uses this space (yet), so we
* can do this. Later, we will add resource management for
* this area. CPM_FCC_SPECIAL_BASE: 0xb000.
*/
mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
/*
* Set maximum bytes per receive buffer.
* It must be a multiple of 32.
*/
pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
CFG_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
pram_ptr->fen_genfcc.fcc_rbdstat = 0;
pram_ptr->fen_genfcc.fcc_rbdlen = 0;
pram_ptr->fen_genfcc.fcc_rdptr = 0;
/* localbus SDRAM should be preferred */
pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
CFG_CPMFCR_RAMTYPE) << 24;
pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
pram_ptr->fen_genfcc.fcc_tbdstat = 0;
pram_ptr->fen_genfcc.fcc_tbdlen = 0;
pram_ptr->fen_genfcc.fcc_tdptr = 0;
/* protocol-specific area */
pram_ptr->fen_statbuf = 0x0;
pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
pram_ptr->fen_crcec = 0;
pram_ptr->fen_alec = 0;
pram_ptr->fen_disfc = 0;
pram_ptr->fen_retlim = 15; /* Retry limit threshold */
pram_ptr->fen_retcnt = 0;
pram_ptr->fen_pper = 0;
pram_ptr->fen_boffcnt = 0;
pram_ptr->fen_gaddrh = 0;
pram_ptr->fen_gaddrl = 0;
pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
/*
* Set Ethernet station address.
*
* This is supplied in the board information structure, so we
* copy that into the controller.
* So far we have only been given one Ethernet address. We make
* it unique by setting a few bits in the upper byte of the
* non-static part of the address.
*/
#define ea eth_get_dev()->enetaddr
pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
#undef ea
pram_ptr->fen_ibdcount = 0;
pram_ptr->fen_ibdstart = 0;
pram_ptr->fen_ibdend = 0;
pram_ptr->fen_txlen = 0;
pram_ptr->fen_iaddrh = 0; /* disable hash */
pram_ptr->fen_iaddrl = 0;
pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
/* pad pointer. use tiptr since we don't need a specific padding char */
pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
#if defined(ET_DEBUG)
printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
pram_ptr->fen_genfcc.fcc_rbase);
printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
pram_ptr->fen_genfcc.fcc_tbase);
#endif
/* 28.9 - (8)(9): clear out events in FCCE */
/* 28.9 - (9): FCCM: mask all events */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc1.fccm = 0;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc2.fccm = 0;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
immr->im_cpm.im_cpm_fcc3.fccm = 0;
}
/* 28.9 - (10-12): we don't use ethernet interrupts */
/* 28.9 - (13)
*
* Let's re-initialize the channel now. We have to do it later
* than the manual describes because we have just now finished
* the BD initialization.
*/
cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
info->cpm_cr_enet_sblock,
0x0c,
CPM_CR_INIT_TRX) | CPM_CR_FLG;
do {
__asm__ __volatile__ ("eieio");
} while (cp->cpcr & CPM_CR_FLG);
/* 28.9 - (14): enable tx/rx in gfmr */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 0;
}
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 1) {
immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 2) {
immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
}
}
int fec_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FCC%d ETHERNET",
ether_fcc_info[i].ether_index + 1);
dev->priv = &ether_fcc_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;
eth_register(dev);
}
return 1;
}
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
#endif /* CONFIG_MPC8560 */

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/*
* (C) Copyright 2003,Motorola Inc.
* Xianghua Xiao <x.xiao@motorola.com>
* Adapted for Motorola 85xx chip.
*
* (C) Copyright 2003
* Gleb Natapov <gnatapov@mrv.com>
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk
*
* Hardware I2C driver for MPC107 PCI bridge.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#define DEBUG
#if defined(DEBUG)
#define DEB(x) x
#else
#define DEB(x)
#endif
#ifdef CONFIG_HARD_I2C
#include <i2c.h>
#define TIMEOUT (CFG_HZ/4)
#define I2C_Addr ((unsigned *)(CFG_CCSRBAR + 0x3000))
#define I2CADR &I2C_Addr[0]
#define I2CFDR &I2C_Addr[1]
#define I2CCCR &I2C_Addr[2]
#define I2CCSR &I2C_Addr[3]
#define I2CCDR &I2C_Addr[4]
#define I2CDFSRR &I2C_Addr[5]
#define I2C_READ 1
#define I2C_WRITE 0
/* taken from linux include/asm-ppc/io.h */
inline unsigned in_le32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
inline void out_le32(volatile unsigned *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
#define writel(val, addr) out_le32(addr, val)
#define readl(addr) in_le32(addr)
void
i2c_init(int speed, int slaveadd)
{
/* stop I2C controller */
writel (0x0, I2CCCR);
/* set clock */
writel (0x3f, I2CFDR);
/* set default filter */
writel (0x10,I2CDFSRR);
/* write slave address */
writel (slaveadd, I2CADR);
/* clear status register */
writel (0x0, I2CCSR);
/* start I2C controller */
writel (MPC85xx_I2CCR_MEN, I2CCCR);
}
static __inline__ int
i2c_wait4bus (void)
{
ulong timeval = get_timer (0);
while (readl (I2CCSR) & MPC85xx_I2CSR_MBB)
if (get_timer (timeval) > TIMEOUT)
return -1;
return 0;
}
static __inline__ int
i2c_wait (int write)
{
u32 csr;
ulong timeval = get_timer (0);
do
{
csr = readl (I2CCSR);
if (!(csr & MPC85xx_I2CSR_MIF))
continue;
writel (0x0, I2CCSR);
if (csr & MPC85xx_I2CSR_MAL)
{
DEB(printf ("i2c_wait: MAL\n"));
return -1;
}
if (!(csr & MPC85xx_I2CSR_MCF))
{
DEB(printf ("i2c_wait: unfinished\n"));
return -1;
}
if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK))
{
DEB(printf ("i2c_wait: No RXACK\n"));
return -1;
}
return 0;
} while (get_timer (timeval) < TIMEOUT);
DEB(printf ("i2c_wait: timed out\n"));
return -1;
}
static __inline__ int
i2c_write_addr (u8 dev, u8 dir, int rsta)
{
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
(rsta?MPC85xx_I2CCR_RSTA:0), I2CCCR);
writel ((dev << 1) | dir, I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
return 0;
return 1;
}
static __inline__ int
__i2c_write (u8 *data, int length)
{
int i;
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, I2CCCR);
for (i=0; i < length; i++)
{
writel (data[i], I2CCDR);
if (i2c_wait (I2C_WRITE) < 0)
break;
}
return i;
}
static __inline__ int
__i2c_read (u8 *data, int length)
{
int i;
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
((length == 1) ? MPC85xx_I2CCR_TXAK : 0), I2CCCR);
/* dummy read */
readl (I2CCDR);
for (i=0; i < length; i++)
{
if (i2c_wait (I2C_READ) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
MPC85xx_I2CCR_TXAK, I2CCCR);
/* Generate stop on last byte */
if (i == length - 1)
writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
data[i] = readl (I2CCDR);
}
return i;
}
int
i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
{
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
goto exit;
if (i2c_write_addr (dev, I2C_READ, 1) == 0)
goto exit;
i = __i2c_read (data, length);
exit:
writel (MPC85xx_I2CCR_MEN, I2CCCR);
return !(i == length);
}
int
i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
{
int i = 0;
u8 *a = (u8*)&addr;
if (i2c_wait4bus () < 0)
goto exit;
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
goto exit;
if (__i2c_write (&a[4 - alen], alen) != alen)
goto exit;
i = __i2c_write (data, length);
exit:
writel (MPC85xx_I2CCR_MEN, I2CCCR);
return !(i == length);
}
int i2c_probe (uchar chip)
{
int tmp;
/*
* Try to read the first location of the chip. The underlying
* driver doesn't appear to support sending just the chip address
* and looking for an <ACK> back.
*/
udelay(10000);
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
char buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
return (buf[0]);
}
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
{
i2c_write (i2c_addr, reg, 1, &val, 1);
}
#endif /* CONFIG_HARD_I2C */

138
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/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 (440 port)
* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
*
* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
* Xianghua Xiao (X.Xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <ppc_asm.tmpl>
unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
static __inline__ unsigned long get_msr(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
asm volatile("isync");
}
void enable_interrupts (void)
{
set_msr (get_msr() | MSR_EE);
}
/* returns flag if MSR_EE was set before */
int disable_interrupts (void)
{
ulong msr = get_msr();
set_msr (msr & ~MSR_EE);
return ((msr & MSR_EE) != 0);
}
/* interrupt is not supported yet */
int interrupt_init (void)
{
return (0);
}
/*
* Install and free a interrupt handler. Not implemented yet.
*/
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
return;
}
void
irq_free_handler(int vec)
{
return;
}
/****************************************************************************/
volatile ulong timestamp = 0;
/*
* timer_interrupt - gets called when the decrementer overflows,
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
void timer_interrupt(struct pt_regs *regs)
{
printf ("*** Timer Interrupt *** ");
timestamp++;
#if defined(CONFIG_WATCHDOG)
if ((timestamp % 1000) == 0)
reset_85xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}
void reset_timer (void)
{
timestamp = 0;
}
ulong get_timer (ulong base)
{
return (timestamp - base);
}
void set_timer (ulong t)
{
timestamp = t;
}
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
/*******************************************************************************
*
* irqinfo - print information about PCI devices,not implemented.
*
*/
int
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf ("\nInterrupt-unsupported:\n");
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */

107
cpu/mpc85xx/pci.c Normal file
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/*
* Copyright (C) 2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI Configuration space access support for MPC85xx PCI Bridge
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ }
};
#endif
struct pci_controller local_hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxads_config_table,
#endif
};
void pci_init_board(void)
{
struct pci_controller* hose = (struct pci_controller *)&local_hose;
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
u16 reg16;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
CFG_PCI_MEM_BASE,
CFG_PCI_MEM_PHYS,
(CFG_PCI_MEM_SIZE/2),
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
(CFG_PCI_MEM_BASE+0x08000000),
(CFG_PCI_MEM_PHYS+0x08000000),
0x1000000, /* 16M */
PCI_REGION_IO);
hose->region_count = 2;
pci_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/* Clear non-reserved bits in status register */
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
pcix->potar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
pcix->powbar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = 0x8004401a; /* 128M MEM space */
pcix->potar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff;
pcix->powbear2 = 0x00000000;
pcix->powar2 = 0x80088017; /* 16M IO space */
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
pcix->piwar1 = 0xa0F5501f;
}
#endif /* CONFIG_PCI */

2
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.section .resetvec,"ax"
b _start_e500

274
cpu/mpc85xx/serial_scc.c Normal file
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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
* Modified based on 8260 for 8560.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
*/
/*
* Minimal serial functions needed to use one of the SCC ports
* as serial console interface.
*/
#include <common.h>
#include <asm/cpm_85xx.h>
#if defined(CONFIG_MPC8560)
#if defined(CONFIG_CONS_ON_SCC)
#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
#define SCC_INDEX 0
#define PROFF_SCC PROFF_SCC1
#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
#define SCC_INDEX 1
#define PROFF_SCC PROFF_SCC2
#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
#define SCC_INDEX 2
#define PROFF_SCC PROFF_SCC3
#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
#define SCC_INDEX 3
#define PROFF_SCC PROFF_SCC4
#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
#else
#error "console not correctly defined"
#endif
int serial_init (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
uint dpaddr;
/* initialize pointers to SCC */
sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
/* Disable transmitter/receiver.
*/
sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/* put the SCC channel into NMSI (non multiplexd serial interface)
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
*/
im->im_cpm.im_cpm_mux.cmxscr = \
(im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
/* Set up the baud rate generator.
*/
serial_setbrg ();
/* Allocate space for two buffer descriptors in the DP ram.
* damm: allocating space after the two buffers for rx/tx data
*/
dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
tbdf = rbdf + 1;
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = BD_SC_WRAP;
/* Set up the uart parameters in the parameter ram.
*/
up->scc_genscc.scc_rbase = dpaddr;
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
up->scc_genscc.scc_rfcr = CPMFCR_EB;
up->scc_genscc.scc_tfcr = CPMFCR_EB;
up->scc_genscc.scc_mrblr = 1;
up->scc_maxidl = 0;
up->scc_brkcr = 1;
up->scc_parec = 0;
up->scc_frmec = 0;
up->scc_nosec = 0;
up->scc_brkec = 0;
up->scc_uaddr1 = 0;
up->scc_uaddr2 = 0;
up->scc_toseq = 0;
up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
up->scc_rccm = 0xc0ff;
/* Mask all interrupts and remove anything pending.
*/
sp->sccm = 0;
sp->scce = 0xffff;
/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
*/
sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
sp->gsmrl = \
SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
/* Set CTS no flow control, 1 stop bit, 8 bit character length,
* normal async UART mode, no parity
*/
sp->psmr = SCU_PSMR_CL;
/* execute the "Init Rx and Tx params" CP command.
*/
while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
/* Enable transmitter/receiver.
*/
sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
return (0);
}
void
serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CONS_USE_EXTC)
m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
#else
m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
#endif
}
void
serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
volatile immap_t *im;
if (c == '\n')
serial_putc ('\r');
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
/* Wait for last character to go.
*/
while (tbdf->cbd_sc & BD_SC_READY)
;
/* Load the character into the transmit buffer.
*/
*(volatile char *)tbdf->cbd_bufaddr = c;
tbdf->cbd_datlen = 1;
tbdf->cbd_sc |= BD_SC_READY;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int
serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
volatile immap_t *im;
unsigned char c;
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
/* Wait for character to show up.
*/
while (rbdf->cbd_sc & BD_SC_EMPTY)
;
/* Grab the char and clear the buffer again.
*/
c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
rbdf->cbd_sc |= BD_SC_EMPTY;
return (c);
}
int
serial_tstc()
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
volatile immap_t *im;
im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
#endif /* CONFIG_CONS_ON_SCC */
#endif /* CONFIG_MPC8560 */

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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
#ifdef CONFIG_SPD_EEPROM
#undef DEBUG
#if defined(DEBUG)
#define DEB(x) x
#else
#define DEB(x)
#endif
#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
long int spd_sdram(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
spd_eeprom_t spd;
unsigned int memsize,tmp,tmp1,tmp2;
unsigned char caslat;
i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
if ( spd.nrows > 2 ) {
printf("DDR:Only two chip selects are supported on ADS.\n");
return 0;
}
if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
printf("DDR:Row or Col number unsupported.\n");
return 0;
}
ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
DEB(printf("\n"));
DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
if ( spd.nrows == 2 ) {
ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
}
memsize = spd.nrows * (4 * spd.row_dens);
if( spd.mem_type == 0x07 ) {
printf("DDR module detected, total size:%dMB.\n",memsize);
} else {
printf("No DDR module found!\n");
return 0;
}
switch(memsize) {
case 16:
tmp = 7; /* TLB size */
tmp1 = 1; /* TLB entry number */
tmp2 = 23; /* Local Access Window size */
break;
case 32:
tmp = 7;
tmp1 = 2;
tmp2 = 24;
break;
case 64:
tmp = 8;
tmp1 = 1;
tmp2 = 25;
break;
case 128:
tmp = 8;
tmp1 = 2;
tmp2 = 26;
break;
case 256:
tmp = 9;
tmp1 = 1;
tmp2 = 27;
break;
case 512:
tmp = 9;
tmp1 = 2;
tmp2 = 28;
break;
case 1024:
tmp = 10;
tmp1 = 1;
tmp2 = 29;
break;
default:
printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
return 0;
break;
}
/* configure DDR TLB to TLB1 Entry 4,5 */
mtspr(MAS0, TLB1_MAS0(1,4,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,0,0,0)));
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1)));
if(tmp1 == 2) {
mtspr(MAS0, TLB1_MAS0(1,5,0));
mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
}
#if defined(CONFIG_RAM_AS_FLASH)
ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
#else
ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
#endif
tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
/* find the largest CAS */
if(spd.cas_lat & 0x40) {
caslat = 7;
} else if (spd.cas_lat & 0x20) {
caslat = 6;
} else if (spd.cas_lat & 0x10) {
caslat = 5;
} else if (spd.cas_lat & 0x08) {
caslat = 4;
} else if (spd.cas_lat & 0x04) {
caslat = 3;
} else if (spd.cas_lat & 0x02) {
caslat = 2;
} else if (spd.cas_lat & 0x01) {
caslat = 1;
} else {
printf("DDR:no valid CAS Latency information.\n");
return 0;
}
tmp1 = get_bus_freq(0)/1000000;
if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
if(spd.clk_cycle3 == 0xa0) caslat -= 2;
else if(spd.clk_cycle2 == 0xa0) caslat--;
} else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
if(spd.clk_cycle3 == 0x75) caslat -= 2;
else if(spd.clk_cycle2 == 0x75) caslat--;
} else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
if(spd.clk_cycle3 == 0x60) caslat -= 2;
else if(spd.clk_cycle2 == 0x60) caslat--;
} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
printf("DDR:platform frequency is not fit for DDR rate\n");
return 0;
}
/* note: caslat must also be programmed into ddr->sdram_mode register */
/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
#if 1
ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
((caslat & 0x07)<< 16 ) | \
(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
( 0x300 ) | \
((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
#else
ddr->timing_cfg_1 = 0x37344321;
caslat = 4;
#endif
DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
/* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
#if defined(CONFIG_MPC85xx_REV1)
ddr->timing_cfg_2 = 0x00000800;
#endif
DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
/* only DDR I is supported, DDR I and II have different mode-register-set definition */
/* burst length is always 4 */
switch(caslat) {
case 2:
ddr->sdram_mode = 0x52; /* 1.5 */
break;
case 3:
ddr->sdram_mode = 0x22; /* 2.0 */
break;
case 4:
ddr->sdram_mode = 0x62; /* 2.5 */
break;
case 5:
ddr->sdram_mode = 0x32; /* 3.0 */
break;
default:
printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
return 0;
}
DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
switch(spd.refresh) {
case 0x00:
case 0x80:
tmp = ns2clk(15625);
break;
case 0x01:
case 0x81:
tmp = ns2clk(3900);
break;
case 0x02:
case 0x82:
tmp = ns2clk(7800);
break;
case 0x03:
case 0x83:
tmp = ns2clk(31300);
break;
case 0x04:
case 0x84:
tmp = ns2clk(62500);
break;
case 0x05:
case 0x85:
tmp = ns2clk(125000);
break;
default:
tmp = 0x512;
break;
}
/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
/* is this an ECC DDR chip? */
#if defined(CONFIG_DDR_ECC)
if(spd.config == 0x02) {
ddr->err_disable = 0x0000000d;
ddr->err_sbe = 0x00ff0000;
}
DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
#endif
asm("sync;isync;msync");
udelay(500);
/* registered or unbuffered? */
#if defined(CONFIG_DDR_ECC)
ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
#endif
ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
((spd.mod_attr == 0x26) ? 0x10000000:0x0));
asm("sync;isync;msync");
udelay(500);
DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
return (memsize*1024*1024);
}
#endif /* CONFIG_SPD_EEPROM */

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/*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc_asm.tmpl>
#include <asm/processor.h>
/* --------------------------------------------------------------- */
#define ONE_BILLION 1000000000
void get_sys_info (sys_info_t * sysInfo)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio,e500_ratio;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
switch(plat_ratio) {
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x08:
case 0x09:
case 0x0a:
case 0x0c:
case 0x10:
sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
break;
default:
sysInfo->freqSystemBus = 0;
break;
}
e500_ratio = (gur->porpllsr) & 0x003f0000;
e500_ratio >>= 16;
switch(e500_ratio) {
case 0x04:
sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
break;
case 0x05:
sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
break;
case 0x06:
sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
break;
case 0x07:
sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
break;
default:
sysInfo->freqProcessor = 0;
break;
}
}
int get_clocks (void)
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
#if defined(CONFIG_MPC8560)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
sccr = immap->im_cpm.im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
#if defined(CONFIG_MPC8560)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
else return (1);
}
/********************************************
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
{
ulong val;
sys_info_t sys_info;
get_sys_info (&sys_info);
val = sys_info.freqSystemBus;
return val;
}

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272
cpu/mpc85xx/traps.c Normal file
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/*
* linux/arch/ppc/kernel/traps.c
*
* Copyright (C) 2003 Motorola
* Modified by Xianghua Xiao(x.xiao@motorola.com)
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Modified by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras (paulus@cs.anu.edu.au)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file handles the architecture-dependent parts of hardware exceptions
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024)
static __inline__ void set_tsr(unsigned long val)
{
asm volatile("mtspr 0x150, %0" : : "r" (val));
}
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
return val;
}
#define ESR_MCI 0x80000000
#define ESR_PIL 0x08000000
#define ESR_PPR 0x04000000
#define ESR_PTR 0x02000000
#define ESR_DST 0x00800000
#define ESR_DIZ 0x00400000
#define ESR_U0F 0x00008000
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
/*
* Trap & Exception support
*/
void
print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *)*sp;
}
printf("\n");
}
void show_regs(struct pt_regs * regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
regs->msr&MSR_IR ? 1 : 0,
regs->msr&MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
printf("\n");
}
}
}
void
_exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
void
CritcalInputException(struct pt_regs *regs)
{
panic("Critical Input Exception");
}
void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
return;
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ",regs);
switch( regs->msr & 0x0000F000)
{
case (1<<12) :
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
case (1<<13) :
printf("Transfer error ack signal\n");
break;
case (1<<14) :
printf("Data parity signal\n");
break;
case (1<<15) :
printf("Address parity signal\n");
break;
default:
printf("Unknown values in msr\n");
}
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");
}
void
AlignmentException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Alignment Exception");
}
void
ProgramCheckException(struct pt_regs *regs)
{
long esr_val;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
esr_val = get_esr();
if( esr_val & ESR_PIL )
printf( "** Illegal Instruction **\n" );
else if( esr_val & ESR_PPR )
printf( "** Privileged Instruction **\n" );
else if( esr_val & ESR_PTR )
printf( "** Trap Instruction **\n" );
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
}
void
PITException(struct pt_regs *regs)
{
/*
* Reset PIT interrupt
*/
set_tsr(0x0c000000);
/*
* Call timer_interrupt routine in interrupts.c
*/
timer_interrupt(NULL);
}
void
UnknownException(struct pt_regs *regs)
{
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
void
DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
int
addr_probe(uint *addr)
{
return 0;
}

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/*
* tsec.c
* Motorola Three Speed Ethernet Controller driver
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
*/
#include <config.h>
#include <mpc85xx.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#if defined(CONFIG_TSEC_ENET)
#include "tsec.h"
#define TX_BUF_CNT 2
#undef TSEC_DEBUG
#ifdef TSEC_DEBUG
#define DBGPRINT(x) printf(x)
#else
#define DBGPRINT(x)
#endif
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
typedef volatile struct rtxbd {
txbd8_t txbd[TX_BUF_CNT];
rxbd8_t rxbd[PKTBUFSRX];
} RTXBD;
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
#else
#error "rtx must be 64-bit aligned"
#endif
static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
static int tsec_recv(struct eth_device* dev);
static int tsec_init(struct eth_device* dev, bd_t * bd);
static void tsec_halt(struct eth_device* dev);
static void init_registers(tsec_t *regs);
static void startup_tsec(tsec_t *regs);
static void init_phy(tsec_t *regs);
/* Initialize device structure. returns 0 on failure, 1 on
* success */
int tsec_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
dev = (struct eth_device*) malloc(sizeof *dev);
if(dev == NULL)
return 0;
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "MOTOROLA ETHERNET");
dev->iobase = 0;
dev->priv = 0;
dev->init = tsec_init;
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
/* Tell u-boot to get the addr from the env */
for(i=0;i<6;i++)
dev->enetaddr[i] = 0;
eth_register(dev);
return 1;
}
/* Initializes data structures and registers for the controller,
* and brings the interface up */
int tsec_init(struct eth_device* dev, bd_t * bd)
{
tsec_t *regs;
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
int i;
regs = (tsec_t *)(TSEC_BASE_ADDR);
/* Make sure the controller is stopped */
tsec_halt(dev);
/* Reset the MAC */
regs->maccfg1 |= MACCFG1_SOFT_RESET;
/* Clear MACCFG1[Soft_Reset] */
regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
/* Init MACCFG2. Defaults to GMII/MII */
regs->maccfg2 = MACCFG2_INIT_SETTINGS;
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
for(i=0;i<MAC_ADDR_LEN;i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = bd->bi_enetaddr[i];
}
(uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
tempval = *((uint *)(tmpbuf +4));
(uint)(regs->macstnaddr2) = tempval;
/* Initialize the PHY */
init_phy(regs);
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
/* Clear out (for the most part) the other registers */
init_registers(regs);
/* Ready the device for tx/rx */
startup_tsec(regs);
return 1;
}
/* Reads from the register at offset in the PHY at phyid, */
/* using the register set defined in regbase. It waits until the */
/* bits in the miimstat are valid (miimind notvalid bit cleared), */
/* and then passes those bits on to the variable specified in */
/* value */
/* Before it does the read, it needs to clear the command field */
uint read_phy_reg(tsec_t *regbase, uint phyid, uint offset)
{
uint value;
/* Put the address of the phy, and the register number into
* MIIMADD
*/
regbase->miimadd = (phyid << 8) | offset;
/* Clear the command register, and wait */
regbase->miimcom = 0;
asm("msync");
/* Initiate a read command, and wait */
regbase->miimcom = MIIM_READ_COMMAND;
asm("msync");
/* Wait for the the indication that the read is done */
while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
/* Grab the value read from the PHY */
value = regbase->miimstat;
return value;
}
/* Setup the PHY */
static void init_phy(tsec_t *regs)
{
uint testval;
unsigned int timeout = TSEC_TIMEOUT;
/* Assign a Physical address to the TBI */
regs->tbipa=TBIPA_VALUE;
/* reset the management interface */
regs->miimcfg=MIIMCFG_RESET;
regs->miimcfg=MIIMCFG_INIT_VALUE;
/* Wait until the bus is free */
while(regs->miimind & MIIMIND_BUSY);
#ifdef CONFIG_PHY_CIS8201
/* override PHY config settings */
write_phy_reg(regs, 0, MIIM_AUX_CONSTAT, MIIM_AUXCONSTAT_INIT);
/* Set up interface mode */
write_phy_reg(regs, 0, MIIM_EXT_CON1, MIIM_EXTCON1_INIT);
#endif
/* Set the PHY to gigabit, full duplex, Auto-negotiate */
write_phy_reg(regs, 0, MIIM_CONTROL, MIIM_CONTROL_INIT);
/* Wait until TBI_STATUS indicates AN is done */
DBGPRINT("Waiting for Auto-negotiation to complete\n");
testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
while((!(testval & MIIM_TBI_STATUS_AN_DONE))&& timeout--) {
testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
}
if(testval & MIIM_TBI_STATUS_AN_DONE)
DBGPRINT("Auto-negotiation done\n");
else
DBGPRINT("Auto-negotiation timed-out.\n");
#ifdef CONFIG_PHY_CIS8201
/* Find out what duplexity (duplicity?) we have */
/* Read it twice to make sure */
testval=read_phy_reg(regs, 0, MIIM_AUX_CONSTAT);
if(testval & MIIM_AUXCONSTAT_DUPLEX) {
DBGPRINT("Enet starting in full duplex\n");
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
} else {
DBGPRINT("Enet starting in half duplex\n");
regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
}
/* Also, we look to see what speed we are at
* if Gigabit, MACCFG2 goes in GMII, otherwise,
* MII mode.
*/
if((testval & MIIM_AUXCONSTAT_SPEED) != MIIM_AUXCONSTAT_GBIT) {
if((testval & MIIM_AUXCONSTAT_SPEED) == MIIM_AUXCONSTAT_100)
DBGPRINT("Enet starting in 100BT\n");
else
DBGPRINT("Enet starting in 10BT\n");
/* mark the mode in MACCFG2 */
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
} else {
DBGPRINT("Enet starting in 1000BT\n");
}
#endif
#ifdef CONFIG_PHY_M88E1011
/* Read the PHY to see what speed and duplex we are */
testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
timeout = TSEC_TIMEOUT;
while((!(testval & MIIM_PHYSTAT_SPDDONE)) && timeout--) {
testval = read_phy_reg(regs,0,MIIM_PHY_STATUS);
}
if(!(testval & MIIM_PHYSTAT_SPDDONE))
DBGPRINT("Enet: Speed not resolved\n");
testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
if(testval & MIIM_PHYSTAT_DUPLEX) {
DBGPRINT("Enet starting in Full Duplex\n");
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
} else {
DBGPRINT("Enet starting in Half Duplex\n");
regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
}
if(!((testval&MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_GBIT)) {
if((testval & MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_100)
DBGPRINT("Enet starting in 100BT\n");
else
DBGPRINT("Enet starting in 10BT\n");
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
} else {
DBGPRINT("Enet starting in 1000BT\n");
}
#endif
}
static void init_registers(tsec_t *regs)
{
/* Clear IEVENT */
regs->ievent = IEVENT_INIT_CLEAR;
regs->imask = IMASK_INIT_CLEAR;
regs->hash.iaddr0 = 0;
regs->hash.iaddr1 = 0;
regs->hash.iaddr2 = 0;
regs->hash.iaddr3 = 0;
regs->hash.iaddr4 = 0;
regs->hash.iaddr5 = 0;
regs->hash.iaddr6 = 0;
regs->hash.iaddr7 = 0;
regs->hash.gaddr0 = 0;
regs->hash.gaddr1 = 0;
regs->hash.gaddr2 = 0;
regs->hash.gaddr3 = 0;
regs->hash.gaddr4 = 0;
regs->hash.gaddr5 = 0;
regs->hash.gaddr6 = 0;
regs->hash.gaddr7 = 0;
regs->rctrl = 0x00000000;
/* Init RMON mib registers */
memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
regs->rmon.cam1 = 0xffffffff;
regs->rmon.cam2 = 0xffffffff;
regs->mrblr = MRBLR_INIT_SETTINGS;
regs->minflr = MINFLR_INIT_SETTINGS;
regs->attr = ATTR_INIT_SETTINGS;
regs->attreli = ATTRELI_INIT_SETTINGS;
}
static void startup_tsec(tsec_t *regs)
{
int i;
/* Point to the buffer descriptors */
regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
for(i=0; i<TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
/* Enable Transmit and Receive */
regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
/* Tell the DMA it is clear to go */
regs->dmactrl |= DMACTRL_INIT_SETTINGS;
regs->tstat = TSTAT_CLEAR_THALT;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
}
/* This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
* do the same. Presumably, this would be zero if there were no
* errors */
static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
{
int i;
int result = 0;
tsec_t * regs = (tsec_t *)(TSEC_BASE_ADDR);
/* Find an empty buffer descriptor */
for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
DBGPRINT("tsec: tx buffers full\n");
return result;
}
}
rtx.txbd[txIdx].bufPtr = (uint)packet;
rtx.txbd[txIdx].length = length;
rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
/* Tell the DMA to go */
regs->tstat = TSTAT_CLEAR_THALT;
/* Wait for buffer to be transmitted */
for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
DBGPRINT("tsec: tx error\n");
return result;
}
}
txIdx = (txIdx + 1) % TX_BUF_CNT;
result = rtx.txbd[txIdx].status & TXBD_STATS;
return result;
}
static int tsec_recv(struct eth_device* dev)
{
int length;
tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
length = rtx.rxbd[rxIdx].length;
/* Send the packet up if there were no errors */
if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
NetReceive(NetRxPackets[rxIdx], length - 4);
}
rtx.rxbd[rxIdx].length = 0;
/* Set the wrap bit if this is the last element in the list */
rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
if(regs->ievent&IEVENT_BSY) {
regs->ievent = IEVENT_BSY;
regs->rstat = RSTAT_CLEAR_RHALT;
}
return -1;
}
static void tsec_halt(struct eth_device* dev)
{
tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
}
#endif /* CONFIG_TSEC_ENET */

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/*
* tsec.h
*
* Driver for the Motorola Triple Speed Ethernet Controller
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
*/
#ifndef __TSEC_H
#define __TSEC_H
#include <net.h>
#include <mpc85xx.h>
#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
#define TSEC_MEM_SIZE 0x01000
#define MAC_ADDR_LEN 6
#define TSEC_TIMEOUT 1000000
#define TOUT_LOOP 1000000
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MACCFG1_RESET_TX_MC 0x00040000
#define MACCFG1_RESET_RX_FUN 0x00020000
#define MACCFG1_RESET_TX_FUN 0x00010000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define MACCFG1_SYNCD_RX_EN 0x00000008
#define MACCFG1_RX_EN 0x00000004
#define MACCFG1_SYNCD_TX_EN 0x00000002
#define MACCFG1_TX_EN 0x00000001
#define MACCFG2_INIT_SETTINGS 0x00007205
#define MACCFG2_FULL_DUPLEX 0x00000001
#define MACCFG2_IF 0x00000300
#define MACCFG2_MII 0x00000100
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
#define TBIPA_VALUE 0x1f
#define MIIMCFG_INIT_VALUE 0x00000003
#define MIIMCFG_RESET 0x80000000
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define MIIM_TBICON 0x11
#define MIIM_TBICON_GMII 0x00000010
#define MIIM_TBICON_AN 0x00000100
#define MIIM_CONTROL 0x00
#define MIIM_CONTROL_INIT 0x00001140
#define MIIM_ANEN 0x00001000
#define MIIM_TBI_STATUS 0x1
#define MIIM_TBI_STATUS_AN_DONE 0x00000020
#define MIIM_TBI_ANEX 0x6
#define MIIM_TBI_ANEX_NP 0x00000004
#define MIIM_TBI_ANEX_PRX 0x00000002
#define MIIM_TBI_ANLPBPA 0x5
#define MIIM_TBI_ANLPBPA_HALF 0x00000040
#define MIIM_TBI_ANLPBPA_FULL 0x00000020
#ifdef CONFIG_PHY_CIS8201
#define MIIM_AUX_CONSTAT 0x1c
#define MIIM_AUXCONSTAT_INIT 0x0004
#define MIIM_AUXCONSTAT_DUPLEX 0x0020
#define MIIM_AUXCONSTAT_SPEED 0x0018
#define MIIM_AUXCONSTAT_GBIT 0x0010
#define MIIM_AUXCONSTAT_100 0x0008
#define MIIM_EXT_CON1 0x17
#define MIIM_EXTCON1_INIT 0x0000
#endif
#ifdef CONFIG_PHY_M88E1011
#define MIIM_ANAR 0x04
#define MIIM_ANAR_ADVERTISEMENT 0x01e1
#define MIIM_GBIT_CON 0x09
#define MIIM_GBIT_CON_ADVERT 0x1e00
#define MIIM_PHY_STATUS 0x11
#define MIIM_PHYSTAT_SPEED 0xc000
#define MIIM_PHYSTAT_GBIT 0x8000
#define MIIM_PHYSTAT_100 0x4000
#define MIIM_PHYSTAT_DUPLEX 0x2000
#define MIIM_PHYSTAT_SPDDONE 0x0800
#define MIIM_PHYSTAT_LINK 0x0400
#endif
#define MIIM_READ_COMMAND 0x00000001
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
#define MINFLR_INIT_SETTINGS 0x00000040
#define DMACTRL_INIT_SETTINGS 0x000000c3
#define DMACTRL_GRS 0x00000010
#define DMACTRL_GTS 0x00000008
#define TSTAT_CLEAR_THALT 0x80000000
#define RSTAT_CLEAR_RHALT 0x00800000
/* Write value to the PHY at phyid to the register at offset, */
/* using the register space defined in regbase. Note that */
/* miimcfg needs to have the clock speed setup correctly. This */
/* macro will wait until the write is done before it finishes */
#define write_phy_reg(regbase, phyid, offset, value) do { \
int timeout=1000000; \
regbase->miimadd = (phyid << 8) | offset; \
regbase->miimcon = value; \
asm("msync"); \
while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
} while(0)
#define IEVENT_INIT_CLEAR 0xffffffff
#define IEVENT_BABR 0x80000000
#define IEVENT_RXC 0x40000000
#define IEVENT_BSY 0x20000000
#define IEVENT_EBERR 0x10000000
#define IEVENT_MSRO 0x04000000
#define IEVENT_GTSC 0x02000000
#define IEVENT_BABT 0x01000000
#define IEVENT_TXC 0x00800000
#define IEVENT_TXE 0x00400000
#define IEVENT_TXB 0x00200000
#define IEVENT_TXF 0x00100000
#define IEVENT_IE 0x00080000
#define IEVENT_LC 0x00040000
#define IEVENT_CRL 0x00020000
#define IEVENT_XFUN 0x00010000
#define IEVENT_RXB0 0x00008000
#define IEVENT_GRSC 0x00000100
#define IEVENT_RXF0 0x00000080
#define IMASK_INIT_CLEAR 0x00000000
#define IMASK_TXEEN 0x00400000
#define IMASK_TXBEN 0x00200000
#define IMASK_TXFEN 0x00100000
#define IMASK_RXFEN0 0x00000080
/* Default Attribute fields */
#define ATTR_INIT_SETTINGS 0x000000c0
#define ATTRELI_INIT_SETTINGS 0x00000000
/* TxBD status field bits */
#define TXBD_READY 0x8000
#define TXBD_PADCRC 0x4000
#define TXBD_WRAP 0x2000
#define TXBD_INTERRUPT 0x1000
#define TXBD_LAST 0x0800
#define TXBD_CRC 0x0400
#define TXBD_DEF 0x0200
#define TXBD_HUGEFRAME 0x0080
#define TXBD_LATECOLLISION 0x0080
#define TXBD_RETRYLIMIT 0x0040
#define TXBD_RETRYCOUNTMASK 0x003c
#define TXBD_UNDERRUN 0x0002
#define TXBD_STATS 0x03ff
/* RxBD status field bits */
#define RXBD_EMPTY 0x8000
#define RXBD_RO1 0x4000
#define RXBD_WRAP 0x2000
#define RXBD_INTERRUPT 0x1000
#define RXBD_LAST 0x0800
#define RXBD_FIRST 0x0400
#define RXBD_MISS 0x0100
#define RXBD_BROADCAST 0x0080
#define RXBD_MULTICAST 0x0040
#define RXBD_LARGE 0x0020
#define RXBD_NONOCTET 0x0010
#define RXBD_SHORT 0x0008
#define RXBD_CRCERR 0x0004
#define RXBD_OVERRUN 0x0002
#define RXBD_TRUNCATED 0x0001
#define RXBD_STATS 0x003f
typedef struct txbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer length */
uint bufPtr; /* Buffer Pointer */
} txbd8_t;
typedef struct rxbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer Length */
uint bufPtr; /* Buffer Pointer */
} rxbd8_t;
typedef struct rmon_mib
{
/* Transmit and Receive Counters */
uint tr64; /* Transmit and Receive 64-byte Frame Counter */
uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
/* Receive Counters */
uint rbyt; /* Receive Byte Counter */
uint rpkt; /* Receive Packet Counter */
uint rfcs; /* Receive FCS Error Counter */
uint rmca; /* Receive Multicast Packet (Counter) */
uint rbca; /* Receive Broadcast Packet */
uint rxcf; /* Receive Control Frame Packet */
uint rxpf; /* Receive Pause Frame Packet */
uint rxuo; /* Receive Unknown OP Code */
uint raln; /* Receive Alignment Error */
uint rflr; /* Receive Frame Length Error */
uint rcde; /* Receive Code Error */
uint rcse; /* Receive Carrier Sense Error */
uint rund; /* Receive Undersize Packet */
uint rovr; /* Receive Oversize Packet */
uint rfrg; /* Receive Fragments */
uint rjbr; /* Receive Jabber */
uint rdrp; /* Receive Drop */
/* Transmit Counters */
uint tbyt; /* Transmit Byte Counter */
uint tpkt; /* Transmit Packet */
uint tmca; /* Transmit Multicast Packet */
uint tbca; /* Transmit Broadcast Packet */
uint txpf; /* Transmit Pause Control Frame */
uint tdfr; /* Transmit Deferral Packet */
uint tedf; /* Transmit Excessive Deferral Packet */
uint tscl; /* Transmit Single Collision Packet */
/* (0x2_n700) */
uint tmcl; /* Transmit Multiple Collision Packet */
uint tlcl; /* Transmit Late Collision Packet */
uint txcl; /* Transmit Excessive Collision Packet */
uint tncl; /* Transmit Total Collision */
uint res2;
uint tdrp; /* Transmit Drop Frame */
uint tjbr; /* Transmit Jabber Frame */
uint tfcs; /* Transmit FCS Error */
uint txcf; /* Transmit Control Frame */
uint tovr; /* Transmit Oversize Frame */
uint tund; /* Transmit Undersize Frame */
uint tfrg; /* Transmit Fragments Frame */
/* General Registers */
uint car1; /* Carry Register One */
uint car2; /* Carry Register Two */
uint cam1; /* Carry Register One Mask */
uint cam2; /* Carry Register Two Mask */
} rmon_mib_t;
typedef struct tsec_hash_regs
{
uint iaddr0; /* Individual Address Register 0 */
uint iaddr1; /* Individual Address Register 1 */
uint iaddr2; /* Individual Address Register 2 */
uint iaddr3; /* Individual Address Register 3 */
uint iaddr4; /* Individual Address Register 4 */
uint iaddr5; /* Individual Address Register 5 */
uint iaddr6; /* Individual Address Register 6 */
uint iaddr7; /* Individual Address Register 7 */
uint res1[24];
uint gaddr0; /* Group Address Register 0 */
uint gaddr1; /* Group Address Register 1 */
uint gaddr2; /* Group Address Register 2 */
uint gaddr3; /* Group Address Register 3 */
uint gaddr4; /* Group Address Register 4 */
uint gaddr5; /* Group Address Register 5 */
uint gaddr6; /* Group Address Register 6 */
uint gaddr7; /* Group Address Register 7 */
uint res2[24];
} tsec_hash_t;
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
uint res000[4];
uint ievent; /* Interrupt Event */
uint imask; /* Interrupt Mask */
uint edis; /* Error Disabled */
uint res01c;
uint ecntrl; /* Ethernet Control */
uint minflr; /* Minimum Frame Length */
uint ptv; /* Pause Time Value */
uint dmactrl; /* DMA Control */
uint tbipa; /* TBI PHY Address */
uint res034[3];
uint res040[48];
/* Transmit Control and Status Registers (0x2_n100) */
uint tctrl; /* Transmit Control */
uint tstat; /* Transmit Status */
uint res108;
uint tbdlen; /* Tx BD Data Length */
uint res110[5];
uint ctbptr; /* Current TxBD Pointer */
uint res128[23];
uint tbptr; /* TxBD Pointer */
uint res188[30];
/* (0x2_n200) */
uint res200;
uint tbase; /* TxBD Base Address */
uint res208[42];
uint ostbd; /* Out of Sequence TxBD */
uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
uint res2b8[18];
/* Receive Control and Status Registers (0x2_n300) */
uint rctrl; /* Receive Control */
uint rstat; /* Receive Status */
uint res308;
uint rbdlen; /* RxBD Data Length */
uint res310[4];
uint res320;
uint crbptr; /* Current Receive Buffer Pointer */
uint res328[6];
uint mrblr; /* Maximum Receive Buffer Length */
uint res344[16];
uint rbptr; /* RxBD Pointer */
uint res388[30];
/* (0x2_n400) */
uint res400;
uint rbase; /* RxBD Base Address */
uint res408[62];
/* MAC Registers (0x2_n500) */
uint maccfg1; /* MAC Configuration #1 */
uint maccfg2; /* MAC Configuration #2 */
uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
uint hafdup; /* Half-duplex */
uint maxfrm; /* Maximum Frame */
uint res514;
uint res518;
uint res51c;
uint miimcfg; /* MII Management: Configuration */
uint miimcom; /* MII Management: Command */
uint miimadd; /* MII Management: Address */
uint miimcon; /* MII Management: Control */
uint miimstat; /* MII Management: Status */
uint miimind; /* MII Management: Indicators */
uint res538;
uint ifstat; /* Interface Status */
uint macstnaddr1; /* Station Address, part 1 */
uint macstnaddr2; /* Station Address, part 2 */
uint res548[46];
/* (0x2_n600) */
uint res600[32];
/* RMON MIB Registers (0x2_n680-0x2_n73c) */
rmon_mib_t rmon;
uint res740[48];
/* Hash Function Registers (0x2_n800) */
tsec_hash_t hash;
uint res900[128];
/* Pattern Registers (0x2_nb00) */
uint resb00[62];
uint attr; /* Default Attribute Register */
uint attreli; /* Default Attribute Extract Length and Index */
/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
uint resc00[256];
} tsec_t;
#endif /* __TSEC_H */

1
cpu/nios/config.mk
View File

@ -22,4 +22,3 @@
#
PLATFORM_RELFLAGS +=

1
doc/README.INCA-IP
View File

@ -41,7 +41,6 @@ to install a U-Boot image into flash.
go 0xb0000000
Ethernet autonegotiation needs some time to complete. Instead of
delaying the boot process in all cases, we just start the
autonegotiation process when U-Boot comes up and that is all. Most

535
doc/README.mpc85xxads Normal file
View File

@ -0,0 +1,535 @@
Motorola MPC8540ADS and MPC8560ADS board
Xianghua Xiao(X.Xiao@motorola.com)
Created 10/15/03
-----------------------------------------
1. SWITCH SETTINGS & JUMPERS
1.1 First, make sure the board default setting is consistent with the document
shipped with your board. Then apply the following changes:
SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
SW11[2]='OFF for dracom, ON for draco' (single switch to toggle draco.dracom mode)
SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
SW22[1-4]="OFF OFF ON OFF"
SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
J1 = "Enable Prog" (Make sure your flash is programmable for development)
Ethernet PHY connectors(J47,J56) should be removed if you want to use the ethernet.
1.2 If you want to test PCI functionality with a 33Mhz PCI card, you will have to change
the system clock from the default 66Mhz to 33Mhz by setting SW15[1]="OFF" and
SW17[8]="OFF". After that you may also need double your platform clock(SW6) because
the system clock is now only half of its original value.
1.3 SW6 is a very important switch, it decides your platform clock and CPU clock based on
the on-board system clock(default 66MHz). Check the document along with your board
for details.
2. MEMORY MAP TO WORK WITH LINUX KERNEL
2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
linux kernel, you can customize it based on your system requirements:
DDR: 0x00000000-0x1fffffff (max 512MB)
PCI: 0xe0000000-0xefffffff (256MB)
RIO: 0xf0000000-0xf7ffffff (128MB)
Local SDRAM: 0xf8000000-0xfbffffff (64MB)
Local CSx: 0xfc000000-0xfdefffff (31MB) BCSR,RTC,ATM config,etc.
CCSRBAR: 0xfdf00000-0xfdffffff (1MB)
Flash: 0xfe000000-0xffffffff (max 32MB)
2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. Hope you will be
able to download them from linuxppc-2.4 public source by the time you are reading
this. Please make sure the kernel's ppcboot.h is consistent with U-Boot's u-boot.h,
then you can use two default configuration files in the kernel source as a test:
arch/ppc/configs/mpc8540ads_defconfig
arch/ppc/configs/mpc8560ads_defconfig
3. DEFINITIONS AND COMPILATION
3.1 Explanation on NEW definitions in include/configs/MPC8540ADS.h and include/
configs/MPC8560ADS.h
CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
CONFIG_MPC85xx_REV1 MPC85xx Rev 1 Chip, in general you will use a Rev2
chip from Nov.2003. If you still see this definition
while you have a Rev2(and newer) chip,undef this.
CONFIG_MPC8540 MPC8540 specific
CONFIG_MPC8560 MPC8560 specific
CONFIG_MPC8540ADS MPC8540ADS board specific
CONFIG_MPC8560ADS MPC8560ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also
manual config the DDR after undef this definition.
CONFIG_DDR_ECC only for ECC DDR module
CONFIG_DDR_DLL possible DLL fix needed for Rev1 chip for more stability.
you can disable this if you're having a newer chip.
CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into localbus
SDRAM and treat localbus SDRAM as a flash. We use this
memory based U-Boot before flash is working while Metrowerks
and Windriver are still working on their flash/JTAG tools.
if you can program the flash directly, undef this.
Other than the above definitions, the rest in the config files are straightforward.
3.2 Compilation
export CROSS_COMPILE=your-cross-compile-prefix(assuming you're using BASH shell)
cd u-boot
make distclean
make MPC8560ADS_config (or make MPC8540ADS_config)
make
4. Note on the 10/100/1000 Ethernet controller:
4.1 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC ethernet. If that
happens, you can try the following steps to make network work:
MPC8560ADS>tftp 1000000 pImage
(if it hangs, use Ctrl-C to quit)
MPC8560ADS>nm fdf24524
>0
>1
>. (to quit this memory operation)
MPC8560ADS>tftp 1000000 pImage
5. Screen dump:
5.1 MPC8540ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8540ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Hit any key to stop autoboot: 0
MPC8540ADS=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
Sector Start Addresses:
FF000000 FF040000 FF080000 FF0C0000 FF100000
FF140000 FF180000 FF1C0000 FF200000 FF240000
FF280000 FF2C0000 FF300000 FF340000 FF380000
FF3C0000 FF400000 FF440000 FF480000 FF4C0000
FF500000 FF540000 FF580000 FF5C0000 FF600000
FF640000 FF680000 FF6C0000 FF700000 FF740000
FF780000 FF7C0000 FF800000 FF840000 FF880000
FF8C0000 FF900000 FF940000 FF980000 FF9C0000
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8540ADS=> imi ff000000
## Checking Image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8540ADS=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x40003F80
intfreq = 792 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
baudrate = 115200 bps
MPC8540ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff300000 0xff700000
bootdelay=3
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
stdin=serial
stdout=serial
stderr=serial
Environment size: 560/8188 bytes
MPC8540ADS=> bootm ff000000
## Booting image at ff000000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 800594 Bytes = 781.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #1 Wed Oct 15 09:05:42 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127488k available (1344k kernel code, 448k data, 248k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
pty: 256 Unix98 ptys configured
Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
ttyS00 at 0xfdf04500 (irq = 90) is a 16550A
ttyS01 at 0xfdf04600 (irq = 0) is a 16550A
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8540ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 248k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: rp_filter.
Disable TCP/IP Explicit Congestion Notification: done.
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8540ads-003 login: root
Last login: Thu Jan 1 00:00:07 1970 on console
Linux mpc8540ads-003 2.4.21-rc5 #1 Wed Oct 15 09:05:42 CDT 2003 ppc unknown
root@mpc8540ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8540ads-003:~# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4576 errors:0 dropped:0 overruns:0 frame:0
TX packets:2587 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4457023 (4.2 Mb) TX bytes:437770 (427.5 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8540ads-003:~# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.2 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.2 ms
root@mpc8540ads-003:~#
5.2 MPC8560ADS board
U-Boot 1.0.0-pre (Oct 15 2003 - 13:42:04)
Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
Board: Motorola MPC8560ADS Board
CPU: 792 MHz
CCB: 264 MHz
DDR: 132 MHz
LBC: 66 MHz
CPM: 264 Mhz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: DDR module detected, total size:128MB.
128 MB
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: MOTOROLA ETHERNE
Hit any key to stop autoboot: 3
MPC8560ADS=> bdinfo
memstart = 0x00000000
memsize = 0x08000000
flashstart = 0xFF000000
flashsize = 0x01000000
flashoffset = 0x00000000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFDF00000
bootflags = 0x00000000
vco = 528 MHz
sccfreq = 132 MHz
brgfreq = 132 MHz
intfreq = 792 MHz
cpmfreq = 264 MHz
busfreq = 264 MHz
ethaddr = 00:01:AF:07:9B:8A
eth1addr = 00:01:AF:07:9B:8B
eth2addr = 00:01:AF:07:9B:8C
IP addr = 10.82.0.105
baudrate = 115200 bps
MPC8560ADS=> printenv
bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
bootcmd=bootm 0xff400000 0xff700000
bootdelay=3
baudrate=115200
loads_echo=1
ethaddr=00:01:af:07:9b:8a
eth1addr=00:01:af:07:9b:8b
eth2addr=00:01:af:07:9b:8c
ipaddr=10.82.0.105
serverip=163.12.64.52
rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
gatewayip=10.82.1.254
netmask=255.255.254.0
hostname=MPC8560ADS_PILOT_003
bootfile=pImage
stdin=serial
stdout=serial
stderr=serial
Environment size: 560/8188 bytes
MPC8560ADS=> fli
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
Size: 16 MB in 64 Sectors
Sector Start Addresses:
FF000000 FF040000 FF080000 FF0C0000 FF100000
FF140000 FF180000 FF1C0000 FF200000 FF240000
FF280000 FF2C0000 FF300000 FF340000 FF380000
FF3C0000 FF400000 FF440000 FF480000 FF4C0000
FF500000 FF540000 FF580000 FF5C0000 FF600000
FF640000 FF680000 FF6C0000 FF700000 FF740000
FF780000 FF7C0000 FF800000 FF840000 FF880000
FF8C0000 FF900000 FF940000 FF980000 FF9C0000
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
MPC8560ADS=> imi ff100000
## Checking Image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
MPC8560ADS=> tftp 1000000 pImage.dracom.public
TFTP from server 163.12.64.52; our IP address is 10.82.0.105; sending through gateway 10.82.1.254
Filename 'pImage.dracom.public'.
Load address: 0x1000000
Loading: *#################################################################
#################################################################
##################
done
Bytes transferred = 755425 (b86e1 hex)
MPC8560ADS=> bootm ff100000
## Booting image at ff100000 ...
Image Name: Linux-2.4.21-rc5
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 755361 Bytes = 737.7 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
mpc85xx_init(): exit
id mach(): done
MMU:enter
Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
MMU:hw init
MMU:mapin
MMU:mapin_ram done
MMU:setio
MMU:exit
Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #2 Wed Oct 15 09:13:46 CDT 2003
setup_arch: enter
setup_arch: bootmem
mpc85xx_setup_arch
Host Bridge Vendor ID = 1057
Host Bridge Device ID = 3
Host Bridge header = 0
arch: exit
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
openpic: enter
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
openpic: timer
openpic: external
openpic: spurious
openpic: exit
time_init: decrementer frequency = 33.000000 MHz
Calibrating delay loop... 226.09 BogoMIPS
Memory: 127624k available (1276k kernel code, 384k data, 236k init, 0k highmem)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
CPM UART driver version 0.01
ttyS0 on SCC1 at 0x8000, BRG1
UART interrupt installed(40)
pty: 256 Unix98 ptys configured
eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
Copyright (c) 1999-2003 Intel Corporation.
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 8192)
IP-Config: Complete:
device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
host=mpc8560ads-003, domain=, nis-domain=(none),
bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 163.12.64.52
Looking up port of RPC 100005/1 on 163.12.64.52
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 236k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: FAILED
Configuring network interfaces: done.
Starting portmap daemon: portmap.
Cleaning: /tmp /var/lock /var/run.
INIT: Entering runlevel: 2
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
mpc8560ads-003 login: root
Last login: Thu Jan 1 00:00:05 1970 on console
Linux mpc8560ads-003 2.4.21-rc5 #2 Wed Oct 15 09:13:46 CDT 2003 ppc unknown
root@mpc8560ads-003:~# ls
21142.o aa e100.o hello.o mii.o timer.o
root@mpc8560ads-003:~# cd /
root@mpc8560ads-003:/# ls
bin boot dev etc home lib mnt opt proc root sbin tmp usr var
root@mpc8560ads-003:/# /sbin/ifconfig
eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:4608 errors:0 dropped:0 overruns:0 frame:0
TX packets:2610 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:100
RX bytes:4465943 (4.2 Mb) TX bytes:440944 (430.6 Kb)
Base address:0x4000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
root@mpc8560ads-003:/# ping 163.12.64.52
PING 163.12.64.52 (163.12.64.52): 56 data bytes
64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
--- 163.12.64.52 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.1/0.1/0.1 ms
root@mpc8560ads-003:/#

2
doc/README.nios
View File

@ -44,7 +44,6 @@ The Nios port also does not use the long-winded peripheral
structure definitions from the Nios SDK.
2. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
@ -189,7 +188,6 @@ for those interested in contributing:
MSTEP and MUL instructions (e.g. CFG_NIOS_MULT_HW and CFG_NIOS_MULT_MSTEP).
Regards,
--Scott

4
drivers/dc2114x.c
View File

@ -169,7 +169,11 @@ static void dc21x4x_halt(struct eth_device* dev);
extern void dc21x4x_select_media(struct eth_device* dev);
#endif
#if defined(CONFIG_E500)
#define phys_to_bus(a) (a)
#else
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static int INL(struct eth_device* dev, u_long addr)
{

5
drivers/eepro100.c
View File

@ -248,8 +248,13 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet,
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
#if defined(CONFIG_E500)
#define bus_to_phys(a) (a)
#define phys_to_bus(a) (a)
#else
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static inline int INW (struct eth_device *dev, u_long addr)
{

11
drivers/pci_indirect.c
View File

@ -32,6 +32,17 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_E500)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \

2
drivers/sk98lin/Makefile
View File

@ -99,5 +99,3 @@ $(LIB): $(OBJS)
sinclude .depend
#########################################################################

3
drivers/sk98lin/h/skdrv1st.h
View File

@ -179,7 +179,7 @@ typedef struct s_AC SK_AC;
#define SK_MEM_MAPPED_IO
// #define SK_RLMT_SLOW_LOOKAHEAD
/* #define SK_RLMT_SLOW_LOOKAHEAD */
#define SK_MAX_MACS 2
#define SK_MAX_NETS 2
@ -262,4 +262,3 @@ extern void SkDbgPrintf(const char *format,...);
extern void SkErrorLog(SK_AC*, int, int, char*);
#endif

4
drivers/sk98lin/h/skdrv2nd.h
View File

@ -188,7 +188,6 @@ struct s_DrvRlmtMbuf {
};
/*
* ioctl definitions
*/
@ -309,7 +308,6 @@ struct s_TxD {
#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
/* The offsets of registers in the TX and RX queue control io area ***********/
#define RX_Q_BUF_CTRL_CNT 0x00
@ -560,6 +558,4 @@ struct s_AC {
};
#endif /* __INC_SKDRV2ND_H */

1
drivers/sk98lin/h/ski2c.h
View File

@ -290,4 +290,3 @@ extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
#endif
#endif /* n_SKI2C_H */

1
drivers/sk98lin/h/skqueue.h
View File

@ -145,4 +145,3 @@ extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc);
#define SKERR_Q_E002 (SKERR_Q_E001+1)
#define SKERR_Q_E002MSG "Undefined event class"
#endif /* _SKQUEUE_H_ */

2
drivers/sk98lin/h/skversion.h
View File

@ -50,5 +50,3 @@ static const char SysKonnectBuildNumber[] =
"(C)Copyright 1999-2003 Marvell(R)."
#define VER_STRING "6.05"

38
drivers/sk98lin/skge.c
View File

@ -384,18 +384,18 @@
* use those defines for a compile-in version of the driver instead
* of command line parameters
*/
// #define LINK_SPEED_A {"Auto", }
// #define LINK_SPEED_B {"Auto", }
// #define AUTO_NEG_A {"Sense", }
// #define AUTO_NEG_B {"Sense", }
// #define DUP_CAP_A {"Both", }
// #define DUP_CAP_B {"Both", }
// #define FLOW_CTRL_A {"SymOrRem", }
// #define FLOW_CTRL_B {"SymOrRem", }
// #define ROLE_A {"Auto", }
// #define ROLE_B {"Auto", }
// #define PREF_PORT {"A", }
// #define RLMT_MODE {"CheckLinkState", }
/* #define LINK_SPEED_A {"Auto", } */
/* #define LINK_SPEED_B {"Auto", } */
/* #define AUTO_NEG_A {"Sense", } */
/* #define AUTO_NEG_B {"Sense", } */
/* #define DUP_CAP_A {"Both", } */
/* #define DUP_CAP_B {"Both", } */
/* #define FLOW_CTRL_A {"SymOrRem", } */
/* #define FLOW_CTRL_B {"SymOrRem", } */
/* #define ROLE_A {"Auto", } */
/* #define ROLE_B {"Auto", } */
/* #define PREF_PORT {"A", } */
/* #define RLMT_MODE {"CheckLinkState", } */
#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
@ -737,7 +737,6 @@ int skge_probe (struct eth_device ** ret_dev)
}
/* Create proc file */
pProcFile = create_proc_entry(dev->name,
S_IFREG | S_IXUSR | S_IWGRP | S_IROTH,
@ -3181,7 +3180,6 @@ unsigned long Flags;
(SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
return 0;
} /* SkGeSetMacAddr */
@ -3386,7 +3384,7 @@ SK_EVPARA EvPara;
* enable/disable hardware support for long frames
*/
if (NewMtu > 1500) {
// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
/* pAC->JumboActivated = SK_TRUE; /#* is never set back !!! */
pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
}
else {
@ -4132,8 +4130,6 @@ unsigned long Flags;
} /* ProductStr */
/****************************************************************************/
/* functions for common modules *********************************************/
/****************************************************************************/
@ -4758,7 +4754,6 @@ static void DumpMsg(struct sk_buff *skb, char *str)
} /* DumpMsg */
/*****************************************************************************
*
* DumpData - print a data area
@ -4867,10 +4862,3 @@ int l;
#endif
#endif /* CONFIG_SK98 */
/*
* Local variables:
* compile-command: "make"
* End:
*/

1
drivers/sk98lin/skgemib.c
View File

@ -107,7 +107,6 @@ PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
#endif
/* defines *******************************************************************/
#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))

1
drivers/sk98lin/skgepnmi.c
View File

@ -7135,7 +7135,6 @@ unsigned int StatIndex) /* Index to statistic value */
break;
case SK_PNMI_HTX_DEFFERAL:
/* Not supported by GMAC */
if (MacType == SK_MAC_GMAC) {

3
drivers/sk98lin/skproc.c
View File

@ -381,9 +381,6 @@ void *data)
}
/*****************************************************************************
*
* SkDoDiv - convert 64bit number

1
drivers/sk98lin/skvpd.c
View File

@ -1281,7 +1281,6 @@ SK_IOC IoC) /* IO Context */
}
/*
* Read the contents of the VPD EEPROM and copy it to the VPD buffer
* if not already done. If the keyword "VF" is not present it will be

2
drivers/sk98lin/skxmac2.c
View File

@ -456,7 +456,6 @@ static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int);
#endif /* OTHER_PHY */
/******************************************************************************
*
* SkXmPhyRead() - Read from XMAC PHY register
@ -1441,7 +1440,6 @@ int Port) /* Port Index (MAC_1 + n) */
} /* SkMacHardRst */
/******************************************************************************
*
* SkXmInitMac() - Initialize the XMAC II

1
examples/nios.lds
View File

@ -58,4 +58,3 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}

1
include/asm-mips/au1x00.h
View File

@ -704,7 +704,6 @@ static __inline__ int au_ffs(int x)
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
/* SSIO */
#define SSI0_STATUS 0xB1600000
#define SSI_STATUS_BF (1<<4)

1
include/asm-nios/byteorder.h
View File

@ -28,4 +28,3 @@
#include <linux/byteorder/little_endian.h>
#endif

1
include/asm-nios/psr.h
View File

@ -25,5 +25,4 @@
#define _NIOS_PSR_H
#endif /* _NIOS_PSR_H */

825
include/asm-ppc/cpm_85xx.h Normal file
View File

@ -0,0 +1,825 @@
/*
* MPC85xx Communication Processor Module
* Copyright (c) 2003,Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* MPC8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* This file contains structures and information for the communication
* processor channels found in the dual port RAM or parameter RAM.
* All CPM control and status is available through the MPC8260 internal
* memory map. See immap.h for details.
*/
#ifndef __CPM_85XX__
#define __CPM_85XX__
#include <asm/immap_85xx.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((uint)0x80000000)
#define CPM_CR_PAGE ((uint)0x7c000000)
#define CPM_CR_SBLOCK ((uint)0x03e00000)
#define CPM_CR_FLG ((uint)0x00010000)
#define CPM_CR_MCN ((uint)0x00003fc0)
#define CPM_CR_OPCODE ((uint)0x0000000f)
/* Device sub-block and page codes.
*/
#define CPM_CR_SCC1_SBLOCK (0x04)
#define CPM_CR_SCC2_SBLOCK (0x05)
#define CPM_CR_SCC3_SBLOCK (0x06)
#define CPM_CR_SCC4_SBLOCK (0x07)
#define CPM_CR_SMC1_SBLOCK (0x08)
#define CPM_CR_SMC2_SBLOCK (0x09)
#define CPM_CR_SPI_SBLOCK (0x0a)
#define CPM_CR_I2C_SBLOCK (0x0b)
#define CPM_CR_TIMER_SBLOCK (0x0f)
#define CPM_CR_RAND_SBLOCK (0x0e)
#define CPM_CR_FCC1_SBLOCK (0x10)
#define CPM_CR_FCC2_SBLOCK (0x11)
#define CPM_CR_FCC3_SBLOCK (0x12)
#define CPM_CR_MCC1_SBLOCK (0x1c)
#define CPM_CR_SCC1_PAGE (0x00)
#define CPM_CR_SCC2_PAGE (0x01)
#define CPM_CR_SCC3_PAGE (0x02)
#define CPM_CR_SCC4_PAGE (0x03)
#define CPM_CR_SPI_PAGE (0x09)
#define CPM_CR_I2C_PAGE (0x0a)
#define CPM_CR_TIMER_PAGE (0x0a)
#define CPM_CR_RAND_PAGE (0x0a)
#define CPM_CR_FCC1_PAGE (0x04)
#define CPM_CR_FCC2_PAGE (0x05)
#define CPM_CR_FCC3_PAGE (0x06)
#define CPM_CR_MCC1_PAGE (0x07)
#define CPM_CR_MCC2_PAGE (0x08)
/* Some opcodes (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
* used for SMC1 and SMC2 parameter RAM, so we start allocating
* BDs above that. All of this must change when we start
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
* pages.
*/
#define NUM_CPM_HOST_PAGES 2
/* Export the base address of the communication processor registers
* and dual port ram.
*/
/*extern cpm8560_t *cpmp; Pointer to comm processor */
uint m8560_cpm_dpalloc(uint size, uint align);
uint m8560_cpm_hostalloc(uint size, uint align);
void m8560_cpm_setbrg(uint brg, uint rate);
void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* ?? */
/* Function code bits, usually generic to devices.
*/
#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
/* Parameter RAM offsets from the base.
*/
#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#define PROFF_SCC4 ((uint)0x8300)
#define PROFF_FCC1 ((uint)0x8400)
#define PROFF_FCC2 ((uint)0x8500)
#define PROFF_FCC3 ((uint)0x8600)
#define PROFF_MCC1 ((uint)0x8700)
#define PROFF_MCC2 ((uint)0x8800)
#define PROFF_SPI_BASE ((uint)0x89fc)
#define PROFF_TIMERS ((uint)0x8ae0)
#define PROFF_REVNUM ((uint)0x8af0)
#define PROFF_RAND ((uint)0x8af8)
#define PROFF_I2C_BASE ((uint)0x8afc)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* CPM Ethernet through SCC1.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PSMR) as used by Ethernet.
*/
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
* Common to SCC and FCC.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
* Common to SCC and FCC.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PSMR when used as a UART.
*/
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* How about some FCCs.....
*/
#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
#define FCC_GFMR_TCI ((uint)0x20000000)
#define FCC_GFMR_TRX ((uint)0x10000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_TTX ((uint)0x08000000)
#define FCC_GFMR_CDP ((uint)0x04000000)
#define FCC_GFMR_CTSP ((uint)0x02000000)
#define FCC_GFMR_CDS ((uint)0x01000000)
#define FCC_GFMR_CTSS ((uint)0x00800000)
#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
#define FCC_GFMR_RTSM ((uint)0x00002000)
#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
#define FCC_GFMR_REVD ((uint)0x00000400)
#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
#define FCC_GFMR_ENR ((uint)0x00000020)
#define FCC_GFMR_ENT ((uint)0x00000010)
#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
/* Generic FCC parameter ram.
*/
typedef struct fcc_param {
ushort fcc_riptr; /* Rx Internal temp pointer */
ushort fcc_tiptr; /* Tx Internal temp pointer */
ushort fcc_res1;
ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
uint fcc_rstate; /* Upper byte is Func code, must be set */
uint fcc_rbase; /* Receive BD base */
ushort fcc_rbdstat; /* RxBD status */
ushort fcc_rbdlen; /* RxBD down counter */
uint fcc_rdptr; /* RxBD internal data pointer */
uint fcc_tstate; /* Upper byte is Func code, must be set */
uint fcc_tbase; /* Transmit BD base */
ushort fcc_tbdstat; /* TxBD status */
ushort fcc_tbdlen; /* TxBD down counter */
uint fcc_tdptr; /* TxBD internal data pointer */
uint fcc_rbptr; /* Rx BD Internal buf pointer */
uint fcc_tbptr; /* Tx BD Internal buf pointer */
uint fcc_rcrc; /* Rx temp CRC */
uint fcc_res2;
uint fcc_tcrc; /* Tx temp CRC */
} fccp_t;
/* Ethernet controller through FCC.
*/
typedef struct fcc_enet {
fccp_t fen_genfcc;
uint fen_statbuf; /* Internal status buffer */
uint fen_camptr; /* CAM address */
uint fen_cmask; /* Constant mask for CRC */
uint fen_cpres; /* Preset CRC */
uint fen_crcec; /* CRC Error counter */
uint fen_alec; /* alignment error counter */
uint fen_disfc; /* discard frame counter */
ushort fen_retlim; /* Retry limit */
ushort fen_retcnt; /* Retry counter */
ushort fen_pper; /* Persistence */
ushort fen_boffcnt; /* backoff counter */
uint fen_gaddrh; /* Group address filter, high 32-bits */
uint fen_gaddrl; /* Group address filter, low 32-bits */
ushort fen_tfcstat; /* out of sequence TxBD */
ushort fen_tfclen;
uint fen_tfcptr;
ushort fen_mflr; /* Maximum frame length (1518) */
ushort fen_paddrh; /* MAC address */
ushort fen_paddrm;
ushort fen_paddrl;
ushort fen_ibdcount; /* Internal BD counter */
ushort fen_ibdstart; /* Internal BD start pointer */
ushort fen_ibdend; /* Internal BD end pointer */
ushort fen_txlen; /* Internal Tx frame length counter */
uint fen_ibdbase[8]; /* Internal use */
uint fen_iaddrh; /* Individual address filter */
uint fen_iaddrl;
ushort fen_minflr; /* Minimum frame length (64) */
ushort fen_taddrh; /* Filter transfer MAC address */
ushort fen_taddrm;
ushort fen_taddrl;
ushort fen_padptr; /* Pointer to pad byte buffer */
ushort fen_cftype; /* control frame type */
ushort fen_cfrange; /* control frame range */
ushort fen_maxb; /* maximum BD count */
ushort fen_maxd1; /* Max DMA1 length (1520) */
ushort fen_maxd2; /* Max DMA2 length (1520) */
ushort fen_maxd; /* internal max DMA count */
ushort fen_dmacnt; /* internal DMA counter */
uint fen_octc; /* Total octect counter */
uint fen_colc; /* Total collision counter */
uint fen_broc; /* Total broadcast packet counter */
uint fen_mulc; /* Total multicast packet count */
uint fen_uspc; /* Total packets < 64 bytes */
uint fen_frgc; /* Total packets < 64 bytes with errors */
uint fen_ospc; /* Total packets > 1518 */
uint fen_jbrc; /* Total packets > 1518 with errors */
uint fen_p64c; /* Total packets == 64 bytes */
uint fen_p65c; /* Total packets 64 < bytes <= 127 */
uint fen_p128c; /* Total packets 127 < bytes <= 255 */
uint fen_p256c; /* Total packets 256 < bytes <= 511 */
uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
uint fen_cambuf; /* Internal CAM buffer poiner */
ushort fen_rfthr; /* Received frames threshold */
ushort fen_rfcnt; /* Received frames count */
} fcc_enet_t;
/* FCC Event/Mask register as used by Ethernet.
*/
#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* FCC Mode Register (FPSMR) as used by Ethernet.
*/
#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
/* IIC parameter RAM.
*/
typedef struct iic {
ushort iic_rbase; /* Rx Buffer descriptor base address */
ushort iic_tbase; /* Tx Buffer descriptor base address */
u_char iic_rfcr; /* Rx function code */
u_char iic_tfcr; /* Tx function code */
ushort iic_mrblr; /* Max receive buffer length */
uint iic_rstate; /* Internal */
uint iic_rdp; /* Internal */
ushort iic_rbptr; /* Internal */
ushort iic_rbc; /* Internal */
uint iic_rxtmp; /* Internal */
uint iic_tstate; /* Internal */
uint iic_tdp; /* Internal */
ushort iic_tbptr; /* Internal */
ushort iic_tbc; /* Internal */
uint iic_txtmp; /* Internal */
} iic_t;
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res; /* Tx temp. */
uint spi_res1[4]; /* SDMA temp. */
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
#define SPI_EB ((u_char)0x10) /* big endian byte order */
#define BD_IIC_START ((ushort)0x0400)
/*-----------------------------------------------------------------------
* CMXFCR - CMX FCC Clock Route Register 15-12
*/
#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
/*-----------------------------------------------------------------------
* CMXSCR - CMX SCC Clock Route Register 15-14
*/
#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
#endif /* __CPM_85XX__ */

4
include/asm-ppc/global_data.h
View File

@ -39,7 +39,7 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
@ -56,7 +56,7 @@ typedef struct global_data {
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260)
#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260) || defined(CONFIG_MPC8560)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif

1562
include/asm-ppc/immap_85xx.h Normal file
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File diff suppressed because it is too large Load Diff

98
include/asm-ppc/mmu.h
View File

@ -370,4 +370,102 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
/*
* e500 support
*/
#define MAS0_TLBSEL 0x10000000
#define MAS0_ESEL 0x000F0000
#define MAS0_NV 0x00000001
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID 0x00FF0000
#define MAS1_TS 0x00001000
#define MAS1_TSIZE 0x00000F00
#define MAS2_EPN 0xFFFFF000
#define MAS2_SHAREN 0x00000200
#define MAS2_X0 0x00000040
#define MAS2_X1 0x00000020
#define MAS2_W 0x00000010
#define MAS2_I 0x00000008
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS3_RPN 0xFFFFF000
#define MAS3_U0 0x00000200
#define MAS3_U1 0x00000100
#define MAS3_U2 0x00000080
#define MAS3_U3 0x00000040
#define MAS3_UX 0x00000020
#define MAS3_SX 0x00000010
#define MAS3_UW 0x00000008
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
#define MAS4_TLBSELD 0x10000000
#define MAS4_TIDDSEL 0x00030000
#define MAS4_DSHAREN 0x00001000
#define MAS4_TSIZED(x) (x << 8)
#define MAS4_X0D 0x00000040
#define MAS4_X1D 0x00000020
#define MAS4_WD 0x00000010
#define MAS4_ID 0x00000008
#define MAS4_MD 0x00000004
#define MAS4_GD 0x00000002
#define MAS4_ED 0x00000001
#define MAS6_SPID 0x00FF0000
#define MAS6_SAS 0x00000001
#define BOOKE_PAGESZ_1K 0
#define BOOKE_PAGESZ_4K 1
#define BOOKE_PAGESZ_16K 2
#define BOOKE_PAGESZ_64K 3
#define BOOKE_PAGESZ_256K 4
#define BOOKE_PAGESZ_1M 5
#define BOOKE_PAGESZ_4M 6
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
#define LAWBAR_BASE_ADDR 0x000FFFFF
#define LAWAR_EN 0x80000000
#define LAWAR_TRGT_IF 0x00F00000
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_RIO 0x00c00000
#define LAWAR_TRGT_IF_DDR 0x00f00000
#define LAWAR_SIZE_BASE 0xa
#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
#endif /* _PPC_MMU_H_ */

200
include/asm-ppc/processor.h
View File

@ -18,7 +18,9 @@
#define MSR_SF (1<<63)
#define MSR_ISF (1<<61)
#endif /* CONFIG_PPC64BRIDGE */
#define MSR_VEC (1<<25) /* Enable AltiVec */
#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
#define MSR_SPE (1<<25) /* Enable SPE(e500) */
#define MSR_POW (1<<18) /* Enable Power Management */
#define MSR_WE (1<<18) /* Wait State Enable */
#define MSR_TGPR (1<<17) /* TLB Update registers in use */
@ -30,14 +32,19 @@
#define MSR_ME (1<<12) /* Machine Check Enable */
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
@ -46,7 +53,11 @@
#else
#define MSR_ MSR_ME|MSR_RI
#endif
#ifndef CONFIG_E500
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
#else
#define MSR_KERNEL MSR_ME
#endif
#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
/* Floating Point Status and Control Register (FPSCR) Fields */
@ -84,8 +95,13 @@
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
#else
#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
#endif /* CONFIG_BOOKE */
#define SPRN_DAR 0x013 /* Data Address Register */
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
@ -136,9 +152,20 @@
#define DBCR_SDA 0x00000004 /* Second DAC Enable */
#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
#ifndef CONFIG_BOOKE
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
#else
#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
#endif /* CONFIG_BOOKE */
#ifndef CONFIG_BOOKE
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#else
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
#endif /* CONFIG_BOOKE */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
@ -146,12 +173,20 @@
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
#define DCWR_WRITE 1 /* Write-through */
#ifndef CONFIG_BOOKE
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
#else
#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
#define SPRN_EAR 0x11A /* External Address Register */
#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
#else
#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
#endif /* CONFIG_BOOKE */
#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
@ -193,8 +228,13 @@
#define HID0_BTCD (1<<1) /* Branch target cache disable */
#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
#else
#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
#endif /* CONFIG_BOOKE */
#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
@ -227,8 +267,13 @@
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
#ifndef CONFIG_BOOKE
#define SPRN_PID 0x3B1 /* Process ID */
#define SPRN_PIR 0x3FF /* Processor Identification Register */
#else
#define SPRN_PID 0x030 /* Book E Process ID */
#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
#endif /* CONFIG_BOOKE */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
@ -258,7 +303,11 @@
#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
#ifndef CONFIG_BOOKE
#define SPRN_TCR 0x3DA /* Timer Control Register */
#else
#define SPRN_TCR 0x154 /* Book E Timer Control Register */
#endif /* CONFIG_BOOKE */
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
#define WP_2_17 0 /* 2^17 clocks */
#define WP_2_21 1 /* 2^21 clocks */
@ -288,7 +337,12 @@
#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
#define THRM3_E (1<<31)
#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
#ifndef CONFIG_BOOKE
#define SPRN_TSR 0x3D8 /* Timer Status Register */
#else
#define SPRN_TSR 0x150 /* Book E Timer Status Register */
#endif /* CONFIG_BOOKE */
#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
@ -308,11 +362,82 @@
#define SPRN_XER 0x001 /* Fixed Point Exception Register */
#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
/* Book E definitions */
#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
#define SPRN_CSRR0 0x03A /* Critical SRR0 */
#define SPRN_CSRR1 0x03B /* Critical SRR0 */
#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
/* e500 definitions */
#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define ESR_ST 0x00800000 /* Store Operation */
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
#define DAR SPRN_DAR /* Data Address Register */
#define DABR SPRN_DABR /* Data Address Breakpoint Register */
#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
@ -329,16 +454,22 @@
#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
@ -360,6 +491,9 @@
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#if defined(CONFIG_E500)
#define PIR SPRN_PIR
#endif
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
@ -377,12 +511,70 @@
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
#define TCR SPRN_TCR /* Timer Control Register */
#define TSR SPRN_TSR /* Timer Status Register */
#define ICTC 1019
#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
#define XER SPRN_XER
#define DECAR SPRN_DECAR
#define CSRR0 SPRN_CSRR0
#define CSRR1 SPRN_CSRR1
#define IVPR SPRN_IVPR
#define USPRG0 SPRN_USPRG0
#define SPRG4R SPRN_SPRG4R
#define SPRG5R SPRN_SPRG5R
#define SPRG6R SPRN_SPRG6R
#define SPRG7R SPRN_SPRG7R
#define SPRG4W SPRN_SPRG4W
#define SPRG5W SPRN_SPRG5W
#define SPRG6W SPRN_SPRG6W
#define SPRG7W SPRN_SPRG7W
#define DEAR SPRN_DEAR
#define DBCR2 SPRN_DBCR2
#define IAC3 SPRN_IAC3
#define IAC4 SPRN_IAC4
#define DVC1 SPRN_DVC1
#define DVC2 SPRN_DVC2
#define IVOR0 SPRN_IVOR0
#define IVOR1 SPRN_IVOR1
#define IVOR2 SPRN_IVOR2
#define IVOR3 SPRN_IVOR3
#define IVOR4 SPRN_IVOR4
#define IVOR5 SPRN_IVOR5
#define IVOR6 SPRN_IVOR6
#define IVOR7 SPRN_IVOR7
#define IVOR8 SPRN_IVOR8
#define IVOR9 SPRN_IVOR9
#define IVOR10 SPRN_IVOR10
#define IVOR11 SPRN_IVOR11
#define IVOR12 SPRN_IVOR12
#define IVOR13 SPRN_IVOR13
#define IVOR14 SPRN_IVOR14
#define IVOR15 SPRN_IVOR15
#define IVOR32 SPRN_IVOR32
#define IVOR33 SPRN_IVOR33
#define IVOR34 SPRN_IVOR34
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
#define BUCSR SPRN_BUCSR
#define PID0 SPRN_PID
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
#define MAS5 SPRN_MAS5
#define MAS6 SPRN_MAS6
/* Device Control Registers */
@ -513,6 +705,12 @@
#define PVR_750 PVR_740
#define PVR_740P 0x10080000
#define PVR_750P PVR_740P
#define PVR_7400 0x000C0000
#define PVR_7410 0x800C0000
#define PVR_7450 0x80000000
#define PVR_8540 0x80200010
#define PVR_8560 0x80200010
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be

12
include/asm-ppc/u-boot.h
View File

@ -38,7 +38,8 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|| defined(CONFIG_E500)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5XXX)
@ -50,7 +51,7 @@ typedef struct bd_info {
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#if defined(CONFIG_8260)
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
@ -80,11 +81,14 @@ typedef struct bd_info {
defined(CONFIG_PN62) || \
defined(CONFIG_PPCHAMELEONEVB) || \
defined(CONFIG_SXNI855T) || \
defined(CONFIG_SVM_SC8xx)
defined(CONFIG_SVM_SC8xx) || \
defined(CONFIG_MPC8540ADS) || \
defined(CONFIG_MPC8560ADS)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx)
#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx) || \
defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif

1
include/bzlib.h
View File

@ -172,7 +172,6 @@ BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
);
/*-- High(er) level library functions --*/
#ifndef BZ_NO_STDIO

12
include/common.h
View File

@ -62,6 +62,10 @@ typedef volatile unsigned char vu_char;
#elif defined(CONFIG_8260)
#include <asm/immap_8260.h>
#endif
#ifdef CONFIG_MPC85xx
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
#endif
@ -287,6 +291,7 @@ int testdram(void);
defined(CONFIG_8xx)
uint get_immr (uint);
#endif
uint get_pir (void);
uint get_pvr (void);
uint rd_ic_cst (void);
void wr_ic_cst (uint);
@ -359,6 +364,11 @@ ulong get_UCLK (void);
#endif
ulong get_bus_freq (ulong);
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
@ -372,7 +382,7 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
#ifdef CONFIG_4xx
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx)
void cpu_init_f (void);
#endif
int cpu_init_r (void);

2
include/configs/AdderII.h
View File

@ -146,7 +146,6 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/* SIU Module Configuration Register */
#define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
@ -223,4 +222,3 @@
#endif
/* __CONFIG_H */

331
include/configs/MPC8540ADS.h Normal file
View File

@ -0,0 +1,331 @@
/*
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* mpc8540ads board configuration file */
/* please refer to doc/README.mpc85xxads for more info */
/* make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1 Chip */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific*/
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#if defined(CONFIG_MPC85xx_REV1)
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#endif
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
*/
#undef CONFIG_RAM_AS_FLASH
#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
#else
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
#endif
#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
#define CONFIG_DDR_SETTING
#endif
/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#undef CONFIG_BTB /* toggle branch predition */
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
#endif
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE 128 /* DDR is now 128MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
#endif
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#if defined(CONFIG_DDR_SETTING)
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
#endif
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
#define CFG_LBC_LSDMR_1 0x2861b723
#define CFG_LBC_LSDMR_2 0x0861b723
#define CFG_LBC_LSDMR_3 0x0861b723
#define CFG_LBC_LSDMR_4 0x1861b723
#define CFG_LBC_LSDMR_5 0x4061b723
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#else
#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
#endif
#define CFG_OR4_PRELIM 0xffffe1f1
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
/* General PCI */
#define CFG_PCI_MEM_BASE 0xe0000000
#define CFG_PCI_MEM_PHYS 0xe0000000
#define CFG_PCI_MEM_SIZE 0x10000000
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#undef CONFIG_EEPRO100
#define CONFIG_TULIP
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
#endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 8 */
#define CFG_PCI_SUBSYS_DEVICEID 0x0003
#else
#define CFG_PCI_SUBSYS_DEVICEID 0x0008
#endif
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
#endif
/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
#define CONFIG_BOOTCOMMAND "bootm 0xff300000 0xff700000"
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | CFG_CMD_LOADS ))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | \
CFG_CMD_LOADS ))
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
#endif
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MPC8540ADS=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* NOTE: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:01:af:07:9b:8a
#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
#endif
#define CONFIG_SERVERIP 163.12.64.52
#define CONFIG_IPADDR 10.82.0.105
#define CONFIG_GATEWAYIP 10.82.1.254
#define CONFIG_NETMASK 255.255.254.0
#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
#define CONFIG_BOOTFILE pImage
#endif /* __CONFIG_H */

377
include/configs/MPC8560ADS.h Normal file
View File

@ -0,0 +1,377 @@
/*
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
#define CONFIG_MPC8560 1 /* MPC8560 specific */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific*/
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#if defined(CONFIG_MPC85xx_REV1)
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#endif
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you need a flash-boot image(u-boot.bin), if so undef this.
*/
#undef CONFIG_RAM_AS_FLASH
#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
#else
#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
#endif
#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
#define CONFIG_DDR_SETTING
#endif
/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#undef CONFIG_BTB /* toggle branch predition */
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
#endif
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
#endif
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#if defined(CONFIG_DDR_SETTING)
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
#define CFG_DDR_CS0_CONFIG 0x80000002
#define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
#endif
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
#define CFG_LBC_LSDMR_1 0x2861b723
#define CFG_LBC_LSDMR_2 0x0861b723
#define CFG_LBC_LSDMR_3 0x0861b723
#define CFG_LBC_LSDMR_4 0x1861b723
#define CFG_LBC_LSDMR_5 0x4061b723
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#else
#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
#endif
#define CFG_OR4_PRELIM 0xffffe1f1
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_PCI_MEM_BASE 0xe0000000
#define CFG_PCI_MEM_PHYS 0xe0000000
#define CFG_PCI_MEM_SIZE 0x10000000
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
#define CFG_PCI_SUBSYS_DEVICEID 0x0003
#else
#define CFG_PCI_SUBSYS_DEVICEID 0x0009
#endif
#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
/*
* - Rx-CLK is CLK13
* - Tx-CLK is CLK14
* - Select bus for bd/buffers
* - Full duplex
*/
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
#define CONFIG_MII /* MII PHY management */
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
else iop->pdat &= ~0x00400000
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
else iop->pdat &= ~0x00200000
#define MIIDELAY udelay(1)
#endif
/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 128K(one sector) for env */
#endif
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200"
/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
#define CONFIG_BOOTCOMMAND "bootm 0xff400000 0xff700000"
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
CFG_CMD_PING | CFG_CMD_I2C) & \
~(CFG_CMD_ENV | \
CFG_CMD_LOADS ))
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
CFG_CMD_I2C ) & \
~(CFG_CMD_ENV))
#elif defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
CFG_CMD_PING | CFG_CMD_I2C) & \
~(CFG_CMD_ENV))
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
CFG_CMD_PING | CFG_CMD_I2C)
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
CFG_CMD_I2C)
#elif defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
CFG_CMD_PING | CFG_CMD_I2C)
#endif
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MPC8560ADS=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_ETHADDR 00:01:af:07:9b:8a
#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
#endif
#define CONFIG_SERVERIP 163.12.64.52
#define CONFIG_IPADDR 10.82.0.105
#define CONFIG_GATEWAYIP 10.82.1.254
#define CONFIG_NETMASK 255.255.254.0
#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
#define CONFIG_BOOTFILE pImage
#endif /* __CONFIG_H */

1
include/configs/PPChameleonEVB.h
View File

@ -208,7 +208,6 @@
} while(0)
#define NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \

1
include/configs/omap1510.h
View File

@ -533,7 +533,6 @@ typedef struct {
#define WDTIM_CONTROL_ST BIT7
/* ---------------------------------------------------------------------------
* Differentiating processor versions for those who care.
* ---------------------------------------------------------------------------

100
include/e500.h Normal file
View File

@ -0,0 +1,100 @@
/*
* Copyright 2003 Motorola,Inc.
* Xianghua Xiao(x.xiao@motorola.com)
*/
#ifndef __E500_H__
#define __E500_H__
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long freqProcessor;
unsigned long freqSystemBus;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
/* Motorola E500 core provides 16 TLB1 entries; they can be used for
* initial memory mapping like legacy BAT registers do. Usually we
* use four MAS registers(MAS0-3) to operate on TLB1 entries.
*
* We also need LAWs(Local Access Window) to associate a range of
* the local 32-bit address space with a particular target interface
* such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
*
* We put TLB1/LAW code here because memory mapping is board-specific
* instead of cpu-specific.
*/
/* MAS0
* tlbsel(TLB Select):0,1
* esel(Entry Select): 0,1,2,...,15 for TLB1
* nv(Next victim):0,1
*/
#define TLB1_MAS0(tlbsel,esel,nv) \
((((tlbsel) << 28) & MAS0_TLBSEL) |\
(((esel) << 16) & MAS0_ESEL ) |\
(nv) )
/* MAS1
* v(TLB valid bit):0,1
* iprot(invalidate protect):0,1
* tid(translation identity):8bit to match process IDs
* ts(translation space,comparing with MSR[IS,DS]): 0,1
* tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
*/
#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
((((v) << 31) & MAS1_VALID) |\
(((iprot) << 30) & MAS1_IPROT) |\
(((tid) << 16) & MAS1_TID) |\
(((ts) << 12) & MAS1_TS) |\
(((tsize) << 8) & MAS1_TSIZE) )
/* MAS2
* epn(effective page number):20bits
* sharen(Shared cache state):0,1
* x0,x1(implementation specific page attribute):0,1
* w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
* endianness):0,1
*/
#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
((((epn) << 12) & MAS2_EPN) |\
(((sharen) << 9) & MAS2_SHAREN) |\
(((x0) << 6) & MAS2_X0) |\
(((x1) << 5) & MAS2_X1) |\
(((w) << 4) & MAS2_W) |\
(((i) << 3) & MAS2_I) |\
(((m) << 2) & MAS2_M) |\
(((g) << 1) & MAS2_G) |\
(e) )
/* MAS3
* rpn(real page number):20bits
* u0-u3(user bits, useful for page table management in OS):0,1
* ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
* write,execute permission).
*/
#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
((((rpn) << 12) & MAS3_RPN) |\
(((u0) << 9) & MAS3_U0) |\
(((u1) << 8) & MAS3_U1) |\
(((u2) << 7) & MAS3_U2) |\
(((u3) << 6) & MAS3_U3) |\
(((ux) << 5) & MAS3_UX) |\
(((sx) << 4) & MAS3_SX) |\
(((uw) << 3) & MAS3_UW) |\
(((sw) << 2) & MAS3_SW) |\
(((ur) << 1) & MAS3_UR) |\
(sr) )
#define RESET_VECTOR 0xfffffffc
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
line aligned data. */
#endif /* __E500_H__ */

4
include/ioports.h
View File

@ -25,7 +25,11 @@ typedef struct {
* the internal memory map aligns the above structure on
* a 0x20 byte boundary
*/
#ifdef CONFIG_MPC8560
#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
#endif
/*
* this structure provides configuration

32
include/mpc85xx.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright(c) 2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*/
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#if defined(CONFIG_E500)
#include <e500.h>
#endif
#if defined(CONFIG_DDR_ECC)
void dma_init(void);
uint dma_check(void);
int dma_xfer(void *dest, uint count, void *src);
#endif
/*-----------------------------------------------------------------------
* SCCR - System Clock Control Register 9-8
*/
#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
#define SCCR_DFBRG_SHIFT 0
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
#endif /* __MPC85xx_H__ */

2
include/net.h
View File

@ -29,7 +29,7 @@
# endif
#endif /* CONFIG_MPC5XXX */
#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_8260)
#if !defined(CONFIG_NET_MULTI) && (defined(CONFIG_8260) || defined(CONFIG_MPC8560))
#include <config.h>
#if defined(CONFIG_ETHER_ON_FCC)
#if defined(CONFIG_ETHER_ON_SCC)

1
include/nios-io.h
View File

@ -93,4 +93,3 @@ typedef volatile struct nios_timer_t {
#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
#endif /* __NIOSIO_H__ */

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