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Patch by Josef Wagner, 04 Jun 2004: 

- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45
This commit is contained in:
wdenk 2004-06-19 21:19:10 +00:00
parent 46a414dc12
commit 49822e23a0
26 changed files with 1714 additions and 1390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
CHANGELOG
View File

@ -2,12 +2,21 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Josef Wagner, 04 Jun 2004:
- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45
* Fix flash parameters passed to Linux for PPChameleon board
* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
* Patch by Paul Ruhland, 10 Jun 2004:
fix support for Logic SDK-LH7A404 board and clean up the
fix support for Logic SDK-LH7A404 board and clean up the
LH7A404 register macros.
* Patch by Matthew McClintock, 10 Jun 2004:

2
CREDITS
View File

@ -362,7 +362,7 @@ D: Port to MPC555/556 microcontrollers and support for cmi board
N: Ming-Len Wu
E: minglen_wu@techware.com.tw
D: Motorola MX1ADS board support
D: Motorola MX1ADS board support
W: http://www.techware.com.tw/
N: Xianghua Xiao

16
Makefile
View File

@ -255,8 +255,20 @@ TOP5200_config: unconfig
@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
PM520_config: unconfig
@./mkconfig $(@:_config=) ppc mpc5xxx pm520
PM520_config \
PM520_DDR_config \
PM520_ROMBOOT_config \
PM520_ROMBOOT_DDR_config: unconfig
@ >include/config.h
@[ -z "$(findstring DDR,$@)" ] || \
{ echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \
echo "... DDR memory revision" ; \
}
@[ -z "$(findstring ROMBOOT,$@)" ] || \
{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
echo "... booting from 8-bit flash" ; \
}
@./mkconfig -a PM520 ppc mpc5xxx pm520
#########################################################################
## MPC8xx Systems

146
board/cpc45/cpc45.c
View File

@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <asm/processor.h>
#include <pci.h>
#include <i2c.h>
int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
@ -58,46 +59,134 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
long int initdram (int board_type)
{
long size;
long new_bank0_end;
long mear1;
long emear1;
int m, row, col, bank, i, ref;
unsigned long start, end;
uint32_t mccr1, mccr2;
uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
uint8_t mber = 0;
unsigned int tmp;
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
if (i2c_reg_read (0x50, 2) != 0x04)
return 0; /* Memory type */
return (size);
m = i2c_reg_read (0x50, 5); /* # of physical banks */
row = i2c_reg_read (0x50, 3); /* # of rows */
col = i2c_reg_read (0x50, 4); /* # of columns */
bank = i2c_reg_read (0x50, 17); /* # of logical banks */
ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
CONFIG_READ_WORD(MCCR2, mccr2);
mccr2 &= 0xffff0000;
start = CFG_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
if (i < 4) {
msar1 |= ((start >> 20) & 0xff) << i * 8;
emsar1 |= ((start >> 28) & 0xff) << i * 8;
mear1 |= ((end >> 20) & 0xff) << i * 8;
emear1 |= ((end >> 28) & 0xff) << i * 8;
} else {
msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
}
mber |= 1 << i;
start += (1 << (col + row + 3) ) * bank;
end += (1 << (col + row + 3) ) * bank;
}
for (; i < 8; i++) {
if (i < 4) {
msar1 |= 0xff << i * 8;
emsar1 |= 0x30 << i * 8;
mear1 |= 0xff << i * 8;
emear1 |= 0x30 << i * 8;
} else {
msar2 |= 0xff << (i-4) * 8;
emsar2 |= 0x30 << (i-4) * 8;
mear2 |= 0xff << (i-4) * 8;
emear2 |= 0x30 << (i-4) * 8;
}
}
switch(ref) {
case 0x00:
case 0x80:
tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
break;
case 0x01:
case 0x81:
tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
break;
case 0x02:
case 0x82:
tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
break;
case 0x03:
case 0x83:
tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
break;
case 0x04:
case 0x84:
tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
break;
case 0x05:
case 0x85:
tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
break;
default:
tmp = 0x512;
break;
}
CONFIG_WRITE_WORD(MCCR1, mccr1);
CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
CONFIG_WRITE_WORD(MSAR1, msar1);
CONFIG_WRITE_WORD(EMSAR1, emsar1);
CONFIG_WRITE_WORD(MEAR1, mear1);
CONFIG_WRITE_WORD(EMEAR1, emear1);
CONFIG_WRITE_WORD(MSAR2, msar2);
CONFIG_WRITE_WORD(EMSAR2, emsar2);
CONFIG_WRITE_WORD(MEAR2, mear2);
CONFIG_WRITE_WORD(EMEAR2, emear2);
CONFIG_WRITE_BYTE(MBER, mber);
return (1 << (col + row + 3) ) * bank * m;
}
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_sandpoint_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
static struct pci_config_table pci_cpc45_config_table[] = {
#ifndef CONFIG_PCI_PNP
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
PCI_PLX9030_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
#endif /*CONFIG_PCI_PNP*/
{ }
};
#endif
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_sandpoint_config_table,
config_table: pci_cpc45_config_table,
#endif
};
@ -108,6 +197,9 @@ void pci_init_board(void)
/* init PCI_to_LOCAL Bus BRIDGE */
Plx9030Init();
/* Clear Display */
DISP_CWORD = 0x0;
sysControlDisplay(0,' ');
sysControlDisplay(1,'C');
sysControlDisplay(2,'P');
@ -130,16 +222,14 @@ void pci_init_board(void)
* RETURNS: NA
*/
int sysControlDisplay
(
int digit, /* number of digit 0..7 */
uchar ascii_code /* ASCII code */
)
int sysControlDisplay (int digit, /* number of digit 0..7 */
uchar ascii_code /* ASCII code */
)
{
if ((digit < 0) || (digit > 7))
return (-1);
*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
return (0);
}

323
board/cpc45/flash.c
View File

@ -41,12 +41,12 @@
#define MAIN_SECT_SIZE 0x40000
#define PARAM_SECT_SIZE 0x8000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
static int write_data (flash_info_t *info, ulong dest, ulong *data);
static void write_via_fpu(vu_long *addr, ulong *data);
static __inline__ unsigned long get_msr(void);
static __inline__ void set_msr(unsigned long msr);
static int write_data (flash_info_t * info, ulong dest, ulong * data);
static void write_via_fpu (vu_long * addr, ulong * data);
static __inline__ unsigned long get_msr (void);
static __inline__ void set_msr (unsigned long msr);
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
@ -62,102 +62,132 @@ static __inline__ void set_msr(unsigned long msr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
uchar tempChar;
int i, j;
ulong size = 0;
uchar tempChar;
vu_long *tmpaddr;
/* Enable flash writes on CPC45 */
/* Enable flash writes on CPC45 */
tempChar = BOARD_CTRL;
tempChar = BOARD_CTRL;
tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
BOARD_CTRL = tempChar;
BOARD_CTRL = tempChar;
__asm__ volatile ("sync\n eieio");
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
addr[0] = 0x00900090;
__asm__ volatile ("sync\n eieio");
udelay (100);
DEBUGF ("Flash bank # %d:\n"
"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
"\tDevice ID @ 0x%08lX: 0x%08lX\n",
i,
(ulong) (&addr[0]), addr[0],
(ulong) (&addr[2]), addr[2]);
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
addr[0] = 0x00900090;
flash_info[i].flash_id =
(FLASH_MAN_INTEL & FLASH_VENDMASK) |
(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
DEBUGF ("Flash bank # %d:\n"
"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
"\tDevice ID @ 0x%08lX: 0x%08lX\n",
i,
(ulong)(&addr[0]), addr[0],
(ulong)(&addr[2]), addr[2]);
} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
&& (addr[2] == addr[3])
&& (addr[2] == INTEL_ID_28F160C3T)) {
flash_info[i].flash_id =
(FLASH_MAN_INTEL & FLASH_VENDMASK) |
(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
{
flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
} else {
flash_info[i].flash_id = FLASH_UNKNOWN;
addr[0] = 0xFFFFFFFF;
goto Done;
}
DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
addr[0] = 0xFFFFFFFF;
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j > 30) {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
(MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
} else {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
j * MAIN_SECT_SIZE;
flash_info[i].flash_id = FLASH_UNKNOWN;
addr[0] = 0xFFFFFFFF;
goto Done;
}
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
addr[0] = 0xFFFFFFFF;
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j > 30) {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
(MAIN_SECT_SIZE * 31) + (j -
31) *
PARAM_SECT_SIZE;
} else {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
j * MAIN_SECT_SIZE;
}
}
/* unlock sectors, if 160C3T */
for (j = 0; j < flash_info[i].sector_count; j++) {
tmpaddr = (vu_long *) flash_info[i].start[j];
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
tmpaddr[0] = 0x00600060;
tmpaddr[0] = 0x00D000D0;
tmpaddr[1] = 0x00600060;
tmpaddr[1] = 0x00D000D0;
}
}
size += flash_info[i].size;
addr[0] = 0x00FF00FF;
addr[1] = 0x00FF00FF;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[1]);
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[1]);
#else
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[1]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
#else
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
#endif
Done:
return size;
return size;
}
/*-----------------------------------------------------------------------
@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
printf ("28F160F3T (16Mbit)\n");
break;
case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
printf ("28F160C3T (16Mbit)\n");
break;
default:
printf ("Unknown Chip Type 0x%04x\n", i);
goto Done;
@ -186,7 +221,7 @@ void flash_print_info (flash_info_t * info)
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
@ -194,7 +229,7 @@ void flash_print_info (flash_info_t * info)
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
@ -205,7 +240,7 @@ Done:
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
@ -229,33 +264,32 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
vu_long *addr = (vu_long *) (info->start[sect]);
DEBUGF ("Erase sect %d @ 0x%08lX\n",
sect, (ulong)addr);
sect, (ulong) addr);
/* Disable interrupts which might cause a timeout
* here.
*/
flag = disable_interrupts();
flag = disable_interrupts ();
addr[0] = 0x00500050; /* clear status register */
addr[0] = 0x00200020; /* erase setup */
@ -267,23 +301,23 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((addr[0] & 0x00800080) != 0x00800080) ||
((addr[1] & 0x00800080) != 0x00800080) ) {
if ((now=get_timer(start)) >
CFG_FLASH_ERASE_TOUT) {
((addr[1] & 0x00800080) != 0x00800080)) {
if ((now = get_timer (start)) >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
addr[0] = 0x00B000B0; /* suspend erase */
addr[0] = 0x00FF00FF; /* to read mode */
addr[0] = 0x00B000B0; /* suspend erase */
addr[0] = 0x00FF00FF; /* to read mode */
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
@ -306,7 +340,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
#define FLASH_WIDTH 8 /* flash bus width in bytes */
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, cp, msr;
int l, rc, i;
@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
ulong *datal = &data[1];
DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
addr, (ulong)src, cnt);
addr, (ulong) src, cnt);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
msr = get_msr();
set_msr(msr | MSR_FP);
msr = get_msr ();
set_msr (msr | MSR_FP);
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
/*
* handle unaligned start bytes
@ -335,39 +369,35 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
for (i = 0, cp = wp; i < l; i++, cp++) {
if (i >= 4) {
*datah = (*datah << 8) |
((*datal & 0xFF000000) >> 24);
((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | (*(uchar *)cp);
*datal = (*datal << 8) | (*(uchar *) cp);
}
for (; i < FLASH_WIDTH && cnt > 0; ++i) {
char tmp;
tmp = *src;
src++;
char tmp = *src++;
if (i >= 4) {
*datah = (*datah << 8) |
((*datal & 0xFF000000) >> 24);
((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | tmp;
--cnt; ++cp;
--cnt;
++cp;
}
for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) |
((*datal & 0xFF000000) >> 24);
((*datal & 0xFF000000) >> 24);
}
*datal = (*datah << 8) | (*(uchar *)cp);
*datal = (*datah << 8) | (*(uchar *) cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
set_msr(msr);
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
@ -378,19 +408,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
*datah = *(ulong *)src;
*datal = *(ulong *)(src + 4);
if ((rc = write_data(info, wp, data)) != 0) {
set_msr(msr);
*datah = *(ulong *) src;
*datal = *(ulong *) (src + 4);
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
wp += FLASH_WIDTH;
wp += FLASH_WIDTH;
cnt -= FLASH_WIDTH;
src += FLASH_WIDTH;
}
if (cnt == 0) {
set_msr(msr);
set_msr (msr);
return (0);
}
@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
*datah = *datal = 0;
for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
char tmp;
tmp = *src;
src++;
char tmp = *src++;
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
24);
}
*datal = (*datal << 8) | tmp;
--cnt;
}
for (; i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
24);
}
*datal = (*datal << 8) | (*(uchar *)cp);
*datal = (*datal << 8) | (*(uchar *) cp);
}
rc = write_data(info, wp, data);
set_msr(msr);
rc = write_data (info, wp, data);
set_msr (msr);
return (rc);
}
@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, ulong *data)
static int write_data (flash_info_t * info, ulong dest, ulong * data)
{
vu_long *addr = (vu_long *)dest;
vu_long *addr = (vu_long *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if (((addr[0] & data[0]) != data[0]) ||
((addr[1] & data[1]) != data[1]) ) {
((addr[1] & data[1]) != data[1])) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
addr[0] = 0x00400040; /* write setup */
write_via_fpu(addr, data);
addr[0] = 0x00400040; /* write setup */
write_via_fpu (addr, data);
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
start = get_timer (0);
while (((addr[0] & 0x00800080) != 0x00800080) ||
((addr[1] & 0x00800080) != 0x00800080) ) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
((addr[1] & 0x00800080) != 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
addr[0] = 0x00FF00FF; /* restore read mode */
return (1);
}
@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)
/*-----------------------------------------------------------------------
*/
static void write_via_fpu(vu_long *addr, ulong *data)
static void write_via_fpu (vu_long * addr, ulong * data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
}
/*-----------------------------------------------------------------------
*/
static __inline__ unsigned long get_msr(void)
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
unsigned long msr;
__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
return msr;
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
static __inline__ void set_msr (unsigned long msr)
{
__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
}

2
board/lpd7a40x/flash.c
View File

@ -300,7 +300,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
do {
ulong now;
/* check timeout */
//if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
/*if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { */
if ((now = get_timer(tstart)) > CFG_FLASH_ERASE_TOUT) {
printf("tstart = 0x%08lx, now = 0x%08lx\n", tstart, now);
*addr = CMD_STATUS_RESET;

48
board/mx1ads/Makefile
View File

@ -1,28 +1,26 @@
#/*
#* board/mx1ads/Makefile
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/Makefile
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk

49
board/mx1ads/config.mk
View File

@ -1,28 +1,25 @@
#/*
#* board/mx1ads/config.mk
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/config.mk
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
TEXT_BASE = 0x08400000

9
board/mx1ads/memsetup.S
View File

@ -1,6 +1,6 @@
/*
* board/mx1ads/memsetup.S
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@ -49,7 +49,7 @@ memsetup:
/* Issue Precharge All Commad */
ldr r3, =0x8200000
ldr r2, [r3]
/* Set AutoRefresh Command */
ldr r3, =0xA2120200
str r3, [r1]
@ -64,11 +64,11 @@ memsetup:
ldr r2, [r3]
ldr r2, [r3]
ldr r2, [r3]
/* Set Mode Register */
ldr r3, =0xB2120200
str r3, [r1]
/* Issue Mode Register Command */
ldr r3, =0x08111800 /* Mode Register Value */
ldr r2, [r3]
@ -79,4 +79,3 @@ memsetup:
/* everything is fine now */
mov pc, lr

41
board/mx1ads/mx1ads.c
View File

@ -1,6 +1,6 @@
/*
* board/mx1ads/mx1ads.c
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@ -61,7 +61,7 @@ static inline void delay (unsigned long loops) {
"bne 1b":"=r" (loops):"0" (loops));
}
#endif
#endif
/*
* Miscellaneous platform dependent initialisations
@ -76,7 +76,7 @@ void SetAsynchMode(void) {
"mcr p15,0,r0,c1,c0,0 \n"
);
}
static u32 mc9328sid;
int board_init (void) {
@ -88,16 +88,13 @@ int board_init (void) {
mc9328sid = MX1_SIDR;
MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
@ -108,13 +105,13 @@ int board_init (void) {
MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
MX1_CS4L = 0x00001501;
MX1_GIUS_A &= 0xFF3FFFFF;
MX1_GPR_A &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
@ -135,9 +132,9 @@ int board_init (void) {
/* set PERCLKs */
MX1_PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
MX1_INTTYPEH = 0;
@ -154,24 +151,24 @@ int board_late_init(void) {
switch (mc9328sid) {
case 0x0005901d :
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x04d4c01d :
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x00d4c01d :
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
default :
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
}
return 0;
}
}
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;

46
board/mx1ads/syncflash.c
View File

@ -1,6 +1,6 @@
/*
* board/mx1ads/syncflash.c
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@ -61,7 +61,7 @@ u32 SF_SR(void) {
reg_SFCTL = CMD_PROGRAM;
tmp = __REG(CFG_FLASH_BASE);
reg_SFCTL = CMD_NORMAL;
reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
@ -97,7 +97,7 @@ void SF_PrechargeAll(void) {
u32 tmp;
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
}
@ -105,7 +105,7 @@ void SF_PrechargeAll(void) {
void SF_Normal(void) {
SF_PrechargeAll();
reg_SFCTL = CMD_NORMAL;
}
@ -118,10 +118,10 @@ void SF_Erase(u32 RowAddress) {
reg_SFCTL = CMD_PREC;
tmp = __REG(RowAddress);
reg_SFCTL = CMD_LCR; /* Set LCR mode */
__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
@ -134,7 +134,7 @@ void SF_NvmodeErase(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
@ -146,7 +146,7 @@ void SF_NvmodeWrite(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
@ -168,11 +168,11 @@ ulong flash_init(void) {
tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
SF_Normal();
i = 0;
flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
@ -181,7 +181,7 @@ ulong flash_init(void) {
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
}
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1,
@ -208,8 +208,8 @@ void flash_print_info (flash_info_t *info) {
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
@ -226,13 +226,13 @@ void flash_print_info (flash_info_t *info) {
printf(" Sector Start Addresses: ");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0)
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
}
@ -248,19 +248,19 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last))
if ((s_first < 0) || (s_first > s_last))
return ERR_INVAL;
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
if (info->protect[sect])
prot++;
}
if (prot) {
printf("protected!\n");
return ERR_PROTECTED;
@ -279,7 +279,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
@ -307,8 +307,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
@ -316,7 +314,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
int i;
for(i = 0; i < cnt; i += 4) {
for(i = 0; i < cnt; i += 4) {
SF_PrechargeAll();
@ -327,6 +325,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
}
SF_Normal();
return ERR_OK;
}

2
board/mx1ads/u-boot.lds
View File

@ -1,6 +1,6 @@
/*
* board/mx1ads/u-boot.lds
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/

25
board/pm520/flash.c
View File

@ -83,12 +83,18 @@ unsigned long flash_init (void)
{
int i;
ulong size = 0;
extern void flash_preinit(void);
extern void flash_afterinit(ulong, ulong);
ulong flashbase = CFG_FLASH_BASE;
flash_preinit();
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
memset(&flash_info[i], 0, sizeof(flash_info_t));
flash_get_size ((FPW *) flashbase, &flash_info[i]);
flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
@ -99,14 +105,22 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#ifndef CONFIG_BOOT_ROM
flash_protect ( FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0] );
#endif
#endif
#ifdef CFG_ENV_IS_IN_FLASH
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
#endif
flash_afterinit(flash_info[0].start[0], flash_info[0].size);
return size;
}
@ -195,6 +209,8 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
addr[0x5555] = (FPW) 0x00900090;
mb ();
udelay(100);
value = addr[0];
switch (value) {
@ -220,18 +236,21 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
info->start[0] = CFG_FLASH_BASE;
break; /* => 32 MB */
case (FPW) INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
info->start[0] = CFG_FLASH_BASE + 0x01000000;
break; /* => 16 MB */
case (FPW) INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
info->size = 0x00800000;
info->size = 0x800000;
info->start[0] = CFG_FLASH_BASE + 0x01800000;
break; /* => 8 MB */
default:

37
board/pm520/mt46v16m16-75.h Normal file
View File

@ -0,0 +1,37 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

43
board/pm520/mt48lc16m16a2-75.h Normal file
View File

@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

298
board/pm520/pm520.c
View File

@ -2,6 +2,9 @@
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -25,127 +28,209 @@
#include <mpc5xxx.h>
#include <pci.h>
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif
#ifndef CFG_RAMBOOT
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
/* set mode register */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
return dramsize + dramsize2;
}
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* configure SDRAM start/end */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
#elif defined(CONFIG_MGT5100)
/* setup and enable SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
/* address select register */
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
#endif
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
__asm__ volatile ("sync");
/* find RAM size */
sdram_start(0);
test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
(0x13 + __builtin_ffs(dramsize >> 20) - 1);
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
#endif
#else
#ifdef CONFIG_MGT5100
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
/* set SDRAM end address according to size */
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
#else /* CFG_RAMBOOT */
/* Retrieve amount of SDRAM available */
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
#else
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
#endif
#endif /* CFG_RAMBOOT */
/* return total ram size */
return dramsize;
}
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif
int checkboard (void)
{
#if defined(CONFIG_MPC5200)
@ -171,14 +256,32 @@ void flash_preinit(void)
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
void flash_afterinit(ulong size)
void flash_afterinit(ulong start, ulong size)
{
if (size == 0x800000) { /* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
#if defined(CONFIG_BOOT_ROM)
/* adjust mapping */
*(vu_long *)MPC5XXX_CS1_START =
START_REG(start);
*(vu_long *)MPC5XXX_CS1_STOP =
STOP_REG(start, size);
#else
/* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(start);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(start, size);
#endif
}
extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* adjust flash start */
gd->bd->bi_flashstart = flash_info[0].start[0];
return (0);
}
#ifdef CONFIG_PCI
@ -191,3 +294,26 @@ void pci_init_board(void)
pci_mpc5xxx_init(&hose);
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

2
common/env_nand.c
View File

@ -78,7 +78,7 @@ char * env_name_spec = "NAND";
extern uchar environment[];
env_t *env_ptr = (env_t *)(&environment[0]);
#else /* ! ENV_IS_EMBEDDED */
env_t *env_ptr = 0; //(env_t *)CFG_ENV_ADDR;
env_t *env_ptr = 0;
#endif /* ENV_IS_EMBEDDED */

2
cpu/mc9328/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
OBJS = serial.o interrupts.o cpu.o
OBJS = serial.o interrupts.o cpu.o
all: .depend $(START) $(LIB)

3
cpu/mc9328/interrupts.c
View File

@ -243,8 +243,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk (void) {
return CFG_HZ;
}

27
cpu/mc9328/serial.c
View File

@ -1,6 +1,6 @@
/*
* cpu/mc9328/serial.c
*
* cpu/mc9328/serial.c
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@ -23,11 +23,10 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <mc9328.h>
#if defined(CONFIG_UART1)
#if defined(CONFIG_UART1)
/* GPIO PORT B */
#define reg_GIUS MX1_GIUS_C
@ -35,7 +34,6 @@
#define GPIO_MASK 0xFFFFE1FF
#define UART_BASE 0x00206000
#elif defined (CONFIG_UART2)
/* GPIO PORT C */
@ -44,7 +42,7 @@
#define GPIO_MASK 0x0FFFFFFF
#define UART_BASE 0x207000
#endif
#endif
#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
@ -64,16 +62,13 @@
#define TXFE_MASK 0x4000 /* Tx buffer empty */
#define RDR_MASK 0x0001 /* receive data ready */
void serial_setbrg (void) {
/* config I/O pins for UART */
/* config I/O pins for UART */
reg_GIUS &= GPIO_MASK;
reg_GPR &= GPIO_MASK;
/* config UART */
/* config UART */
reg_UCR1 = 5;
reg_UCR2 = 0x4027;
reg_UCR4 = 1;
@ -84,22 +79,18 @@ void serial_setbrg (void) {
reg_UBRC = 8;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void) {
serial_setbrg ();
return (0);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
@ -112,7 +103,6 @@ int serial_getc (void) {
return (u8)reg_URXD;
}
/*
* Output a single byte to the serial port.
*/
@ -129,7 +119,6 @@ void serial_putc (const char c) {
}
/*
* Test whether a character is in the RX buffer
*/
@ -137,10 +126,8 @@ int serial_tstc (void) {
return reg_USR2 & RDR_MASK;
}
void serial_puts (const char *s) {
while (*s) {
serial_putc (*s++);
}
}

404
include/configs/CPC45.h
View File

@ -59,10 +59,13 @@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_PCI | \
0 /* CFG_CMD_DATE */ )
CFG_CMD_SDRAM )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
@ -77,17 +80,17 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#if 1
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* Print Buffer Size
*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
@ -97,29 +100,29 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE 0x00000000
#if defined(CONFIG_BOOT_ROM)
#define CFG_FLASH_BASE 0xFF000000
#define CFG_FLASH_BASE 0xFF000000
#else
#define CFG_FLASH_BASE 0xFF800000
#define CFG_FLASH_BASE 0xFF800000
#endif
#define CFG_RESET_ADDRESS 0xFFF00100
#define CFG_RESET_ADDRESS 0xFFF00100
#define CFG_EUMB_ADDR 0xFCE00000
#define CFG_EUMB_ADDR 0xFCE00000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
/* Maximum amount of RAM.
*/
#define CFG_MAX_RAM_SIZE 0x10000000
/* Maximum amount of RAM.
*/
#define CFG_MAX_RAM_SIZE 0x10000000
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
@ -133,13 +136,13 @@
* Definitions for initial stack pointer and data area
*/
/* Size in bytes reserved for initial data
*/
#define CFG_GBL_DATA_SIZE 128
/* Size in bytes reserved for initial data
*/
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* NS16550 Configuration
@ -153,7 +156,30 @@
#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*
* Low Level Configuration Settings
@ -162,62 +188,49 @@
* For the detail description refer to the MPC8240 user's manual.
*/
#define CONFIG_SYS_CLK_FREQ 33000000
#define CFG_HZ 1000
/*
* SDRAM Configuration Settings
* Please note: currently only 64 and 128 MB SDRAM size supported
* set CFG_SDRAM_SIZE to 64 or 128
* Memory configuration using SPD information stored on the SODIMMs
* not yet supported.
#define CONFIG_SYS_CLK_FREQ 33000000
#define CFG_HZ 1000
/* Bit-field values for MCCR1.
*/
#define CFG_ROMNAL 0
#define CFG_ROMFAL 8
#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
#define CFG_BANK1_ROW 0
#define CFG_BANK2_ROW 0
#define CFG_BANK3_ROW 0
#define CFG_BANK4_ROW 0
#define CFG_BANK5_ROW 0
#define CFG_BANK6_ROW 0
#define CFG_BANK7_ROW 0
/* Bit-field values for MCCR2.
*/
#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
#define CFG_REFINT 0x2ec
/* Bit-field values for MCCR1.
*/
#define CFG_ROMNAL 0
#define CFG_ROMFAL 7
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
*/
#define CFG_BSTOPRE 160
#if (CFG_SDRAM_SIZE == 64) /* 64 MB */
#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */
#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
#else
# error "SDRAM size not supported"
#endif
#define CFG_BANK1_ROW 0
#define CFG_BANK2_ROW 0
#define CFG_BANK3_ROW 0
#define CFG_BANK4_ROW 0
#define CFG_BANK5_ROW 0
#define CFG_BANK6_ROW 0
#define CFG_BANK7_ROW 0
/* Bit-field values for MCCR3.
*/
#define CFG_REFREC 2 /* Refresh to activate interval */
#define CFG_RDLAT 0 /* Data latancy from read command */
/* Bit-field values for MCCR2.
*/
#define CFG_REFINT 430 /* Refresh interval */
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
*/
#define CFG_BSTOPRE 192
/* Bit-field values for MCCR3.
*/
#define CFG_REFREC 2 /* Refresh to activate interval */
#define CFG_RDLAT 3 /* Data latancy from read command */
/* Bit-field values for MCCR4.
*/
#define CFG_PRETOACT 2 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
#define CFG_ACTORW 2
/* Bit-field values for MCCR4.
*/
#define CFG_PRETOACT 2 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
#define CFG_ACTORW 2
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
#define CFG_EXTROM 0
#define CFG_REGDIMM 0
/* Memory bank settings.
* Only bits 20-29 are actually used from these vales to set the
@ -226,32 +239,35 @@
* address. Refer to the MPC8240 book.
*/
#define CFG_BANK0_START 0x00000000
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x3ff00000
#define CFG_BANK1_END 0x3fffffff
#define CFG_BANK1_ENABLE 0
#define CFG_BANK2_START 0x3ff00000
#define CFG_BANK2_END 0x3fffffff
#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x3ff00000
#define CFG_BANK3_END 0x3fffffff
#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x3ff00000
#define CFG_BANK4_END 0x3fffffff
#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x3ff00000
#define CFG_BANK5_END 0x3fffffff
#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x3ff00000
#define CFG_BANK6_END 0x3fffffff
#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x3ff00000
#define CFG_BANK7_END 0x3fffffff
#define CFG_BANK7_ENABLE 0
#define CFG_BANK0_START 0x00000000
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x3ff00000
#define CFG_BANK1_END 0x3fffffff
#define CFG_BANK1_ENABLE 0
#define CFG_BANK2_START 0x3ff00000
#define CFG_BANK2_END 0x3fffffff
#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x3ff00000
#define CFG_BANK3_END 0x3fffffff
#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x3ff00000
#define CFG_BANK4_END 0x3fffffff
#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x3ff00000
#define CFG_BANK5_END 0x3fffffff
#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x3ff00000
#define CFG_BANK6_END 0x3fffffff
#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x3ff00000
#define CFG_BANK7_END 0x3fffffff
#define CFG_BANK7_ENABLE 0
#define CFG_ODCR 0xff
#define CFG_ODCR 0xff
#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
/* currently accessed page in memory */
/* see 8240 book for details */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@ -279,7 +295,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
@ -295,7 +311,7 @@
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
@ -317,118 +333,118 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define SRAM_END 0x801FFFFF
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define SRAM_END 0x801FFFFF
/*---------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*---------------------------------------------------------------------*/
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
#define BCSR_BASE 0x80600000 /* board control / status registers */
#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
/*----------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*----------------------------------------------------------------------*/
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
#define BCSR_BASE 0x80600000 /* board control / status registers */
#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers */
/* CPC45 Control/Status Registers */
/*---------------------------------------------------------------------*/
#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
/* IRQ_ENA_1 bit definitions */
#define I_ENA_1_IERA 0x80 /* INTA enable */
#define I_ENA_1_IERB 0x40 /* INTB enable */
#define I_ENA_1_IERC 0x20 /* INTC enable */
#define I_ENA_1_IERD 0x10 /* INTD enable */
#define I_ENA_1_IERA 0x80 /* INTA enable */
#define I_ENA_1_IERB 0x40 /* INTB enable */
#define I_ENA_1_IERC 0x20 /* INTC enable */
#define I_ENA_1_IERD 0x10 /* INTD enable */
/* IRQ_STAT_1 bit definitions */
#define I_STAT_1_INTA 0x80 /* INTA status */
#define I_STAT_1_INTB 0x40 /* INTB status */
#define I_STAT_1_INTC 0x20 /* INTC status */
#define I_STAT_1_INTD 0x10 /* INTD status */
#define I_STAT_1_INTA 0x80 /* INTA status */
#define I_STAT_1_INTB 0x40 /* INTB status */
#define I_STAT_1_INTC 0x20 /* INTC status */
#define I_STAT_1_INTD 0x10 /* INTD status */
/* IRQ_ENA_2 bit definitions */
#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
/* IRQ_STAT_2 bit definitions */
#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
/* BOARD_CTRL bit definitions */
#define USER_LEDS 2 /* 2 user LEDs */
#define USER_LEDS 2 /* 2 user LEDs */
#if (USER_LEDS == 4)
#define B_CTRL_WRSE 0x80
#define B_CTRL_KRSE 0x40
#define B_CTRL_FWRE 0x20 /* Flash write enable */
#define B_CTRL_FWPT 0x10 /* Flash write protect */
#define B_CTRL_LED3 0x08 /* LED 3 control */
#define B_CTRL_LED2 0x04 /* LED 2 control */
#define B_CTRL_LED1 0x02 /* LED 1 control */
#define B_CTRL_LED0 0x01 /* LED 0 control */
#define B_CTRL_WRSE 0x80
#define B_CTRL_KRSE 0x40
#define B_CTRL_FWRE 0x20 /* Flash write enable */
#define B_CTRL_FWPT 0x10 /* Flash write protect */
#define B_CTRL_LED3 0x08 /* LED 3 control */
#define B_CTRL_LED2 0x04 /* LED 2 control */
#define B_CTRL_LED1 0x02 /* LED 1 control */
#define B_CTRL_LED0 0x01 /* LED 0 control */
#else
#define B_CTRL_WRSE 0x80
#define B_CTRL_KRSE 0x40
#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
#define B_CTRL_LED1 0x08 /* LED 1 control */
#define B_CTRL_LED0 0x04 /* LED 0 control */
#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
#define B_CTRL_WRSE 0x80
#define B_CTRL_KRSE 0x40
#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
#define B_CTRL_LED1 0x08 /* LED 1 control */
#define B_CTRL_LED0 0x04 /* LED 0 control */
#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
#endif
/* BOARD_STAT bit definitions */
#define B_STAT_WDGE 0x80
#define B_STAT_WDGS 0x40
#define B_STAT_WRST 0x20
#define B_STAT_KRST 0x10
#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
#define B_STAT_WDGE 0x80
#define B_STAT_WDGS 0x40
#define B_STAT_WRST 0x20
#define B_STAT_KRST 0x10
#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
/*---------------------------------------------------------------------*/
/* Display addresses */
/* Display addresses */
/*---------------------------------------------------------------------*/
#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
/*-----------------------------------------------------------------------
@ -436,14 +452,16 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define PCI_ENET0_IOADDR 0x00104000
#define PCI_ENET0_IOADDR 0x82000000
#define PCI_ENET0_MEMADDR 0x82000000
#define PCI_PLX9030_MEMADDR 0x82100000
#define PCI_PLX9030_IOADDR 0x82100000
#define PCI_PLX9030_MEMADDR 0x82100000
#endif /* __CONFIG_H */

154
include/configs/PM520.h
View File

@ -35,6 +35,8 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
@ -82,11 +84,37 @@
#endif
/* Partitions */
#define CONFIG_DOS_PARTITION
/* USB */
#if 1
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD 0
#endif
#if defined(CONFIG_BOOT_ROM)
#define ADD_DOC_CMD 0
#else
#define ADD_DOC_CMD CFG_CMD_DOC
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
ADD_DOC_CMD | \
ADD_PCI_CMD | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
ADD_USB_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -95,8 +123,32 @@
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pm520\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk30/ppc_82xx\0" \
"bootfile=/tftpboot/PM520/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if defined(CONFIG_MPC5200)
/*
@ -128,11 +180,44 @@
#define CFG_I2C_RTC_ADDR 0x51
/*
* Flash configuration
* Disk-On-Chip configuration
*/
#define CFG_FLASH_BASE 0xff800000
#define CFG_FLASH_SIZE 0x00800000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#define CFG_DOC_BASE 0xE0000000
#define CFG_DOC_SIZE 0x00100000
#if defined(CONFIG_BOOT_ROM)
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 32 MB
* 0xFD000000 for 16 MB
* 0xFD800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfc000000
#define CFG_FLASH_SIZE 0x02000000
#define CFG_BOOTROM_BASE 0xFFF00000
#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
#else
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfe000000
#define CFG_FLASH_SIZE 0x02000000
#define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
#endif
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
@ -228,15 +313,68 @@
#define CFG_HID0_FINAL 0
#endif
#if defined(CONFIG_BOOT_ROM)
#define CFG_BOOTCS_START CFG_BOOTROM_BASE
#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
#define CFG_BOOTCS_CFG 0x00047800
#define CFG_CS0_START CFG_BOOTROM_BASE
#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
#define CFG_CS1_START CFG_FLASH_BASE
#define CFG_CS1_SIZE CFG_FLASH_SIZE
#define CFG_CS1_CFG 0x0004fb00
#else
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x0004fb00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS1_START CFG_DOC_BASE
#define CFG_CS1_SIZE CFG_DOC_SIZE
#define CFG_CS1_CFG 0x00047800
#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */

2
include/configs/RPXlite_DW.h
View File

@ -178,8 +178,6 @@
#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/

2
include/configs/Sandpoint8245.h
View File

@ -229,7 +229,7 @@
#else
#define CFG_NS16550_CLK 1843200
#endif
#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)

24
include/configs/mx1ads.h
View File

@ -1,6 +1,6 @@
/*
* include/configs/mx1ads.h
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@ -43,17 +43,17 @@
#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
#define BOARD_LATE_INIT 1
#define BOARD_LATE_INIT 1
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#if 0
#if 0
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
#endif
#endif
/*
* Size of malloc() pool
@ -73,7 +73,7 @@
* select serial console configuration
*/
#define CONFIG_UART1 1
#define CONFIG_UART1 1
/* #define CONFIG_UART2 1 */
#define CONFIG_BAUDRATE 115200
@ -90,13 +90,13 @@
/*CFG_CMD_I2C |*/ \
/*CFG_CMD_USB |*/ \
CFG_CMD_REGINFO | \
CFG_CMD_ELF)
CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.22
@ -113,10 +113,10 @@
/*
* Miscellaneous configurable options
*/
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CFG_HUSH_PARSER
@ -126,7 +126,7 @@
#endif
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@ -158,7 +158,7 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
@ -178,7 +178,7 @@
#define PHYS_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_SECT (16)
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x100000

1386
include/mc9328.h
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