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Patch by Josef Wagner, 04 Jun 2004: 

- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45
This commit is contained in:
wdenk 2004-06-19 21:19:10 +00:00
parent 46a414dc12
commit 49822e23a0
26 changed files with 1714 additions and 1390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
CHANGELOG
View File

@ -2,6 +2,15 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Josef Wagner, 04 Jun 2004:
- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45
* Fix flash parameters passed to Linux for PPChameleon board
* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.

16
Makefile
View File

@ -255,8 +255,20 @@ TOP5200_config: unconfig
@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
PM520_config: unconfig
@./mkconfig $(@:_config=) ppc mpc5xxx pm520
PM520_config \
PM520_DDR_config \
PM520_ROMBOOT_config \
PM520_ROMBOOT_DDR_config: unconfig
@ >include/config.h
@[ -z "$(findstring DDR,$@)" ] || \
{ echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \
echo "... DDR memory revision" ; \
}
@[ -z "$(findstring ROMBOOT,$@)" ] || \
{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
echo "... booting from 8-bit flash" ; \
}
@./mkconfig -a PM520 ppc mpc5xxx pm520
#########################################################################
## MPC8xx Systems

142
board/cpc45/cpc45.c
View File

@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <asm/processor.h>
#include <pci.h>
#include <i2c.h>
int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
@ -58,46 +59,134 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
long int initdram (int board_type)
{
long size;
long new_bank0_end;
long mear1;
long emear1;
int m, row, col, bank, i, ref;
unsigned long start, end;
uint32_t mccr1, mccr2;
uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
uint8_t mber = 0;
unsigned int tmp;
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
if (i2c_reg_read (0x50, 2) != 0x04)
return 0; /* Memory type */
return (size);
m = i2c_reg_read (0x50, 5); /* # of physical banks */
row = i2c_reg_read (0x50, 3); /* # of rows */
col = i2c_reg_read (0x50, 4); /* # of columns */
bank = i2c_reg_read (0x50, 17); /* # of logical banks */
ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
CONFIG_READ_WORD(MCCR2, mccr2);
mccr2 &= 0xffff0000;
start = CFG_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
if (i < 4) {
msar1 |= ((start >> 20) & 0xff) << i * 8;
emsar1 |= ((start >> 28) & 0xff) << i * 8;
mear1 |= ((end >> 20) & 0xff) << i * 8;
emear1 |= ((end >> 28) & 0xff) << i * 8;
} else {
msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
}
mber |= 1 << i;
start += (1 << (col + row + 3) ) * bank;
end += (1 << (col + row + 3) ) * bank;
}
for (; i < 8; i++) {
if (i < 4) {
msar1 |= 0xff << i * 8;
emsar1 |= 0x30 << i * 8;
mear1 |= 0xff << i * 8;
emear1 |= 0x30 << i * 8;
} else {
msar2 |= 0xff << (i-4) * 8;
emsar2 |= 0x30 << (i-4) * 8;
mear2 |= 0xff << (i-4) * 8;
emear2 |= 0x30 << (i-4) * 8;
}
}
switch(ref) {
case 0x00:
case 0x80:
tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
break;
case 0x01:
case 0x81:
tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
break;
case 0x02:
case 0x82:
tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
break;
case 0x03:
case 0x83:
tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
break;
case 0x04:
case 0x84:
tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
break;
case 0x05:
case 0x85:
tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
break;
default:
tmp = 0x512;
break;
}
CONFIG_WRITE_WORD(MCCR1, mccr1);
CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
CONFIG_WRITE_WORD(MSAR1, msar1);
CONFIG_WRITE_WORD(EMSAR1, emsar1);
CONFIG_WRITE_WORD(MEAR1, mear1);
CONFIG_WRITE_WORD(EMEAR1, emear1);
CONFIG_WRITE_WORD(MSAR2, msar2);
CONFIG_WRITE_WORD(EMSAR2, emsar2);
CONFIG_WRITE_WORD(MEAR2, mear2);
CONFIG_WRITE_WORD(EMEAR2, emear2);
CONFIG_WRITE_BYTE(MBER, mber);
return (1 << (col + row + 3) ) * bank * m;
}
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_sandpoint_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
static struct pci_config_table pci_cpc45_config_table[] = {
#ifndef CONFIG_PCI_PNP
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
PCI_PLX9030_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
#endif /*CONFIG_PCI_PNP*/
{ }
};
#endif
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_sandpoint_config_table,
config_table: pci_cpc45_config_table,
#endif
};
@ -108,6 +197,9 @@ void pci_init_board(void)
/* init PCI_to_LOCAL Bus BRIDGE */
Plx9030Init();
/* Clear Display */
DISP_CWORD = 0x0;
sysControlDisplay(0,' ');
sysControlDisplay(1,'C');
sysControlDisplay(2,'P');
@ -130,16 +222,14 @@ void pci_init_board(void)
* RETURNS: NA
*/
int sysControlDisplay
(
int digit, /* number of digit 0..7 */
int sysControlDisplay (int digit, /* number of digit 0..7 */
uchar ascii_code /* ASCII code */
)
{
if ((digit < 0) || (digit > 7))
return (-1);
*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
return (0);
}

191
board/cpc45/flash.c
View File

@ -43,10 +43,10 @@
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
static int write_data (flash_info_t *info, ulong dest, ulong *data);
static void write_via_fpu(vu_long *addr, ulong *data);
static __inline__ unsigned long get_msr(void);
static __inline__ void set_msr(unsigned long msr);
static int write_data (flash_info_t * info, ulong dest, ulong * data);
static void write_via_fpu (vu_long * addr, ulong * data);
static __inline__ unsigned long get_msr (void);
static __inline__ void set_msr (unsigned long msr);
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
@ -62,11 +62,12 @@ static __inline__ void set_msr(unsigned long msr);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
uchar tempChar;
vu_long *tmpaddr;
/* Enable flash writes on CPC45 */
@ -78,27 +79,40 @@ unsigned long flash_init(void)
BOARD_CTRL = tempChar;
__asm__ volatile ("sync\n eieio");
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
addr[0] = 0x00900090;
__asm__ volatile ("sync\n eieio");
udelay (100);
DEBUGF ("Flash bank # %d:\n"
"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
"\tDevice ID @ 0x%08lX: 0x%08lX\n",
i,
(ulong)(&addr[0]), addr[0],
(ulong)(&addr[2]), addr[2]);
(ulong) (&addr[0]), addr[0],
(ulong) (&addr[2]), addr[2]);
if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
{
(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
flash_info[i].flash_id =
(FLASH_MAN_INTEL & FLASH_VENDMASK) |
(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
&& (addr[2] == addr[3])
&& (addr[2] == INTEL_ID_28F160C3T)) {
flash_info[i].flash_id =
(FLASH_MAN_INTEL & FLASH_VENDMASK) |
(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
} else {
flash_info[i].flash_id = FLASH_UNKNOWN;
addr[0] = 0xFFFFFFFF;
@ -111,48 +125,64 @@ unsigned long flash_init(void)
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j > 30) {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
(MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
(MAIN_SECT_SIZE * 31) + (j -
31) *
PARAM_SECT_SIZE;
} else {
flash_info[i].start[j] = CFG_FLASH_BASE +
i * FLASH_BANK_SIZE +
j * MAIN_SECT_SIZE;
}
}
/* unlock sectors, if 160C3T */
for (j = 0; j < flash_info[i].sector_count; j++) {
tmpaddr = (vu_long *) flash_info[i].start[j];
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
tmpaddr[0] = 0x00600060;
tmpaddr[0] = 0x00D000D0;
tmpaddr[1] = 0x00600060;
tmpaddr[1] = 0x00D000D0;
}
}
size += flash_info[i].size;
addr[0] = 0x00FF00FF;
addr[1] = 0x00FF00FF;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect(FLAG_PROTECT_SET,
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[1]);
#else
flash_protect(FLAG_PROTECT_SET,
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
flash_protect(FLAG_PROTECT_SET,
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[1]);
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
#else
flash_protect(FLAG_PROTECT_SET,
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
#endif
@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
printf ("28F160F3T (16Mbit)\n");
break;
case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
printf ("28F160C3T (16Mbit)\n");
break;
default:
printf ("Unknown Chip Type 0x%04x\n", i);
goto Done;
@ -205,7 +240,7 @@ Done:
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
@ -229,15 +264,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -245,17 +279,17 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
start = get_timer (0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
vu_long *addr = (vu_long *) (info->start[sect]);
DEBUGF ("Erase sect %d @ 0x%08lX\n",
sect, (ulong)addr);
sect, (ulong) addr);
/* Disable interrupts which might cause a timeout
* here.
*/
flag = disable_interrupts();
flag = disable_interrupts ();
addr[0] = 0x00500050; /* clear status register */
addr[0] = 0x00200020; /* erase setup */
@ -267,14 +301,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((addr[0] & 0x00800080) != 0x00800080) ||
((addr[1] & 0x00800080) != 0x00800080) ) {
if ((now=get_timer(start)) >
((addr[1] & 0x00800080) != 0x00800080)) {
if ((now = get_timer (start)) >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
addr[0] = 0x00B000B0; /* suspend erase */
@ -306,7 +340,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
#define FLASH_WIDTH 8 /* flash bus width in bytes */
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, cp, msr;
int l, rc, i;
@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
ulong *datal = &data[1];
DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
addr, (ulong)src, cnt);
addr, (ulong) src, cnt);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
msr = get_msr();
set_msr(msr | MSR_FP);
msr = get_msr ();
set_msr (msr | MSR_FP);
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
/*
* handle unaligned start bytes
@ -338,14 +372,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | (*(uchar *)cp);
*datal = (*datal << 8) | (*(uchar *) cp);
}
for (; i < FLASH_WIDTH && cnt > 0; ++i) {
char tmp;
tmp = *src;
src++;
char tmp = *src++;
if (i >= 4) {
*datah = (*datah << 8) |
@ -353,8 +383,8 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
}
*datal = (*datal << 8) | tmp;
--cnt; ++cp;
--cnt;
++cp;
}
for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
@ -363,11 +393,11 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
((*datal & 0xFF000000) >> 24);
}
*datal = (*datah << 8) | (*(uchar *)cp);
*datal = (*datah << 8) | (*(uchar *) cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
set_msr(msr);
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
@ -378,10 +408,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
*datah = *(ulong *)src;
*datal = *(ulong *)(src + 4);
if ((rc = write_data(info, wp, data)) != 0) {
set_msr(msr);
*datah = *(ulong *) src;
*datal = *(ulong *) (src + 4);
if ((rc = write_data (info, wp, data)) != 0) {
set_msr (msr);
return (rc);
}
wp += FLASH_WIDTH;
@ -390,7 +420,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
}
if (cnt == 0) {
set_msr(msr);
set_msr (msr);
return (0);
}
@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
*datah = *datal = 0;
for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
char tmp;
tmp = *src;
src++;
char tmp = *src++;
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
24);
}
*datal = (*datal << 8) | tmp;
--cnt;
}
for (; i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
24);
}
*datal = (*datal << 8) | (*(uchar *)cp);
*datal = (*datal << 8) | (*(uchar *) cp);
}
rc = write_data(info, wp, data);
set_msr(msr);
rc = write_data (info, wp, data);
set_msr (msr);
return (rc);
}
@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, ulong *data)
static int write_data (flash_info_t * info, ulong dest, ulong * data)
{
vu_long *addr = (vu_long *)dest;
vu_long *addr = (vu_long *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if (((addr[0] & data[0]) != data[0]) ||
((addr[1] & data[1]) != data[1]) ) {
((addr[1] & data[1]) != data[1])) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
addr[0] = 0x00400040; /* write setup */
write_via_fpu(addr, data);
write_via_fpu (addr, data);
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
start = get_timer (0);
while (((addr[0] & 0x00800080) != 0x00800080) ||
((addr[1] & 0x00800080) != 0x00800080) ) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
((addr[1] & 0x00800080) != 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
addr[0] = 0x00FF00FF; /* restore read mode */
return (1);
}
@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)
/*-----------------------------------------------------------------------
*/
static void write_via_fpu(vu_long *addr, ulong *data)
static void write_via_fpu (vu_long * addr, ulong * data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
}
/*-----------------------------------------------------------------------
*/
static __inline__ unsigned long get_msr(void)
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
static __inline__ void set_msr (unsigned long msr)
{
__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
}

2
board/lpd7a40x/flash.c
View File

@ -300,7 +300,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
do {
ulong now;
/* check timeout */
//if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
/*if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { */
if ((now = get_timer(tstart)) > CFG_FLASH_ERASE_TOUT) {
printf("tstart = 0x%08lx, now = 0x%08lx\n", tstart, now);
*addr = CMD_STATUS_RESET;

48
board/mx1ads/Makefile
View File

@ -1,28 +1,26 @@
#/*
#* board/mx1ads/Makefile
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/Makefile
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk

49
board/mx1ads/config.mk
View File

@ -1,28 +1,25 @@
#/*
#* board/mx1ads/config.mk
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/config.mk
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
TEXT_BASE = 0x08400000

1
board/mx1ads/memsetup.S
View File

@ -79,4 +79,3 @@ memsetup:
/* everything is fine now */
mov pc, lr

5
board/mx1ads/mx1ads.c
View File

@ -92,12 +92,9 @@ int board_init (void) {
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)

2
board/mx1ads/syncflash.c
View File

@ -307,8 +307,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/

25
board/pm520/flash.c
View File

@ -83,12 +83,18 @@ unsigned long flash_init (void)
{
int i;
ulong size = 0;
extern void flash_preinit(void);
extern void flash_afterinit(ulong, ulong);
ulong flashbase = CFG_FLASH_BASE;
flash_preinit();
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
memset(&flash_info[i], 0, sizeof(flash_info_t));
flash_get_size ((FPW *) flashbase, &flash_info[i]);
flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
@ -99,14 +105,22 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#ifndef CONFIG_BOOT_ROM
flash_protect ( FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0] );
#endif
#endif
#ifdef CFG_ENV_IS_IN_FLASH
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
#endif
flash_afterinit(flash_info[0].start[0], flash_info[0].size);
return size;
}
@ -195,6 +209,8 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
addr[0x5555] = (FPW) 0x00900090;
mb ();
udelay(100);
value = addr[0];
switch (value) {
@ -220,18 +236,21 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
info->start[0] = CFG_FLASH_BASE;
break; /* => 32 MB */
case (FPW) INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
info->start[0] = CFG_FLASH_BASE + 0x01000000;
break; /* => 16 MB */
case (FPW) INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
info->size = 0x00800000;
info->size = 0x800000;
info->start[0] = CFG_FLASH_BASE + 0x01800000;
break; /* => 8 MB */
default:

37
board/pm520/mt46v16m16-75.h Normal file
View File

@ -0,0 +1,37 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

43
board/pm520/mt48lc16m16a2-75.h Normal file
View File

@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

294
board/pm520/pm520.c
View File

@ -2,6 +2,9 @@
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -25,127 +28,209 @@
#include <mpc5xxx.h>
#include <pci.h>
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif
#ifndef CFG_RAMBOOT
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
/* set mode register */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
return dramsize + dramsize2;
}
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* configure SDRAM start/end */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
#elif defined(CONFIG_MGT5100)
/* setup and enable SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
/* address select register */
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
#endif
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
__asm__ volatile ("sync");
/* find RAM size */
sdram_start(0);
test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
(0x13 + __builtin_ffs(dramsize >> 20) - 1);
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
#endif
#else
#ifdef CONFIG_MGT5100
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
/* set SDRAM end address according to size */
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
#else /* CFG_RAMBOOT */
/* Retrieve amount of SDRAM available */
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
#else
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
#endif
#endif /* CFG_RAMBOOT */
/* return total ram size */
return dramsize;
}
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif
int checkboard (void)
{
#if defined(CONFIG_MPC5200)
@ -171,14 +256,32 @@ void flash_preinit(void)
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
void flash_afterinit(ulong size)
void flash_afterinit(ulong start, ulong size)
{
if (size == 0x800000) { /* adjust mapping */
#if defined(CONFIG_BOOT_ROM)
/* adjust mapping */
*(vu_long *)MPC5XXX_CS1_START =
START_REG(start);
*(vu_long *)MPC5XXX_CS1_STOP =
STOP_REG(start, size);
#else
/* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
START_REG(start);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
STOP_REG(start, size);
#endif
}
extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* adjust flash start */
gd->bd->bi_flashstart = flash_info[0].start[0];
return (0);
}
#ifdef CONFIG_PCI
@ -191,3 +294,26 @@ void pci_init_board(void)
pci_mpc5xxx_init(&hose);
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

2
common/env_nand.c
View File

@ -78,7 +78,7 @@ char * env_name_spec = "NAND";
extern uchar environment[];
env_t *env_ptr = (env_t *)(&environment[0]);
#else /* ! ENV_IS_EMBEDDED */
env_t *env_ptr = 0; //(env_t *)CFG_ENV_ADDR;
env_t *env_ptr = 0;
#endif /* ENV_IS_EMBEDDED */

1
cpu/mc9328/interrupts.c
View File

@ -247,4 +247,3 @@ unsigned long long get_ticks(void)
ulong get_tbclk (void) {
return CFG_HZ;
}

17
cpu/mc9328/serial.c
View File

@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <mc9328.h>
@ -35,7 +34,6 @@
#define GPIO_MASK 0xFFFFE1FF
#define UART_BASE 0x00206000
#elif defined (CONFIG_UART2)
/* GPIO PORT C */
@ -64,16 +62,13 @@
#define TXFE_MASK 0x4000 /* Tx buffer empty */
#define RDR_MASK 0x0001 /* receive data ready */
void serial_setbrg (void) {
/* config I/O pins for UART */
/* config I/O pins for UART */
reg_GIUS &= GPIO_MASK;
reg_GPR &= GPIO_MASK;
/* config UART */
/* config UART */
reg_UCR1 = 5;
reg_UCR2 = 0x4027;
reg_UCR4 = 1;
@ -84,8 +79,6 @@ void serial_setbrg (void) {
reg_UBRC = 8;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
@ -98,8 +91,6 @@ int serial_init (void) {
return (0);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
@ -112,7 +103,6 @@ int serial_getc (void) {
return (u8)reg_URXD;
}
/*
* Output a single byte to the serial port.
*/
@ -129,7 +119,6 @@ void serial_putc (const char c) {
}
/*
* Test whether a character is in the RX buffer
*/
@ -137,10 +126,8 @@ int serial_tstc (void) {
return reg_USR2 & RDR_MASK;
}
void serial_puts (const char *s) {
while (*s) {
serial_putc (*s++);
}
}

80
include/configs/CPC45.h
View File

@ -60,9 +60,12 @@
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_PCI | \
0 /* CFG_CMD_DATE */ )
CFG_CMD_SDRAM )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
@ -117,7 +120,7 @@
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
/* Maximum amount of RAM.
/* Maximum amount of RAM.
*/
#define CFG_MAX_RAM_SIZE 0x10000000
@ -133,7 +136,7 @@
* Definitions for initial stack pointer and data area
*/
/* Size in bytes reserved for initial data
/* Size in bytes reserved for initial data
*/
#define CFG_GBL_DATA_SIZE 128
@ -155,6 +158,29 @@
#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
@ -164,28 +190,14 @@
#define CONFIG_SYS_CLK_FREQ 33000000
#define CFG_HZ 1000
/*
* SDRAM Configuration Settings
* Please note: currently only 64 and 128 MB SDRAM size supported
* set CFG_SDRAM_SIZE to 64 or 128
* Memory configuration using SPD information stored on the SODIMMs
* not yet supported.
*/
#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
/* Bit-field values for MCCR1.
/* Bit-field values for MCCR1.
*/
#define CFG_ROMNAL 0
#define CFG_ROMFAL 7
#define CFG_ROMFAL 8
#if (CFG_SDRAM_SIZE == 64) /* 64 MB */
#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */
#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
#else
# error "SDRAM size not supported"
#endif
#define CFG_BANK1_ROW 0
#define CFG_BANK2_ROW 0
#define CFG_BANK3_ROW 0
@ -194,20 +206,21 @@
#define CFG_BANK6_ROW 0
#define CFG_BANK7_ROW 0
/* Bit-field values for MCCR2.
/* Bit-field values for MCCR2.
*/
#define CFG_REFINT 430 /* Refresh interval */
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
#define CFG_REFINT 0x2ec
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
*/
#define CFG_BSTOPRE 192
#define CFG_BSTOPRE 160
/* Bit-field values for MCCR3.
/* Bit-field values for MCCR3.
*/
#define CFG_REFREC 2 /* Refresh to activate interval */
#define CFG_RDLAT 3 /* Data latancy from read command */
#define CFG_RDLAT 0 /* Data latancy from read command */
/* Bit-field values for MCCR4.
/* Bit-field values for MCCR4.
*/
#define CFG_PRETOACT 2 /* Precharge to activate interval */
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
@ -216,7 +229,7 @@
#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
#define CFG_ACTORW 2
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 1
#define CFG_EXTROM 0
#define CFG_REGDIMM 0
/* Memory bank settings.
@ -252,6 +265,9 @@
#define CFG_BANK7_ENABLE 0
#define CFG_ODCR 0xff
#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
/* currently accessed page in memory */
/* see 8240 book for details */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@ -295,7 +311,7 @@
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
@ -320,9 +336,9 @@
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define SRAM_END 0x801FFFFF
/*---------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*---------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
#define SRAM_BASE 0x80000000 /* SRAM base address */
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
@ -437,13 +453,15 @@
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define PCI_ENET0_IOADDR 0x00104000
#define PCI_ENET0_IOADDR 0x82000000
#define PCI_ENET0_MEMADDR 0x82000000
#define PCI_PLX9030_IOADDR 0x82100000
#define PCI_PLX9030_MEMADDR 0x82100000
#endif /* __CONFIG_H */

154
include/configs/PM520.h
View File

@ -35,6 +35,8 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
@ -82,11 +84,37 @@
#endif
/* Partitions */
#define CONFIG_DOS_PARTITION
/* USB */
#if 1
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD 0
#endif
#if defined(CONFIG_BOOT_ROM)
#define ADD_DOC_CMD 0
#else
#define ADD_DOC_CMD CFG_CMD_DOC
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
ADD_DOC_CMD | \
ADD_PCI_CMD | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
ADD_USB_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -95,8 +123,32 @@
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pm520\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk30/ppc_82xx\0" \
"bootfile=/tftpboot/PM520/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if defined(CONFIG_MPC5200)
/*
@ -128,11 +180,44 @@
#define CFG_I2C_RTC_ADDR 0x51
/*
* Flash configuration
* Disk-On-Chip configuration
*/
#define CFG_FLASH_BASE 0xff800000
#define CFG_FLASH_SIZE 0x00800000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#define CFG_DOC_BASE 0xE0000000
#define CFG_DOC_SIZE 0x00100000
#if defined(CONFIG_BOOT_ROM)
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 32 MB
* 0xFD000000 for 16 MB
* 0xFD800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfc000000
#define CFG_FLASH_SIZE 0x02000000
#define CFG_BOOTROM_BASE 0xFFF00000
#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
#else
/*
* Flash configuration (8,16 or 32 MB)
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfe000000
#define CFG_FLASH_SIZE 0x02000000
#define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
#endif
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
@ -228,15 +313,68 @@
#define CFG_HID0_FINAL 0
#endif
#if defined(CONFIG_BOOT_ROM)
#define CFG_BOOTCS_START CFG_BOOTROM_BASE
#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
#define CFG_BOOTCS_CFG 0x00047800
#define CFG_CS0_START CFG_BOOTROM_BASE
#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
#define CFG_CS1_START CFG_FLASH_BASE
#define CFG_CS1_SIZE CFG_FLASH_SIZE
#define CFG_CS1_CFG 0x0004fb00
#else
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x0004fb00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS1_START CFG_DOC_BASE
#define CFG_CS1_SIZE CFG_DOC_SIZE
#define CFG_CS1_CFG 0x00047800
#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */

2
include/configs/RPXlite_DW.h
View File

@ -178,8 +178,6 @@
#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/

236
include/mc9328.h
View File

@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
#ifndef __MC9328_H__
#define __MC9328_H__
@ -32,12 +31,9 @@ typedef VU32 * P_VU32;
#define __REG(x) (*((volatile u32 *)(x)))
/*
* MX1 Chip selects & internal memory's
*/
#define MX1_DMI_PHYS 0x00000000 /* double map image */
#define MX1_BROM_PHYS 0x00100000 /* Bootstrape ROM */
#define MX1_ESRAM_PHYS 0x00300000 /* Embedded SRAM (128KB)*/
@ -51,22 +47,16 @@ typedef VU32 * P_VU32;
#define MX1_CS4_PHYS 0x15000000 /* CS4 16MB (Spare) */
#define MX1_CS5_PHYS 0x16000000 /* CS5 16MB (Spare) */
/*
* MX1 Watchdog registers
*/
#define MX1_WCR __REG(0x00201000) /* Watchdog Control Register */
#define MX1_WSR __REG(0x00201004) /* Watchdog Service Register */
#define MX1_WSTR __REG(0x00201008) /* Watchdog Status Register */
/*
* MX1 Timer registers
*/
#define MX1_TCTL1 __REG(0x00202000) /* Timer 1 Control Register */
#define MX1_TPRER1 __REG(0x00202004) /* Timer 1 Prescaler Register */
#define MX1_TCMP1 __REG(0x00202008) /* Timer 1 Compare Register */
@ -74,7 +64,6 @@ typedef VU32 * P_VU32;
#define MX1_TCN1 __REG(0x00202010) /* Timer 1 Counter Register */
#define MX1_TSTAT1 __REG(0x00202014) /* Timer 1 Status Register */
#define MX1_TCTL2 __REG(0x00203000) /* Timer 2 Control Register */
#define MX1_TPRER2 __REG(0x00203004) /* Timer 2 Prescaler Register */
#define MX1_TCMP2 __REG(0x00203008) /* Timer 2 Compare Register */
@ -82,12 +71,9 @@ typedef VU32 * P_VU32;
#define MX1_TCN2 __REG(0x00203010) /* Timer 2 Counter Register */
#define MX1_TSTAT2 __REG(0x00203014) /* Timer 2 Status Register */
/*
* MX1 RTC registers
*/
#define MX1_HOURMIN __REG(0x00204000) /* RTC Hour & Min Counter Registers */
#define MX1_SECONDS __REG(0x00204004) /* RTC Seconds Counter Registers */
#define MX1_ALRM_HM __REG(0x00204008) /* RTC Hour & Min Alarm Registers */
@ -99,11 +85,9 @@ typedef VU32 * P_VU32;
#define MX1_DAYR __REG(0x00204020) /* RTC Days Counter Registers */
#define MX1_DAYALARM __REG(0x00204020) /* RTC Day Alarm Registers */
/*
* MX1 LCD Controller registers
*/
#define MX1_SSA __REG(0x00205000) /* Screen Start Address Register */
#define MX1_SIZE __REG(0x00205004) /* Size Register */
#define MX1_VPW __REG(0x00205008) /* Virtual Page Width Register */
@ -121,7 +105,6 @@ typedef VU32 * P_VU32;
#define MX1_LCDICR __REG(0x00205038) /* Interrupt Configuration Register */
#define MX1_LCDISR __REG(0x00205040) /* Interrupt Status Register */
/*
* MX1 UART registers
*/
@ -144,7 +127,6 @@ typedef VU32 * P_VU32;
#define MX1_URX14D_1 __REG(0x00206038) /* UART 1 Receiver Register 14 */
#define MX1_URX15D_1 __REG(0x0020603c) /* UART 1 Receiver Register 15 */
#define MX1_UTX0D_1 __REG(0x00206040) /* UART 1 Transmitter Register 0 */
#define MX1_UTX1D_1 __REG(0x00206044) /* UART 1 Transmitter Register 1 */
#define MX1_UTX2D_1 __REG(0x00206048) /* UART 1 Transmitter Register 2 */
@ -184,7 +166,6 @@ typedef VU32 * P_VU32;
#define MX1_BMPR4_1 __REG(0x002060CC) /* UART 1 BRM Modulator Preset Register 4 */
#define MX1_UTS_1 __REG(0x002060D0) /* UART 1 Test Register 1 */
/* UART 2 */
#define MX1_URX0D_2 __REG(0x00207000) /* UART 2 Receiver Register 0 */
#define MX1_URX1D_2 __REG(0x00207004) /* UART 2 Receiver Register 1 */
@ -203,7 +184,6 @@ typedef VU32 * P_VU32;
#define MX1_URX14D_2 __REG(0x00207038) /* UART 2 Receiver Register 14 */
#define MX1_URX15D_2 __REG(0x0020703c) /* UART 2 Receiver Register 15 */
#define MX1_UTX0D_2 __REG(0x00207040) /* UART 2 Transmitter Register 0 */
#define MX1_UTX1D_2 __REG(0x00207044) /* UART 2 Transmitter Register 1 */
#define MX1_UTX2D_2 __REG(0x00207048) /* UART 2 Transmitter Register 2 */
@ -243,22 +223,17 @@ typedef VU32 * P_VU32;
#define MX1_BMPR4_2 __REG(0x002070CC) /* UART 2 BRM Modulator Preset Register 4 */
#define MX1_UTS_2 __REG(0x002070D0) /* UART 2 Test Register 1 */
/*
* MX1 PWM registers
*/
#define MX1_PWMC __REG(0x00208000) /* PWM Control Register */
#define MX1_PWMS __REG(0x00208004) /* PWM Sample Register */
#define MX1_PWMP __REG(0x00208008) /* PWM Period Register */
#define MX1_PWMCNT __REG(0x0020800C) /* PWM Counter Register */
/*
* MX1 DMAC registers
*/
#define MX1_DCR __REG(0x00209000) /* DMA Control Register */
#define MX1_DISR __REG(0x00209004) /* DMA Interrupt Status Register */
#define MX1_DIMR __REG(0x00209008) /* DMA Interrupt Mask Register */
@ -287,7 +262,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR0 __REG(0x00209098) /* Channel 0 Request Time-Out Register */
#define MX1_BUCR0 __REG(0x00209098) /* Channel 0 Bus Utilization Control Register */
/* Channel 1 */
#define MX1_SAR1 __REG(0x002090C0) /* Channel 1 Source Address Register */
@ -299,7 +273,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR1 __REG(0x002090D8) /* Channel 1 Request Time-Out Register */
#define MX1_BUCR1 __REG(0x002090D8) /* Channel 1 Bus Utilization Control Register */
/* Channel 2 */
#define MX1_SAR2 __REG(0x00209100) /* Channel 2 Source Address Register */
@ -311,8 +284,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR2 __REG(0x00209118) /* Channel 2 Request Time-Out Register */
#define MX1_BUCR2 __REG(0x00209118) /* Channel 2 Bus Utilization Control Register */
/* Channel 3 */
#define MX1_SAR3 __REG(0x00209140) /* Channel 3 Source Address Register */
@ -324,7 +295,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR3 __REG(0x00209158) /* Channel 3 Request Time-Out Register */
#define MX1_BUCR3 __REG(0x00209158) /* Channel 3 Bus Utilization Control Register */
/* Channel 4 */
#define MX1_SAR4 __REG(0x00209180) /* Channel 4 Source Address Register */
@ -336,7 +306,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR4 __REG(0x00209198) /* Channel 4 Request Time-Out Register */
#define MX1_BUCR4 __REG(0x00209198) /* Channel 4 Bus Utilization Control Register */
/* Channel 5 */
#define MX1_SAR5 __REG(0x002091C0) /* Channel 5 Source Address Register */
@ -348,7 +317,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR5 __REG(0x002091D8) /* Channel 5 Request Time-Out Register */
#define MX1_BUCR5 __REG(0x002091D8) /* Channel 5 Bus Utilization Control Register */
/* Channel 6 */
#define MX1_SAR6 __REG(0x00209200) /* Channel 6 Source Address Register */
@ -360,7 +328,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR6 __REG(0x00209218) /* Channel 6 Request Time-Out Register */
#define MX1_BUCR6 __REG(0x00209218) /* Channel 6 Bus Utilization Control Register */
/* Channel 7 */
#define MX1_SAR7 __REG(0x00209240) /* Channel 7 Source Address Register */
@ -372,7 +339,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR7 __REG(0x00209258) /* Channel 7 Request Time-Out Register */
#define MX1_BUCR7 __REG(0x00209258) /* Channel 7 Bus Utilization Control Register */
/* Channel 8 */
#define MX1_SAR8 __REG(0x00209280) /* Channel 8 Source Address Register */
@ -384,7 +350,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR8 __REG(0x00209298) /* Channel 8 Request Time-Out Register */
#define MX1_BUCR8 __REG(0x00209298) /* Channel 8 Bus Utilization Control Register */
/* Channel 9 */
#define MX1_SAR9 __REG(0x002092C0) /* Channel 9 Source Address Register */
@ -396,7 +361,6 @@ typedef VU32 * P_VU32;
#define MX1_RTOR9 __REG(0x002092D8) /* Channel 9 Request Time-Out Register */
#define MX1_BUCR9 __REG(0x002092D8) /* Channel 9 Bus Utilization Control Register */
/* Channel 10 */
#define MX1_SAR10 __REG(0x00209300) /* Channel 10 Source Address Register */
@ -408,15 +372,12 @@ typedef VU32 * P_VU32;
#define MX1_RTOR10 __REG(0x00209318) /* Channel 10 Request Time-Out Register */
#define MX1_BUCR10 __REG(0x00209318) /* Channel 10 Bus Utilization Control Register */
#define MX1_TCR __REG(0x00209340) /* Test Control Register */
#define MX1_TFIFOAR __REG(0x00209344) /* Test FIFO A Register */
#define MX1_TDRR __REG(0x00209348) /* Test DMA Request Register */
#define MX1_TDIPR __REG(0x0020934C) /* Test DMA In Progress Register */
#define MX1_TFIFOBR __REG(0x00209350) /* Test FIFO B Register */
/*
* MX1 SIM registers
*/
@ -439,7 +400,6 @@ typedef VU32 * P_VU32;
#define MX1_GPCNT __REG(0x0021103C) /* General Purpose Counter Register */
#define MX1_DIVISOR __REG(0x00211040) /* Divisor Register */
/*
* MX1 USBD registers
*/
@ -454,7 +414,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_MASK __REG(0x0021201C) /* USB Interrupt Mask Register */
#define MX1_USB_ENAB __REG(0x00212024) /* USB Enable Register */
/* Endpoint 0 */
#define MX1_USB_EP0_STAT __REG(0x00212030) /* Endpoint 0 Status/Control Register */
#define MX1_USB_EP0_INTR __REG(0x00212034) /* Endpoint 0 Interrupt Status Register */
@ -468,7 +427,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP0_FRDP __REG(0x00212054) /* Endpoint 0 FIFO Read Pointer Register */
#define MX1_USB_EP0_FWRP __REG(0x00212058) /* Endpoint 0 FIFO Write Pointer Register */
/* Endpoint 1 */
#define MX1_USB_EP1_STAT __REG(0x00212060) /* Endpoint 1 Status/Control Register */
#define MX1_USB_EP1_INTR __REG(0x00212064) /* Endpoint 1 Interrupt Status Register */
@ -482,7 +440,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP1_FRDP __REG(0x00212084) /* Endpoint 1 FIFO Read Pointer Register */
#define MX1_USB_EP1_FWRP __REG(0x00212088) /* Endpoint 1 FIFO Write Pointer Register */
/* Endpoint 2 */
#define MX1_USB_EP2_STAT __REG(0x00212090) /* Endpoint 2 Status/Control Register */
#define MX1_USB_EP2_INTR __REG(0x00212094) /* Endpoint 2 Interrupt Status Register */
@ -496,7 +453,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP2_FRDP __REG(0x002120B4) /* Endpoint 2 FIFO Read Pointer Register */
#define MX1_USB_EP2_FWRP __REG(0x002120B8) /* Endpoint 2 FIFO Write Pointer Register */
/* Endpoint 3 */
#define MX1_USB_EP3_STAT __REG(0x002120C0) /* Endpoint 3 Status/Control Register */
#define MX1_USB_EP3_INTR __REG(0x002120C4) /* Endpoint 3 Interrupt Status Register */
@ -510,8 +466,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP3_FRDP __REG(0x002120E4) /* Endpoint 3 FIFO Read Pointer Register */
#define MX1_USB_EP3_FWRP __REG(0x002120E8) /* Endpoint 3 FIFO Write Pointer Register */
/* Endpoint 4 */
#define MX1_USB_EP4_STAT __REG(0x002120F0) /* Endpoint 4 Status/Control Register */
#define MX1_USB_EP4_INTR __REG(0x002120F4) /* Endpoint 4 Interrupt Status Register */
@ -525,8 +479,6 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP4_FRDP __REG(0x00212114) /* Endpoint 4 FIFO Read Pointer Register */
#define MX1_USB_EP4_FWRP __REG(0x00212118) /* Endpoint 4 FIFO Write Pointer Register */
/* Endpoint 5 */
#define MX1_USB_EP5_STAT __REG(0x00212120) /* Endpoint 5 Status/Control Register */
#define MX1_USB_EP5_INTR __REG(0x00212124) /* Endpoint 5 Interrupt Status Register */
@ -540,13 +492,9 @@ typedef VU32 * P_VU32;
#define MX1_USB_EP5_FRDP __REG(0x00212144) /* Endpoint 5 FIFO Read Pointer Register */
#define MX1_USB_EP5_FWRP __REG(0x00212148) /* Endpoint 5 FIFO Write Pointer Register */
/*
* MX1 SPI 1 registers
*/
#define MX1_RXDATAREG1 __REG(0x00213000) /* SPI 1 Rx Data Register */
#define MX1_TXDATAREG1 __REG(0x00213004) /* SPI 1 Tx Data Register */
#define MX1_CONTROLREG1 __REG(0x00213008) /* SPI 1 Control Register */
@ -556,13 +504,9 @@ typedef VU32 * P_VU32;
#define MX1_DMAREG1 __REG(0x00213018) /* SPI 1 DMA Control Register */
#define MX1_RESETREG1 __REG(0x00213018) /* SPI 1 Soft Reset Register */
/*
* MX1 MMC/SDHC registers
*/
#define MX1_STR_STP_CLK __REG(0x00214000) /* MMC/SD Clock Control Register */
#define MX1_STATUS __REG(0x00214004) /* MMC/SD Status Register */
#define MX1_CLK_RATE __REG(0x00214008) /* MMC/SD Clock Rate Register */
@ -579,12 +523,9 @@ typedef VU32 * P_VU32;
#define MX1_RES_FIFO __REG(0x00214034) /* MMC/SD Response FIFO Register */
#define MX1_BUFFER_ACCESS __REG(0x00214038) /* MMC/SD Buffer Access Register */
/*
* MX1 ASP registers
*/
#define MX1_ASP_PADFIFO __REG(0x00215000) /* Pen Sample FIFO */
#define MX1_ASP_VADFIFO __REG(0x00215004) /* Voice ADC Register */
#define MX1_ASP_VDAFIFO __REG(0x00215008) /* Voice DAC Register */
@ -599,29 +540,22 @@ typedef VU32 * P_VU32;
#define MX1_ASP_CLKDIV __REG(0x0021502C) /* Clock Divide Register */
#define MX1_ASP_CMPCNTL __REG(0x0021502C) /* Compare Control Register */
/*
* MX1 BTA registers
*/
/*
* MX1 I2C registers
*/
#define MX1_IADR __REG(0x00217000) /* I2C Address Register */
#define MX1_IFDR __REG(0x00217004) /* I2C Frequency Divider Register */
#define MX1_I2CR __REG(0x00217008) /* I2C Control Register */
#define MX1_I2CSR __REG(0x0021700C) /* I2C Status Register */
#define MX1_I2DR __REG(0x00217010) /* I2C Data I/O Register */
/*
* MX1 SSI registers
*/
#define MX1_STX __REG(0x00218000) /* SSI Transmit Data Register */
#define MX1_SRX __REG(0x00218004) /* SSI Receive Data Register */
#define MX1_SCSR __REG(0x00218008) /* SSI Control/Status Register */
@ -633,12 +567,9 @@ typedef VU32 * P_VU32;
#define MX1_SFCSR __REG(0x00218020) /* SSI FIFO Control/Status Register */
#define MX1_SOR __REG(0x00218024) /* SSI Option Register */
/*
* MX1 SPI 2 registers
*/
#define MX1_RXDATAREG2 __REG(0x00219000) /* SPI 2 Rx Data Register */
#define MX1_TXDATAREG2 __REG(0x00219004) /* SPI 2 Tx Data Register */
#define MX1_CONTROLREG2 __REG(0x00219008) /* SPI 2 Control Register */
@ -648,12 +579,9 @@ typedef VU32 * P_VU32;
#define MX1_DMAREG2 __REG(0x00219018) /* SPI 2 DMA Control Register */
#define MX1_RESETREG2 __REG(0x00219018) /* SPI 2 Soft Reset Register */
/*
* MX1 MSHC registers
*/
#define MX1_MSCMD __REG(0x0021A000) /* Memory Stick Command Register */
#define MX1_MSCS __REG(0x0021A002) /* Memory Stick Control/Status Register */
#define MX1_MSTDATA __REG(0x0021A004) /* Memory Stick Transmit FIFO Data Register */
@ -666,12 +594,9 @@ typedef VU32 * P_VU32;
#define MX1_MSCLKD __REG(0x0021A010) /* Memory Stick Serial Clock divider Register */
#define MX1_MSDRQC __REG(0x0021A012) /* Memory Stick DMA Request Control Register */
/*
* MX1 PLLCLK registers
*/
#define MX1_CSCR __REG(0x0021B000) /* Clock Source Control Register */
#define MX1_MPCTL0 __REG(0x0021B004) /* MCU PLL Control Register 0 */
#define MX1_MPCTL1 __REG(0x0021B008) /* MCU PLL & System Clock Control Register 1 */
@ -679,24 +604,18 @@ typedef VU32 * P_VU32;
#define MX1_UPCTL1 __REG(0x0021B010) /* USB PLL Control Register 1 */
#define MX1_PCDR __REG(0x0021B020) /* Peripheral Clock Divider Register */
/*
* MX1 RESET registers
*/
#define MX1_RSR __REG(0x0021B800) /* Reset Source Register */
/*
* MX1 SYS CTRL registers
*/
#define MX1_SIDR __REG(0x0021B804) /* Silicon ID Register */
#define MX1_FMCR __REG(0x0021B808) /* Function MultiPlexing Control Register */
#define MX1_GPCR __REG(0x0021B80C) /* Global Peripheral Control Register */
/*
* MX1 GPIO registers
*/
@ -720,7 +639,6 @@ typedef VU32 * P_VU32;
#define MX1_SWR_A __REG(0x0021C03C) /* Port A Software Reset Register */
#define MX1_PUEN_A __REG(0x0021C040) /* Port A Pull Up Enable Register */
/* Port B */
#define MX1_DDIR_B __REG(0x0021C100) /* Port B Data Direction Register */
#define MX1_OCR1_B __REG(0x0021C104) /* Port B Output Configuration Register 1 */
@ -740,8 +658,6 @@ typedef VU32 * P_VU32;
#define MX1_SWR_B __REG(0x0021C13C) /* Port B Software Reset Register */
#define MX1_PUEN_B __REG(0x0021C140) /* Port B Pull Up Enable Register */
/* Port C */
#define MX1_DDIR_C __REG(0x0021C200) /* Port C Data Direction Register */
#define MX1_OCR1_C __REG(0x0021C204) /* Port C Output Configuration Register 1 */
@ -761,8 +677,6 @@ typedef VU32 * P_VU32;
#define MX1_SWR_C __REG(0x0021C23C) /* Port C Software Reset Register */
#define MX1_PUEN_C __REG(0x0021C240) /* Port C Pull Up Enable Register */
/* Port D */
#define MX1_DDIR_D __REG(0x0021C300) /* Port D Data Direction Register */
#define MX1_OCR1_D __REG(0x0021C304) /* Port D Output Configuration Register 1 */
@ -782,12 +696,9 @@ typedef VU32 * P_VU32;
#define MX1_SWR_D __REG(0x0021C33C) /* Port D Software Reset Register */
#define MX1_PUEN_D __REG(0x0021C340) /* Port D Pull Up Enable Register */
/*
* MX1 EIM registers
*/
#define MX1_CS0U __REG(0x00220000) /* Chip Select 0 Upper Control Register */
#define MX1_CS0L __REG(0x00220004) /* Chip Select 0 Lower Control Register */
#define MX1_CS1U __REG(0x00220008) /* Chip Select 1 Upper Control Register */
@ -802,23 +713,17 @@ typedef VU32 * P_VU32;
#define MX1_CS5L __REG(0x0022002C) /* Chip Select 5 Lower Control Register */
#define MX1_WEIM __REG(0x00220030) /* weim cONFIGURATION Register */
/*
* MX1 SDRAMC registers
*/
#define MX1_SDCTL0 __REG(0x00221000) /* SDRAM 0 Control Register */
#define MX1_SDCTL1 __REG(0x00221004) /* SDRAM 1 Control Register */
#define MX1_MISCELLANEOUS __REG(0x00221014) /* Miscellaneous Register */
#define MX1_SDRST __REG(0x00221018) /* SDRAM Reset Register */
/*
* MX1 MMA registers
*/
#define MX1_MMA_MAC_MOD __REG(0x00222000) /* MMA MAC Module Register */
#define MX1_MMA_MAC_CTRL __REG(0x00222004) /* MMA MAC Control Register */
#define MX1_MMA_MAC_MULT __REG(0x00222008) /* MMA MAC Multiply Counter Register */
@ -837,7 +742,6 @@ typedef VU32 * P_VU32;
#define MX1_MMA_MAC_XINCR __REG(0x00222210) /* MMA MAC X Increment Register */
#define MX1_MMA_MAC_XCOUNT __REG(0x00222214) /* MMA MAC X Count Register */
#define MX1_MMA_MAC_YBASE __REG(0x00222300) /* MMA MAC Y Base Address Register */
#define MX1_MMA_MAC_YINDEX __REG(0x00222304) /* MMA MAC Y Index Register */
#define MX1_MMA_MAC_YLENGTH __REG(0x00222308) /* MMA MAC Y Length Register */
@ -845,7 +749,6 @@ typedef VU32 * P_VU32;
#define MX1_MMA_MAC_YINCR __REG(0x00222310) /* MMA MAC Y Increment Register */
#define MX1_MMA_MAC_YCOUNT __REG(0x00222314) /* MMA MAC Y Count Register */
#define MX1_MMA_DCTCTRL __REG(0x00222400) /* DCT/iDCT Control Register */
#define MX1_MMA_DCTVERSION __REG(0x00222404) /* DCT/iDCT Version Register */
#define MX1_MMA_DCTIRQENA __REG(0x00222408) /* DCT/iDCT IRQ Enable Register */
@ -858,13 +761,9 @@ typedef VU32 * P_VU32;
#define MX1_MMA_DCTSKIP __REG(0x00222424) /* DCT/iDCT Skip Address */
#define MX1_MMA_DCTFIFO __REG(0x00222500) /* DCT/iDCT Data FIFO */
/*
* MX1 AITC registers
*/
#define MX1_INTCNTL __REG(0x00223000) /* Interrupt Control Register */
#define MX1_NIMASK __REG(0x00223004) /* Normal Interrupt Mask Register */
#define MX1_INTENNUM __REG(0x00223008) /* Interrupt Enable Number Register */
@ -892,84 +791,25 @@ typedef VU32 * P_VU32;
#define MX1_FIPNDH __REG(0x00223060) /* Fast Interrupt Pending Register High */
#define MX1_FIPNDL __REG(0x00223064) /* Fast Interrupt Pending Register Low */
/*
* MX1 CSI registers
*/
#define MX1_CSICR1 __REG(0x00224000) /* CSI Control Register 1 */
#define MX1_CSICR2 __REG(0x00224004) /* CSI Control Register 2 */
#define MX1_CSISR __REG(0x00224008) /* CSI Status Register 1 */
#define MX1_CSISTATR __REG(0x0022400C) /* CSI Statistic FIFO Register 1 */
#define MX1_CSIRXR __REG(0x00224010) /* CSI RxFIFO Register 1 */
#endif /* __MC9328_H__ */
#if 0
/*
MX1 dma definition
*/
#define MAX_DMA_ADDRESS 0xffffffff
//#define MAX_DMA_CHANNELS 0
/*#define MAX_DMA_CHANNELS 0 */
#define MAX_DMA_CHANNELS 11
#define MAX_DMA_2D_REGSET 2
@ -977,35 +817,34 @@ typedef VU32 * P_VU32;
/* MX1 DMA module registers' address */
#define MX1_DMA_BASE IO_ADDRESS(0x00209000)
#define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) // DMA control register
#define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) // DMA interrupt status register
#define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) // DMA interrupt mask register
#define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) // DMA burst time-out status register
#define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) // DMA request time-out status register
#define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) // DMA transfer error status register
#define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) // DMA buffer overflow status register
#define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) // DMA burst time-out control register
#define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) // W-size register A
#define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) // X-size register A
#define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) // Y-size register A
#define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) // W-size register B
#define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) // X-size register B
#define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) // Y-size register B
#define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) /* DMA control register */
#define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) /* DMA interrupt status register */
#define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) /* DMA interrupt mask register */
#define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) /* DMA burst time-out status register */
#define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) /* DMA request time-out status register */
#define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) /* DMA transfer error status register */
#define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) /* DMA buffer overflow status register */
#define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) /* DMA burst time-out control register */
#define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) /* W-size register A */
#define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) /* X-size register A */
#define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) /* Y-size register A */
#define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) /* W-size register B */
#define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) /* X-size register B */
#define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) /* Y-size register B */
#define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) // source address register 0
#define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) // destination address register 0
#define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) // count register 0
#define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) // channel control register 0
#define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) // request source select register 0
#define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) // burst length register 0
#define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) // request time-out register 0
#define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) // bus utilization control register 0
#define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) /* source address register 0 */
#define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) /* destination address register 0 */
#define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) /* count register 0 */
#define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) /* channel control register 0 */
#define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) /* request source select register 0 */
#define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) /* burst length register 0 */
#define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) /* request time-out register 0 */
#define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) /* bus utilization control register 0 */
/* register set 1 to 10 are offseted by 0x40 each = 0x10 pointers away */
#define DMA_REG_SET_OFS 0x10
/* MX1 DMA module registers */
#define _reg_DMA_DCR (*((P_VU32)MX1_DMA_DCR))
#define _reg_DMA_DISR (*((P_VU32)MX1_DMA_DISR))
@ -1031,11 +870,10 @@ typedef VU32 * P_VU32;
#define _reg_DMA_BUCR0 (*((P_VU32)MX1_DMA_BUCR0))
/* DMA error type definition */
#define MX1_DMA_ERR_BTO 0 // burst time-out
#define MX1_DMA_ERR_RTO 1 // request time-out
#define MX1_DMA_ERR_TE 2 // transfer error
#define MX1_DMA_ERR_BO 3 // buffer overflow
#define MX1_DMA_ERR_BTO 0 /* burst time-out */
#define MX1_DMA_ERR_RTO 1 /* request time-out */
#define MX1_DMA_ERR_TE 2 /* transfer error */
#define MX1_DMA_ERR_BO 3 /* buffer overflow */
/* Embedded SRAM */
@ -1044,7 +882,6 @@ typedef VU32 * P_VU32;
#define
#define MX1ADS_SFLASH_BASE 0x0C000000
#define MX1ADS_SFLASH_SIZE SZ_16M
@ -1056,12 +893,12 @@ typedef VU32 * P_VU32;
#define MX1ADS_VID_START IO_ADDRESS(MX1ADS_VID_BASE)
#define MX1_GPIO_BASE 0x0021C000 // GPIO
#define MX1_EXT_UART_BASE 0x15000000 // external UART
#define MX1_TMR1_BASE 0x00202000 // Timer1
#define MX1ADS_FLASH_BASE 0x0C000000 // sync FLASH
#define MX1_ESRAM_BASE 0x00300000 // embedded SRAM
#define MX1ADS_SDRAM_DISK_BASE 0x0B000000 // SDRAM disk base (last 16M of SDRAM)
#define MX1_GPIO_BASE 0x0021C000 /* GPIO */
#define MX1_EXT_UART_BASE 0x15000000 /* external UART */
#define MX1_TMR1_BASE 0x00202000 /* Timer1 */
#define MX1ADS_FLASH_BASE 0x0C000000 /* sync FLASH */
#define MX1_ESRAM_BASE 0x00300000 /* embedded SRAM */
#define MX1ADS_SDRAM_DISK_BASE 0x0B000000 /* SDRAM disk base (last 16M of SDRAM) */
/* ------------------------------------------------------------------------
* Motorola MX1 system registers
@ -1103,7 +940,6 @@ typedef VU32 * P_VU32;
#define MX1ADS_AITC_OFFSET 0x23000
#define MX1ADS_CSI_OFFSET 0x24000
/*
* Register BASEs, based on OFFSETs
*
@ -1138,7 +974,6 @@ typedef VU32 * P_VU32;
#define MX1ADS_AITC_BASE (MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
#define MX1ADS_CSI_BASE (MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
/*
* MX1 Interrupt numbers
*
@ -1197,12 +1032,10 @@ typedef VU32 * P_VU32;
#define DMA_INT 61
#define GPIO_INT_PORTD 62
#define MAXIRQNUM 62
#define MAXFIQNUM 62
#define MAXSWINUM 62
#define TICKS_PER_uSEC 24
/*
@ -1215,7 +1048,4 @@ typedef VU32 * P_VU32;
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
#endif