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ARM: am33xx: make DDR PLL frequency configurable 

Needed for 400MHz DDR3.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2013-08-22 22:28:32 +02:00
parent e3cbf4f762
commit abd545d2f9
4 changed files with 11 additions and 9 deletions
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2
arch/arm/boards/beaglebone/lowlevel.c
View File

@ -89,7 +89,7 @@ static int beaglebone_board_init(void)
if (running_in_sdram())
return 0;
pll_init(MPUPLL_M_500, 24);
pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs, &ddr2_data);

2
arch/arm/boards/pcm051/lowlevel.c
View File

@ -68,7 +68,7 @@ static int pcm051_board_init(void)
if (running_in_sdram())
return 0;
pll_init(MPUPLL_M_600, 25);
pll_init(MPUPLL_M_600, 25, DDRPLL_M_266);
am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
&MT41J256M8HX15E_2x256M8_regs,

10
arch/arm/mach-omap/am33xx_clock.c
View File

@ -248,7 +248,7 @@ static void per_pll_config(int osc)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
}
static void ddr_pll_config(int osc)
static void ddr_pll_config(int osc, int ddrpll_M)
{
u32 clkmode, clksel, div_m2;
@ -263,7 +263,7 @@ static void ddr_pll_config(int osc)
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((DDRPLL_M << 0x8) | (osc - 1));
clksel = clksel | ((ddrpll_M << 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 & 0xFFFFFFE0;
@ -288,18 +288,18 @@ void enable_ddr_clocks(void)
PRCM_L3_GCLK_ACTIVITY));
/* Poll if module is functional */
while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
void pll_init(int mpupll_M, int osc)
void pll_init(int mpupll_M, int osc, int ddrpll_M)
{
mpu_pll_config(mpupll_M, osc);
core_pll_config(osc);
per_pll_config(osc);
ddr_pll_config(osc);
ddr_pll_config(osc, ddrpll_M);
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */

6
arch/arm/mach-omap/include/mach/am33xx-clock.h
View File

@ -48,7 +48,9 @@
/* DDR Freq is 266 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M 266
#define DDRPLL_M_266 266
#define DDRPLL_M_400 400
#define DDRPLL_N (OSC - 1)
#define DDRPLL_M2 1
/* PRCM */
@ -181,7 +183,7 @@
#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
extern void pll_init(int mpupll_M, int osc);
extern void pll_init(int mpupll_M, int osc, int ddrpll_M);
extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */