ARM: am33xx: make DDR PLL frequency configurable
Needed for 400MHz DDR3. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -89,7 +89,7 @@ static int beaglebone_board_init(void)
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if (running_in_sdram())
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if (running_in_sdram())
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return 0;
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return 0;
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pll_init(MPUPLL_M_500, 24);
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pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs, &ddr2_data);
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs, &ddr2_data);
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@ -68,7 +68,7 @@ static int pcm051_board_init(void)
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if (running_in_sdram())
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if (running_in_sdram())
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return 0;
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return 0;
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pll_init(MPUPLL_M_600, 25);
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pll_init(MPUPLL_M_600, 25, DDRPLL_M_266);
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am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
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am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
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&MT41J256M8HX15E_2x256M8_regs,
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&MT41J256M8HX15E_2x256M8_regs,
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@ -248,7 +248,7 @@ static void per_pll_config(int osc)
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
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}
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}
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static void ddr_pll_config(int osc)
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static void ddr_pll_config(int osc, int ddrpll_M)
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{
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{
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u32 clkmode, clksel, div_m2;
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u32 clkmode, clksel, div_m2;
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@ -263,7 +263,7 @@ static void ddr_pll_config(int osc)
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((DDRPLL_M << 0x8) | (osc - 1));
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clksel = clksel | ((ddrpll_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
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__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
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div_m2 = div_m2 & 0xFFFFFFE0;
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div_m2 = div_m2 & 0xFFFFFFE0;
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@ -288,18 +288,18 @@ void enable_ddr_clocks(void)
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PRCM_L3_GCLK_ACTIVITY));
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PRCM_L3_GCLK_ACTIVITY));
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/* Poll if module is functional */
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/* Poll if module is functional */
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while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
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while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
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}
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}
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/*
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/*
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* Configure the PLL/PRCM for necessary peripherals
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* Configure the PLL/PRCM for necessary peripherals
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*/
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*/
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void pll_init(int mpupll_M, int osc)
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void pll_init(int mpupll_M, int osc, int ddrpll_M)
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{
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{
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mpu_pll_config(mpupll_M, osc);
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mpu_pll_config(mpupll_M, osc);
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core_pll_config(osc);
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core_pll_config(osc);
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per_pll_config(osc);
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per_pll_config(osc);
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ddr_pll_config(osc);
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ddr_pll_config(osc, ddrpll_M);
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/* Enable the required interconnect clocks */
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/* Enable the required interconnect clocks */
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interface_clocks_enable();
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interface_clocks_enable();
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/* Enable power domain transition */
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/* Enable power domain transition */
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@ -48,7 +48,9 @@
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/* DDR Freq is 266 MHZ for now*/
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/* DDR Freq is 266 MHZ for now*/
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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#define DDRPLL_M 266
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#define DDRPLL_M_266 266
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#define DDRPLL_M_400 400
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#define DDRPLL_N (OSC - 1)
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#define DDRPLL_M2 1
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#define DDRPLL_M2 1
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/* PRCM */
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/* PRCM */
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@ -181,7 +183,7 @@
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#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
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#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
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extern void pll_init(int mpupll_M, int osc);
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extern void pll_init(int mpupll_M, int osc, int ddrpll_M);
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extern void enable_ddr_clocks(void);
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extern void enable_ddr_clocks(void);
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#endif /* endif _AM33XX_CLOCKS_H_ */
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#endif /* endif _AM33XX_CLOCKS_H_ */
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