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Merge branch 'for-next/imx' 

Conflicts:
	arch/arm/boards/dmo-mx6-realq7/lowlevel.c
This commit is contained in:
Sascha Hauer 2014-02-03 09:55:13 +01:00
parent 3cbd92bf6e cc66cf109b
commit c224cd3161
118 changed files with 8735 additions and 2629 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boards/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK) += at91sam9n12ek/
obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/
obj-$(CONFIG_MACH_BEAGLE) += beagle/
obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/
obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/
obj-$(CONFIG_MACH_CCMX51) += ccxmx51/
obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/
obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/
@ -78,7 +79,7 @@ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += solidrun-carrier-1/
obj-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += solidrun-hummingboard/
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/

3
arch/arm/boards/boundarydevices-nitrogen6x/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += board.o flash-header-nitrogen6x-1g.dcd.o
extra-y += flash-header-nitrogen6x-1g.dcd.S flash-header-nitrogen6x-1g.dcd
lwl-y += lowlevel.o

77
arch/arm/boards/boundarydevices-nitrogen6x/board.c Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright (C) 2014 Lucas Stach, Pengutronix
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <init.h>
#include <environment.h>
#include <mach/bbu.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <mach/imx6.h>
static int nitrogen6x_devices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") &&
!of_machine_is_compatible("fsl,imx6q-nitrogen6x"))
return 0;
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
return 0;
}
device_initcall(nitrogen6x_devices_init);
static int ksz9021rn_phy_fixup(struct phy_device *dev)
{
phy_write(dev, 0x09, 0x0f00);
/* do same as linux kernel */
/* min rx data delay */
phy_write(dev, 0x0b, 0x8105);
phy_write(dev, 0x0c, 0x0000);
/* max rx/tx clock delay, min rx/tx control delay */
phy_write(dev, 0x0b, 0x8104);
phy_write(dev, 0x0c, 0xf0f0);
phy_write(dev, 0x0b, 0x104);
return 0;
}
static int nitrogen6x_coredevices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") &&
!of_machine_is_compatible("fsl,imx6q-nitrogen6x"))
return 0;
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
return 0;
}
coredevice_initcall(nitrogen6x_coredevices_init);
static int nitrogen6x_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") &&
!of_machine_is_compatible("fsl,imx6q-nitrogen6x"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("nitrogen6x");
return 0;
}
postcore_initcall(nitrogen6x_postcore_init);

6
arch/arm/boards/boundarydevices-nitrogen6x/env/config-board vendored Normal file
View File

@ -0,0 +1,6 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

106
arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg Normal file
View File

@ -0,0 +1,106 @@
soc imx6
loadaddr 0x20000000
dcdofs 0x400
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05b0 0x00000030
wm 32 0x020e0524 0x00000030
wm 32 0x020e051c 0x00000030
wm 32 0x020e0518 0x00000030
wm 32 0x020e050c 0x00000030
wm 32 0x020e05b8 0x00000030
wm 32 0x020e05c0 0x00000030
wm 32 0x020e05ac 0x00020030
wm 32 0x020e05b4 0x00020030
wm 32 0x020e0528 0x00020030
wm 32 0x020e0520 0x00020030
wm 32 0x020e0514 0x00020030
wm 32 0x020e0510 0x00020030
wm 32 0x020e05bc 0x00020030
wm 32 0x020e05c4 0x00020030
wm 32 0x020e056c 0x00020030
wm 32 0x020e0578 0x00020030
wm 32 0x020e0588 0x00020030
wm 32 0x020e0594 0x00020030
wm 32 0x020e057c 0x00020030
wm 32 0x020e0590 0x00003000
wm 32 0x020e0598 0x00003000
wm 32 0x020e058c 0x00000000
wm 32 0x020e059c 0x00003030
wm 32 0x020e05a0 0x00003030
wm 32 0x020e0784 0x00000030
wm 32 0x020e0788 0x00000030
wm 32 0x020e0794 0x00000030
wm 32 0x020e079c 0x00000030
wm 32 0x020e07a0 0x00000030
wm 32 0x020e07a4 0x00000030
wm 32 0x020e07a8 0x00000030
wm 32 0x020e0748 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e0758 0x00000000
wm 32 0x020e0774 0x00020000
wm 32 0x020e078c 0x00000030
wm 32 0x020e0798 0x000c0000
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
wm 32 0x021b0018 0x00081740
wm 32 0x021b001c 0x00008000
wm 32 0x021b000c 0x555a7975
wm 32 0x021b0010 0xff538e64
wm 32 0x021b0014 0x01ff00db
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 0x005b0e21
wm 32 0x021b0008 0x09444040
wm 32 0x021b0004 0x00025576
wm 32 0x021b0040 0x00000027
wm 32 0x021b0000 0x831a0000
wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x0408803a
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x0000803b
wm 32 0x021b001c 0x00428031
wm 32 0x021b001c 0x00428039
wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x09408038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
wm 32 0x021b0800 0xa1380003
wm 32 0x021b4800 0xa1380003
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00022227
wm 32 0x021b4818 0x00022227
wm 32 0x021b083c 0x434b0350
wm 32 0x021b0840 0x034c0359
wm 32 0x021b483c 0x434b0350
wm 32 0x021b4840 0x03650348
wm 32 0x021b0848 0x4436383b
wm 32 0x021b4848 0x39393341
wm 32 0x021b0850 0x35373933
wm 32 0x021b4850 0x48254A36
wm 32 0x021b080c 0x001f001f
wm 32 0x021b0810 0x001f001f
wm 32 0x021b480c 0x00440044
wm 32 0x021b4810 0x00440044
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b001c 0x00000000
wm 32 0x021b0404 0x00011006
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
/* enable AXI cache for VDOA/VPU/IPU */
wm 32 0x020e0010 0xf00000cf
/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f

30
arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c Normal file
View File

@ -0,0 +1,30 @@
#include <common.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
extern char __dtb_imx6q_nitrogen6x_start[];
ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6q_nitrogen6x_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
extern char __dtb_imx6dl_nitrogen6x_start[];
ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}

5
arch/arm/boards/dfi-fs700-m60/Makefile
View File

@ -1,5 +1,4 @@
obj-y += board.o
obj-y += flash-header-fs700-m60-6s.dcd.o flash-header-fs700-m60-6q.dcd.o
extra-y += flash-header-fs700-m60-6s.dcd.S flash-header-fs700-m60-6q.dcd.S
extra-y += flash-header-fs700-m60-6s.dcd flash-header-fs700-m60-6q.dcd
extra-y += flash-header-fs700-m60-6s.dcd.S flash-header-fs700-m60-6q-nanya.dcd.S flash-header-fs700-m60-6q-micron.dcd.S
extra-y += flash-header-fs700-m60-6s.dcd flash-header-fs700-m60-6q-nanya.dcd flash-header-fs700-m60-6q-micron.dcd
lwl-y += lowlevel.o

45
arch/arm/boards/dfi-fs700-m60/board.c
View File

@ -19,6 +19,9 @@
#define pr_fmt(fmt) "dfi-fs700-m60: " fmt
#include <generated/mach-types.h>
#include <environment.h>
#include <bootsource.h>
#include <globalvar.h>
#include <common.h>
#include <sizes.h>
#include <envfs.h>
@ -36,6 +39,37 @@
#include <mach/generic.h>
#include <mach/bbu.h>
/*
* This board can have 512MiB, 1GiB or 2GiB of SDRAM. The actual amount of SDRAM
* is detected using mirror detection in lowlevel init and is stored in the first
* SDRAM address from the lowlevel code.
*/
static int dfi_fs700_m60_mem_init(void)
{
u32 memsize;
if (!of_machine_is_compatible("dfi,fs700-m60"))
return 0;
memsize = *(u32 *)0x10000000;
/* play safe if we find some corrupted amount of SDRAM */
switch (memsize) {
case SZ_512M:
case SZ_1G:
case SZ_2G:
break;
default:
pr_err("unknown SDRAM size 0x%08x defaulting to 512MiB\n", memsize);
memsize = SZ_512M;
}
arm_add_mem_device("ram0", 0x10000000, memsize);
return 0;
}
mem_initcall(dfi_fs700_m60_mem_init);
static int ar8031_phy_fixup(struct phy_device *dev)
{
u16 val;
@ -64,13 +98,22 @@ static int ar8031_phy_fixup(struct phy_device *dev)
static int dfi_fs700_m60_init(void)
{
unsigned flag_spi = 0, flag_mmc = 0;
if (!of_machine_is_compatible("dfi,fs700-m60"))
return 0;
phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup);
if (bootsource_get() == BOOTSOURCE_SPI)
flag_spi |= BBU_HANDLER_FLAG_DEFAULT;
else
flag_mmc |= BBU_HANDLER_FLAG_DEFAULT;
imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.boot0",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
flag_mmc, NULL, 0, 0);
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0",
flag_spi, NULL, 0, 0);
armlinux_set_architecture(MACH_TYPE_MX6Q_SABRESD);

130
arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q.imxcfg → arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg
View File

@ -1,128 +1,104 @@
loadaddr 0x27800000
soc imx6
dcdofs 0x400
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05b0 0x00000030
wm 32 0x020e0524 0x00000030
wm 32 0x020e051c 0x00000030
wm 32 0x020e0518 0x00000030
wm 32 0x020e050c 0x00000030
wm 32 0x020e05b8 0x00000030
wm 32 0x020e05c0 0x00000030
wm 32 0x020e05ac 0x00020030
wm 32 0x020e05b4 0x00020030
wm 32 0x020e0528 0x00020030
wm 32 0x020e0520 0x00020030
wm 32 0x020e0514 0x00020030
wm 32 0x020e0510 0x00020030
wm 32 0x020e05bc 0x00020030
wm 32 0x020e05c4 0x00020030
wm 32 0x020e0514 0x00020030
wm 32 0x020e0518 0x00000030
wm 32 0x020e051c 0x00000030
wm 32 0x020e0520 0x00020030
wm 32 0x020e0524 0x00000030
wm 32 0x020e0528 0x00020030
wm 32 0x020e056c 0x00020030
wm 32 0x020e0578 0x00020030
wm 32 0x020e0588 0x00020030
wm 32 0x020e0594 0x00020030
wm 32 0x020e057c 0x00020030
wm 32 0x020e0590 0x00003000
wm 32 0x020e0598 0x00003000
wm 32 0x020e0588 0x00020030
wm 32 0x020e058c 0x00000000
wm 32 0x020e0590 0x00003000
wm 32 0x020e0594 0x00020030
wm 32 0x020e0598 0x00003000
wm 32 0x020e059c 0x00003030
wm 32 0x020e05a0 0x00003030
wm 32 0x020e0784 0x00000030
wm 32 0x020e0788 0x00000030
wm 32 0x020e0794 0x00000030
wm 32 0x020e079c 0x00000030
wm 32 0x020e07a0 0x00000030
wm 32 0x020e07a4 0x00000030
wm 32 0x020e07a8 0x00000030
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05ac 0x00020030
wm 32 0x020e05b0 0x00000030
wm 32 0x020e05b4 0x00020030
wm 32 0x020e05bc 0x00020030
wm 32 0x020e05b8 0x00000030
wm 32 0x020e05c0 0x00000030
wm 32 0x020e05c4 0x00020030
wm 32 0x020e0748 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e0758 0x00000000
wm 32 0x020e0774 0x00020000
wm 32 0x020e0784 0x00000030
wm 32 0x020e0788 0x00000030
wm 32 0x020e078c 0x00000030
wm 32 0x020e0798 0x000C0000
wm 32 0x020e0794 0x00000030
wm 32 0x020e0798 0x000c0000
wm 32 0x020e079c 0x00000030
wm 32 0x020e07a0 0x00000030
wm 32 0x020e07a4 0x00000030
wm 32 0x020e07a8 0x00000030
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
wm 32 0x021b0018 0x00081740
wm 32 0x021b001c 0x00008000
wm 32 0x021b000c 0x555A7974
wm 32 0x021b0010 0xDB538F64
wm 32 0x021b0014 0x01FF00DB
wm 32 0x021b002c 0x000026D2
wm 32 0x021b0030 0x005A1023
wm 32 0x021b000c 0x555a7974
wm 32 0x021b0010 0xdb538f64
wm 32 0x021b0014 0x01ff00db
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 0x005a1023
wm 32 0x021b0008 0x09444040
wm 32 0x021b0004 0x00025576
wm 32 0x021b0040 0x00000027
wm 32 0x021b0000 0x831A0000
wm 32 0x021b0000 0x831a0000
wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x0408803A
wm 32 0x021b001c 0x0408803a
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x0000803B
wm 32 0x021b001c 0x0000803b
wm 32 0x021b001c 0x00428031
wm 32 0x021b001c 0x00428039
wm 32 0x021b001c 0x19308030
wm 32 0x021b001c 0x19308038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
wm 32 0x021b0800 0xA1380003
wm 32 0x021b4800 0xA1380003
wm 32 0x021b0800 0xa1380003
wm 32 0x021b4800 0xa1380003
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00022227
wm 32 0x021b4818 0x00022227
wm 32 0x021b083c 0x434B0350
wm 32 0x021b0840 0x034C0359
wm 32 0x021b483c 0x434B0350
wm 32 0x021b083c 0x434b0350
wm 32 0x021b0840 0x034c0359
wm 32 0x021b483c 0x434b0350
wm 32 0x021b4840 0x03650348
wm 32 0x021b0848 0x4436383B
wm 32 0x021b0848 0x4436383b
wm 32 0x021b4848 0x39393341
wm 32 0x021b0850 0x35373933
wm 32 0x021b4850 0x48254A36
wm 32 0x021b080c 0x001F001F
wm 32 0x021b0810 0x001F001F
wm 32 0x021b4850 0x48254a36
wm 32 0x021b080c 0x001f001f
wm 32 0x021b0810 0x001f001f
wm 32 0x021b480c 0x00440044
wm 32 0x021b4810 0x00440044
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b001c 0x00000000
wm 32 0x021b0404 0x00011006
wm 32 0x020c4068 0x00C03F3F
wm 32 0x020c406c 0x0030FC03
wm 32 0x020c4070 0x0FFFC000
wm 32 0x020c4074 0x3FF00000
wm 32 0x020c4078 0x00FFF300
wm 32 0x020c407c 0x0F0000C3
wm 32 0x020c4080 0x000003FF
wm 32 0x020e0010 0xF00000CF
wm 32 0x020e0018 0x007F007F
wm 32 0x020e001c 0x007F007F
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
wm 32 0x020e0010 0xf00000cf
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f

102
arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg Normal file
View File

@ -0,0 +1,102 @@
loadaddr 0x27800000
soc imx6
dcdofs 0x400
wm 32 0x020e0798 0x000C0000
wm 32 0x020e0758 0x00000000
wm 32 0x020e0588 0x00000030
wm 32 0x020e0594 0x00000030
wm 32 0x020e056c 0x00000030
wm 32 0x020e0578 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e057c 0x00000030
wm 32 0x020e058c 0x00000000
wm 32 0x020e059c 0x00000030
wm 32 0x020e05a0 0x00000030
wm 32 0x020e078c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05b0 0x00000028
wm 32 0x020e0524 0x00000028
wm 32 0x020e051c 0x00000028
wm 32 0x020e0518 0x00000028
wm 32 0x020e050c 0x00000028
wm 32 0x020e05b8 0x00000028
wm 32 0x020e05c0 0x00000028
wm 32 0x020e0774 0x00020000
wm 32 0x020e0784 0x00000028
wm 32 0x020e0788 0x00000028
wm 32 0x020e0794 0x00000028
wm 32 0x020e079c 0x00000028
wm 32 0x020e07a0 0x00000028
wm 32 0x020e07a4 0x00000028
wm 32 0x020e07a8 0x00000028
wm 32 0x020e0748 0x00000028
wm 32 0x020e05ac 0x00000028
wm 32 0x020e05b4 0x00000028
wm 32 0x020e0528 0x00000028
wm 32 0x020e0520 0x00000028
wm 32 0x020e0514 0x00000028
wm 32 0x020e0510 0x00000028
wm 32 0x020e05bc 0x00000028
wm 32 0x020e05c4 0x00000028
wm 32 0x021b0800 0xA1390003
wm 32 0x021b080c 0x001F001F
wm 32 0x021b0810 0x001F001F
wm 32 0x021b480c 0x001F001F
wm 32 0x021b4810 0x001F001F
wm 32 0x021b083c 0x43260335
wm 32 0x021b0840 0x031A030B
wm 32 0x021b483c 0x4323033B
wm 32 0x021b4840 0x0323026F
wm 32 0x021b0848 0x483D4545
wm 32 0x021b4848 0x44433E48
wm 32 0x021b0850 0x41444840
wm 32 0x021b4850 0x4835483E
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b0004 0x00020036
wm 32 0x021b0008 0x09444040
wm 32 0x021b000c 0x8A8F7955
wm 32 0x021b0010 0xFF328F64
wm 32 0x021b0014 0x01FF00DB
wm 32 0x021b0018 0x00001740
wm 32 0x021b001c 0x00008000
wm 32 0x021b002c 0x000026D2
wm 32 0x021b0030 0x008F1023
wm 32 0x021b0040 0x00000047
wm 32 0x021b0000 0x841A0000
wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x00048031
wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x04008040
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00011117
wm 32 0x021b4818 0x00011117
wm 32 0x021b0004 0x00025576
wm 32 0x021b0404 0x00011006
wm 32 0x021b001c 0x00000000

40
arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg
View File

@ -15,40 +15,40 @@ wm 32 0x020e04b4 0x00000030
wm 32 0x020e04b8 0x00000030
wm 32 0x020e076c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e04bc 0x00000030
wm 32 0x020e04c0 0x00000030
wm 32 0x020e04c4 0x00000030
wm 32 0x020e04c8 0x00000030
wm 32 0x020e04bc 0x00000028
wm 32 0x020e04c0 0x00000028
wm 32 0x020e04c4 0x00000028
wm 32 0x020e04c8 0x00000028
wm 32 0x020e0760 0x00020000
wm 32 0x020e0764 0x00000030
wm 32 0x020e0770 0x00000030
wm 32 0x020e0778 0x00000030
wm 32 0x020e077c 0x00000030
wm 32 0x020e0470 0x00000030
wm 32 0x020e0474 0x00000030
wm 32 0x020e0478 0x00000030
wm 32 0x020e047c 0x00000030
wm 32 0x020e0764 0x00000028
wm 32 0x020e0770 0x00000028
wm 32 0x020e0778 0x00000028
wm 32 0x020e077c 0x00000028
wm 32 0x020e0470 0x00000028
wm 32 0x020e0474 0x00000028
wm 32 0x020e0478 0x00000028
wm 32 0x020e047c 0x00000028
wm 32 0x021b0800 0xa1390003
wm 32 0x021b080c 0x001f001f
wm 32 0x021b0810 0x001f001f
wm 32 0x021b083c 0x42190219
wm 32 0x021b0840 0x017b0177
wm 32 0x021b0848 0x4b4d4e4d
wm 32 0x021b0850 0x3f3e2d36
wm 32 0x021b083c 0x421c0216
wm 32 0x021b0840 0x017b017a
wm 32 0x021b0848 0x4b4a4e4c
wm 32 0x021b0850 0x3f3f3334
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b08b8 0x00000800
wm 32 0x021b0004 0x0002002d
wm 32 0x021b0004 0x00020025
wm 32 0x021b0008 0x00333030
wm 32 0x021b000c 0x3f435313
wm 32 0x021b000c 0x676b5313
wm 32 0x021b0010 0xb66e8b63
wm 32 0x021b0014 0x01ff00db
wm 32 0x021b0018 0x00001740
wm 32 0x021b001c 0x00008000
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 0x00431023
wm 32 0x021b0030 0x006b1023
wm 32 0x021b0040 0x00000027
wm 32 0x021b0000 0x84190000
wm 32 0x021b001c 0x04008032
@ -58,6 +58,6 @@ wm 32 0x021b001c 0x05208030
wm 32 0x021b001c 0x04008040
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00011117
wm 32 0x021b0004 0x0002556d
wm 32 0x021b0004 0x00025565
wm 32 0x021b0404 0x00011006
wm 32 0x021b001c 0x00000000

69
arch/arm/boards/dfi-fs700-m60/lowlevel.c
View File

@ -35,6 +35,8 @@ static inline void early_uart_init(void)
writel(0x0000047f, MX6_UART1_BASE_ADDR + 0xa4);
writel(0x0000c34f, MX6_UART1_BASE_ADDR + 0xa8);
writel(0x00000001, MX6_UART1_BASE_ADDR + 0x80);
putc_ll('>');
}
static inline void early_uart_init_6q(void)
@ -59,20 +61,83 @@ static inline void early_uart_init_6s(void)
early_uart_init();
}
static inline unsigned int memsize_512M_1G(void)
{
volatile u32 *a = (u32 *)0x10000000;
volatile u32 *b = (u32 *)0x30000000;
u32 size;
*a = 0x55555555;
*b = 0xaaaaaaaa;
if (*a == 0xaaaaaaaa)
size = SZ_512M;
else
size = SZ_1G;
*a = size;
return size;
}
static inline unsigned int memsize_1G_2G(void)
{
volatile u32 *a = (u32 *)0x10000000;
volatile u32 *b = (u32 *)0x50000000;
u32 size;
*a = 0x55555555;
*b = 0xaaaaaaaa;
if (*a == 0xaaaaaaaa)
size = SZ_1G;
else
size = SZ_2G;
*a = size;
return size;
}
extern char __dtb_imx6q_dfi_fs700_m60_6q_start[];
ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q, r0, r1, r2)
ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1, r2)
{
uint32_t fdt;
int i;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00940000 - 8);
for (i = 0x68; i <= 0x80; i += 4)
writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
early_uart_init_6q();
fdt = (uint32_t)__dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
barebox_arm_entry(0x10000000, memsize_1G_2G(), fdt);
}
ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1, r2)
{
uint32_t fdt;
int i;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00940000 - 8);
for (i = 0x68; i <= 0x80; i += 4)
writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
early_uart_init_6q();
fdt = (uint32_t)__dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
*(uint32_t *)0x10000000 = SZ_1G;
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
@ -94,5 +159,5 @@ ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2)
fdt = (uint32_t)__dtb_imx6dl_dfi_fs700_m60_6s_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
barebox_arm_entry(0x10000000, memsize_512M_1G(), fdt);
}

6
arch/arm/boards/dmo-mx6-realq7/board.c
View File

@ -74,7 +74,7 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
static int realq7_enet_init(void)
{
if (!of_machine_is_compatible("dmo,imx6q-realq7"))
if (!of_machine_is_compatible("dmo,imx6q-edmqmx6"))
return 0;
mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio));
@ -100,7 +100,7 @@ fs_initcall(realq7_enet_init);
static int realq7_env_init(void)
{
if (!of_machine_is_compatible("dmo,imx6q-realq7"))
if (!of_machine_is_compatible("dmo,imx6q-edmqmx6"))
return 0;
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
@ -113,7 +113,7 @@ late_initcall(realq7_env_init);
static int realq7_console_init(void)
{
if (!of_machine_is_compatible("dmo,imx6q-realq7"))
if (!of_machine_is_compatible("dmo,imx6q-edmqmx6"))
return 0;
barebox_set_hostname("eDM-QMX6");

10
arch/arm/boards/dmo-mx6-realq7/lowlevel.c
View File

@ -140,8 +140,8 @@ static void sdram_init(void)
putc_ll('>');
}
extern char __dtb_imx6q_dmo_realq7_start[];
extern char __dtb_imx6q_dmo_realq7_end[];
extern char __dtb_imx6q_dmo_edmqmx6_start[];
extern char __dtb_imx6q_dmo_edmqmx6_end[];
ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
{
@ -151,7 +151,7 @@ ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
arm_setup_stack(0x00940000 - 8);
fdt = (unsigned long)__dtb_imx6q_dmo_realq7_start - get_runtime_offset();
fdt = (unsigned long)__dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset();
if (get_pc() < 0x10000000) {
sdram_init();
@ -164,8 +164,8 @@ ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
* inside valid SDRAM instead of SRAM.
*/
memcpy((void *)sdram, (void *)fdt,
__dtb_imx6q_dmo_realq7_end -
__dtb_imx6q_dmo_realq7_start);
__dtb_imx6q_dmo_edmqmx6_start -
__dtb_imx6q_dmo_edmqmx6_end);
fdt = sdram;
}

2
arch/arm/boards/efika-mx-smartbook/env/config vendored
View File

@ -20,7 +20,7 @@ global.autoboot_timeout=1
#global.boot.default=net
# base bootargs
global.linux.bootargs.base="console=ttymxc0,115200 console=tty1"
global.linux.bootargs.base="console=tty1"
# suitable for 800MHz
global linux.bootargs.lpj="lpj=3997696"

10
arch/arm/boards/eukrea_cpuimx25/lowlevel.c
View File

@ -127,12 +127,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12);
imx25_barebox_boot_nand_external();
#endif
imx25_barebox_boot_nand_external(0);
}
out:
imx25_barebox_entry(0);
}

5
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
View File

@ -123,12 +123,13 @@ barebox_arm_reset_vector:
1:
sdram_init
#ifdef CONFIG_NAND_IMX_BOOT
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* Setup a temporary stack in SDRAM */
ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
mov r0, #0
b imx27_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
b imx27_barebox_entry

21
arch/arm/boards/eukrea_cpuimx35/lowlevel.c
View File

@ -130,18 +130,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
imx35_barebox_boot_nand_external(0);
}
imx35_barebox_boot_nand_external();
#endif
out:
imx35_barebox_entry(0);
}

6
arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
View File

@ -97,12 +97,14 @@ barebox_arm_reset_vector:
ldr r3, ESDCTL_DELAY5
str r3, [r0, #0x30]
#ifdef CONFIG_NAND_IMX_BOOT
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* Setup a temporary stack in SRAM */
ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
mov r0, #0
b imx25_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
b imx25_barebox_entry

5
arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
View File

@ -154,12 +154,13 @@ barebox_arm_reset_vector:
ldr r3, =ESDCTL_DELAY_LINE5
str r3, [r0, #0x30]
#ifdef CONFIG_NAND_IMX_BOOT
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* Setup a temporary stack in internal SRAM */
ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
mov r0, #0
b imx35_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
b imx35_barebox_entry

9
arch/arm/boards/freescale-mx51-pdk/board.c
View File

@ -141,21 +141,14 @@ static void babbage_power_init(void)
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = 0x208;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
#define GPIO_LAN8700_RESET (1 * 32 + 14)
/* Reset the ethernet controller over GPIO */
gpio_direction_output(GPIO_LAN8700_RESET, 0);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
gpio_set_value(GPIO_LAN8700_RESET, 1);
mdelay(50);
}
extern char flash_header_imx51_babbage_start[];

13
arch/arm/boards/freescale-mx53-loco/lowlevel.c
View File

@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2)
imx53_barebox_entry(fdt);
}
extern char __dtb_imx53_qsrb_start[];
ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset();
imx53_barebox_entry(fdt);
}

3
arch/arm/boards/freescale-mx53-vmx53/board.c
View File

@ -30,6 +30,9 @@ extern char flash_header_imx53_vmx53_end[];
static int vmx53_late_init(void)
{
if (!of_machine_is_compatible("voipac,imx53-dmm-668"))
return 0;
armlinux_set_architecture(MACH_TYPE_VMX53);
barebox_set_model("Voipac VMX53");

9
arch/arm/boards/freescale-mx6-sabrelite/board.c
View File

@ -124,7 +124,8 @@ static void sabrelite_ehci_init(void)
static int sabrelite_devices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
!of_machine_is_compatible("fsl,imx6dl-sabrelite"))
return 0;
sabrelite_ehci_init();
@ -140,7 +141,8 @@ device_initcall(sabrelite_devices_init);
static int sabrelite_coredevices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
!of_machine_is_compatible("fsl,imx6dl-sabrelite"))
return 0;
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
@ -151,7 +153,8 @@ coredevice_initcall(sabrelite_coredevices_init);
static int sabrelite_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
!of_machine_is_compatible("fsl,imx6dl-sabrelite"))
return 0;
imx6_init_lowlevel();

15
arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
View File

@ -5,7 +5,7 @@
extern char __dtb_imx6q_sabrelite_start[];
ENTRY_FUNCTION(start_imx6_sabrelite, r0, r1, r2)
ENTRY_FUNCTION(start_imx6q_sabrelite, r0, r1, r2)
{
uint32_t fdt;
@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx6_sabrelite, r0, r1, r2)
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
extern char __dtb_imx6dl_sabrelite_start[];
ENTRY_FUNCTION(start_imx6dl_sabrelite, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6dl_sabrelite_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}

21
arch/arm/boards/guf-cupid/lowlevel.c
View File

@ -306,18 +306,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */
setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00);
#ifdef CONFIG_NAND_IMX_BOOT
/* Speed up NAND controller by adjusting the NFC divider */
r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r0 &= ~(0xf << 28);
r0 |= 0x1 << 28;
writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* Speed up NAND controller by adjusting the NFC divider */
r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r0 &= ~(0xf << 28);
r0 |= 0x1 << 28;
writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
imx35_barebox_boot_nand_external(0);
}
imx35_barebox_boot_nand_external();
#endif
out:
imx35_barebox_entry(0);
}

11
arch/arm/boards/guf-neso/lowlevel.c
View File

@ -86,12 +86,13 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call imx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* setup a stack to be able to call imx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
imx27_barebox_boot_nand_external(0);
}
imx27_barebox_boot_nand_external();
#endif
out:
imx27_barebox_entry(0);
}

5
arch/arm/boards/imx21ads/lowlevel_init.S
View File

@ -118,12 +118,13 @@ barebox_arm_reset_vector:
ldr r1, =0x6419a007
str r1, [r0]
#ifdef CONFIG_NAND_IMX_BOOT
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND {
/* Setup a temporary stack in SRAM */
ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4
b imx21_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
mov r0, #0xc0000000

134
arch/arm/boards/karo-tx25/board.c
View File

@ -17,6 +17,8 @@
*
*/
#define pr_fmt(fmt) "tx25: " fmt
#include <common.h>
#include <init.h>
#include <driver.h>
@ -31,131 +33,69 @@
#include <partition.h>
#include <generated/mach-types.h>
#include <mach/imx-nand.h>
#include <fec.h>
#include <nand.h>
#include <mach/iomux-mx25.h>
#include <mach/generic.h>
#include <mach/iim.h>
#include <linux/err.h>
#include <mach/devices-imx25.h>
#include <mach/bbu.h>
#include <asm/mmu.h>
static struct fec_platform_data fec_info = {
.xcv_type = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0x1f,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static iomux_v3_cfg_t karo_tx25_padsd_fec[] = {
MX25_PAD_D11__GPIO_4_9, /* FEC PHY power on pin */
MX25_PAD_D13__GPIO_4_7, /* FEC reset */
MX25_PAD_FEC_MDC__FEC_MDC,
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_TDATA0__FEC_TDATA0,
MX25_PAD_FEC_TDATA1__FEC_TDATA1,
MX25_PAD_FEC_TX_EN__FEC_TX_EN,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
};
#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
static struct gpio fec_gpios[] = {
{
.gpio = TX25_FEC_PWR_GPIO,
.flags = GPIOF_OUT_INIT_LOW,
.label = "fec-pwr",
}, {
.gpio = TX25_FEC_RST_GPIO,
.flags = GPIOF_OUT_INIT_LOW,
.label = "fec-rst",
},
};
static void noinline gpio_fec_active(void)
{
mxc_iomux_v3_setup_multiple_pads(karo_tx25_padsd_fec,
ARRAY_SIZE(karo_tx25_padsd_fec));
int ret;
/* power down phy, put into reset */
gpio_direction_output(TX25_FEC_PWR_GPIO, 0);
gpio_direction_output(TX25_FEC_RST_GPIO, 0);
ret = gpio_request_array(fec_gpios, ARRAY_SIZE(fec_gpios));
if (ret) {
pr_err("Failed to request fec gpios: %s\n", strerror(-ret));
return;
}
udelay(10);
/* power up phy, get out of reset */
gpio_direction_output(TX25_FEC_PWR_GPIO, 1);
gpio_direction_output(TX25_FEC_RST_GPIO, 1);
/* power up phy, but leave in reset */
gpio_set_value(TX25_FEC_PWR_GPIO, 1);
udelay(100);
/* apply a reset to the powered phy again */
gpio_direction_output(TX25_FEC_RST_GPIO, 0);
udelay(100);
gpio_direction_output(TX25_FEC_RST_GPIO, 1);
/* FEC driver picks up the reset gpio later */
gpio_free(TX25_FEC_RST_GPIO);
}
static int tx25_devices_init(void)
static int tx25_init(void)
{
if (!of_machine_is_compatible("karo,imx25-tx25"))
return 0;
gpio_fec_active();
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
add_mem_device("sram0", 0x78000000, 128 * 1024,
IORESOURCE_MEM_WRITEABLE);
barebox_set_hostname("tx25");
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}
device_initcall(tx25_devices_init);
static iomux_v3_cfg_t tx25_pads[] = {
MX25_PAD_D12__GPIO_4_8,
MX25_PAD_D10__GPIO_4_10,
MX25_PAD_NF_CE0__NF_CE0,
MX25_PAD_NFWE_B__NFWE_B,
MX25_PAD_NFRE_B__NFRE_B,
MX25_PAD_NFALE__NFALE,
MX25_PAD_NFCLE__NFCLE,
MX25_PAD_NFWP_B__NFWP_B,
MX25_PAD_NFRB__NFRB,
MX25_PAD_D7__D7,
MX25_PAD_D6__D6,
MX25_PAD_D5__D5,
MX25_PAD_D4__D4,
MX25_PAD_D3__D3,
MX25_PAD_D2__D2,
MX25_PAD_D1__D1,
MX25_PAD_D0__D0,
MX25_PAD_UART1_TXD__UART1_TXD,
MX25_PAD_UART1_RXD__UART1_RXD,
MX25_PAD_UART1_CTS__UART1_CTS,
MX25_PAD_UART1_RTS__UART1_RTS,
};
static int tx25_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(tx25_pads, ARRAY_SIZE(tx25_pads));
barebox_set_model("Ka-Ro TX25");
barebox_set_hostname("tx25");
imx25_add_uart0();
return 0;
}
console_initcall(tx25_console_init);
console_initcall(tx25_init);
static iomux_v3_cfg_t tx25_lcdc_gpios[] = {
MX25_PAD_A18__GPIO_2_4, /* LCD Reset (active LOW) */
@ -232,6 +172,12 @@ static struct imx_fb_platform_data tx25_fb_data = {
static int tx25_init_fb(void)
{
if (!IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX))
return 0;
if (!of_machine_is_compatible("karo,imx25-tx25"))
return 0;
tx25_fb_enable(0);
mxc_iomux_v3_setup_multiple_pads(tx25_lcdc_gpios,

2
arch/arm/boards/karo-tx25/env/init/mtdparts-nand vendored
View File

@ -5,7 +5,7 @@ if [ "$1" = menu ]; then
exit
fi
mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

23
arch/arm/boards/karo-tx25/lowlevel.c
View File

@ -75,7 +75,7 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
writel(esdctl, esdctlreg);
}
void __bare_init __naked barebox_arm_reset_vector(void)
static void __bare_init karo_tx25_common_init(uint32_t fdt)
{
uint32_t r;
@ -157,12 +157,21 @@ void __bare_init __naked barebox_arm_reset_vector(void)
setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);
setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
imx25_barebox_boot_nand_external(fdt);
out:
imx25_barebox_entry(fdt);
}
extern char __dtb_imx25_karo_tx25_start[];
ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2)
{
uint32_t fdt;
arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
imx25_barebox_boot_nand_external();
#endif
out:
imx25_barebox_entry(0);
fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset();
karo_tx25_common_init(fdt);
}

14
arch/arm/boards/pcm037/lowlevel.c
View File

@ -125,12 +125,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
#endif
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call imx31_barebox_boot_nand_external() */
arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* setup a stack to be able to call imx31_barebox_boot_nand_external() */
arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
imx31_barebox_boot_nand_external();
#else
imx31_barebox_entry(0);
#endif
imx31_barebox_boot_nand_external(0);
} else {
imx31_barebox_entry(0);
}
}

10
arch/arm/boards/pcm038/lowlevel.c
View File

@ -93,12 +93,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call mx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* setup a stack to be able to call mx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
imx27_barebox_boot_nand_external();
#endif
imx27_barebox_boot_nand_external(0);
}
out:
imx27_barebox_entry(0);
}

21
arch/arm/boards/pcm043/lowlevel.c
View File

@ -182,18 +182,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* enable Auto-Refresh */
writel(0x00002000, esdctl_base + IMX_ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
imx35_barebox_boot_nand_external(0);
}
imx35_barebox_boot_nand_external();
#endif
out:
imx35_barebox_entry(0);
}

2
arch/arm/boards/phycard-i.MX27/Makefile
View File

@ -1,3 +1,3 @@
lwl-y += lowlevel_init.o
lwl-y += lowlevel.o
obj-y += pca100.o

48
arch/arm/boards/phycard-i.MX27/env/config vendored
View File

@ -1,48 +0,0 @@
#!/bin/sh
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp', 'nor' or 'nand'
kernel_loc=tftp
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-${global.hostname}.$rootfs_type
kernelimage=zImage-${global.hostname}
#kernelimage=uImage-${global.hostname}
#kernelimage=Image-${global.hostname}
#kernelimage=Image-${global.hostname}.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

103
arch/arm/boards/phycard-i.MX27/lowlevel.c Normal file
View File

@ -0,0 +1,103 @@
/*
* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
* Applications Processor Reference Manual, Rev. 0.2".
*
*/
#include <common.h>
#include <init.h>
#include <io.h>
#include <config.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <mach/imx-nand.h>
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
static void sdram_init(void)
{
int i;
/*
* DDR on CSD0
*/
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
/* Set the driving strength */
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* precharge CSD0 all banks */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
void __bare_init __naked barebox_arm_reset_vector(void)
{
unsigned long r;
arm_cpu_lowlevel_init();
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0xa0000000 && r < 0xc0000000)
imx27_barebox_entry(0);
/* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
sdram_init();
imx27_barebox_boot_nand_external(0);
}

119
arch/arm/boards/phycard-i.MX27/lowlevel_init.S
View File

@ -1,119 +0,0 @@
/*
* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
* Applications Processor Reference Manual, Rev. 0.2".
*
*/
#include <config.h>
#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
#define writel(val, reg) \
ldr r0, =reg; \
ldr r1, =val; \
str r1, [r0];
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
.macro sdram_init
/*
* DDR on CSD0
*/
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
/* Set the driving strength */
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
/* precharge CSD0 all banks */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
mov r2, #8
1:
str r1, [r0]
subs r2, #1
bne 1b
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
ldr r0, =0xA1000000
mov r1, #0xff
strb r1, [r0]
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
.endm
.section ".text_bare_init","ax"
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
bl arm_cpu_lowlevel_init
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
bls 1f
cmp pc, #0xc0000000
bhi 1f
b imx27_barebox_entry
1:
/* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR)
sdram_init
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
b imx27_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
ret:
b imx27_barebox_entry

175
arch/arm/boards/phycard-i.MX27/pca100.c
View File

@ -21,6 +21,7 @@
#include <mach/imx27-regs.h>
#include <fec.h>
#include <gpio.h>
#include <sizes.h>
#include <asm/armlinux.h>
#include <asm/sections.h>
#include <generated/mach-types.h>
@ -36,97 +37,10 @@
#include <gpio.h>
#include <asm/mmu.h>
#include <usb/ulpi.h>
#include <mach/bbu.h>
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct fec_platform_data fec_info = {
.xcv_type = PHY_INTERFACE_MODE_MII,
.phy_addr = 1,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct imx_fb_videomode imxfb_mode[] = {
{
.mode = {
.name = "Primeview-PD050VL1",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 40000, /* in ps (25MHz) */
.hsync_len = 32,
.left_margin = 112,
.right_margin = 36,
.vsync_len = 2,
.upper_margin = 33,
.lower_margin = 33,
},
.pcr = 0xF0C88080,
.bpp = 16,
}, {
.mode = {
.name = "Primeview-PD035VL1",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 40000, /* in ps (25 MHz) */
.hsync_len = 30,
.left_margin = 98,
.right_margin = 36,
.vsync_len = 2,
.upper_margin = 15,
.lower_margin = 33,
},
.pcr = 0xF0C88080,
.bpp = 16,
}, {
.mode = {
.name = "Primeview-PD104SLF",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000, /* in ps (40,0 MHz) */
.hsync_len = 40,
.left_margin = 174,
.right_margin = 174,
.vsync_len = 4,
.upper_margin = 24,
.lower_margin = 23,
},
.pcr = 0xF0C88080,
.bpp = 16,
}, {
.mode = {
.name = "Primeview-PM070WL4",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 31250, /* in ps (32 MHz) */
.hsync_len = 40,
.left_margin = 174,
.right_margin = 174,
.vsync_len = 2,
.upper_margin = 33,
.lower_margin = 23,
},
.pcr = 0xF0C88080,
.bpp = 16,
},
};
static struct imx_fb_platform_data pca100_fb_data = {
.mode = imxfb_mode,
.num_modes = ARRAY_SIZE(imxfb_mode),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00040060,
};
#ifdef CONFIG_USB
static void pca100_usb_register(void)
{
mdelay(10);
@ -141,7 +55,6 @@ static void pca100_usb_register(void)
ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
}
#endif
static void pca100_usb_init(void)
{
@ -178,38 +91,7 @@ static void pca100_usb_init(void)
static int pca100_devices_init(void)
{
int i;
struct device_d *nand;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
PD26_PF_CSPI1_SS2,
PD27_PF_CSPI1_SS1,
PD28_PF_CSPI1_SS0,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
@ -223,13 +105,6 @@ static int pca100_devices_init(void)
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
@ -242,33 +117,6 @@ static int pca100_devices_init(void)
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA26_PF_PS,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
/* external I2C */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
};
pca100_usb_init();
@ -277,21 +125,11 @@ static int pca100_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
imx27_add_nand(&nand_info);
imx27_add_fec(&fec_info);
imx27_add_mmc1(NULL);
imx27_add_fb(&pca100_fb_data);
if (IS_ENABLED(CONFIG_USB))
pca100_usb_register();
#ifdef CONFIG_USB
pca100_usb_register();
#endif
nand = get_device_by_name("nand0");
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
BBU_HANDLER_FLAG_DEFAULT);
armlinux_set_architecture(2149);
@ -305,7 +143,6 @@ static int pca100_console_init(void)
barebox_set_model("Phytec phyCARD-i.MX27");
barebox_set_hostname("phycard-imx27");
imx27_add_uart0();
return 0;
}

3
arch/arm/boards/solidrun-carrier-1/Makefile
View File

@ -1,3 +0,0 @@
obj-y += board.o flash-header-solidrun-carrier-1.dcd.o
extra-y += flash-header-solidrun-carrier-1.dcd.S flash-header-solidrun-carrier-1.dcd
lwl-y += lowlevel.o

18
arch/arm/boards/solidrun-carrier-1/lowlevel.c
View File

@ -1,18 +0,0 @@
#include <common.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
extern char __dtb_imx6dl_cubox_i_carrier_1_start[];
ENTRY_FUNCTION(start_imx6dl_cubox_i_carrier_1, r0, r1, r2)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6dl_cubox_i_carrier_1_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_512M, fdt);
}

3
arch/arm/boards/solidrun-hummingboard/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += board.o flash-header-solidrun-hummingboard.dcd.o
extra-y += flash-header-solidrun-hummingboard.dcd.S flash-header-solidrun-hummingboard.dcd
lwl-y += lowlevel.o

14
arch/arm/boards/solidrun-carrier-1/board.c → arch/arm/boards/solidrun-hummingboard/board.c
View File

@ -60,9 +60,9 @@ static int ar8035_phy_fixup(struct phy_device *dev)
return 0;
}
static int carrier1_device_init(void)
static int hummingboard_device_init(void)
{
if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1"))
if (!of_machine_is_compatible("solidrun,hummingboard"))
return 0;
phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
@ -73,17 +73,17 @@ static int carrier1_device_init(void)
return 0;
}
device_initcall(carrier1_device_init);
device_initcall(hummingboard_device_init);
static int carrier1_lwl_init(void)
static int hummingboard_lwl_init(void)
{
if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1"))
if (!of_machine_is_compatible("solidrun,hummingboard"))
return 0;
barebox_set_hostname("carrier-1");
barebox_set_hostname("hummingboard");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(carrier1_lwl_init);
postcore_initcall(hummingboard_lwl_init);

0
arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg → arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg
View File

16
arch/arm/boards/solidrun-hummingboard/lowlevel.c Normal file
View File

@ -0,0 +1,16 @@
#include <common.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
extern char __dtb_imx6dl_hummingboard_start[];
ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6dl_hummingboard_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_512M, fdt);
}

1
arch/arm/boards/tqma53/Makefile
View File

@ -1,3 +1,2 @@
obj-y += board.o
lwl-y += flash_header.o
lwl-y += lowlevel.o

247
arch/arm/boards/tqma53/board.c
View File

@ -13,251 +13,32 @@
*
*/
#include <common.h>
#include <environment.h>
#include <fcntl.h>
#include <fec.h>
#include <fs.h>
#include <bootsource.h>
#include <common.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <sizes.h>
#include <gpio.h>
#include <mci.h>
#include <io.h>
#include <asm/armlinux.h>
#include <asm/mmu.h>
#include <generated/mach-types.h>
#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx5.h>
static struct fec_platform_data fec_info = {
.xcv_type = PHY_INTERFACE_MODE_RMII,
};
static iomux_v3_cfg_t tqma53_pads[] = {
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
MX53_PAD_KEY_ROW2__CAN1_RXCAN,
MX53_PAD_KEY_COL2__CAN1_TXCAN,
MX53_PAD_KEY_ROW4__CAN2_RXCAN,
MX53_PAD_KEY_COL4__CAN2_TXCAN,
MX53_PAD_GPIO_19__CCM_CLKO,
MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK,
MX53_PAD_SD1_DATA0__CSPI_MISO,
MX53_PAD_SD1_CMD__CSPI_MOSI,
MX53_PAD_SD1_CLK__CSPI_SCLK,
MX53_PAD_SD1_DATA1__CSPI_SS0,
MX53_PAD_SD1_DATA2__CSPI_SS1,
MX53_PAD_SD1_DATA3__CSPI_SS2,
MX53_PAD_EIM_D17__ECSPI1_MISO,
MX53_PAD_EIM_D18__ECSPI1_MOSI,
MX53_PAD_EIM_D16__ECSPI1_SCLK,
MX53_PAD_EIM_EB2__ECSPI1_SS0,
MX53_PAD_EIM_D19__ECSPI1_SS1,
MX53_PAD_EIM_D24__ECSPI1_SS2,
MX53_PAD_EIM_D25__ECSPI1_SS3,
MX53_PAD_GPIO_4__ESDHC2_CD,
MX53_PAD_SD2_CLK__ESDHC2_CLK,
MX53_PAD_SD2_CMD__ESDHC2_CMD,
MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
MX53_PAD_GPIO_2__ESDHC2_WP,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_FEC_MDC__FEC_MDC,
MX53_PAD_FEC_MDIO__FEC_MDIO,
MX53_PAD_FEC_RXD0__FEC_RDATA_0,
MX53_PAD_FEC_RXD1__FEC_RDATA_1,
MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
MX53_PAD_FEC_RX_ER__FEC_RX_ER,
MX53_PAD_FEC_TXD0__FEC_TDATA_0,
MX53_PAD_FEC_TXD1__FEC_TDATA_1,
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
MX53_PAD_FEC_TX_EN__FEC_TX_EN,
MX53_PAD_GPIO_7__FIRI_RXD,
MX53_PAD_GPIO_8__FIRI_TXD,
MX53_PAD_GPIO_0__GPIO1_0,
MX53_PAD_GPIO_3__GPIO1_3,
MX53_PAD_PATA_DATA14__GPIO2_14,
MX53_PAD_PATA_DATA15__GPIO2_15,
MX53_PAD_EIM_CS0__GPIO2_23,
MX53_PAD_EIM_OE__GPIO2_25,
MX53_PAD_EIM_RW__GPIO2_26,
MX53_PAD_EIM_LBA__GPIO2_27,
MX53_PAD_PATA_DATA5__GPIO2_5,
MX53_PAD_PATA_DATA6__GPIO2_6,
MX53_PAD_PATA_DATA7__GPIO2_7,
MX53_PAD_EIM_DA11__GPIO3_11,
MX53_PAD_EIM_DA12__GPIO3_12,
MX53_PAD_EIM_DA13__GPIO3_13,
MX53_PAD_EIM_DA14__GPIO3_14,
MX53_PAD_EIM_D20__GPIO3_20,
MX53_PAD_EIM_D21__GPIO3_21,
MX53_PAD_EIM_D22__GPIO3_22,
MX53_PAD_EIM_D28__GPIO3_28,
MX53_PAD_EIM_D29__GPIO3_29,
MX53_PAD_EIM_WAIT__GPIO5_0,
MX53_PAD_PATA_DA_1__GPIO7_7,
MX53_PAD_PATA_DA_2__GPIO7_8,
MX53_PAD_KEY_COL3__I2C2_SCL,
MX53_PAD_KEY_ROW3__I2C2_SDA,
MX53_PAD_GPIO_5__I2C3_SCL,
MX53_PAD_GPIO_6__I2C3_SDA,
MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10,
MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11,
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4,
MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5,
MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6,
MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7,
MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8,
MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9,
MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN,
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
MX53_PAD_EIM_D23__IPU_DI1_PIN2,
MX53_PAD_EIM_EB3__IPU_DI1_PIN3,
MX53_PAD_EIM_DA15__IPU_DI1_PIN4,
MX53_PAD_EIM_CS1__IPU_DI1_PIN6,
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
MX53_PAD_GPIO_18__OWIRE_LINE,
MX53_PAD_GPIO_1__PWM2_PWMO,
MX53_PAD_GPIO_16__SPDIF_IN1,
MX53_PAD_GPIO_17__SPDIF_OUT1,
MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
MX53_PAD_PATA_INTRQ__UART2_CTS,
MX53_PAD_PATA_DIOR__UART2_RTS,
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
/* SD2 card detect */
MX53_PAD_GPIO_4__GPIO1_4,
/* SD2 write protect */
MX53_PAD_GPIO_2__GPIO1_2,
/* phy reset */
MX53_PAD_PATA_DA_0__GPIO7_6,
};
#define GPIO_FEC_NRESET IMX_GPIO_NR(7, 6)
#define GPIO_SD2_CD IMX_GPIO_NR(1, 4)
#define GPIO_SD2_WP IMX_GPIO_NR(1, 2)
static struct esdhc_platform_data tqma53_sd2_data = {
.cd_gpio = GPIO_SD2_CD,
.wp_gpio = GPIO_SD2_WP,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_GPIO,
};
static struct esdhc_platform_data tqma53_sd3_data = {
.cd_type = ESDHC_CD_PERMANENT,
.wp_type = ESDHC_WP_NONE,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
};
static int tqma53_devices_init(void)
{
gpio_direction_output(GPIO_FEC_NRESET, 0);
mdelay(1);
gpio_set_value(GPIO_FEC_NRESET, 1);
char *of_env_path = "/chosen/environment-emmc";
imx53_iim_register_fec_ethaddr();
imx53_add_fec(&fec_info);
imx53_add_mmc1(&tqma53_sd2_data);
imx53_add_mmc2(&tqma53_sd3_data);
if (!of_machine_is_compatible("tq,tqma53"))
return 0;
barebox_set_model("TQ tqma53");
barebox_set_hostname("tqma53");
if (bootsource_get() == BOOTSOURCE_MMC &&
bootsource_get_instance() == 1)
of_env_path = "/chosen/environment-sd";
of_device_enable_path(of_env_path);
armlinux_set_architecture(MACH_TYPE_TQMA53);
return 0;
}
device_initcall(tqma53_devices_init);
static int tqma53_part_init(void)
{
devfs_add_partition("disk0", 0x00000, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
late_initcall(tqma53_part_init);
static int tqma53_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(tqma53_pads, ARRAY_SIZE(tqma53_pads));
barebox_set_model("TQ tqma53");
barebox_set_hostname("tqma53");
imx53_add_uart1();
return 0;
}
console_initcall(tqma53_console_init);

5
arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg Normal file
View File

@ -0,0 +1,5 @@
#define SETUP_512MIB_1GIB \
wm 32 0x63fd9018 0x00011740; \
wm 32 0x63fd9000 0xc3190000
#include "flash-header-tq-tqma53.h"

5
arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg Normal file
View File

@ -0,0 +1,5 @@
#define SETUP_512MIB_1GIB \
wm 32 0x63fd9018 0x00101740; \
wm 32 0x63fd9000 0x83190000
#include "flash-header-tq-tqma53.h"

61
arch/arm/boards/tqma53/flash-header-tq-tqma53.h Normal file
View File

@ -0,0 +1,61 @@
soc imx53
loadaddr 0x70000000
dcdofs 0x400
/* IOMUX */
wm 32 0x53fa8554 0x00300000
wm 32 0x53fa8558 0x00300040
wm 32 0x53fa8560 0x00300000
wm 32 0x53fa8564 0x00300040
wm 32 0x53fa8568 0x00300040
wm 32 0x53fa8570 0x00300000
wm 32 0x53fa8574 0x00300000
wm 32 0x53fa8578 0x00300000
wm 32 0x53fa857c 0x00300040
wm 32 0x53fa8580 0x00300040
wm 32 0x53fa8584 0x00300000
wm 32 0x53fa8588 0x00300000
wm 32 0x53fa8590 0x00300040
wm 32 0x53fa8594 0x00300000
wm 32 0x53fa86f0 0x00300000
wm 32 0x53fa86f4 0x00000000
wm 32 0x53fa86fc 0x00000000
wm 32 0x53fa8714 0x00000000
wm 32 0x53fa8718 0x00300000
wm 32 0x53fa871c 0x00300000
wm 32 0x53fa8720 0x00300000
wm 32 0x53fa8724 0x04000000
wm 32 0x53fa8728 0x00300000
wm 32 0x53fa872c 0x00300000
/* ESDCTL */
wm 32 0x63fd9088 0x35343535
wm 32 0x63fd9090 0x4d444c44
wm 32 0x63fd907c 0x01370138
wm 32 0x63fd9080 0x013b013c
wm 32 0x63fd90f8 0x00000800
SETUP_512MIB_1GIB
wm 32 0x63fd900c 0x9f5152e3
wm 32 0x63fd9010 0xb68e8a63
wm 32 0x63fd9014 0x01ff00db
wm 32 0x63fd902c 0x000026d2
/* Engcm12377 / errata sheet 03/2013 */
wm 32 0x63fd9030 0x009f0e23
wm 32 0x63fd9008 0x12273030
wm 32 0x63fd9004 0x0002002d
wm 32 0x63fd901c 0x00008032
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00028031
wm 32 0x63fd901c 0x052080b0
wm 32 0x63fd901c 0x04008040
wm 32 0x63fd901c 0x0000803a
wm 32 0x63fd901c 0x0000803b
wm 32 0x63fd901c 0x00028039
wm 32 0x63fd901c 0x05208138
wm 32 0x63fd901c 0x04008048
wm 32 0x63fd9020 0x00005800
/* prevent reserved value, use default TZQ_CS */
wm 32 0x63fd9040 0x05380003
wm 32 0x63fd9058 0x00022227
wm 32 0x63fd901C 0x00000000

113
arch/arm/boards/tqma53/flash_header.c
View File

@ -1,113 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
/* IOMUX */
{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
/* ESDCTL */
{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
{ .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
#ifdef CONFIG_MACH_TQMA53_1GB_RAM
/* sync with u-boot: add WALAT for 4 chip variant */
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
#else
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00101740), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x83190000), },
#endif
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
/* Engcm12377 / errata sheet 03/2013 */
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e23), },
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
/* prevent reserved value, use default TZQ_CS */
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x05380003), },
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
{ .addr = cpu_to_be32(0x63fd901C), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST 0x70000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = DCD_BAREBOX_SIZE,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

62
arch/arm/boards/tqma53/lowlevel.c
View File

@ -1,11 +1,65 @@
#include <common.h>
#include <debug_ll.h>
#include <io.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/imx5.h>
void __naked barebox_arm_reset_vector(void)
extern char __dtb_imx53_mba53_start[];
static inline void setup_uart(void __iomem *base)
{
arm_cpu_lowlevel_init();
imx53_init_lowlevel_early(800);
imx53_barebox_entry(0);
/* Enable UART for lowlevel debugging purposes */
writel(0x00000000, base + 0x80);
writel(0x00004027, base + 0x84);
writel(0x00000704, base + 0x88);
writel(0x00000a81, base + 0x90);
writel(0x0000002b, base + 0x9c);
writel(0x0001046a, base + 0xb0);
writel(0x0000047f, base + 0xa4);
writel(0x0000a2c1, base + 0xa8);
writel(0x00000001, base + 0x80);
}
static void __noreturn start_imx53_tqma53_common(uint32_t fdt)
{
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
setup_uart((void *)MX53_UART2_BASE_ADDR);
putc_ll('>');
}
imx53_barebox_entry(fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
imx53_init_lowlevel_early(800);
fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
imx53_init_lowlevel_early(800);
fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}

6
arch/arm/configs/imx_v7_defconfig
View File

@ -3,12 +3,16 @@ CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
CONFIG_MACH_FREESCALE_MX51_PDK=y
CONFIG_MACH_FREESCALE_MX53_LOCO=y
CONFIG_MACH_TQMA53=y
CONFIG_MACH_FREESCALE_MX53_VMX53=y
CONFIG_MACH_PHYTEC_PFLA02=y
CONFIG_MACH_DFI_FS700_M60=y
CONFIG_MACH_REALQ7=y
CONFIG_MACH_GK802=y
CONFIG_MACH_TQMA6X=y
CONFIG_MACH_SOLIDRUN_CARRIER1=y
CONFIG_MACH_SABRELITE=y
CONFIG_MACH_NITROGEN6X=y
CONFIG_MACH_SOLIDRUN_HUMMINGBOARD=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_IMX_OCOTP=y

51
arch/arm/configs/pca100_defconfig
View File

@ -1,58 +1,70 @@
CONFIG_BUILTIN_DTB=y
CONFIG_BUILTIN_DTB_NAME="imx27-phytec-phycard-s-rdk"
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX27=y
CONFIG_MACH_PCA100=y
CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x01000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-i.MX27/env"
CONFIG_MENU=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH=""
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_CMD_TFTP=y
CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
@ -62,9 +74,18 @@ CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_UBI=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MCI=y
CONFIG_MCI_IMX=y
CONFIG_IMX_WEIM=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_FS_UBIFS=y
CONFIG_FS_UBIFS_COMPRESSION_LZO=y

19
arch/arm/configs/tqma53_defconfig
View File

@ -1,5 +1,5 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX53=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TQMA53=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
@ -7,13 +7,17 @@ CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_TEXT_BASE=0x0
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_RELOCATABLE=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tqma53/env/"
CONFIG_DEBUG_INFO=y
@ -25,8 +29,6 @@ CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BASENAME=y
CONFIG_CMD_DIRNAME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
@ -38,20 +40,27 @@ CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MCI=y

21
arch/arm/configs/tx25stk5_defconfig
View File

@ -1,13 +1,10 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX25=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TX25=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x91d00000
CONFIG_MALLOC_SIZE=0x1000000
@ -17,6 +14,7 @@ CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx25/env"
CONFIG_RESET_SOURCE=y
@ -28,9 +26,7 @@ CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_DIRNAME=y
CONFIG_CMD_LN=y
CONFIG_CMD_READLINK=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
@ -40,7 +36,6 @@ CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
@ -51,10 +46,10 @@ CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OFTREE_PROBE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
@ -63,18 +58,22 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_CMD_WD=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_UBI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_WATCHDOG=y

25
arch/arm/dts/Makefile
View File

@ -2,20 +2,28 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-phytec-phycore.dtb
dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb
dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \
imx27-phytec-phycard-s-som.dtb
dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb \
dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-qsrb.dtb \
imx53-voipac-bsb.dtb
dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6dl-dfi-fs700-m60-6s.dtb \
imx6q-dfi-fs700-m60-6q.dtb \
imx6q-dmo-realq7.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-sabrelite.dtb \
imx6dl-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6dl-mba6x.dtb \
imx6q-mba6x.dtb \
imx6q-phytec-pbab01.dtb \
imx6dl-cubox-i-carrier-1.dtb
imx6dl-hummingboard.dtb \
imx6q-nitrogen6x.dtb \
imx6dl-nitrogen6x.dtb
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb
@ -29,21 +37,24 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o
pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o
pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
pbl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += imx6dl-cubox-i-carrier-1.dtb.o
pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o
pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))

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arch/arm/dts/imx25-karo-tx25.dts Normal file
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/*
* Copyright 2012 Sascha Hauer, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx25.dtsi"
/ {
model = "Ka-Ro TX25";
compatible = "karo,imx25-tx25", "fsl,imx25";
chosen {
linux,stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
device-path = &nfc, "partname:environment";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_fec_phy: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "fec-phy";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 9 0>;
};
};
memory {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX25_PAD_NF_CE0__NF_CE0 0x80000000
MX25_PAD_NFWE_B__NFWE_B 0x80000000
MX25_PAD_NFRE_B__NFRE_B 0x80000000
MX25_PAD_NFALE__NFALE 0x80000000
MX25_PAD_NFCLE__NFCLE 0x80000000
MX25_PAD_NFWP_B__NFWP_B 0x80000000
MX25_PAD_NFRB__NFRB 0x80000000
MX25_PAD_D7__D7 0x80000000
MX25_PAD_D6__D6 0x80000000
MX25_PAD_D5__D5 0x80000000
MX25_PAD_D4__D4 0x80000000
MX25_PAD_D3__D3 0x80000000
MX25_PAD_D2__D2 0x80000000
MX25_PAD_D1__D1 0x80000000
MX25_PAD_D0__D0 0x80000000
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-reset-gpios = <&gpio4 7 0>;
phy-mode = "rmii";
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&iim {
barebox,provide-mac-address = <&fec 0 26>;
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
#address-cells = <1>;
#size-cells = <1>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-bus-width = <8>;
status = "okay";
partition@0 {
label = "boot";
reg = <0x0 0x80000>;
};
partition@1 {
label = "environment";
reg = <0x80000 0x80000>;
};
partition@2 {
label = "kernel";
reg = <0x100000 0x400000>;
};
partition@3 {
label = "root";
reg = <0x500000 0x7b00000>;
};
};

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/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
* Based on imx35-pinfunc.h in the same directory Which is:
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX25_PINFUNC_H
#define __DTS_IMX25_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000
#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000
#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000
#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000
#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000
#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000
#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000
#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000
#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000
#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000
#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000
#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000
#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000
#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000
#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000
#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000
#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000
#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000
#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000
#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000
#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000
#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000
#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000
#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000
#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000
#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000
#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000
#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000
#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000
#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000
#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000
#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000
#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000
#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000
#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000
#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000
#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000
#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000
#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000
#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000
#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000
#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000
#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000
#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000
#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000
#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000
#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000
#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000
#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000
#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000
#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000
#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000
#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000
#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000
#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000
#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000
#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000
#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000
#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000
#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000
#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000
#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000
#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000
#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000
#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001
#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000
#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000
#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001
#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000
#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000
#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000
#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000
#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001
#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000
#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000
#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000
#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000
#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
#endif /* __DTS_IMX25_PINFUNC_H */

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/*
* Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc2 = &esdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
spi0 = &spi1;
spi1 = &spi2;
spi2 = &spi3;
usb0 = &usbotg;
usb1 = &usbhost1;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm926ej-s";
device_type = "cpu";
};
};
asic: asic-interrupt-controller@68000000 {
compatible = "fsl,imx25-asic", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x68000000 0x8000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&asic>;
ranges;
aips@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x43f00000 0x100000>;
ranges;
i2c1: i2c@43f80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f80000 0x4000>;
clocks = <&clks 48>;
clock-names = "";
interrupts = <3>;
status = "disabled";
};
i2c3: i2c@43f84000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f84000 0x4000>;
clocks = <&clks 48>;
clock-names = "";
interrupts = <10>;
status = "disabled";
};
can1: can@43f88000 {
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
reg = <0x43f88000 0x4000>;
interrupts = <43>;
clocks = <&clks 75>, <&clks 75>;
clock-names = "ipg", "per";
status = "disabled";
};
can2: can@43f8c000 {
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
reg = <0x43f8c000 0x4000>;
interrupts = <44>;
clocks = <&clks 76>, <&clks 76>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@43f90000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 120>, <&clks 57>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@43f94000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x43f94000 0x4000>;
interrupts = <32>;
clocks = <&clks 121>, <&clks 57>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@43f98000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f98000 0x4000>;
clocks = <&clks 48>;
clock-names = "";
interrupts = <4>;
status = "disabled";
};
owire@43f9c000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x43f9c000 0x4000>;
clocks = <&clks 51>;
clock-names = "";
interrupts = <2>;
status = "disabled";
};
spi1: cspi@43fa4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
reg = <0x43fa4000 0x4000>;
clocks = <&clks 62>, <&clks 62>;
clock-names = "ipg", "per";
interrupts = <14>;
status = "disabled";
};
kpp@43fa8000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x43fa8000 0x4000>;
clocks = <&clks 102>;
clock-names = "";
interrupts = <24>;
status = "disabled";
};
iomuxc: iomuxc@43fac000 {
compatible = "fsl,imx25-iomuxc";
reg = <0x43fac000 0x4000>;
};
audmux: audmux@43fb0000 {
compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
reg = <0x43fb0000 0x4000>;
status = "disabled";
};
};
spba@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
spi3: cspi@50004000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
reg = <0x50004000 0x4000>;
interrupts = <0>;
clocks = <&clks 80>, <&clks 80>;
clock-names = "ipg", "per";
status = "disabled";
};
uart4: serial@50008000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x50008000 0x4000>;
interrupts = <5>;
clocks = <&clks 123>, <&clks 57>;
clock-names = "ipg", "per";
status = "disabled";
};
uart3: serial@5000c000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <18>;
clocks = <&clks 122>, <&clks 57>;
clock-names = "ipg", "per";
status = "disabled";
};
spi2: cspi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
reg = <0x50010000 0x4000>;
clocks = <&clks 79>, <&clks 79>;
clock-names = "ipg", "per";
interrupts = <13>;
status = "disabled";
};
ssi2: ssi@50014000 {
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <11>;
clocks = <&clks 118>;
clock-names = "ipg";
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
esai@50018000 {
reg = <0x50018000 0x4000>;
interrupts = <7>;
};
uart5: serial@5002c000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x5002c000 0x4000>;
interrupts = <40>;
clocks = <&clks 124>, <&clks 57>;
clock-names = "ipg", "per";
status = "disabled";
};
tsc: tsc@50030000 {
compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
reg = <0x50030000 0x4000>;
interrupts = <46>;
clocks = <&clks 119>;
clock-names = "ipg";
status = "disabled";
};
ssi1: ssi@50034000 {
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50034000 0x4000>;
interrupts = <12>;
clocks = <&clks 117>;
clock-names = "ipg";
dmas = <&sdma 28 1 0>,
<&sdma 29 1 0>;
dma-names = "rx", "tx";
status = "disabled";
};
fec: ethernet@50038000 {
compatible = "fsl,imx25-fec";
reg = <0x50038000 0x4000>;
interrupts = <57>;
clocks = <&clks 88>, <&clks 65>;
clock-names = "ipg", "ahb";
status = "disabled";
};
};
aips@53f00000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x53f00000 0x100000>;
ranges;
clks: ccm@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
gpt4: timer@53f84000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f84000 0x4000>;
clocks = <&clks 9>, <&clks 45>;
clock-names = "ipg", "per";
interrupts = <1>;
};
gpt3: timer@53f88000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f88000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <29>;
};
gpt2: timer@53f8c000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f8c000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <53>;
};
gpt1: timer@53f90000 {
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
reg = <0x53f90000 0x4000>;
clocks = <&clks 9>, <&clks 47>;
clock-names = "ipg", "per";
interrupts = <54>;
};
epit1: timer@53f94000 {
compatible = "fsl,imx25-epit";
reg = <0x53f94000 0x4000>;
interrupts = <28>;
};
epit2: timer@53f98000 {
compatible = "fsl,imx25-epit";
reg = <0x53f98000 0x4000>;
interrupts = <27>;
};
gpio4: gpio@53f9c000 {
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
reg = <0x53f9c000 0x4000>;
interrupts = <23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pwm2: pwm@53fa0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
reg = <0x53fa0000 0x4000>;
clocks = <&clks 106>, <&clks 36>;
clock-names = "ipg", "per";
interrupts = <36>;
};
gpio3: gpio@53fa4000 {
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
reg = <0x53fa4000 0x4000>;
interrupts = <16>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pwm3: pwm@53fa8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
reg = <0x53fa8000 0x4000>;
clocks = <&clks 107>, <&clks 36>;
clock-names = "ipg", "per";
interrupts = <41>;
};
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <9>;
clocks = <&clks 86>, <&clks 63>, <&clks 45>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc2: esdhc@53fb8000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
clocks = <&clks 87>, <&clks 64>, <&clks 46>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
lcdc: lcdc@53fbc000 {
compatible = "fsl,imx25-fb", "fsl,imx21-fb";
reg = <0x53fbc000 0x4000>;
interrupts = <39>;
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
slcdc@53fc0000 {
reg = <0x53fc0000 0x4000>;
interrupts = <38>;
status = "disabled";
};
pwm4: pwm@53fc8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
reg = <0x53fc8000 0x4000>;
clocks = <&clks 108>, <&clks 36>;
clock-names = "ipg", "per";
interrupts = <42>;
};
gpio1: gpio@53fcc000 {
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
reg = <0x53fcc000 0x4000>;
interrupts = <52>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@53fd0000 {
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
reg = <0x53fd0000 0x4000>;
interrupts = <51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sdma: sdma@53fd4000 {
compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
interrupts = <34>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
};
wdog@53fdc000 {
compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
reg = <0x53fdc000 0x4000>;
clocks = <&clks 126>;
clock-names = "";
interrupts = <55>;
};
pwm1: pwm@53fe0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
reg = <0x53fe0000 0x4000>;
clocks = <&clks 105>, <&clks 36>;
clock-names = "ipg", "per";
interrupts = <26>;
};
iim: iim@53ff0000 {
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
clocks = <&clks 99>;
};
usbphy1: usbphy@1 {
compatible = "nop-usbphy";
status = "disabled";
};
usbphy2: usbphy@2 {
compatible = "nop-usbphy";
status = "disabled";
};
usbotg: usb@53ff4000 {
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>;
interrupts = <37>;
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbhost1: usb@53ff4400 {
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>;
interrupts = <35>;
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbmisc: usbmisc@53ff4600 {
#index-cells = <1>;
compatible = "fsl,imx25-usbmisc";
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>;
};
dryice@53ffc000 {
compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
reg = <0x53ffc000 0x4000>;
clocks = <&clks 81>;
clock-names = "ipg";
interrupts = <25>;
};
};
iram: sram@78000000 {
compatible = "mmio-sram";
reg = <0x78000000 0x20000>;
};
emi@80000000 {
compatible = "fsl,emi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x3b002000>;
ranges;
nfc: nand@bb000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx25-nand";
reg = <0xbb000000 0x2000>;
clocks = <&clks 50>;
clock-names = "";
interrupts = <33>;
status = "disabled";
};
};
};
};

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/*
* Copyright 2012 Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-phytec-phycard-s-som.dts"
/ {
model = "Phytec pca100 rapid development kit";
compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
display: display {
model = "Primeview-PD050VL1";
native-mode = <&timing0>;
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
timing0: 640x480 {
hactive = <640>;
vactive = <480>;
hback-porch = <112>;
hfront-porch = <36>;
hsync-len = <32>;
vback-porch = <33>;
vfront-porch = <33>;
vsync-len = <2>;
clock-frequency = <25000000>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&fb {
display = <&display>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
adc@64 {
compatible = "maxim,max1037";
vcc-supply = <&reg_3v3>;
reg = <0x64>;
};
};
&iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX27_I2C2_PINGRP1>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <MX27_OWIRE1_PINGRP1>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <MX27_SDHC2_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_UART1_PINGRP1
MX27_UART1_RTSCTS_PINGRP1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_UART2_PINGRP1
MX27_UART2_RTSCTS_PINGRP1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_UART3_PINGRP1
MX27_UART3_RTSCTS_PINGRP1
>;
};
};
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire1>;
status = "okay";
};
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc2>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};

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/*
* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
* and Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
chosen {
linux,stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
device-path = &nfc, "partname:environment";
};
};
memory {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
};
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp {
fsl,pins = <MX27_FEC1_PINGRP1>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX27_I2C2_PINGRP1>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <MX27_NFC_PINGRP1>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
partition@0 {
label = "boot";
reg = <0x0 0x80000>;
};
partition@1 {
label = "environment";
reg = <0x80000 0x80000>;
};
partition@2 {
label = "kernel";
reg = <0x100000 0x400000>;
};
partition@3 {
label = "root";
reg = <0x500000 0x7b00000>;
};
};

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/*
* Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DTS_IMX27_PINFUNC_H
#define __DTS_IMX27_PINFUNC_H
/*
* The pin function ID is a tuple of
* <pin mux_id>
* mux_id consists of
* function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
*
* function: 0 - Primary function
* 1 - Alternate function
* 2 - GPIO
* direction: 0 - Input
* 1 - Output
* gpio_oconf: 0 - A_IN
* 1 - B_IN
* 2 - C_IN
* 3 - Data Register
* gpio_iconfa/b: 0 - GPIO_IN
* 1 - Interrupt Status Register
* 2 - 0
* 3 - 1
*
* 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
* number on the specific port (between 0 and 31).
*/
#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032
#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032
#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032
#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032
#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032
#define MX27_PAD_LD0__LD0 0x06 0x004
#define MX27_PAD_LD0__GPIO1_6 0x06 0x032
#define MX27_PAD_LD1__LD1 0x07 0x004
#define MX27_PAD_LD1__GPIO1_7 0x07 0x032
#define MX27_PAD_LD2__LD2 0x08 0x004
#define MX27_PAD_LD2__GPIO1_8 0x08 0x032
#define MX27_PAD_LD3__LD3 0x09 0x004
#define MX27_PAD_LD3__GPIO1_9 0x09 0x032
#define MX27_PAD_LD4__LD4 0x0a 0x004
#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032
#define MX27_PAD_LD5__LD5 0x0b 0x004
#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032
#define MX27_PAD_LD6__LD6 0x0c 0x004
#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032
#define MX27_PAD_LD7__LD7 0x0d 0x004
#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032
#define MX27_PAD_LD8__LD8 0x0e 0x004
#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032
#define MX27_PAD_LD9__LD9 0x0f 0x004
#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032
#define MX27_PAD_LD10__LD10 0x10 0x004
#define MX27_PAD_LD10__GPIO1_16 0x10 0x032
#define MX27_PAD_LD11__LD11 0x11 0x004
#define MX27_PAD_LD11__GPIO1_17 0x11 0x032
#define MX27_PAD_LD12__LD12 0x12 0x004
#define MX27_PAD_LD12__GPIO1_18 0x12 0x032
#define MX27_PAD_LD13__LD13 0x13 0x004
#define MX27_PAD_LD13__GPIO1_19 0x13 0x032
#define MX27_PAD_LD14__LD14 0x14 0x004
#define MX27_PAD_LD14__GPIO1_20 0x14 0x032
#define MX27_PAD_LD15__LD15 0x15 0x004
#define MX27_PAD_LD15__GPIO1_21 0x15 0x032
#define MX27_PAD_LD16__LD16 0x16 0x004
#define MX27_PAD_LD16__GPIO1_22 0x16 0x032
#define MX27_PAD_LD17__LD17 0x17 0x004
#define MX27_PAD_LD17__GPIO1_23 0x17 0x032
#define MX27_PAD_REV__REV 0x18 0x004
#define MX27_PAD_REV__GPIO1_24 0x18 0x032
#define MX27_PAD_CLS__CLS 0x19 0x004
#define MX27_PAD_CLS__GPIO1_25 0x19 0x032
#define MX27_PAD_PS__PS 0x1a 0x004
#define MX27_PAD_PS__GPIO1_26 0x1a 0x032
#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032
#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032
#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032
#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032
#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032
#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032
#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032
#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032
#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032
#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032
#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032
#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032
#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032
#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032
#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032
#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032
#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032
#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032
#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032
#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032
#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032
#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032
#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032
#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032
#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032
#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032
#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032
#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032
#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032
#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032
#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032
#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032
#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032
#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032
#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032
#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032
#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032
#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032
#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032
#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032
#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032
#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032
#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032
#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032
#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032
#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032
#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032
#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032
#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032
#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032
#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032
#define MX27_PAD_TOUT__TOUT 0x4e 0x004
#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032
#define MX27_PAD_TIN__TIN 0x4f 0x000
#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032
#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032
#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032
#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032
#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032
#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032
#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032
#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032
#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032
#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032
#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032
#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032
#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032
#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032
#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032
#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032
#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032
#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032
#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032
#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032
#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032
#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032
#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032
#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032
#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032
#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032
#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032
#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032
#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032
#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032
#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032
#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032
#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032
#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032
#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032
#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032
#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032
#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032
#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032
#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032
#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032
#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032
#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032
#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032
#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032
#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032
#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032
#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032
#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032
#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032
#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032
#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032
#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032
#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032
#define MX27_PAD_PWMO__PWMO 0x85 0x004
#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032
#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032
#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032
#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032
#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032
#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032
#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032
#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032
#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032
#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032
#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032
#define MX27_PAD_RTCK__RTCK 0x90 0x004
#define MX27_PAD_RTCK__OWIRE 0x90 0x005
#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032
#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032
#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032
#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032
#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032
#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032
#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032
#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032
#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032
#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032
#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032
#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032
#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032
#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032
#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032
#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032
#define MX27_PAD_NFRB__NFRB 0xa0 0x000
#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032
#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032
#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032
#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032
#define MX27_PAD_NFALE__NFALE 0xa4 0x004
#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032
#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032
#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032
#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032
#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032
#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032
#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032
#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032
#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032
#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032
#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032
#define MX27_PAD_CLKO__CLKO 0xaf 0x004
#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032
#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032
#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032
#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032
#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032
#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032
#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032
#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032
#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032
#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032
#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032
#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032
#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032
#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032
#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032
#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032
#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032
#endif /* __DTS_IMX27_PINFUNC_H */

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/*
* Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DTS_IMX27_PINGRP_H
#define __DTS_IMX27_PINGRP_H
#include "imx27-pinfunc.h"
#define MX27_CSPI1_PINGRP1 \
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
#define MX27_CSPI2_PINGRP1 \
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
#define MX27_CSPI3_PINGRP1 \
MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \
MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \
MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0
#define MX27_FB_PINGRP1 \
MX27_PAD_CLS__CLS 0x0 \
MX27_PAD_CONTRAST__CONTRAST 0x0 \
MX27_PAD_LD0__LD0 0x0 \
MX27_PAD_LD1__LD1 0x0 \
MX27_PAD_LD2__LD2 0x0 \
MX27_PAD_LD3__LD3 0x0 \
MX27_PAD_LD4__LD4 0x0 \
MX27_PAD_LD5__LD5 0x0 \
MX27_PAD_LD6__LD6 0x0 \
MX27_PAD_LD7__LD7 0x0 \
MX27_PAD_LD8__LD8 0x0 \
MX27_PAD_LD9__LD9 0x0 \
MX27_PAD_LD10__LD10 0x0 \
MX27_PAD_LD11__LD11 0x0 \
MX27_PAD_LD12__LD12 0x0 \
MX27_PAD_LD13__LD13 0x0 \
MX27_PAD_LD14__LD14 0x0 \
MX27_PAD_LD15__LD15 0x0 \
MX27_PAD_LD16__LD16 0x0 \
MX27_PAD_LD17__LD17 0x0 \
MX27_PAD_LSCLK__LSCLK 0x0 \
MX27_PAD_OE_ACD__OE_ACD 0x0 \
MX27_PAD_PS__PS 0x0 \
MX27_PAD_REV__REV 0x0 \
MX27_PAD_SPL_SPR__SPL_SPR 0x0 \
MX27_PAD_HSYNC__HSYNC 0x0 \
MX27_PAD_VSYNC__VSYNC 0x0
#define MX27_FEC1_PINGRP1 \
MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \
MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \
MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \
MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \
MX27_PAD_ATA_DATA13__FEC_COL 0x0 \
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
#define MX27_I2C1_PINGRP1 \
MX27_PAD_I2C_DATA__I2C_DATA 0x0 \
MX27_PAD_I2C_CLK__I2C_CLK 0x0
#define MX27_I2C2_PINGRP1 \
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
#define MX27_NFC_PINGRP1 \
MX27_PAD_NFRB__NFRB 0x0 \
MX27_PAD_NFCLE__NFCLE 0x0 \
MX27_PAD_NFWP_B__NFWP_B 0x0 \
MX27_PAD_NFCE_B__NFCE_B 0x0 \
MX27_PAD_NFALE__NFALE 0x0 \
MX27_PAD_NFRE_B__NFRE_B 0x0 \
MX27_PAD_NFWE_B__NFWE_B 0x0
#define MX27_OWIRE1_PINGRP1 \
MX27_PAD_RTCK__OWIRE 0x0
#define MX27_PWM_PINGRP1 \
MX27_PAD_PWMO__PWMO 0x0
#define MX27_SDHC1_PINGRP1 \
MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
MX27_PAD_SD1_D0__SD1_D0 0x0 \
MX27_PAD_SD1_D1__SD1_D1 0x0 \
MX27_PAD_SD1_D2__SD1_D2 0x0 \
MX27_PAD_SD1_D3__SD1_D3 0x0
#define MX27_SDHC2_PINGRP1 \
MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
MX27_PAD_SD2_D0__SD2_D0 0x0 \
MX27_PAD_SD2_D1__SD2_D1 0x0 \
MX27_PAD_SD2_D2__SD2_D2 0x0 \
MX27_PAD_SD2_D3__SD2_D3 0x0
#define MX27_SDHC3_PINGRP1 \
MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
MX27_PAD_SD3_D0__SD3_D0 0x0 \
MX27_PAD_SD3_D1__SD3_D1 0x0 \
MX27_PAD_SD3_D2__SD3_D2 0x0 \
MX27_PAD_SD3_D3__SD3_D3 0x0
#define MX27_UART1_PINGRP1 \
MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
MX27_PAD_UART1_RXD__UART1_RXD 0x0
#define MX27_UART1_RTSCTS_PINGRP1 \
MX27_PAD_UART1_CTS__UART1_CTS 0x0 \
MX27_PAD_UART1_RTS__UART1_RTS 0x0
#define MX27_UART2_PINGRP1 \
MX27_PAD_UART2_TXD__UART2_TXD 0x0 \
MX27_PAD_UART2_RXD__UART2_RXD 0x0
#define MX27_UART2_RTSCTS_PINGRP1 \
MX27_PAD_UART2_CTS__UART2_CTS 0x0 \
MX27_PAD_UART2_RTS__UART2_RTS 0x0
#define MX27_UART3_PINGRP1 \
MX27_PAD_UART3_TXD__UART3_TXD 0x0 \
MX27_PAD_UART3_RXD__UART3_RXD 0x0
#define MX27_UART3_RTSCTS_PINGRP1 \
MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
MX27_PAD_UART3_RTS__UART3_RTS 0x0
#endif /* __DTS_IMX27_PINGRP_H */

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/*
* Copyright 2012 Sascha Hauer, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx27-pingrp.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
i2c0 = &i2c1;
i2c1 = &i2c2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
spi0 = &cspi1;
spi1 = &cspi2;
spi2 = &cspi3;
};
aitc: aitc-interrupt-controller@e0000000 {
compatible = "fsl,imx27-aitc", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10040000 0x1000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock";
clock-frequency = <26000000>;
};
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
operating-points = <
/* kHz uV */
266000 1300000
399000 1450000
>;
clock-latency = <62500>;
clocks = <&clks 18>;
voltage-tolerance = <5>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&aitc>;
ranges;
aipi@10000000 { /* AIPI1 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10000000 0x20000>;
ranges;
dma: dma@10001000 {
compatible = "fsl,imx27-dma";
reg = <0x10001000 0x1000>;
interrupts = <32>;
clocks = <&clks 50>, <&clks 70>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
#dma-channels = <16>;
};
wdog: wdog@10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x1000>;
interrupts = <27>;
clocks = <&clks 74>;
};
gpt1: timer@10003000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x10003000 0x1000>;
interrupts = <26>;
clocks = <&clks 46>, <&clks 61>;
clock-names = "ipg", "per";
};
gpt2: timer@10004000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x10004000 0x1000>;
interrupts = <25>;
clocks = <&clks 45>, <&clks 61>;
clock-names = "ipg", "per";
};
gpt3: timer@10005000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x10005000 0x1000>;
interrupts = <24>;
clocks = <&clks 44>, <&clks 61>;
clock-names = "ipg", "per";
};
pwm: pwm@10006000 {
#pwm-cells = <2>;
compatible = "fsl,imx27-pwm";
reg = <0x10006000 0x1000>;
interrupts = <23>;
clocks = <&clks 34>, <&clks 61>;
clock-names = "ipg", "per";
};
kpp: kpp@10008000 {
compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
reg = <0x10008000 0x1000>;
interrupts = <21>;
clocks = <&clks 37>;
status = "disabled";
};
owire: owire@10009000 {
compatible = "fsl,imx27-owire", "fsl,imx21-owire";
reg = <0x10009000 0x1000>;
clocks = <&clks 35>;
status = "disabled";
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks 81>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@1000b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000b000 0x1000>;
interrupts = <19>;
clocks = <&clks 80>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart3: serial@1000c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000c000 0x1000>;
interrupts = <18>;
clocks = <&clks 79>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart4: serial@1000d000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000d000 0x1000>;
interrupts = <17>;
clocks = <&clks 78>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
cspi1: cspi@1000e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";
reg = <0x1000e000 0x1000>;
interrupts = <16>;
clocks = <&clks 53>, <&clks 60>;
clock-names = "ipg", "per";
status = "disabled";
};
cspi2: cspi@1000f000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";
reg = <0x1000f000 0x1000>;
interrupts = <15>;
clocks = <&clks 52>, <&clks 60>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi1: ssi@10010000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
reg = <0x10010000 0x1000>;
interrupts = <14>;
clocks = <&clks 26>;
dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
dma-names = "rx0", "tx0", "rx1", "tx1";
fsl,fifo-depth = <8>;
status = "disabled";
};
ssi2: ssi@10011000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
reg = <0x10011000 0x1000>;
interrupts = <13>;
clocks = <&clks 25>;
dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
dma-names = "rx0", "tx0", "rx1", "tx1";
fsl,fifo-depth = <8>;
status = "disabled";
};
i2c1: i2c@10012000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
reg = <0x10012000 0x1000>;
interrupts = <12>;
clocks = <&clks 40>;
status = "disabled";
};
sdhci1: sdhci@10013000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10013000 0x1000>;
interrupts = <11>;
clocks = <&clks 30>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 7>;
dma-names = "rx-tx";
status = "disabled";
};
sdhci2: sdhci@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <10>;
clocks = <&clks 29>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 6>;
dma-names = "rx-tx";
status = "disabled";
};
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@10015100 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015100 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@10015200 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015200 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@10015300 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015300 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@10015400 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015400 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@10015500 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015500 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
audmux: audmux@10016000 {
compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
reg = <0x10016000 0x1000>;
clocks = <&clks 0>;
clock-names = "audmux";
status = "disabled";
};
cspi3: cspi@10017000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";
reg = <0x10017000 0x1000>;
interrupts = <6>;
clocks = <&clks 51>, <&clks 60>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt4: timer@10019000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x10019000 0x1000>;
interrupts = <4>;
clocks = <&clks 43>, <&clks 61>;
clock-names = "ipg", "per";
};
gpt5: timer@1001a000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x1001a000 0x1000>;
interrupts = <3>;
clocks = <&clks 42>, <&clks 61>;
clock-names = "ipg", "per";
};
uart5: serial@1001b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001b000 0x1000>;
interrupts = <49>;
clocks = <&clks 77>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart6: serial@1001c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001c000 0x1000>;
interrupts = <48>;
clocks = <&clks 78>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@1001d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
reg = <0x1001d000 0x1000>;
interrupts = <1>;
clocks = <&clks 39>;
status = "disabled";
};
sdhci3: sdhci@1001e000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x1001e000 0x1000>;
interrupts = <9>;
clocks = <&clks 28>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 36>;
dma-names = "rx-tx";
status = "disabled";
};
gpt6: timer@1001f000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x1001f000 0x1000>;
interrupts = <2>;
clocks = <&clks 41>, <&clks 61>;
clock-names = "ipg", "per";
};
};
aipi@10020000 { /* AIPI2 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10020000 0x20000>;
ranges;
fb: fb@10021000 {
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
interrupts = <61>;
reg = <0x10021000 0x1000>;
clocks = <&clks 36>, <&clks 65>, <&clks 59>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
coda: coda@10023000 {
compatible = "fsl,imx27-vpu";
reg = <0x10023000 0x0200>;
interrupts = <53>;
clocks = <&clks 57>, <&clks 66>;
clock-names = "per", "ahb";
iram = <&iram>;
};
sahara2: sahara@10025000 {
compatible = "fsl,imx27-sahara";
reg = <0x10025000 0x1000>;
interrupts = <59>;
clocks = <&clks 32>, <&clks 64>;
clock-names = "ipg", "ahb";
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
iim: iim@10028000 {
compatible = "fsl,imx27-iim";
reg = <0x10028000 0x1000>;
interrupts = <62>;
clocks = <&clks 38>;
};
fec: ethernet@1002b000 {
compatible = "fsl,imx27-fec";
reg = <0x1002b000 0x4000>;
interrupts = <50>;
clocks = <&clks 48>, <&clks 67>;
clock-names = "ipg", "ahb";
status = "disabled";
};
};
nfc: nand@d8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx27-nand";
reg = <0xd8000000 0x1000>;
interrupts = <29>;
clocks = <&clks 54>;
status = "disabled";
};
weim: weim@d8002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx27-weim";
reg = <0xd8002000 0x1000>;
clocks = <&clks 0>;
ranges = <
0 0 0xc0000000 0x08000000
1 0 0xc8000000 0x08000000
2 0 0xd0000000 0x02000000
3 0 0xd2000000 0x02000000
4 0 0xd4000000 0x02000000
5 0 0xd6000000 0x02000000
>;
status = "disabled";
};
iram: iram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
};
};

149
arch/arm/dts/imx51-babbage.dts
View File

@ -35,7 +35,21 @@
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
native-mode = <&timing0>;
timing0: dvi {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
display@di1 {
@ -43,7 +57,26 @@
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
pinctrl-0 = <&pinctrl_ipu_disp2>;
status = "disabled";
display-timings {
native-mode = <&timing1>;
timing1: claawvga {
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
@ -51,7 +84,7 @@
power {
label = "Power Button";
gpios = <&gpio2 21 0>;
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -70,11 +103,25 @@
mux-int-port = <2>;
mux-ext-port = <3>;
};
clocks {
ckih1 {
clock-frequency = <22579200>;
};
clk_26M: codec_clock {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <26000000>;
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
pinctrl-0 = <&pinctrl_esdhc1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
@ -89,24 +136,25 @@
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
pmic: mc13892@0 {
@ -117,7 +165,7 @@
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 0x4>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
regulators {
sw1_reg: sw1 {
@ -240,7 +288,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx51-babbage {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
@ -250,34 +298,93 @@
MX51_PAD_EIM_A27__GPIO2_21 0x5
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
MX51_PAD_EIM_A20__GPIO2_14 0x85
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX51_AUDMUX_PINGRP1>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <MX51_ECSPI1_PINGRP1>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <MX51_ESDHC1_PINGRP1>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <MX51_ESDHC2_PINGRP1>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_FEC_PINGRP1
MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX51_I2C2_PINGRP1>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <MX51_IPU_DISP1_PINGRP1>;
};
pinctrl_ipu_disp2: ipudisp2grp {
fsl,pins = <MX51_IPU_DISP2_PINGRP1>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <MX51_KPP_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX51_UART1_PINGRP1>;
};
pinctrl_uart1_rtscts: uart1rtsctsgrp {
fsl,pins = <MX51_UART1_RTSCTS_PINGRP1>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX51_UART2_PINGRP1>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <MX51_UART3_PINGRP1>;
};
pinctrl_uart3_rtscts: uart3rtsctsgrp {
fsl,pins = <MX51_UART3_RTSCTS_PINGRP1>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <26000000>;
clocks = <&clk_26M>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
@ -285,20 +392,22 @@
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <0x00000067 /* KEY_UP */
0x0001006c /* KEY_DOWN */
0x00020072 /* KEY_VOLUMEDOWN */

156
arch/arm/dts/imx51-genesi-efika-sb.dts
View File

@ -38,33 +38,37 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
mail {
label = "mail";
gpios = <&gpio1 3 1>;
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
white {
label = "white";
gpios = <&gpio2 25 0>;
gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keys>;
power {
label = "Power";
gpios = <&gpio2 31 0>;
gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
lid {
label = "Lid";
gpios = <&gpio3 14 0>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
@ -78,8 +82,7 @@
model = "imx51-efikasb-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"Headphone Jack", "HP_OUT";
audio-routing = "Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
@ -101,52 +104,115 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx51-genesi-efika-sb {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_EIM_DTACK__GPIO2_31 0x800000c0 /* Power button */
MX51_PAD_EIM_A16__GPIO2_10 0x80000000 /* WLAN reset */
MX51_PAD_EIM_A22__GPIO2_16 0x80000000 /* WLAN power */
MX51_PAD_CSI2_D13__GPIO4_10 0x80000000 /* WWAN power? */
MX51_PAD_DI1_PIN12__GPIO3_1 0x80000000 /* WLAN switch */
MX51_PAD_EIM_A17__GPIO2_11 0x80000000 /* Bluetooth power */
MX51_PAD_EIM_A23__GPIO2_17 0x80000000 /* Audio amp enable, 1 = on */
MX51_PAD_GPIO1_6__REF_EN_B 0x80000000 /* PMIC interrupt */
MX51_PAD_DI1_PIN11__GPIO3_0 0x80000000 /* Battery low */
MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* Power good */
MX51_PAD_CSI1_VSYNC__GPIO3_14 0x80000000 /* Lid switch, 0 = closed */
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
MX51_PAD_CSI1_D8__GPIO3_12 0x80000000 /* LVDS enable, 1 = on */
MX51_PAD_GPIO1_2__GPIO1_2 0x80000000 /* Backlight PWM */
MX51_PAD_CSI2_D19__GPIO4_12 0x80000000 /* Backlight power, 0 = on */
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x80000000 /* LVDS reset, 1 = reset */
MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x80000000 /* LVDS reset (1 = reset) */
MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x80000000 /* LVDS power, 1 = on */
MX51_PAD_CSI1_D9__GPIO3_13 0x80000000 /* LCD enable (1 = on */
MX51_PAD_NANDF_CS0__GPIO3_16 0x80000000 /* Camera power, 0 = on */
MX51_PAD_GPIO1_5__GPIO1_5 0x80000000 /* USB hub reset, 0 = reset */
MX51_PAD_EIM_D27__GPIO2_9 0x80000000 /* USB phy reset, 0 = reset */
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x80000000 /* Battery, 0 = inserted */
MX51_PAD_GPIO1_3__GPIO1_3 0x80000000 /* Alarm LED, 0 = on */
MX51_PAD_EIM_CS0__GPIO2_25 0x80000000 /* Caps LED, 1 = on */
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 /* Audio clk enable */
MX51_PAD_EIM_A26__GPIO2_20 0x80000000
MX51_PAD_USBH1_STP__GPIO1_27 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX51_AUDMUX_PINGRP1>;
};
pinctrl_battery: batterygrp {
fsl,pins = <
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0xe5 /* Battery */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_ECSPI1_PINGRP1
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* PMIC IRQ */
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_ESDHC1_PINGRP1
MX51_PAD_GPIO1_1__GPIO1_1 0xe5 /* WP */
MX51_PAD_EIM_CS2__GPIO2_27 0xe5 /* CD */
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_ESDHC2_PINGRP1
MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* WP */
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* CD */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX51_I2C2_PINGRP1>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <MX51_IPU_DISP1_PINGRP1>;
};
pinctrl_keys: keysgrp {
fsl,pins = <
MX51_PAD_EIM_DTACK__GPIO2_31 0xe5 /* Power btn */
MX51_PAD_CSI1_VSYNC__GPIO3_14 0xe5 /* Lid switch */
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX51_PAD_GPIO1_3__GPIO1_3 0x85 /* Alarm LED */
MX51_PAD_EIM_CS0__GPIO2_25 0x85 /* Caps LED */
>;
};
pinctrl_pata: patagrp {
fsl,pins = <MX51_PATA_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_UART1_PINGRP1
MX51_UART1_RTSCTS_PINGRP1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <MX51_USBH1_PINGRP1>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <MX51_USBH2_PINGRP1>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
@ -161,34 +227,36 @@
battery: battery@0b {
compatible = "sbs,sbs-battery";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_battery>;
reg = <0x0b>;
sbs,battery-detect-gpios = <&gpio3 6 1>;
sbs,battery-detect-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
lvds: mtl017@3a {
compatible = "mtl017";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
reg = <0x3a>;
crtcs = <&ipu 1>;
edid-i2c = <&i2c2>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio2 27 0>;
wp-gpios = <&gpio1 1 0>;
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 8 0>;
wp-gpios = <&gpio1 7 0>;
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
@ -200,23 +268,22 @@
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 23 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <20000000>;
reg = <0>;
spi-cs-high;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio1>;
interrupts = <6 0x4>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
regulators {
sw1_reg: sw1 {
@ -321,34 +388,31 @@
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&pata {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pata_1>;
pinctrl-0 = <&pinctrl_pata>;
status = "okay";
};
&usbotg {
barebox,phy_type = "utmi_wide";
phy_type = "ulpi";
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_1>;
barebox,phy_type = "ulpi";
pinctrl-0 = <&pinctrl_usbh1>;
phy_type = "ulpi";
status = "okay";
};
&usbh2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh2_1>;
barebox,phy_type = "ulpi";
pinctrl-0 = <&pinctrl_usbh2>;
phy_type = "ulpi";
status = "okay";
};

249
arch/arm/dts/imx51-pingrp.h Normal file
View File

@ -0,0 +1,249 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX51_PINGRP_H
#define __DTS_IMX51_PINGRP_H
#include "imx51-pinfunc.h"
#define MX51_AUDMUX_PINGRP1 \
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 \
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 \
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 \
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
#define MX51_FEC_PINGRP1 \
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 \
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 \
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 \
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 \
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 \
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 \
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 \
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 \
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 \
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 \
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 \
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 \
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 \
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 \
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 \
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 \
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
#define MX51_FEC_PINGRP2 \
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 \
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 \
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 \
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 \
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 \
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 \
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 \
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 \
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 \
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 \
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 \
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 \
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 \
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 \
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 \
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 \
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 \
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
#define MX51_ECSPI1_PINGRP1 \
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 \
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 \
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
#define MX51_ECSPI2_PINGRP1 \
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 \
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 \
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
#define MX51_ESDHC1_PINGRP1 \
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 \
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 \
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 \
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 \
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 \
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
#define MX51_ESDHC2_PINGRP1 \
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 \
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 \
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 \
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 \
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 \
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
#define MX51_I2C1_PINGRP1 \
MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed \
MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
#define MX51_I2C2_PINGRP1 \
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed \
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
#define MX51_I2C2_PINGRP2 \
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed \
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
#define MX51_I2C2_PINGRP3 \
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed \
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
#define MX51_IPU_DISP1_PINGRP1 \
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 \
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 \
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 \
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 \
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 \
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 \
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 \
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 \
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 \
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 \
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 \
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 \
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 \
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 \
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 \
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 \
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 \
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 \
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 \
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 \
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 \
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 \
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 \
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 \
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 \
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
#define MX51_IPU_DISP2_PINGRP1 \
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 \
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 \
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 \
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 \
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 \
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 \
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 \
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 \
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 \
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 \
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 \
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 \
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 \
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 \
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 \
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 \
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 \
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 \
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 \
MX51_PAD_DI_GP4__DI2_PIN15 0x5
#define MX51_KPP_PINGRP1 \
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 \
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 \
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 \
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 \
MX51_PAD_KEY_COL0__KEY_COL0 0xe8 \
MX51_PAD_KEY_COL1__KEY_COL1 0xe8 \
MX51_PAD_KEY_COL2__KEY_COL2 0xe8 \
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
#define MX51_PATA_PINGRP1 \
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 \
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 \
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 \
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 \
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 \
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 \
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 \
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 \
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 \
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 \
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 \
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 \
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 \
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 \
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 \
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 \
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 \
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 \
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 \
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 \
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 \
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 \
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 \
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 \
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 \
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 \
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 \
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 \
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
#define MX51_UART1_PINGRP1 \
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 \
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
#define MX51_UART1_RTSCTS_PINGRP1 \
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 \
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
#define MX51_UART2_PINGRP1 \
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 \
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
#define MX51_UART3_PINGRP1 \
MX51_PAD_EIM_D25__UART3_RXD 0x1c5 \
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
#define MX51_UART3_RTSCTS_PINGRP1 \
MX51_PAD_EIM_D27__UART3_RTS 0x1c5 \
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
#define MX51_UART3_PINGRP2 \
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 \
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
#define MX51_UART3_RTSCTS_PINGRP2 \
MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 \
MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
#define MX51_USBH1_PINGRP1 \
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 \
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 \
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 \
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 \
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 \
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 \
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 \
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 \
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 \
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 \
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 \
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
#define MX51_USBH2_PINGRP1 \
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 \
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 \
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 \
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 \
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 \
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 \
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 \
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 \
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 \
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 \
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 \
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
#endif /* __DTS_IMX51_PINGRP_H */

465
arch/arm/dts/imx51.dtsi
View File

@ -11,7 +11,10 @@
*/
#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include "imx51-pingrp.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
@ -21,11 +24,6 @@
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
pata0 = &pata;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@ -69,18 +67,32 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 24>;
clock-latency = <62500>;
clocks = <&clks IMX5_CLK_CPU_PODF>;
clock-names = "cpu";
operating-points = <
/* kHz uV (No regulator support) */
160000 0
800000 0
166000 1000000
600000 1050000
800000 1100000
>;
voltage-tolerance = <5>;
};
};
usbphy {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
clock-names = "main_clk";
};
};
@ -101,7 +113,9 @@
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
};
@ -124,7 +138,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@ -133,7 +149,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -143,7 +161,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks 32>, <&clks 33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -154,7 +173,8 @@
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks 51>, <&clks 52>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -163,9 +183,9 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
dmas = <&sdma 24 22 0>,
<&sdma 25 22 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
@ -176,7 +196,9 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -186,25 +208,20 @@
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks 124>;
clock-names = "main_clk";
status = "okay";
};
usbotg: usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
@ -214,7 +231,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
@ -223,7 +240,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@ -232,7 +249,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
@ -241,7 +258,7 @@
#index-cells = <1>;
compatible = "fsl,imx51-usbmisc";
reg = <0x73f80800 0x200>;
clocks = <&clks 108>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
};
gpio1: gpio@73f84000 {
@ -288,7 +305,7 @@
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
@ -296,14 +313,14 @@
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: wdog@73f9c000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks 0>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
@ -311,7 +328,8 @@
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks 36>, <&clks 41>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@ -324,7 +342,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks 37>, <&clks 38>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -333,7 +352,8 @@
#pwm-cells = <2>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks 39>, <&clks 40>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -342,7 +362,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks 28>, <&clks 29>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -351,7 +372,8 @@
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks 30>, <&clks 31>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -381,14 +403,14 @@
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks 107>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
};
owire: owire@83fa4000 {
compatible = "fsl,imx51-owire", "fsl,imx21-owire";
reg = <0x83fa4000 0x4000>;
interrupts = <88>;
clocks = <&clks 159>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
@ -398,7 +420,8 @@
compatible = "fsl,imx51-ecspi";
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks 53>, <&clks 54>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -407,7 +430,8 @@
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks 56>, <&clks 56>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@ -419,7 +443,8 @@
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks 55>, <&clks 55>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -430,7 +455,7 @@
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks 35>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
@ -440,7 +465,7 @@
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks 34>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
@ -448,7 +473,7 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks 48>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
@ -460,6 +485,8 @@
audmux: audmux@83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
clocks = <&clks IMX5_CLK_DUMMY>;
clock-names = "audmux";
status = "disabled";
};
@ -468,7 +495,7 @@
#size-cells = <1>;
compatible = "fsl,imx51-weim";
reg = <0x83fda000 0x1000>;
clocks = <&clks 57>;
clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
ranges = <
0 0 0xb0000000 0x08000000
1 0 0xb8000000 0x08000000
@ -484,7 +511,7 @@
compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>;
clocks = <&clks 60>;
clocks = <&clks IMX5_CLK_NFC_GATE>;
status = "disabled";
};
@ -492,7 +519,7 @@
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 172>;
clocks = <&clks IMX5_CLK_PATA_GATE>;
status = "disabled";
};
@ -500,7 +527,7 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks 50>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
@ -513,336 +540,12 @@
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};
&iomuxc {
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
>;
};
};
ecspi2 {
pinctrl_ecspi2_1: ecspi2grp-1 {
fsl,pins = <
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
>;
};
pinctrl_i2c2_3: i2c2grp-3 {
fsl,pins = <
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
>;
};
};
ipu_disp1 {
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
>;
};
};
ipu_disp2 {
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
fsl,pins = <
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
>;
};
};
kpp {
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
};
pata {
pinctrl_pata_1: patagrp-1 {
fsl,pins = <
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart1_rtscts_1: uart1rtscts-1 {
fsl,pins = <
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
>;
};
pinctrl_uart3_rtscts_1: uart3rtscts-1 {
fsl,pins = <
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
};
usbh1 {
pinctrl_usbh1_1: usbh1grp-1 {
fsl,pins = <
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
>;
};
};
usbh2 {
pinctrl_usbh2_1: usbh2grp-1 {
fsl,pins = <
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
>;
};
};
};

253
arch/arm/dts/imx53-mba53.dts Normal file
View File

@ -0,0 +1,253 @@
/*
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-tqma53.dtsi"
/ {
model = "TQ MBa53 starter kit";
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
chosen {
linux,stdout-path = &uart2;
environment-sd {
compatible = "barebox,environment";
device-path = &esdhc2, "partname:environment";
status = "disabled";
};
};
reg_backlight: fixed@0 {
compatible = "regulator-fixed";
regulator-name = "lcd-supply";
gpio = <&gpio2 5 0>;
startup-delay-us = <5000>;
enable-active-low;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000>;
brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
default-brightness-level = <10>;
enable-gpios = <&gpio7 7 0>;
power-supply = <&reg_backlight>;
};
disp1: display@disp1 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp1_1>;
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb24";
status = "disabled";
};
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
sound {
compatible = "tq,imx53-mba53-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-mba53-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&ldb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_1>;
status = "disabled";
};
&iomuxc {
lvds1 {
pinctrl_lvds1_1: lvds1-grp1 {
fsl,pins = <
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
>;
};
pinctrl_lvds1_2: lvds1-grp2 {
fsl,pins = <
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
>;
};
};
disp1 {
pinctrl_disp1_1: disp1-grp1 {
fsl,pins = <
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
>;
};
};
tve {
pinctrl_vga_sync_1: vgasync-grp1 {
fsl,pins = <
/* VGA_VSYNC, HSYNC with max drive strength */
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
>;
};
};
};
&cspi {
status = "okay";
};
&audmux {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
&i2c2 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 150>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};
expander: pca9554@20 {
compatible = "pca9554";
reg = <0x20>;
interrupts = <109>;
#gpio-cells = <2>;
gpio-controller;
};
sensor2: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
};
&fec {
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&esdhc2 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "environment";
reg = <0x80000 0x80000>;
};
};
&uart3 {
status = "okay";
};
&ecspi1 {
status = "okay";
};
&usbotg {
dr_mode = "host";
status = "okay";
};
&usbh1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart2 {
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync_1>;
ddc = <&i2c3>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <4>;
fsl,vsync-pin = <6>;
status = "okay";
};

224
arch/arm/dts/imx53-qsb-common.dtsi Normal file
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@ -0,0 +1,224 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
chosen {
linux,stdout-path = "/soc/aips@50000000/serial@53fbc000";
environment@0 {
compatible = "barebox,environment";
device-path = &esdhc1, "partname:barebox-environment";
};
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox-environment";
reg = <0x80000 0x20000>;
};
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
&iim {
barebox,provide-mac-address = <&fec 1 9>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};

210
arch/arm/dts/imx53-qsb.dts
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@ -11,199 +11,15 @@
*/
/dts-v1/;
#include "imx53.dtsi"
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
chosen {
linux,stdout-path = "/soc/aips@50000000/serial@53fbc000";
environment@0 {
compatible = "barebox,environment";
device-path = &esdhc1, "partname:barebox-environment";
};
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox-environment";
reg = <0x80000 0x20000>;
};
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
&iim {
barebox,provide-mac-address = <&fec 1 9>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7@0 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
@ -298,25 +114,3 @@
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start-R Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
};
&iomuxc {
i2c1 {
/* open drain */
pinctrl_i2c1_qsrb: i2c1grp-1 {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_qsrb>;
pmic: ripley@8 {
compatible = "fsl,mc34708";
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <23 0x8>;
regulators {
sw1_reg: sw1a {
regulator-name = "SW1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw1b_reg: sw1b {
regulator-name = "SW1B";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-name = "SW2";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1437500>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-name = "SW3";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1425000>;
regulator-boot-on;
};
sw4a_reg: sw4a {
regulator-name = "SW4A";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw4b_reg: sw4b {
regulator-name = "SW4B";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw5_reg: sw5 {
regulator-name = "SW5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "SWBST";
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-name = "VPLL";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
vrefddr_reg: vrefddr {
regulator-name = "VREFDDR";
regulator-boot-on;
regulator-always-on;
};
vusb_reg: vusb {
regulator-name = "VUSB";
regulator-boot-on;
regulator-always-on;
};
vusb2_reg: vusb2 {
regulator-name = "VUSB2";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vdac_reg: vdac {
regulator-name = "VDAC";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "VGEN1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1550000>;
regulator-boot-on;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-name = "VGEN2";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

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/*
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
model = "TQ TQMa53";
compatible = "tq,tqma53", "fsl,imx53";
chosen {
environment-emmc {
compatible = "barebox,environment";
device-path = &esdhc3, "partname:boot1";
status = "disabled";
};
};
memory {
reg = <0x70000000 0x0>; /* Up to 1GiB */
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>,
<&pinctrl_tqma53_esdhc2_2>;
vmmc-supply = <&reg_3p3v>;
wp-gpios = <&gpio1 2 0>;
cd-gpios = <&gpio1 4 0>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
<&gpio3 24 0>, <&gpio3 25 0>;
status = "disabled";
};
&esdhc3 { /* EMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
vmmc-supply = <&reg_3p3v>;
non-removable;
bus-width = <8>;
dsr = <0x100>;
status = "okay";
};
&iim {
barebox,provide-mac-address = <&fec 1 9>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
esdhc2_2 {
pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
fsl,pins = <
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
>;
};
};
i2s {
pinctrl_i2s_1: i2s-grp1 {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
>;
};
};
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
MX53_PAD_GPIO_3__GPIO1_3 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_2>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_1>;
status = "disabled";
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi_1>;
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
<&gpio1 21 0>;
status = "disabled";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc34708@8 {
compatible = "fsl,mc34708";
reg = <0x8>;
fsl,mc13xxx-uses-rtc;
interrupt-parent = <&gpio2>;
interrupts = <6 4>; /* PATA_DATA6, active high */
};
sensor1: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom: 24c64@50 {
compatible = "at,24c64";
pagesize = <32>;
reg = <0x50>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
status = "disabled";
};

24
arch/arm/dts/imx6dl-cubox-i-carrier-1.dts → arch/arm/dts/imx6dl-hummingboard.dts
View File

@ -11,8 +11,8 @@
#include "imx6qdl-microsom-ar8035.dtsi"
/ {
model = "SolidRun Cubox-i DL/Solo Carrier-1 Board";
compatible = "solidrun,cubox-i-carrier-1", "fsl,imx6dl";
model = "SolidRun HummingBoard DL/Solo";
compatible = "solidrun,hummingboard", "fsl,imx6dl";
chosen {
linux,stdout-path = &uart1;
@ -31,13 +31,13 @@
compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_gpio1_2>;
pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
};
codec: spdif-transmitter {
compatible = "linux,spdif-dit";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_spdif>;
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
};
sound-spdif {
@ -51,7 +51,7 @@
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
@ -65,18 +65,22 @@
};
&iomuxc {
carrier1 {
pinctrl_carrier1_gpio1_2: carrier1-gpio1_2 {
hummingboard {
pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
pinctrl_carrier1_spdif: carrier1-spdif {
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
};
pinctrl_carrier1_usdhc2: carrier1-usdhc2 {
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
@ -96,7 +100,7 @@
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_usdhc2>;
pinctrl-0 = <&pinctrl_hummingboard_usdhc2>;
vmmc-supply = <&reg_3p3v>;
fsl,cd-controller;
status = "okay";

21
arch/arm/dts/imx6dl-nitrogen6x.dts Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-nitrogen6x.dtsi"
/ {
model = "Freescale i.MX6 DualLite Nitrogen6x Board";
compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl";
};

2
arch/arm/dts/imx6dl-pinfunc.h
View File

@ -755,6 +755,7 @@
#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609
#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
@ -950,6 +951,7 @@
#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0
#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0

20
arch/arm/dts/imx6dl-sabrelite.dts Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-sabrelite.dtsi"
/ {
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};

36
arch/arm/dts/imx6dl.dtsi
View File

@ -8,7 +8,9 @@
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
@ -21,6 +23,26 @@
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1075000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@1 {
@ -32,6 +54,12 @@
};
soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks 142>;
};
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
@ -39,17 +67,17 @@
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
epdc: epdc@020f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -59,7 +87,7 @@
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};

54
arch/arm/dts/imx6q-dmo-realq7.dts → arch/arm/dts/imx6q-dmo-edmqmx6.dts
View File

@ -14,8 +14,8 @@
#include "imx6q.dtsi"
/ {
model = "Data Modul RealQ7 Board";
compatible = "dmo,imx6q-realq7", "fsl,imx6q";
model = "Data Modul eDM-QMX6 Board";
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
chosen {
linux,stdout-path = "/soc/aips-bus@02100000/serial@021e8000";
@ -116,7 +116,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
@ -280,19 +280,17 @@
i2c2 {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
fsl,pins = <MX6QDL_I2C2_PINGRP3>;
};
};
uart {
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
>;
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP2>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
};
};
@ -329,6 +327,28 @@
>;
};
};
enet {
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
};
usb {
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
};
};
usdhc {
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
};
};
};
&sata {
@ -337,14 +357,14 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
pinctrl-0 = <&pinctrl_uart2>;
};
&usbh1 {
@ -356,21 +376,21 @@
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
pinctrl-0 = <&pinctrl_usdhc4>;
vmmc-supply = <&reg_3p3v>;
non-removable;
bus-width = <8>;

22
arch/arm/dts/imx6q-gk802.dts
View File

@ -99,6 +99,22 @@
>;
};
};
uart {
pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_UART4_PINGRP1>;
};
};
usdhc {
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <MX6QDL_USDHC4_PINGRP_D4>;
};
};
};
&uart2 {
@ -107,7 +123,7 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
@ -130,7 +146,7 @@
/* External microSD */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
cd-gpios = <&gpio6 11 0>;
vmmc-supply = <&reg_3p3v>;
@ -140,7 +156,7 @@
/* Internal microSD */
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";

25
arch/arm/dts/imx6q-nitrogen6x.dts Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-nitrogen6x.dtsi"
/ {
model = "Freescale i.MX6 Quad Nitrogen6x Board";
compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q";
};
&sata {
status = "okay";
};

146
arch/arm/dts/imx6q-phytec-pfla02.dtsi
View File

@ -22,7 +22,7 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3_1>;
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
@ -35,34 +35,140 @@
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom: m24c32@50 {
compatible = "st,24c32", "at24";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
pmic@58 {
compatible = "dialog,da9063";
reg = <0x58>;
interrupt-parent = <&gpio4>;
interrupts = <17 0x8>; /* active-low GPIO4_17 */
regulators {
vddcore_reg: bcore1 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vddsoc_reg: bcore2 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vdd_ddr3_reg: bpro {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vdd_3v3_reg: bperi {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_buckmem_reg: bmem {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_eth_reg: bio {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_eth_io_reg: ldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_mx6_snvs_reg: ldo5 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vdd_3v3_pmic_io_reg: ldo6 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sd0_reg: ldo9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_sd1_reg: ldo10 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_mx6_high_reg: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx6q-phytec-pfla02 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
>;
};
};
pfla02 {
pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <MX6QDL_ECSPI3_PINGRP1>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP3>;
};
pinctrl_gpmi_nand: gpmigrp {
fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_UART4_PINGRP1>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
@ -70,7 +176,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3>;
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "disabled";
@ -93,7 +199,7 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
#address-cells = <1>;
@ -110,19 +216,19 @@
};
};
&ocotp1 {
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_2>;
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
@ -130,8 +236,8 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2
&pinctrl_usdhc3_pfla02>;
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";

10
arch/arm/dts/imx6q-pinfunc.h
View File

@ -207,8 +207,8 @@
#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
@ -536,7 +536,7 @@
#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100
#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
@ -654,7 +654,7 @@
#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
@ -673,6 +673,7 @@
#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609
#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
@ -1024,6 +1025,7 @@
#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0
#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0

179
arch/arm/dts/imx6q-sabrelite.dts
View File

@ -12,188 +12,13 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabrelite.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Lite Board";
compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
chosen {
linux,stdout-path = &uart2;
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
reg_2p5v: 2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: usb_otg_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
};
&ssi1 {
fsl,mode = "i2s-slave";
&sata {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
};
};
&ocotp1 {
barebox,provide-mac-address = <&fec 0x620>;
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
disable-over-current;
phy-mode = "utmi";
dr_mode = "host";
status = "okay";
};
&usbh1 {
phy-mode = "utmi";
dr_mode = "host";
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&audmux {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 169>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};

20
arch/arm/dts/imx6q-sabresd.dts
View File

@ -20,24 +20,10 @@
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
chosen {
linux,stdout-path = "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000";
linux,stdout-path = &uart1;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
>;
};
};
&sata {
status = "okay";
};

67
arch/arm/dts/imx6q.dtsi
View File

@ -8,7 +8,9 @@
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
@ -30,7 +32,14 @@
1200000 1275000
996000 1250000
792000 1150000
396000 950000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
@ -65,6 +74,12 @@
};
soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks 142>;
};
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi5: ecspi@02018000 {
@ -72,7 +87,7 @@
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x4000>;
interrupts = <0 35 0x04>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 116>, <&clks 116>;
clock-names = "ipg", "per";
status = "disabled";
@ -81,14 +96,60 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
ipu2 {
pinctrl_ipu2_1: ipu2grp-1 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
>;
};
};
};
};
sata: sata@02200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 154>, <&clks 187>, <&clks 105>;
clock-names = "sata", "sata_ref", "ahb";
status = "disabled";
};
ipu2: ipu@02800000 {
#crtc-cells = <1>;
compatible = "fsl,imx6q-ipu";
reg = <0x02800000 0x400000>;
interrupts = <0 8 0x4 0 7 0x4>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
<0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
clock-names = "bus", "di0", "di1";
resets = <&src 4>;

75
arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
View File

@ -1,8 +1,4 @@
/ {
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
@ -31,9 +27,25 @@
};
};
&ecspi3 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf040b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
pinctrl-0 = <&pinctrl_enet>;
status = "okay";
phy-mode = "rgmii";
};
@ -42,7 +54,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
imx6qdl-dfi-fs700-m60 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
@ -52,12 +64,49 @@
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* SD2 card detect */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_I2C2_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
};
};
ecspi3 {
pinctrl_ecspi3: ecspi3_csgrp {
fsl,pins = <
MX6QDL_ECSPI3_PINGRP1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pf0100@08 {
@ -68,13 +117,13 @@
};
};
&ocotp1 {
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
@ -87,7 +136,7 @@
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_2>;
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
phy_type = "utmi";
dr_mode = "host";
@ -96,19 +145,19 @@
&usdhc2 { /* module slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_2>;
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio2 2 0>;
status = "okay";
};
&usdhc3 { /* baseboard slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
pinctrl-0 = <&pinctrl_usdhc3>;
};
&usdhc4 { /* eMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
status = "okay";

16
arch/arm/dts/imx6qdl-mba6x.dtsi
View File

@ -96,7 +96,7 @@
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
@ -116,6 +116,18 @@
status = "okay";
};
&iomuxc {
imx6qdl-mba6x {
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
};
};
};
&i2c1 {
codec: tlv320@18 {
compatible = "ti,tlv320aic23";
@ -176,7 +188,7 @@
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;

17
arch/arm/dts/imx6qdl-microsom.dtsi
View File

@ -7,17 +7,21 @@
/ {
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: 3p3v {
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: usb_h1_vbus {
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -25,8 +29,9 @@
enable-active-high;
};
reg_usb_otg_vbus: usb_otg_vbus {
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -51,6 +56,10 @@
>;
};
pinctrl_microsom_uart1: microsom-uart1 {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_microsom_usbotg: microsom-usbotg {
/*
* Similar to pinctrl_usbotg_2, but we want it
@ -63,7 +72,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_microsom_uart1>;
status = "okay";
};

412
arch/arm/dts/imx6qdl-nitrogen6x.dtsi Normal file
View File

@ -0,0 +1,412 @@
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
linux,stdout-path = &uart2;
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6x-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
backlight_lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 27 0>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-nitrogen6x {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_ECSPI1_PINGRP1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
/* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP2>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_USDHC3_PINGRP_D4
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_USDHC4_PINGRP_D4
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

532
arch/arm/dts/imx6qdl-pingrp.h Normal file
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@ -0,0 +1,532 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6QDL_PINGRP_H
#define __DTS_IMX6QDL_PINGRP_H
#define MX6QDL_AUDMUX_PINGRP1 \
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
#define MX6QDL_AUDMUX_PINGRP2 \
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
#define MX6QDL_AUDMUX_PINGRP3 \
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \
#define MX6QDL_AUDMUX_PINGRP4 \
MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \
MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
#define MX6QDL_AUDMUX_PINGRP5 \
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 \
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 \
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 \
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
#define MX6QDL_ECSPI1_PINGRP1 \
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 \
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
#define MX6QDL_ECSPI1_PINGRP2 \
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 \
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 \
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
#define MX6QDL_ECSPI3_PINGRP1 \
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 \
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 \
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
#define MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
MX6QDL_PAD_RGMII_RXC__RGMII_RXC rx_pad \
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 rx_pad \
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 rx_pad \
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 rx_pad \
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 rx_pad \
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL rx_pad \
MX6QDL_PAD_RGMII_TXC__RGMII_TXC tx_pad \
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 tx_pad \
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 tx_pad \
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 tx_pad \
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 tx_pad \
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL tx_pad \
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK tx_pad
#define MX6QDL_ENET_PINGRP_RGMII_MD(rx_pad, tx_pad) \
MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
MX6QDL_PAD_ENET_MDIO__ENET_MDIO tx_pad \
MX6QDL_PAD_ENET_MDC__ENET_MDC tx_pad
#define MX6QDL_ENET_PINGRP1 \
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
#define MX6QDL_ENET_PINGRP2 \
MX6QDL_ENET_PINGRP_RGMII(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 \
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
#define MX6QDL_ENET_PINGRP3 \
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
#define MX6QDL_ENET_PINGRP4 \
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 \
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 \
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 \
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 \
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 \
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 \
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
#define MX6QDL_ENET_PINGRP1_GPIO6 MX6QDL_ENET_PINGRP1 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ENET_PINGRP2_GPIO6 MX6QDL_ENET_PINGRP2 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ENET_PINGRP3_GPIO6 MX6QDL_ENET_PINGRP3 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ESAI_PINGRP1 \
MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 \
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 \
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 \
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
#define MX6QDL_ESAI_PINGRP2 \
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 \
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 \
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 \
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 \
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
#define MX6QDL_FLEXCAN1_PINGRP1 \
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 \
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
#define MX6QDL_FLEXCAN1_PINGRP2 \
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 \
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
#define MX6QDL_FLEXCAN2_PINGRP1 \
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 \
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
#define MX6QDL_GPMI_NAND_PINGRP1 \
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 \
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
#define MX6QDL_GPMI_NAND_PINGRP1_NODQS \
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
#define MX6QDL_HDMI_HDCP_PINGRP1 \
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_HDCP_PINGRP2 \
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_HDCP_PINGRP3 \
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_CEC_PINGRP1 \
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
#define MX6QDL_HDMI_CEC_PINGRP2 \
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
#define MX6QDL_I2C1_PINGRP1 \
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
#define MX6QDL_I2C1_PINGRP2 \
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 \
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
#define MX6QDL_I2C2_PINGRP1 \
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C2_PINGRP2 \
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C2_PINGRP3 \
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP1 \
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP2 \
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP3 \
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP4 \
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
#define MX6QDL_IPU1_PINGRP1 \
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 \
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 \
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 \
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 \
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 \
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 \
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 \
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 \
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 \
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 \
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 \
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 \
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 \
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 \
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 \
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 \
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 \
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 \
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 \
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 \
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 \
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 \
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 \
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 \
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 \
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 \
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 \
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 \
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
/* parallel camera */
#define MX6QDL_IPU1_PINGRP2 \
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 \
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
/* parallel port 16-bit */
#define MX6QDL_IPU1_PINGRP3 \
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 \
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 \
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 \
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 \
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 \
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 \
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 \
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 \
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
#define MX6QDL_MLB_PINGRP1 \
MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 \
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
#define MX6QDL_MLB_PINGRP2 \
MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 \
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
#define MX6QDL_PWM1_PINGRP1 \
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
#define MX6QDL_PWM3_PINGRP1 \
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
#define MX6QDL_SPDIF_PINGRP1 \
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
#define MX6QDL_SPDIF_PINGRP2 \
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 \
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
#define MX6QDL_SPDIF_PINGRP3 \
MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
#define MX6QDL_UART1_PINGRP1 \
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 \
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
#define MX6QDL_UART1_PINGRP2 \
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 \
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
#define MX6QDL_UART2_PINGRP1 \
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
/* DTE mode */
#define MX6QDL_UART2_PINGRP2 \
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
#define MX6QDL_UART2_PINGRP3 \
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
#define MX6QDL_UART3_PINGRP1 \
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 \
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
#define MX6QDL_UART3_PINGRP2 \
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
#define MX6QDL_UART3_PINGRP3 \
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
#define MX6QDL_UART4_PINGRP1 \
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 \
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
#define MX6QDL_UART5_PINGRP1 \
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 \
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
#define MX6QDL_USBOTG_PINGRP1 \
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
#define MX6QDL_USBOTG_PINGRP2 \
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
#define MX6QDL_USBH2_PINGRP1 \
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 \
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
#define MX6QDL_USBH2_PINGRP2 \
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
#define MX6QDL_USBH3_PINGRP1 \
MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 \
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
#define MX6QDL_USBH3_PINGRP2 \
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD1_CMD__SD1_CMD pad \
MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \
MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \
MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \
MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad
#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD2_CMD__SD2_CMD pad \
MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \
MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \
MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \
MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad
#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD3_CMD__SD3_CMD pad \
MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad
#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD4_CMD__SD4_CMD pad \
MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3
#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad
#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_WEIM_CS0_PINGRP1 \
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
#define MX6QDL_WEIM_NOR_PINGRP1 \
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 \
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 \
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 \
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 \
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 \
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 \
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 \
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 \
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 \
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 \
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 \
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 \
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 \
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 \
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 \
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 \
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 \
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 \
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 \
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 \
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 \
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 \
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 \
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 \
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 \
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 \
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 \
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 \
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 \
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 \
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 \
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 \
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 \
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 \
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 \
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 \
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 \
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 \
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 \
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 \
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 \
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 \
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
#endif /* __DTS_IMX6QDL_PINGRP_H */

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arch/arm/dts/imx6qdl-sabrelite.dtsi Normal file
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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
linux,stdout-path = &uart2;
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
backlight_lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_ECSPI1_PINGRP1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP2>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_USDHC3_PINGRP_D4
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_USDHC4_PINGRP_D4
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

233
arch/arm/dts/imx6qdl-sabresd.dtsi
View File

@ -17,15 +17,36 @@
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: usb_otg_vbus {
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 0>;
enable-active-high;
};
reg_audio: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
};
gpio-keys {
@ -34,49 +55,246 @@
volume-up {
label = "Volume Up";
gpios = <&gpio1 4 0>;
gpio-key,wakeup;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 5 0>;
gpio-key,wakeup;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"MICBIAS", "AMIC",
"IN3R", "MICBIAS",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>;
status = "okay";
};
&ocotp1 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks 201>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio6>;
interrupts = <7 2>;
wakeup-gpios = <&gpio6 7 0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <MX6QDL_ECSPI1_PINGRP2>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP2>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_I2C3_PINGRP2>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <MX6QDL_PWM1_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D8>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
};
};
};
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_2>;
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
@ -84,7 +302,8 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";

36
arch/arm/dts/imx6qdl-tqma6x.dtsi
View File

@ -11,7 +11,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
status = "okay";
@ -25,11 +25,35 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
};
&ocotp1 {
&iomuxc {
imx6qdl-tqma6x {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP2>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_I2C3_PINGRP2>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
};
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
@ -37,14 +61,14 @@
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_2>;
pinctrl-0 = <&pinctrl_i2c1>;
};
&i2c3 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
pinctrl-0 = <&pinctrl_i2c3>;
pmic: pf0100@08 {
compatible = "pf0100-regulator";
@ -158,7 +182,7 @@
&usdhc3 { /* eMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
bus-width = <8>;
status = "okay";

577
arch/arm/dts/imx6qdl.dtsi
View File

File diff suppressed because it is too large Load Diff

17
arch/arm/lib/pbl.lds.S
View File

@ -24,15 +24,17 @@
#include <asm-generic/barebox.lds.h>
#include <asm-generic/memory_layout.h>
#ifdef CONFIG_PBL_RELOCATABLE
#define BASE 0x0
#else
#define BASE (TEXT_BASE - SZ_2M)
#endif
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SECTIONS
{
#ifdef CONFIG_PBL_RELOCATABLE
. = 0x0;
#else
. = TEXT_BASE - SZ_2M;
#endif
. = BASE;
PRE_IMAGE
@ -91,7 +93,6 @@ SECTIONS
KEEP(*(.image_end))
}
__image_end = .;
_barebox_image_size = __image_end - (TEXT_BASE - SZ_2M);
_barebox_pbl_size = __bss_start - (TEXT_BASE - SZ_2M);
_barebox_image_size = __image_end - BASE;
_barebox_pbl_size = __bss_start - BASE;
}

68
arch/arm/mach-imx/Kconfig
View File

@ -38,8 +38,9 @@ config ARCH_TEXT_BASE
default 0x4fc00000 if MACH_PHYTEC_PFLA02
default 0x4fc00000 if MACH_DFI_FS700_M60
choice
prompt "Select boot mode"
config ARCH_IMX_INTERNAL_BOOT
bool "support internal boot mode"
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
depends on !HAVE_PBL_MULTI_IMAGES
help
i.MX processors support two different boot modes. With the internal
@ -58,16 +59,6 @@ choice
The external boot mode is supported on older i.MX processors (i.MX1,
i.MX21, i.MX25, i.MX27, i.MX31, i.MX35).
config ARCH_IMX_INTERNAL_BOOT
bool "support internal boot mode"
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
config ARCH_IMX_EXTERNAL_BOOT
bool "support external boot mode"
depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35
endchoice
config ARCH_IMX_IMXIMAGE
bool
default y
@ -105,16 +96,10 @@ config ARCH_IMX_INTERNAL_BOOT_SERIAL
endchoice
config NAND_IMX_BOOT
bool
depends on ARCH_IMX_EXTERNAL_BOOT_NAND
default y
config ARCH_IMX_EXTERNAL_BOOT_NAND
bool
depends on !ARCH_IMX1
prompt "Support Starting barebox from NAND"
depends on ARCH_IMX_EXTERNAL_BOOT
depends on ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35
prompt "Support Starting barebox from NAND in external bootmode"
config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
bool
@ -182,6 +167,13 @@ config IMX_MULTI_BOARDS
if IMX_MULTI_BOARDS
config MACH_TX25
bool "Ka-Ro TX25"
select ARCH_IMX25
select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using the Ka-Ro tx25 board
config MACH_EFIKA_MX_SMARTBOOK
bool "Efika MX smartbook"
select ARCH_IMX51
@ -196,6 +188,10 @@ config MACH_FREESCALE_MX53_LOCO
bool "Freescale i.MX53 LOCO"
select ARCH_IMX53
config MACH_TQMA53
bool "TQ i.MX53 TQMa53"
select ARCH_IMX53
config MACH_FREESCALE_MX53_VMX53
bool "Voipac i.MX53"
select ARCH_IMX53
@ -229,8 +225,12 @@ config MACH_SABRELITE
select HAVE_DEFAULT_ENVIRONMENT_NEW
select HAVE_PBL_MULTI_IMAGES
config MACH_SOLIDRUN_CARRIER1
bool "SolidRun CuBox-i Carrier-1"
config MACH_NITROGEN6X
bool "BoundaryDevices Nitrogen6x"
select ARCH_IMX6
config MACH_SOLIDRUN_HUMMINGBOARD
bool "SolidRun Hummingboard"
select ARCH_IMX6
endif
@ -282,13 +282,6 @@ config MACH_FREESCALE_MX25_3STACK
Say Y here if you are using the Freescale MX25 3stack board equipped
with a Freescale i.MX25 Processor
config MACH_TX25
bool "Ka-Ro TX25"
select ARCH_IMX25
select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say Y here if you are using the Ka-Ro tx25 board
# ----------------------------------------------------------
comment "i.MX27 Boards"
@ -310,6 +303,8 @@ config MACH_IMX27ADS
config MACH_PCA100
bool "phyCard-i.MX27"
select ARCH_IMX27
select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
@ -439,11 +434,6 @@ config MACH_FREESCALE_MX53_SMD
bool "Freescale i.MX53 SMD"
select ARCH_IMX53
config MACH_TQMA53
bool "TQ i.MX53 TQMa53"
select ARCH_IMX53
select HAVE_DEFAULT_ENVIRONMENT_NEW
config MACH_TX53
bool "Ka-Ro TX53"
select ARCH_IMX53
@ -539,16 +529,6 @@ endchoice
endif
if MACH_TQMA53
config MACH_TQMA53_1GB_RAM
bool "Use 1GiB of SDRAM"
depends on MACH_TQMA53
help
use 1GiB of SDRAM (512MiB otherwise)
endif
if MACH_TX53
choice

3
arch/arm/mach-imx/clk-imx25.c
View File

@ -140,6 +140,9 @@ static int imx25_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);

44
arch/arm/mach-imx/clk-imx27.c
View File

@ -92,8 +92,23 @@
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
clko_en, lcdc_per_gate, lcdc_ahb_gate, lcdc_ipg_gate, clk_max
per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
mpll_sel, spll_gate, clk_max
};
static struct clk *clks[clk_max];
@ -103,6 +118,16 @@ static const char *cpu_sel_clks[] = {
"mpll",
};
static const char *mpll_sel_clks[] = {
"fpm",
"mpll_osc_sel",
};
static const char *mpll_osc_sel_clks[] = {
"ckih",
"ckih_div1p5",
};
static const char *clko_sel_clks[] = {
"ckil",
NULL,
@ -152,7 +177,16 @@ static int imx27_ccm_probe(struct device_d *dev)
clks[dummy] = clk_fixed("dummy", 0);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL0);
clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
clks[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
clks[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", base + CCM_CSCR, 4, 1,
mpll_osc_sel_clks,
ARRAY_SIZE(mpll_osc_sel_clks));
clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
ARRAY_SIZE(mpll_sel_clks));
clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
@ -179,7 +213,7 @@ static int imx27_ccm_probe(struct device_d *dev)
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 8);
clks[per3_gate] = imx_clk_gate("per3_gate", "per3_div", base + CCM_PCCR1, 8);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15);
clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14);
@ -203,7 +237,7 @@ static int imx27_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);

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