ARM: MXS: introduce stmp device support
MXS specific devices have some common infrastructure in the kernel known as STMP devices. We have the same in barebox, but with a mxs_ prefix instead of a stmp_ prefix. As some STMP devices are also found on i.MX6 move the common infrastructure out of MXS specific files and use the stmp_ prefix. This is done in preparation for i.MX6 NAND support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
66891566cc
commit
ca13a84ac2
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@ -24,11 +24,13 @@ choice
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config ARCH_IMX23
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config ARCH_IMX23
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bool "i.MX23"
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bool "i.MX23"
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select STMP_DEVICE
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select CPU_ARM926T
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select CPU_ARM926T
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config ARCH_IMX28
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config ARCH_IMX28
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bool "i.MX28"
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bool "i.MX28"
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select CPU_ARM926T
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select CPU_ARM926T
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select STMP_DEVICE
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select ARCH_HAS_FEC_IMX
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select ARCH_HAS_FEC_IMX
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endchoice
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endchoice
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@ -1,4 +1,4 @@
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obj-y += imx.o iomux-imx.o power.o common.o
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obj-y += imx.o iomux-imx.o power.o
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obj-$(CONFIG_ARCH_IMX23) += clocksource-imx23.o usb-imx23.o soc-imx23.o
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obj-$(CONFIG_ARCH_IMX23) += clocksource-imx23.o usb-imx23.o soc-imx23.o
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obj-$(CONFIG_ARCH_IMX28) += clocksource-imx28.o usb-imx28.o soc-imx28.o
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obj-$(CONFIG_ARCH_IMX28) += clocksource-imx28.o usb-imx28.o soc-imx28.o
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obj-$(CONFIG_MXS_OCOTP) += ocotp.o
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obj-$(CONFIG_MXS_OCOTP) += ocotp.o
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@ -19,6 +19,7 @@
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#include <complete.h>
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#include <complete.h>
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#include <init.h>
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#include <init.h>
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#include <io.h>
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#include <io.h>
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#include <stmp-device.h>
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#include <mach/generic.h>
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#include <mach/generic.h>
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#include <mach/imx-regs.h>
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#include <mach/imx-regs.h>
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@ -39,7 +40,7 @@ static int imx_reset_usb_bootstrap(void)
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* To prevent this (and boot from the configured bootsource instead)
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* To prevent this (and boot from the configured bootsource instead)
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* clear this bit here.
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* clear this bit here.
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*/
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*/
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writel(0x2, IMX_WDT_BASE + HW_RTC_PERSISTENT1 + BIT_CLR);
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writel(0x2, IMX_WDT_BASE + HW_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
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return 0;
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return 0;
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}
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}
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@ -16,11 +16,6 @@
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#ifndef _IMX_REGS_H
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#ifndef _IMX_REGS_H
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# define _IMX_REGS_H
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# define _IMX_REGS_H
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/* Note: Some registers do not support this bit change feature! */
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#define BIT_SET 0x04
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#define BIT_CLR 0x08
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#define BIT_TGL 0x0C
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#if defined CONFIG_ARCH_IMX23
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#if defined CONFIG_ARCH_IMX23
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# include <mach/imx23-regs.h>
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# include <mach/imx23-regs.h>
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#endif
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#endif
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@ -1,6 +0,0 @@
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#ifndef __MACH_MXS_H
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#define __MACH_MXS_H
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int mxs_reset_block(void __iomem *reg, int just_enable);
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#endif /* __MACH_MXS_H */
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@ -18,6 +18,7 @@
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#include <gpio.h>
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#include <gpio.h>
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#include <errno.h>
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#include <errno.h>
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#include <io.h>
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#include <io.h>
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#include <stmp-device.h>
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#include <mach/imx-regs.h>
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#include <mach/imx-regs.h>
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#define HW_PINCTRL_CTRL 0x000
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#define HW_PINCTRL_CTRL 0x000
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@ -112,22 +113,24 @@ void imx_gpio_mode(uint32_t m)
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reg_offset = calc_strength_reg(gpio_pin);
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reg_offset = calc_strength_reg(gpio_pin);
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if (GET_VOLTAGE(m) == 1)
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if (GET_VOLTAGE(m) == 1)
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writel(0x1 << (((gpio_pin % 8) << 2) + 2),
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writel(0x1 << (((gpio_pin % 8) << 2) + 2),
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IMX_IOMUXC_BASE + reg_offset + BIT_SET);
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IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
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else
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else
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writel(0x1 << (((gpio_pin % 8) << 2) + 2),
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writel(0x1 << (((gpio_pin % 8) << 2) + 2),
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IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
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IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
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}
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}
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if (PE_PRESENT(m)) {
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if (PE_PRESENT(m)) {
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reg_offset = calc_pullup_reg(gpio_pin);
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reg_offset = calc_pullup_reg(gpio_pin);
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
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(GET_PULLUP(m) == 1 ? BIT_SET : BIT_CLR));
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(GET_PULLUP(m) == 1 ?
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STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
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}
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}
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if (BK_PRESENT(m)) {
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if (BK_PRESENT(m)) {
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reg_offset = calc_pullup_reg(gpio_pin);
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reg_offset = calc_pullup_reg(gpio_pin);
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset +
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(GET_BITKEEPER(m) == 1 ? BIT_CLR : BIT_SET));
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(GET_BITKEEPER(m) == 1 ?
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STMP_OFFSET_REG_CLR : STMP_OFFSET_REG_SET));
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}
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}
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if (GET_FUNC(m) == IS_GPIO) {
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if (GET_FUNC(m) == IS_GPIO) {
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@ -135,16 +138,17 @@ void imx_gpio_mode(uint32_t m)
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/* first set the output value */
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/* first set the output value */
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reg_offset = calc_output_reg(gpio_pin);
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reg_offset = calc_output_reg(gpio_pin);
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE +
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writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE +
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reg_offset + (GET_GPIOVAL(m) == 1 ? BIT_SET : BIT_CLR));
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reg_offset + (GET_GPIOVAL(m) == 1 ?
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STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
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/* then the direction */
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/* then the direction */
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reg_offset = calc_output_enable_reg(gpio_pin);
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reg_offset = calc_output_enable_reg(gpio_pin);
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writel(0x1 << (gpio_pin % 32),
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writel(0x1 << (gpio_pin % 32),
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IMX_IOMUXC_BASE + reg_offset + BIT_SET);
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IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
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} else {
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} else {
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/* then the direction */
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/* then the direction */
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reg_offset = calc_output_enable_reg(gpio_pin);
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reg_offset = calc_output_enable_reg(gpio_pin);
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writel(0x1 << (gpio_pin % 32),
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writel(0x1 << (gpio_pin % 32),
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IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
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IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
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}
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}
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}
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}
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}
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}
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@ -157,7 +161,7 @@ int gpio_direction_input(unsigned gpio)
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return -EINVAL;
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return -EINVAL;
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reg_offset = calc_output_enable_reg(gpio);
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reg_offset = calc_output_enable_reg(gpio);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_CLR);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR);
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return 0;
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return 0;
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}
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}
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@ -172,10 +176,10 @@ int gpio_direction_output(unsigned gpio, int val)
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/* first set the output value... */
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/* first set the output value... */
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reg_offset = calc_output_reg(gpio);
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reg_offset = calc_output_reg(gpio);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
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reg_offset + (val != 0 ? BIT_SET : BIT_CLR));
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reg_offset + (val != 0 ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
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/* ...then the direction */
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/* ...then the direction */
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reg_offset = calc_output_enable_reg(gpio);
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reg_offset = calc_output_enable_reg(gpio);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_SET);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET);
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return 0;
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return 0;
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}
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}
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@ -186,7 +190,8 @@ void gpio_set_value(unsigned gpio, int val)
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reg_offset = calc_output_reg(gpio);
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reg_offset = calc_output_reg(gpio);
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
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writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE +
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reg_offset + (val != 0 ? BIT_SET : BIT_CLR));
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reg_offset + (val != 0 ?
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STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR));
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}
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}
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int gpio_get_value(unsigned gpio)
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int gpio_get_value(unsigned gpio)
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@ -20,6 +20,7 @@
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#include <fcntl.h>
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#include <fcntl.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <io.h>
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#include <io.h>
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#include <stmp-device.h>
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#include <clock.h>
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#include <clock.h>
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#include <linux/clk.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/err.h>
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@ -75,13 +76,13 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count,
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*/
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*/
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/* try to clear ERROR bit */
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/* try to clear ERROR bit */
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writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + BIT_CLR);
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writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
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if (mxs_ocotp_wait_busy(priv))
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if (mxs_ocotp_wait_busy(priv))
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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/* open OCOTP banks for read */
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/* open OCOTP banks for read */
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_SET);
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_SET);
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/* approximately wait 32 hclk cycles */
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/* approximately wait 32 hclk cycles */
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udelay(1);
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udelay(1);
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@ -96,7 +97,7 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count,
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(((i + offset) & 0xfc) << 2) + ((i + offset) & 3));
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(((i + offset) & 0xfc) << 2) + ((i + offset) & 3));
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/* close banks for power saving */
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/* close banks for power saving */
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR);
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
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return size;
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return size;
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}
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}
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@ -139,7 +140,7 @@ static ssize_t mxs_ocotp_cdev_write(struct cdev *cdev, const void *buf, size_t c
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clk_set_rate(priv->clk, 24000000);
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clk_set_rate(priv->clk, 24000000);
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imx_set_vddio(2800000);
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imx_set_vddio(2800000);
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR);
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writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + STMP_OFFSET_REG_CLR);
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if (mxs_ocotp_wait_busy(priv)) {
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if (mxs_ocotp_wait_busy(priv)) {
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ret = -ETIMEDOUT;
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ret = -ETIMEDOUT;
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@ -11,6 +11,7 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <io.h>
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#include <io.h>
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#include <stmp-device.h>
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#include <errno.h>
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#include <errno.h>
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#include <mach/imx-regs.h>
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#include <mach/imx-regs.h>
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* Set these bits so that we can force the OTG bits high
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* Set these bits so that we can force the OTG bits high
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* so the ARC core operates properly
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* so the ARC core operates properly
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*/
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*/
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writel(POWER_CTRL_CLKGATE, POWER_CTRL + BIT_CLR);
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writel(POWER_CTRL_CLKGATE, POWER_CTRL + STMP_OFFSET_REG_CLR);
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writel(POWER_DEBUG_VBUSVALIDPIOLOCK |
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writel(POWER_DEBUG_VBUSVALIDPIOLOCK |
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POWER_DEBUG_AVALIDPIOLOCK |
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POWER_DEBUG_AVALIDPIOLOCK |
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POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + BIT_SET);
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POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + STMP_OFFSET_REG_SET);
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reg = readl(POWER_STS);
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reg = readl(POWER_STS);
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reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID;
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reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID;
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@ -3,6 +3,7 @@ menu "DMA support"
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config MXS_APBH_DMA
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config MXS_APBH_DMA
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tristate "MXS APBH DMA ENGINE"
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tristate "MXS APBH DMA ENGINE"
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depends on ARCH_IMX23 || ARCH_IMX28
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depends on ARCH_IMX23 || ARCH_IMX28
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select STMP_DEVICE
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help
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help
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Experimental!
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Experimental!
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endmenu
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endmenu
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@ -20,12 +20,12 @@
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#include <common.h>
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#include <common.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <errno.h>
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#include <errno.h>
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#include <stmp-device.h>
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#include <asm/mmu.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <mach/clock.h>
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#include <mach/clock.h>
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#include <mach/imx-regs.h>
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#include <mach/imx-regs.h>
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#include <mach/dma.h>
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#include <mach/dma.h>
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#include <mach/mxs.h>
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#define HW_APBHX_CTRL0 0x000
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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@ -165,7 +165,7 @@ static int mxs_dma_enable(int channel)
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writel(pchan->active_num,
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writel(pchan->active_num,
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apbh_regs + HW_APBHX_CHn_SEMA(channel));
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apbh_regs + HW_APBHX_CHn_SEMA(channel));
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channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
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channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
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writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_CLR);
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writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
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}
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}
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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@ -202,7 +202,7 @@ static int mxs_dma_disable(int channel)
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return -EINVAL;
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return -EINVAL;
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channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
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channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
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writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
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writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
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pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
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pchan->active_num = 0;
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pchan->active_num = 0;
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@ -226,10 +226,10 @@ static int mxs_dma_reset(int channel)
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if (apbh_is_old)
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if (apbh_is_old)
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writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
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writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
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apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
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apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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else
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else
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writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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apbh_regs + HW_APBHX_CHANNEL_CTRL + BIT_SET);
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apbh_regs + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
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return 0;
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return 0;
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}
|
}
|
||||||
|
@ -250,10 +250,10 @@ static int mxs_dma_enable_irq(int channel, int enable)
|
||||||
|
|
||||||
if (enable)
|
if (enable)
|
||||||
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
||||||
apbh_regs + HW_APBHX_CTRL1 + BIT_SET);
|
apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
|
||||||
else
|
else
|
||||||
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
||||||
apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
|
apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -273,8 +273,8 @@ static int mxs_dma_ack_irq(int channel)
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
|
writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||||
writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + BIT_CLR);
|
writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -555,7 +555,7 @@ int mxs_dma_init(void)
|
||||||
int ret, channel;
|
int ret, channel;
|
||||||
u32 val, reg;
|
u32 val, reg;
|
||||||
|
|
||||||
ret = mxs_reset_block(apbh_regs, 0);
|
ret = stmp_reset_block(apbh_regs, 0);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
@ -569,10 +569,10 @@ int mxs_dma_init(void)
|
||||||
apbh_is_old = (readl((void *)reg) >> 24) < 3;
|
apbh_is_old = (readl((void *)reg) >> 24) < 3;
|
||||||
|
|
||||||
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
||||||
apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
||||||
apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
apbh_regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
|
for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
|
||||||
pchan = mxs_dma_channels + channel;
|
pchan = mxs_dma_channels + channel;
|
||||||
|
|
|
@ -36,10 +36,10 @@
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <clock.h>
|
#include <clock.h>
|
||||||
#include <io.h>
|
#include <io.h>
|
||||||
|
#include <stmp-device.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <asm/bitops.h>
|
#include <asm/bitops.h>
|
||||||
#include <mach/mxs.h>
|
|
||||||
#include <mach/imx-regs.h>
|
#include <mach/imx-regs.h>
|
||||||
#include <mach/mci.h>
|
#include <mach/mci.h>
|
||||||
#include <mach/clock.h>
|
#include <mach/clock.h>
|
||||||
|
@ -457,7 +457,7 @@ static int mxs_mci_initialize(struct mci_host *host, struct device_d *mci_dev)
|
||||||
writel(SSP_CTRL0_CLKGATE, mxs_mci->regs + HW_SSP_CTRL0 + 8);
|
writel(SSP_CTRL0_CLKGATE, mxs_mci->regs + HW_SSP_CTRL0 + 8);
|
||||||
|
|
||||||
/* reset the unit */
|
/* reset the unit */
|
||||||
mxs_reset_block(mxs_mci->regs + HW_SSP_CTRL0, 0);
|
stmp_reset_block(mxs_mci->regs + HW_SSP_CTRL0, 0);
|
||||||
|
|
||||||
/* restore the last settings */
|
/* restore the last settings */
|
||||||
mxs_mci_setup_timeout(mxs_mci, 0xffff);
|
mxs_mci_setup_timeout(mxs_mci, 0xffff);
|
||||||
|
|
|
@ -28,12 +28,12 @@
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <driver.h>
|
#include <driver.h>
|
||||||
#include <init.h>
|
#include <init.h>
|
||||||
|
#include <stmp-device.h>
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <mach/clock.h>
|
#include <mach/clock.h>
|
||||||
#include <mach/imx-regs.h>
|
#include <mach/imx-regs.h>
|
||||||
#include <mach/dma.h>
|
#include <mach/dma.h>
|
||||||
#include <mach/mxs.h>
|
|
||||||
|
|
||||||
#define MX28_BLOCK_SFTRST (1 << 31)
|
#define MX28_BLOCK_SFTRST (1 << 31)
|
||||||
#define MX28_BLOCK_CLKGATE (1 << 30)
|
#define MX28_BLOCK_CLKGATE (1 << 30)
|
||||||
|
@ -313,7 +313,7 @@ static int mxs_nand_wait_for_bch_complete(void)
|
||||||
|
|
||||||
ret = (timeout == 0) ? -ETIMEDOUT : 0;
|
ret = (timeout == 0) ? -ETIMEDOUT : 0;
|
||||||
|
|
||||||
writel(BCH_CTRL_COMPLETE_IRQ, bch_regs + BCH_CTRL + BIT_CLR);
|
writel(BCH_CTRL_COMPLETE_IRQ, bch_regs + BCH_CTRL + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -1048,7 +1048,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
|
/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
|
||||||
ret = mxs_reset_block(bch_regs + BCH_CTRL,
|
ret = stmp_reset_block(bch_regs + BCH_CTRL,
|
||||||
nand_info->version == GPMI_VERSION_TYPE_MX23);
|
nand_info->version == GPMI_VERSION_TYPE_MX23);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -1073,7 +1073,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
|
||||||
writel(0, bch_regs + BCH_LAYOUTSELECT);
|
writel(0, bch_regs + BCH_LAYOUTSELECT);
|
||||||
|
|
||||||
/* Enable BCH complete interrupt */
|
/* Enable BCH complete interrupt */
|
||||||
writel(BCH_CTRL_COMPLETE_IRQ_EN, bch_regs + BCH_CTRL + BIT_SET);
|
writel(BCH_CTRL_COMPLETE_IRQ_EN, bch_regs + BCH_CTRL + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
/* Hook some operations at the MTD level. */
|
/* Hook some operations at the MTD level. */
|
||||||
if (mtd->read_oob != mxs_nand_hook_read_oob) {
|
if (mtd->read_oob != mxs_nand_hook_read_oob) {
|
||||||
|
@ -1154,7 +1154,7 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
|
||||||
mxs_dma_init();
|
mxs_dma_init();
|
||||||
|
|
||||||
/* Reset the GPMI block. */
|
/* Reset the GPMI block. */
|
||||||
ret = mxs_reset_block(gpmi_regs + GPMI_CTRL0, 0);
|
ret = stmp_reset_block(gpmi_regs + GPMI_CTRL0, 0);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
@ -1162,7 +1162,7 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
|
||||||
info->version = val >> GPMI_VERSION_MINOR_OFFSET;
|
info->version = val >> GPMI_VERSION_MINOR_OFFSET;
|
||||||
|
|
||||||
/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
|
/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
|
||||||
ret = mxs_reset_block(bch_regs + BCH_CTRL,
|
ret = stmp_reset_block(bch_regs + BCH_CTRL,
|
||||||
info->version == GPMI_VERSION_TYPE_MX23);
|
info->version == GPMI_VERSION_TYPE_MX23);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
@ -171,7 +171,7 @@ static int auart_clocksource_clock_change(struct notifier_block *nb, unsigned lo
|
||||||
|
|
||||||
static void auart_serial_init_port(struct auart_priv *priv)
|
static void auart_serial_init_port(struct auart_priv *priv)
|
||||||
{
|
{
|
||||||
mxs_reset_block(priv->base + HW_UARTAPP_CTRL0, 0);
|
stmp_reset_block(priv->base + HW_UARTAPP_CTRL0, 0);
|
||||||
|
|
||||||
/* Disable UART */
|
/* Disable UART */
|
||||||
writel(0x0, priv->base + HW_UARTAPP_CTRL2);
|
writel(0x0, priv->base + HW_UARTAPP_CTRL2);
|
||||||
|
|
|
@ -20,6 +20,7 @@
|
||||||
#include <clock.h>
|
#include <clock.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <io.h>
|
#include <io.h>
|
||||||
|
#include <stmp-device.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
@ -99,11 +100,11 @@ static int mxs_spi_setup(struct spi_device *spi)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
mxs_reset_block(mxs->regs + HW_SSP_CTRL0, 0);
|
stmp_reset_block(mxs->regs + HW_SSP_CTRL0);
|
||||||
|
|
||||||
val |= SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
|
val |= SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
|
||||||
val |= SSP_CTRL0_BUS_WIDTH(0);
|
val |= SSP_CTRL0_BUS_WIDTH(0);
|
||||||
writel(val, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(val, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
val = SSP_CTRL1_SSP_MODE(0) | SSP_CTRL1_WORD_LENGTH(7);
|
val = SSP_CTRL1_SSP_MODE(0) | SSP_CTRL1_WORD_LENGTH(7);
|
||||||
val |= (mxs->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
|
val |= (mxs->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
|
||||||
|
@ -120,14 +121,14 @@ static int mxs_spi_setup(struct spi_device *spi)
|
||||||
|
|
||||||
static void mxs_spi_start_xfer(struct mxs_spi *mxs)
|
static void mxs_spi_start_xfer(struct mxs_spi *mxs)
|
||||||
{
|
{
|
||||||
writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
|
writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mxs_spi_end_xfer(struct mxs_spi *mxs)
|
static void mxs_spi_end_xfer(struct mxs_spi *mxs)
|
||||||
{
|
{
|
||||||
writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
|
writel(SSP_CTRL0_LOCK_CS, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||||
writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(SSP_CTRL0_IGNORE_CRC, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mxs_spi_set_cs(struct spi_device *spi)
|
static void mxs_spi_set_cs(struct spi_device *spi)
|
||||||
|
@ -136,8 +137,8 @@ static void mxs_spi_set_cs(struct spi_device *spi)
|
||||||
const uint32_t mask = SSP_CTRL0_WAIT_FOR_CMD | SSP_CTRL0_WAIT_FOR_IRQ;
|
const uint32_t mask = SSP_CTRL0_WAIT_FOR_CMD | SSP_CTRL0_WAIT_FOR_IRQ;
|
||||||
uint32_t select = SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
|
uint32_t select = SSP_CTRL0_SSP_ASSERT_OUT(spi->chip_select);
|
||||||
|
|
||||||
writel(mask, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
|
writel(mask, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||||
writel(select, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(select, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mxs_spi_xfer_pio(struct spi_device *spi,
|
static int mxs_spi_xfer_pio(struct spi_device *spi,
|
||||||
|
@ -159,11 +160,11 @@ static int mxs_spi_xfer_pio(struct spi_device *spi,
|
||||||
writel(1, mxs->regs + HW_SSP_XFER_COUNT);
|
writel(1, mxs->regs + HW_SSP_XFER_COUNT);
|
||||||
|
|
||||||
if (write)
|
if (write)
|
||||||
writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + BIT_CLR);
|
writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||||
else
|
else
|
||||||
writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(SSP_CTRL0_READ, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
writel(SSP_CTRL0_RUN, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(SSP_CTRL0_RUN, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
|
if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
|
||||||
(readl(mxs->regs + HW_SSP_CTRL0) & SSP_CTRL0_RUN) == SSP_CTRL0_RUN)) {
|
(readl(mxs->regs + HW_SSP_CTRL0) & SSP_CTRL0_RUN) == SSP_CTRL0_RUN)) {
|
||||||
|
@ -174,7 +175,7 @@ static int mxs_spi_xfer_pio(struct spi_device *spi,
|
||||||
if (write)
|
if (write)
|
||||||
writel(*data++, mxs->regs + HW_SSP_DATA);
|
writel(*data++, mxs->regs + HW_SSP_DATA);
|
||||||
|
|
||||||
writel(SSP_CTRL0_DATA_XFER, mxs->regs + HW_SSP_CTRL0 + BIT_SET);
|
writel(SSP_CTRL0_DATA_XFER, mxs->regs + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
if (!write) {
|
if (!write) {
|
||||||
if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
|
if (wait_on_timeout(MXS_SPI_MAX_TIMEOUT,
|
||||||
|
@ -240,7 +241,7 @@ static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
writel(SSP_CTRL1_DMA_ENABLE, mxs->regs + HW_SSP_CTRL1 + BIT_CLR);
|
writel(SSP_CTRL1_DMA_ENABLE, mxs->regs + HW_SSP_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||||
ret = mxs_spi_xfer_pio(spi, data, t->len, write, flags);
|
ret = mxs_spi_xfer_pio(spi, data, t->len, write, flags);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <xfuncs.h>
|
#include <xfuncs.h>
|
||||||
#include <io.h>
|
#include <io.h>
|
||||||
|
#include <stmp-device.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <mach/imx-regs.h>
|
#include <mach/imx-regs.h>
|
||||||
|
@ -222,7 +223,7 @@ static void stmfb_enable_controller(struct fb_info *fb_info)
|
||||||
* Sometimes some data is still present in the FIFO. This leads into
|
* Sometimes some data is still present in the FIFO. This leads into
|
||||||
* a correct but shifted picture. Clearing the FIFO helps
|
* a correct but shifted picture. Clearing the FIFO helps
|
||||||
*/
|
*/
|
||||||
writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + BIT_SET);
|
writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
/* if it was disabled, re-enable the mode again */
|
/* if it was disabled, re-enable the mode again */
|
||||||
reg = readl(fbi->base + HW_LCDIF_CTRL);
|
reg = readl(fbi->base + HW_LCDIF_CTRL);
|
||||||
|
@ -255,14 +256,14 @@ static void stmfb_enable_controller(struct fb_info *fb_info)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* stop FIFO reset */
|
/* stop FIFO reset */
|
||||||
writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + BIT_CLR);
|
writel(CTRL1_FIFO_CLEAR, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
/* enable LCD using LCD_RESET signal*/
|
/* enable LCD using LCD_RESET signal*/
|
||||||
if (fbi->pdata->flags & USE_LCD_RESET)
|
if (fbi->pdata->flags & USE_LCD_RESET)
|
||||||
writel(CTRL1_RESET, fbi->base + HW_LCDIF_CTRL1 + BIT_SET);
|
writel(CTRL1_RESET, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
/* start the engine right now */
|
/* start the engine right now */
|
||||||
writel(CTRL_RUN, fbi->base + HW_LCDIF_CTRL + BIT_SET);
|
writel(CTRL_RUN, fbi->base + HW_LCDIF_CTRL + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
if (fbi->pdata->enable)
|
if (fbi->pdata->enable)
|
||||||
fbi->pdata->enable(1);
|
fbi->pdata->enable(1);
|
||||||
|
@ -277,7 +278,7 @@ static void stmfb_disable_controller(struct fb_info *fb_info)
|
||||||
|
|
||||||
/* disable LCD using LCD_RESET signal*/
|
/* disable LCD using LCD_RESET signal*/
|
||||||
if (fbi->pdata->flags & USE_LCD_RESET)
|
if (fbi->pdata->flags & USE_LCD_RESET)
|
||||||
writel(CTRL1_RESET, fbi->base + HW_LCDIF_CTRL1 + BIT_CLR);
|
writel(CTRL1_RESET, fbi->base + HW_LCDIF_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
if (fbi->pdata->enable)
|
if (fbi->pdata->enable)
|
||||||
fbi->pdata->enable(0);
|
fbi->pdata->enable(0);
|
||||||
|
|
|
@ -0,0 +1,22 @@
|
||||||
|
/*
|
||||||
|
* basic functions for devices following the "stmp" style register layout
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __STMP_DEVICE_H__
|
||||||
|
#define __STMP_DEVICE_H__
|
||||||
|
|
||||||
|
#include <linux/compiler.h>
|
||||||
|
|
||||||
|
#define STMP_OFFSET_REG_SET 0x4
|
||||||
|
#define STMP_OFFSET_REG_CLR 0x8
|
||||||
|
#define STMP_OFFSET_REG_TOG 0xc
|
||||||
|
|
||||||
|
extern int stmp_reset_block(void __iomem *, int just_enable);
|
||||||
|
#endif /* __STMP_DEVICE_H__ */
|
|
@ -43,6 +43,9 @@ config LIBUBIGEN
|
||||||
config LIBMTD
|
config LIBMTD
|
||||||
bool
|
bool
|
||||||
|
|
||||||
|
config STMP_DEVICE
|
||||||
|
bool
|
||||||
|
|
||||||
source lib/gui/Kconfig
|
source lib/gui/Kconfig
|
||||||
|
|
||||||
source lib/bootstrap/Kconfig
|
source lib/bootstrap/Kconfig
|
||||||
|
|
|
@ -41,3 +41,4 @@ obj-$(CONFIG_LIBMTD) += libmtd.o
|
||||||
obj-y += gui/
|
obj-y += gui/
|
||||||
obj-$(CONFIG_XYMODEM) += xymodem.o
|
obj-$(CONFIG_XYMODEM) += xymodem.o
|
||||||
obj-y += unlink-recursive.o
|
obj-y += unlink-recursive.o
|
||||||
|
obj-$(CONFIG_STMP_DEVICE) += stmp-device.o
|
||||||
|
|
|
@ -14,46 +14,45 @@
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <io.h>
|
#include <io.h>
|
||||||
|
#include <stmp-device.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <clock.h>
|
#include <clock.h>
|
||||||
#include <mach/mxs.h>
|
|
||||||
#include <mach/imx-regs.h>
|
|
||||||
|
|
||||||
#define MXS_IP_RESET_TIMEOUT (10 * MSECOND)
|
#define STMP_IP_RESET_TIMEOUT (10 * MSECOND)
|
||||||
|
|
||||||
#define MXS_BLOCK_SFTRST (1 << 31)
|
#define STMP_BLOCK_SFTRST (1 << 31)
|
||||||
#define MXS_BLOCK_CLKGATE (1 << 30)
|
#define STMP_BLOCK_CLKGATE (1 << 30)
|
||||||
|
|
||||||
int mxs_reset_block(void __iomem *reg, int just_enable)
|
int stmp_reset_block(void __iomem *reg, int just_enable)
|
||||||
{
|
{
|
||||||
/* Clear SFTRST */
|
/* Clear SFTRST */
|
||||||
writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
|
writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
|
if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_SFTRST)))
|
||||||
goto timeout;
|
goto timeout;
|
||||||
|
|
||||||
/* Clear CLKGATE */
|
/* Clear CLKGATE */
|
||||||
writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
|
writel(STMP_BLOCK_CLKGATE, reg + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
if (!just_enable) {
|
if (!just_enable) {
|
||||||
/* Set SFTRST */
|
/* Set SFTRST */
|
||||||
writel(MXS_BLOCK_SFTRST, reg + BIT_SET);
|
writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_SET);
|
||||||
|
|
||||||
/* Wait for CLKGATE being set */
|
/* Wait for CLKGATE being set */
|
||||||
if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, readl(reg) & MXS_BLOCK_CLKGATE))
|
if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, readl(reg) & STMP_BLOCK_CLKGATE))
|
||||||
goto timeout;
|
goto timeout;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Clear SFTRST */
|
/* Clear SFTRST */
|
||||||
writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
|
writel(STMP_BLOCK_SFTRST, reg + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
|
if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_SFTRST)))
|
||||||
goto timeout;
|
goto timeout;
|
||||||
|
|
||||||
/* Clear CLKGATE */
|
/* Clear CLKGATE */
|
||||||
writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
|
writel(STMP_BLOCK_CLKGATE, reg + STMP_OFFSET_REG_CLR);
|
||||||
|
|
||||||
if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_CLKGATE)))
|
if (wait_on_timeout(STMP_IP_RESET_TIMEOUT, !(readl(reg) & STMP_BLOCK_CLKGATE)))
|
||||||
goto timeout;
|
goto timeout;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
Loading…
Reference in New Issue