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ARM: i.MX6 Phytec phyFLEX: Add watchdog reset workaround 

phyFLEX boards beginning with 1362.2 have a workaround for this
i.MX6 bug:

ERR006282 ROM code uses nonreset PFDs to generate clocks, which may
lead to random boot failures

On these boards the SD4_DAT3 pin os connected to the CMIC. The CMIC
will reset the board after 10s when the pin isn't toggled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2014-07-02 15:19:15 +02:00
parent c8890e057a
commit d44edfe4f9
2 changed files with 35 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
arch/arm/boards/phytec-phyflex-imx6/board.c
View File

@ -26,10 +26,42 @@
#include <linux/micrel_phy.h>
#include <mach/iomux-mx6.h>
#include <mach/imx6.h>
#define ETH_PHY_RST IMX_GPIO_NR(3, 23)
#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL))
#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL)
#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
static void phyflex_err006282_workaround(void)
{
/*
* Boards beginning with 1362.2 have the SD4_DAT3 pin connected
* to the CMIC. If this pin isn't toggled within 10s the boards
* reset. The pin is unconnected on older boards, so we do not
* need a check for older boards before applying this fixup.
*/
gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
mdelay(2);
gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
mdelay(2);
gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
if (cpu_is_mx6q())
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
else if (cpu_is_mx6dl())
mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
gpio_direction_input(MX6_PHYFLEX_ERR006282);
}
static int eth_phy_reset(void)
{
gpio_request(ETH_PHY_RST, "phy reset");
@ -62,6 +94,8 @@ static int phytec_pfla02_init(void)
!of_machine_is_compatible("phytec,imx6s-pfla02"))
return 0;
phyflex_err006282_workaround();
eth_phy_reset();
phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
ksz9031rn_phy_fixup);

2
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -48,7 +48,6 @@
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
>;
};
};
@ -106,6 +105,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
>;
};
};