ARM: i.MX6 Phytec phyFLEX: Add watchdog reset workaround
phyFLEX boards beginning with 1362.2 have a workaround for this i.MX6 bug: ERR006282 ROM code uses nonreset PFDs to generate clocks, which may lead to random boot failures On these boards the SD4_DAT3 pin os connected to the CMIC. The CMIC will reset the board after 10s when the pin isn't toggled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -26,10 +26,42 @@
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#include <linux/micrel_phy.h>
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#include <mach/iomux-mx6.h>
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#include <mach/imx6.h>
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#define ETH_PHY_RST IMX_GPIO_NR(3, 23)
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#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
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MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
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#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL))
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#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL)
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#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
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static void phyflex_err006282_workaround(void)
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{
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/*
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* Boards beginning with 1362.2 have the SD4_DAT3 pin connected
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* to the CMIC. If this pin isn't toggled within 10s the boards
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* reset. The pin is unconnected on older boards, so we do not
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* need a check for older boards before applying this fixup.
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*/
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
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mdelay(2);
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
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mdelay(2);
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gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
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if (cpu_is_mx6q())
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mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
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else if (cpu_is_mx6dl())
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mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
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gpio_direction_input(MX6_PHYFLEX_ERR006282);
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}
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static int eth_phy_reset(void)
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{
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gpio_request(ETH_PHY_RST, "phy reset");
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@ -62,6 +94,8 @@ static int phytec_pfla02_init(void)
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!of_machine_is_compatible("phytec,imx6s-pfla02"))
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return 0;
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phyflex_err006282_workaround();
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eth_phy_reset();
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
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ksz9031rn_phy_fixup);
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@ -48,7 +48,6 @@
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MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
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MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
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MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
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>;
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};
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};
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@ -106,6 +105,7 @@
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
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>;
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};
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};
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