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21 Commits

Author SHA1 Message Date
Lucas Stach dc726ec5b5 clk: tegra: add Tegra124 driver
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:15 +02:00
Lucas Stach 89b062b430 clk: tegra: don't bug out on zero PLL postdiv
As the real value is 2^p a input value of 0 is
actually valid.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach d95bb6f81f clk: tegra: allow variable sized muxes
Tegra124 extended the mux by 1bit to allow for
more PLL sources.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach bf9b3842b4 clk: tegra20: register i2c clocks
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach 86a752954b clk: tegra30: register i2c clocks
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach a1f576c1e9 clk: tegra: allow to register clocks with 16 bit divider
Some peripherals have a double wide divider in front
of them.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach bbe4ddd10c clk: tegra: remove device reset hack
Now that we have a proper reset controller, it
isn't necessary anymore to keep the device reset
hack coupled to the clock.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach ee493a6152 clk: tegra: reset UARTS from clock controller
The console devices are the only ones that can't
use the reset controller properly, as they get
registered from platform code. Reset those devices
from the clock controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach 77d45d43c2 reset: add tegra reset controller
Allows us to drop the hack in the clock controller
and implement proper reset at device level.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Sascha Hauer 7b7631791e Merge branch 'for-next/tegra'
Conflicts:
	arch/arm/dts/tegra20-colibri.dtsi
	arch/arm/dts/tegra20-paz00.dts
	arch/arm/dts/tegra20.dtsi
	drivers/clk/tegra/clk-periph.c
2014-05-05 13:34:21 +02:00
Beniamino Galvani 32a2a673c6 clk: gate: add flags argument to clock gate constructor
This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-29 08:15:24 +02:00
Lucas Stach f427316ce2 clk: tegra: add Tegra3 driver
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:57 +02:00
Lucas Stach b809c5b410 clk: tegra: consider new T30 clock registers
Tegra3 has some new clocks and resets. The new
registers don't form a linear range with the
old ones.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:57 +02:00
Lucas Stach 7de93b77e6 clk: tegra20: convert to dt-binding defines
Allows to make relationship between DT and driver
more explicit and avoids duplication.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-07 08:36:03 +02:00
Sascha Hauer 82163afcf0 clk: clk-fixed-factor: pass flags to initializers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-03-28 21:03:14 +01:00
Sascha Hauer f4c7536514 clk: clk-gate: pass flags to initializers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-03-28 21:03:02 +01:00
Sascha Hauer b33e5ba246 clk: clk-mux: pass clk flags from initializers
struct clk has a flags field, let the clk-mux initializers set this
field.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-03-28 10:51:30 +01:00
Lucas Stach 3504f23ed8 clk: tegra: add SDMMC clocks
Provide peripheral clocks for the SD controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-12-04 14:59:39 +01:00
Lucas Stach 7b6c063f57 tegra: speed up system bus
We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-12-04 14:59:39 +01:00
Lucas Stach 3cfd3be736 tegra: add peripheral clocks
Only UART clocks are included for now, but the code should cover
other peripherals needs, too.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-07-02 08:36:09 +02:00
Lucas Stach c16730e3c6 tegra: add new clock framework driver
This removes the existing Tegra CAR driver and replaces it with code
ported from the Linux clock framework.

In the current state only the relevant PLLs are supported, but this is
no functional regression from the existing code.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-07-02 08:36:09 +02:00