check the 4 mac address register and return at the first valid
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, that uses this core on the
Zynq SoCs, opted for on. Turn it off for all devices.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The macb/gem core is used by the Zynq SoC. In preparation of sharing
the macb driver between at91 and Zynq, rename the platform data to
'struct macb_platform_data', and move the definition to a common
location.
Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we use a full buffer no need to check the SOF
and reset the rx_tail
fix at the same time the gem detection so we can have the rx_buffer
allocated correctly according to the IP
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
based on the kernel code
detect it via IP version
In the GEM we can use a full packet buffer for receive but the buffer size
need to be 64bit size aligned.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
the mininal tx ring size is 2 as if one we wrap on the same descriptor
and can cause IP lock on GEM (gigabit version) this is always the case
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as eth_device init is planning for remove and we need the init before register
the mdio bus
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we will add later the GMAC IP verion support (GEM)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as in the kernel use is_rmii
flags for pinctrl
phy_flags for phylib flags
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adapt phylib from linux
switch all the driver to it
reimplement mii bus
This will allow to have
- phy drivers
- to only connect the phy at then opening of the device
- if the phy is not ready or not up fail on open
Same behaviour as in linux and will allow to share code and simplify porting.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will ensure that we send an other packet only when the first one is send.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We never had interrupt support in barebox and we have no plans to
add interrupt support. Even if we do I doubt the current fragments
of irq support are helpful, so remove them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this rework is done in order to add a phylib and allow to have phy driver support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this implementation is based on linux one (v2.6.35-rc5-76-gd0c6f62)
it will calculate all the clock dynamically instead of statictly
this will use also the new clock framework
it will also print the clock status after the console init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When operating in plain MII mode, the driver assumes the RMII bit not
set. Although this is the power on reset value, clearing this bit helps
when playing with different network setups.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
The driver was not using the phy address supplied by the platform
data. With this patch the miiphy.address is set phy addr supplied
by the mac platform data.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Sascha Hauer
Jean-Christophe PLAGNIOL-VILLARD
Steffen Trumtrar
Josh Cartwright
Alexander Shiyan
Hubert Feurstein
Marc Kleine-Budde