The partition layout is board-specific, so only the barebox partitions
need to be in the fixed location expected by the MLO code.
Signed-off-by: Jan Luebbe <jluebbe@debian.org>
We need to wait some time between activating the ethernet and
being able to send the first frame. I have not investigated why
that is the case.
Fixes: SYS#488
As this is the bootm image handler implementation for the kwbootimage
it is of no use if BOOTM is missing and fails to link.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The instructions used in those files are only supported on ARMv7.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The wdog1 pinctrl got fixed with linux upstream commit 213e51ca8df1 ("ARM:
dts: imx7: Add "LPSR" to LPSR iomux pin names").
Remove the old workaround, since it triggers a build error.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
fsl,imx7d-iomuxc is provided by selecting PINCTRL_IMX_IOMUX_V3. Select it
since a system without it will not be very usefull.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in the routine's description this routine is to return void,
hence fix its declaration to remove compiler warning.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move PIT driver code to 'drivers/clocsource' and accomodate it by
adjusting Kconfig variables. Rename the file to 'timer-atmel-pit.c' to
re-align the driver with code in Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
if not set, barebox will use first console by default.
On this board first console is KEYBOARD_GPIO, so we will end
in unusable state.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.
This is really important on newer CPU core with bigger write buffers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
(including the cache handling) is still at v6. As we don't make use of
the more advanced features of the v7 MMU in Barebox, it's okay to just
override this to properly identify the CPU as ARMv6.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARMv7 the exception vectors inside the barebox binary are used directly
by remapping the vectors base through the VBAR register. While VBAR allows
to remap the exception vectors freely, it still imposes a minimum alignment
of 32 byte, as the lower bits are treated as the exception vector offset.
Enforce this alignment inside the barebox binary.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is necessary to make second stage booting work when the register
window is already moved.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This just starts the main image of the mvebu image assuming that the
header images just setup the RAM. The position of the internal register
window is provided in the header as introduced in the previous commit.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
A problem when using 2nd stage booting on mvebu is that the first bootloader
already switched the register window location from 0xd0000000 to
0xf1000000 by writing to 0xd0000080. When the second bootloader also
tries to do this switch it writes to the wrong location resulting in an
exception and so a boot failure.
For this reason the base address of the register window is passed in the
barebox header and picked up from there by early code. In a further
patch bootm is taught to put the actual position of the window there for
the second bootloader to finally make second stage booting work.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
binary.0 sets up all RAM but the address decoding isn't adapted accordingly
which makes barebox assume that there are only 512 MiB of RAM on a single
bank instead of two banks with 1 GiB each.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Similar to the two previous commits, this gets rid of a of-fixup which
is strange because the soc init stuff is rerun then when a new dt for
booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Similar to the previous commit, this gets rid of a of-fixup which is
strange because the soc init stuff is rerun then when a new dt for
booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This gets rid of a of-fixup which is strange because the soc init stuff
is rerun then when a new dt for booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit switches the RaspberryPi arch over to probe Barebox
from the builtin DT and enables multi-image builds.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To let the user select the right base, when building multi-image.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Makes more space available for the malloc area and will allow
to switch to multi-image later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This way we can print the correct model in the Barebox banner.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Raspberry PIs use different versions schemes for the older and newer
variants. The decoding arrays for these schemes were split up in rpi.c
and rpi2.c. This is not required, as the appropriate versioning scheme
can be determined programmatically.
Signed-off-by: Enrico Joerns <ejo@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This machine was a prototype and was never shipped to customers.
Since it has no dependencies to any image, it can be removed.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MACH_SABRELITE is only selectable if IMX_MULTI_BOARDS is enabled. The latter
already selects HAVE_PBL_MULTI_IMAGES.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Status quo is that initially a size of 64 MiB is assumed (which is also
used to determine the size of the malloc area) and then later the dtb
is fixed up with the actually available RAM which is then used.
Instead detect the real RAM size earlier and don't fixup the device tree.
The device tree is fixed up instead by generic code. This way the malloc
area is more appropriately sized and RAM detection is more similar to mach-imx
which is both nice.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This isn't needed since mvebu was converted to multi-pbl
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have a number of sama5d3 devices that sometimes hangs at the
barebox prompt during boot due to floating RX pins. This patch
fixes the problem for us (and probably others). It is similar in
nature to linux kernel commit 138c2b2f175b ("ARM: dts: at91: fixes
dbgu pinctrl, set pullup on rx, clear pullup on tx")
While at it, remove pointless waste of power that the pullup of
the TX pins causes and fix the signal comments for SAMA5D4.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IIM unit in defferent i.MX SoCs is always the same, but the
number of actually equipped fuses differs between the SoCs.
Reading nonexistent fuses oopses, so only register the fuses
we can actually read.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).
The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.
In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.
With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.
The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).
We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory
The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.
The PSCI and secure monitor code is based on the corresponding U-Boot
code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Jan Luebbe
Holger Hans Peter Freyther
Lucas Stach
Alexander Kurz
Yegor Yefremov
Sascha Hauer
Andrey Smirnov
Oleksij Rempel
Uwe Kleine-König
Enrico Joerns
Daniel Schultz
Peter Rosin
Wadim Egorov