The 32KHz from dmtimer0 is derived from a SoC internal RC oscillator
which is quite inaccurate. Switch to dmtimer2 which is driven from
the high frequency oscillator clock.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyFLEX-AM335x modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyCORE-AM335x
modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Added support for IM8G16D3FBBG15EI 1024MiB RAM on one chip.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only enable eeprom when populated. So disable it in dtsi
file and enable if needed in board dts.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When doing USB boot without having it enabled in the config func is used
unitialized. Explicitly set this to NULL so that booting fails in this case.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To make updating barebox to nand easy. To bootstrap from a SD
card:
barebox_update -t nand-xload /boot/MLO
barebox_update -t nand /boot/barebox.bin
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Breathe some life back into the beagleboard:
- switch to multiimage support
- update config
- initialize early UART for debugging
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Multi machine barebox builds have to pass information on which
board we are running on via boarddata. Usually this will be a
pointer to a device tree. Some boards might not have a device
tree available though because they are either not ported over
to device tree yet, or are running in some limited first state
environment which does not offer enough space for a device
tree. For these cases this patch adds a mechanism to embed a
machine number into a struct type along with a magic number.
This makes it possible to check for a specific machine
later during regular runtime.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OMAP3 supports uploading the first stage bootloader via USB.
The ROM leaves the MUSB controller enabled and it can then be used
to upload a 2nd stage image. This patch adds the omap3-usb-loader tool
and the necessary barebox support to upload the 2nd stage image.
The omap usb loader tool is downloaded from https://github.com/grant-h/omap_loader
and changed to also accept CHSETTINGS images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
U-Boot uses 2 as the DSS divider, so do the same in barebox. This
shouldn't currently have any effect to barebox, but makes porting
some U-Boot code easier which makes assumptions about the DSS clock
rate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a barrier after setup_c(). This is necessary because otherwise
some global variable assignments may be reordered by the compiler to be
executed before setup_c which cannot work.
This was observed when doing other unrelated changes to the start function,
it seems in current mainline state the compiler does not actually reorder
the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The AM335x SPI NOR barebox update handlers only writes a file to a device,
so use the generic handler for this purpose.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix the DDR init sequence the same way as done by aee0013e53b339a5
from U-boot in order to prevent the boot hang under reboot stress test.
Quoting this commit log:
"Currently by running the following test:
=> setenv bootcmd reset
=> save
=> reset
, we observe a hang after approximately 20-30 minutes of stress reboot test.
Investigation of this issue revealed that when a single DDR chip select is used,
the hang does not happen. It only happens when the two chip selects are active.
MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":
"The controller must keep the memory lines quiet (except for CK) for the ZQ
calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
for other ZQCL and 64 for ZQCS)."
According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:
"Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"
So make sure to activate one chip select at time (CS0 first and then CS1 later),
so that the required JEDEC delay is respected for each chip select.
With this change applied the board has gone through three days of reboot stress
test without any hang."
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are still some nodes not used in barebox. Removed them.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There is no point in repeating the board setup on the main cluster.
It is done either in the AVP startup path or from a first stage loader.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
So we can drop it from the defconfig and stop bothering
the user with this choice by default.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As SoCFPGA is multi-image enabled there is no real reason
to bother the user with asking for the text base. Fixes a
bunch of randcfg failures.
Regenerate defconfig to drop the explicit config there, which
unfortunately introduces quite a bit of churn.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On AM335x SOCs the maximum size of a downloaded MLO/PBLX image is 109 KB.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With device tree the device name starts with a number, so
the device parameters are not accessible on the shell. Register
a separate device for the ocotp to make the permanent_write_enable
variable accessible again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Due to the DBBT, multiple FCBs, two bootloaders and the possibility
of bad blocks the bootloader partition needs more space. Increase
it to 4MB.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Michael Grzeschik
Daniel Schultz
Teresa Remmet
Sascha Hauer
Antony Pavlov
Fabio Estevam
Lucas Stach
Lucas Stach
Wadim Egorov
Juergen Borleis
Herve Codina