SoCFPGA is completely multi-image enabled and probes the barebox
from a built-in DT, so there is no point in building a barebox
image that isn't able to probe from DT.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the missing stdout-path properties for the socfpga boards and
enable CONFIG_CONSOLE_ACTIVATE_NONE.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of using internal devicetree files, use the official ones from
/dts/src/arm.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Above the 0x800 offset the manufacturer provides the board type, a serial
number and the MAC as three simple strings. Extract these strings, provide
their value as global variables and set the MAC into the ethernet unit.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This IP core is shared between many FSL SoCs. The MPC5200 provides this
core as well.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In preparation to re-use the i.MX I2C driver for the MPC5200 SoC use
clock.h instead of clocks.h for the clock API.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This change in the port config register enables the USB/OHCI support and
makes USB work on the PCM030's regular development baseboard.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In order to enable and use USB/OHCI on the MPC5200 the USB PLL register must be
set.
It's not easy to find a correct value for this register, it seems it depends on
the used external reference frequency and some other 'magic' things. There are
some values out in the wild for the 33,333333 MHz and 33,333000 MHz reference
frequency case, but they are not consistent over the boards.
The value used here in this change for the USB PLL register is from the first
days of support for this platform and works at least on the reference
baseboard.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The files flash-header-*.imxfg contains two defines which are use in
include files flash-header-phytec-*.h. The first define is SETUP_MDCFG0.
In the second define name some RAM size value were used, e.g.
SETUP_S_DL_512MB_1GB or SETUP_1GIB_2GIB_4GIB.
It's better to name also the second define after the register names,
here MMDC1_MDCTL and MMDC1_MDASP, because these values changes for every
RAM configurations and it's consistent with the first define.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox currently names the SPI NOR device "/dev/sst25vf016b",
but the barebox update handler still points to "/dev/m25p80",
causing barebox_update to fail.
Choose a descriptive name instead.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
for bank2_size get_ram_size must be called with the CS1 area. With the
recent fix to calculate CS1 start this now starts at 0x90000000 and no
longer at 0x80000000.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
DDR_64BIT_2GB corresponds to two chip selects (ncs = 2) with 1GiB
each. In this case cs_density must be configured to 8Gb (1GiB).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current calculation does not take the 0x10000000 offset where
SDRAM starts into account. For example with a 1GiB chip density
the current code calculates cs1 start to 0x40000000, but it
has to be 0x10000000 + 0x40000000 = 0x50000000. Add the missing
8 32MiB chunks.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The cm-fx6 board is a module from Compulab with different i.MX6 SoCs.
This module is also found in the Utilite Mini Computer this patch
also adds support for.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have functions to setup the i.MX uart for early use, but these all
depend on DEBUG_LL. Move them to imx-uart.h to make them usable for
the regular PBL console.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Several i.MX6 boards like to do their SDRAM setup in code rather than
in DCD tables. Add the SDRAM setup code from U-Boot to make it easy
to adopt the SDRAM setup from the U-Boot port of these boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Avoids a build failure if the config does not include ULPI support.
This is similar to what has been done to the PCA100 board.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently Barebox fails to boot a kernel/devicetree pair on PowerPC.
With of_find_node_by_path() the framework uses a global variable to find
the root node and fails. With of_find_node_by_path_from() and forwarding
the 'root' parameter it works again as expected.
This fixes the following error message at run-time:
Loading U-Boot uImage '/tmp/tftpcmd/kernel'
Loading devicetree from '/tmp/tftpcmd/oftree'
bootm: No devicetree given.
handler failed with: Invalid argument
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The variable partname is used in the error path for debugging.
We have to free it after this use.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
LoaderTimeInitUSec and LoaderTimeExecUSec are used e.g. in systemd-analyze
to calculate the time spent in the firmare and barebox.
LoaderDevicePartUUID is used to mount the EFI partition to /boot.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
AT91 has a custom barebox head that doesn't support Thumb2.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current supported Rockchip board is initialized from a
builtin DTB and I suppose all future boards will do the same.
Fixes various missing functions and prototypes in Rockchip clk
driver.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
So we can drop it from the defconfig and stop bothering
the user with this choice by default.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use allocate_pages() instead of allocate_pool(). With allocate_pages() we
can specify the address. This way, any address passed to the kernel will
never exceed the lower 32 bit.
If possible, try to allocate a larger pool.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Explain the relationship between the OCOTP addresses from the i.MX6
Reference Manual and the file offset in '/dev/imx-ocotp'.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The 32KHz from dmtimer0 is derived from a SoC internal RC oscillator
which is quite inaccurate. Switch to dmtimer2 which is driven from
the high frequency oscillator clock.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The sandbox defconfig hasn't been updated for a long time. This enables
tons of features since the binary size is not relevant at all for sandbox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyFLEX-AM335x modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyCORE-AM335x
modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
