Barebox crashes during startup, because the SDRAM controller has not been
initialized.
Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The PLL setup occasionally fails when the setup code runs
from SDRAM, so copy a little assembler helper function to
SRAM and execute it there.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
edb93xx SDRAM initialization: Issue a precharge all command before forcing the
precharge of all SDRAM banks. Write to the SDRAM in order to force a precharge,
reading causes the edb93xx boards to hang
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch updates the definitions of the __raw_read and __raw_write
functions so that "sparse" doesn't complain.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
The tags for the command line parameters are not used, so let's remove them:
- CMDLINE_TAG
- SETUP_MEMORY_TAGS
- INITRD_TAG
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
If the DEBUG macro is defined the compiler complains about a missing
'ipu_base' variable.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Previous code ran the edb9302(a) boards with the PLL same settings as the
edb9301, at 166MHz core and 66MHz system bus clock. In difference to the edb9301
board the edb9302(a) is equipped with an EP9302 processor, which can be clocked
at higher rates than the EP9301. Therefore we can configure the edb9302(a) with
the same PLL settings as the other non-edb9301 boards, namely at 200MHz for
the core and 100MHz for the system bus clock.
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Before programming the SDRAM mode registers, mode register update mode must be
selected by setting the MRS bit and clearing INIT in GlConfig
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
EP93xx: The system controller register definition doesn't take into account a 4
byte gap between ChipId and SysCfg, in consequence all accesses to syscon registers
ahead of ChipId fail. Fix this by inserting a filler field
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
edb93xx: The purpose of early_udelay() is to provide delay functionality in the
early board setup, when the stack isn't set up yet. With some compiler versions
the current implementation makes use of the stack and ends up crashing. Fix this
by removing an explicit division from early_udelay()
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
edb93xx: according to the datasheet UART1 needs to be enabled explicitly
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This file has no useful things for others than the driver,
so move it next to the driver and remove the corresponding
include from other files.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ep93xx eth driver: Remove unnecessary parentheses in definition of the constants
MII_ADDRESS_MAX and MII_REGISTER_MAX
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ep93xx eth driver: Define ep93xx_eth_send_packet() and ep93xx_eth_rcv_packet()
before ep93xx_eth_probe(), and eliminate their prototype declarations
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
These cache functions have been extracted from
arch/arm/boot/compressed/head.S. The old code only worked
properly on ARMv4. Tested on ARMv4, ARMv5, ARMv6 hardware.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Using these macros simplify the configuration for special GPIO usage. But they
should use correct bit positions for usage in the IOMUX_PAD() macro.
Note: These are the bit positions of the i.MX35 CPU. Not checked for the other
i.MX3x CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fixes a alignment problem which may show during this
scenario:
- 32 or 64 attached NOR flash
- flashing an image directly from network to the nor flash
The involved network driver is "smc9111.c".
The data that comes from the network stack and should be written into
the flash isn't 32 bit alligned (at least with this network driver).
This is probably due to the 48 bit wide ethernet addresses.
However the "cfi_flash.c" driver doesn't handle this situation, and
accesses the not-alligned address with a 32 bit pointer.
This patch fixes the problem by reducing the access width if an
alligment problem between source and destination is found.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On my little endian PXA270, the ethernet address is byte swapped:
correct ethernet address: 00:50:c2:80:a7:bd
broken ethernet address: 50:00:80:c2:bd:a7
The correct value is what the sticker on the baoard and the linux driver
says. This patch fixes the problem by reading the ethaddr byte-wise from
the eeprom.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Juergen Beisert
Jaccon Bastiaansen
Matthias Kaehlcke
Marc Kleine-Budde