Based on Linux's support by Thomas Petazzoni:
commit b9d12085f2f531fdea67f0361564e0812696227c
Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Tue Apr 15 15:50:19 2014 +0200
net: phy: add minimal support for QSGMII PHY
This commit adds the necessary definitions for the PHY layer to
recognize "qsgmii" as a valid PHY interface. A QSMII interface, as
defined at
http://en.wikipedia.org/wiki/Media_Independent_Interface#Quad_Serial_Gigabit_Media_Independent_Interface,
is "is a method of combining four SGMII lines into a 5Gbit/s
interface. QSGMII, like SGMII, uses LVDS signalling for the TX and RX
data and a single LVDS clock signal. QSGMII uses significantly fewer
signal lines than four SGMII busses."
This type of MAC <-> PHY connection might require special handling on
the MAC driver side, so it should be possible to express this type of
MAC <-> PHY connection, for example in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When using more than one PCI bus, we have to assign unique numbers
to each bus. Use an auto-incremented bus index and assign it to
each registered bus. Also, allow the PCI host controller to update
internal registers by calling set_busno with assigned bus number.
While at it, add pci_controller struct to set_busno callback,
add a back reference to pci_controller to pci_bus, and clean up
unused left-overs from Linux import.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
EHCI HCD has a private version of min3() determining the smallest
number out of 3. We already have min()/max() imported from Linux,
also get min3()/max3() and use it instead of EHCI's private one.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On Marvell MVEBU SoCs internal registers are usually remapped from reset
default. While Dove and Kirkwood always had their registers remapped,
some Armada 370 and XP where shipped with bootloaders that did not remap
them.
On Barebox these registers are remapped early and on all MVEBU SoCs, so
provided DTs should always reflect that in their mbus ranges property.
This patch registers a fixup for DTBs and allows individual SoCs to add
specific remap ranges to the fixup list. The fixup is registered on
pure_initcall to even allow to fixup pbl or appended DTBs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Yes, we already have roundup/rounddown. Unlike these macros
round_up/round_down are optimized to (and only work with)
power-of-2 arguments. It's a poor name, but kernel code needs
it, so add it to barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With upcoming EFI payload support the efi.h file will diverge
from the kernel, so move it from include/linux/ to include/
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This driver is based on Linux 2.6.39 8139too driver.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The doxygen documentation is long outdated. Remove it. It will
be replaced with sphinx based documentation later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Even when both the ethernet controller and the phy support certain
features a board may have additional limitations. Allow specifying
it in the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add stripped sown version of the reset controller
framework from the Linux kernel.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Clock gates having the CLK_GATE_HIWORD_MASK flag set use the upper 16
bits of the register as a "write enable" mask for the value in the
lower 16 bits.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When a mtd device can have bad blocks we want to create a
bb device, so do this automatically. This allows us to
drop bb device creation from the environment.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Rework the current framework so that I/O mapped I/O resources are
also possible.
Signed-off-by: Michel Stam <michel@reverze.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This updates the clk-divider to Kernel code, but without power-of-two
divider support which we do not need yet. This also adds table based
divider support to the divider.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This macros are used in exported from linux TI DaVinci code.
Also this macros are used in MIPS cache support code.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MTD internal API presently uses 32-bit values to represent device
size. This patch updates them to 64-bits but leaves the external API
unchanged.
In general, changing from 32-bit to 64-bit values cause little
or no changes to the majority of the code with the following
exceptions:
- printk message formats;
- division and modulus of 64-bit values (mtd_div_by_wb,
mtd_div_by_eb may be used in some of such cases).
Was tested on phyFLEX i.MX6.
Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev@sam-solutions.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Antony Pavlov
Ezequiel Garcia
Sebastian Hesselbarth
Lucas Stach
Beniamino Galvani
Michel Stam
Dmitry Lavnikevich