These are necessary for USB support. To make sure they are actually
enabled when a USB capable barebox is started call the clock enable
function during startup also for the full barebox, not only the MLO.
Signed-off-by: Rolf Evers-Fischer <rolf.evers.fischer@delphi.com>
Since 93a6c6a808("dts: update to v3.17-rc2") we have a correct gpio
configuration. This results in a double gpio request what receipted in a
error message like this one:
gpiolib: _gpio_request: gpio-25 (phy-reset) status -16
Now with this patch the problem is gone.
Signed-off-by: Silvio Fricke <silvio.fricke@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This driver is based on mach-at91/gpio.c and linux pinctrl driver.
The driver contains the gpio and pinctrl parts (like in linux) because the two parts
share some structures and logics.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit add functions from mach-at91/gpio.h in include/mach/gpio.h.
This allow to use these functions outside the mach-at91 folder.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
By retrieving the ecc_mode from pdata we can use the same code for device tree and
non device tree probing. Which was not possible before, because ecc_mode was arbitrarily set to
NAND_ECC_SOFT.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
dts/ is for upstream dts files only. Move barebox specific file
to arch/arm/dts/ so that it doesn't get removed by the next
dts update.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As of 3.17-rc1 the upstream dts sources for the rockchip rk3188 use
incompatible clock bindings. We currently do not have the resources
to update the clock driver to this new binding, so we use local copies
of the Linux 3.16 dtsi files. Due to the incompatible change the
internal device tree won't work with kernels newer than 3.17-rc1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
By adding this structure member, we can retrieve the pmecc config, through the device tree.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This fixes various stability issues seen on new boards
with the old setup.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds a new Marvell Kirkwood-based board, by following the currently
supported boards.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It's often useful to get some information about a barebox image
before starting or flashing it. This patch introduces barebox
Image MetaData (IMD). When enabled a barebox image will contain
a list of tags containing the desired information. We have tags
for:
- the barebox release (2014.07.0-00160-g035de50-dirty)
- the build timestamp (#741 Mon Jul 28 15:08:54 CEST 2014)
- the board model the image is intended for
- the device tree toplevel compatible property
Also there is an additional generic key-value store which stores
parameters for which no dedicated tag exists. In this patch it
is used for the memory size an image supports.
Since there is no fixed offset in a barebox image which can be
used for storing the information, the metadata is stored somewhere
in the image and found by iterating over the image. This works
for most image types, but obviously not for SoC images which are
encoded or encrypted in some way.
There is a 'imd' tool compiled from the same sources for barebox,
for the compile host and for the target, so the metadata information
is available whereever needed.
For device tree boards the model and of_compatible tags are automatically
generated.
Example output of the imd tool for a Phytec phyFLEX image:
build: #889 Wed Jul 30 16:08:54 CEST 2014
release: 2014.07.0-00167-g6b2070d-dirty
parameter: memsize=1024
of_compatible: phytec,imx6x-pbab01 phytec,imx6dl-pfla02 fsl,imx6dl
model: Phytec phyFLEX-i.MX6 Duallite Carrier-Board
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To build an object file from a device tree currently we currently
have to add them to the Makefile twice, once to dtb-y and once to
obj-y. This patch introduces obj-dtb-y and pbl-dtb-y to directly
compile a device tree object file for inclusion in the barebox binary
or the pbl respectively.
The now unneeded dtb-y targets are removed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have our file helper functions in several places. Move them
all to lib/libfile.c.
With this we no longer have file helpers in fs/fs.c which contains
the core fs functions and no functions in lib/libbb.c which are
not from busybox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ethernet mac and mdio nodes must be explicitly enabled to override
the disabled setting in am33xx.dtsi.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
[voice.shen@atmel.com: apply this patch from Matteo Fortini for
sama5d3xek to sama5d3_xplained board]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Most diffstat comes from refreshing the config. The only real change
is that the NAND xload update handler is enabled now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for 256MB and 128MB RAM configurations of the
phyCORE-AM335x. This is done as new images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- use am335x_barebox_entry() to remove the need for hardcoded SDRAM
size
- remove hardcoded memory settings from device tree since there are
different memory sizes available for this board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a function which reads back the SDRAM controller settings.
This is used in a AM33xx specific barebox entry function and a
SDRAM driver which registers a SDRAM memory bank.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With an update of the am33xx.dtsi (commit 9313920df6) the mdio and mac
nodes are not enabled on default any more. Enable them explicit
in the board dts now.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the functional driver itself, it also adds SoC specific PHY
setup required for PCIe. Currently, only Armada 370 is fully supported.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM946E-S is used in the DIGIC family SoCs.
ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:
.word 0x41009400 @ ARM94x
.word 0xff00ff00
W(b) __armv4_mpu_cache_on
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On at91sam9n12 soc, it has pllb, while on sama5d3 soc,
it doesn't has pllb.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On Marvell MVEBU SoCs memory size is set up by BootROM and can be read
from SoC's RAM controller. With early DT fixups available, set corresponding
DT node to reflect accessible amount of directly attached RAM.
This patch also removes non-DT call to arm_add_mem_device to silence a
warning about request_region conflict due to adding a mem device twice.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With proper DT fixup in place, we can now remove the overwrite of
mbus ranges in Armada 370 Mirabox and Armada XP Openblocks AX3.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>