Commit graph

5232 commits

Author SHA1 Message Date
Stephen Warren
f5c03006dd usb: ci_udc: Support larger packets
ci_ep_queue() currently only fills in the page0/page1 fields in the
queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB
(page-aligned), then this prevents the HW from knowing where to write
the balance of the data.

Fix this by initializing all 5 pageN pointers, which allows up to
16KiB (potentially non-page-aligned) buffers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-30 10:30:57 +02:00
Lukasz Majewski
672ad18c27 dfu:fix: Replace wrong return value with proper one
This patch remove always false (since we tested ret = 0) ternary operator
with ret value returned.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-04-30 10:30:57 +02:00
andrey.konovalov@linaro.org
e6e493f341 exynos: usb: Fix data abort on boards w/o vbus-gpio node in the DT
Commit 4a271cb1b4 doesn't take into account that fdtdec_setup_gpio()
returns success when the gpio passed to it is FDT_GPIO_NONE (no
gpio node found in the fdtdec_decode_gpio() call). This results in
calling gpio_direction_output() on invalid gpio. For this reason
executing "usb start" command on Arndale causes data abort in the
ehci-exynos driver.

Add the fdt_gpio_isvalid() check to fix that problem.

Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
2014-04-30 10:30:57 +02:00
Rob Herring
078d7302ac usb: musb: fill in usb_gadget_unregister_driver
Add missing missing disconnect and unbind calls to the musb gadget driver's
usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail
to uninitialize and run a 2nd time.

Signed-off-by: Rob Herring <robh@kernel.org>
2014-04-30 10:30:57 +02:00
Rob Herring
52d45012ff usb: handle NULL table in usb_gadget_get_string
Allow a NULL table to be passed to usb_gadget_get_string for cases
when a string table may not be populated.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
2014-04-30 10:30:57 +02:00
Przemyslaw Marczak
fd2a89b20b usb:gadget:f_thor: fix write to filesystem by add dfu_flush()
Since dfu read/write operations needs to be flushed manually,
writing to filesystem on MMC by thor was broken. MMC raw write
actually is working fine because current dfu_flush() function
writes filesystem only. This commit adds dfu_flush() to f_thor
and now filesystem write is working.

This change was tested on Trats2 board.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-04-30 10:30:57 +02:00
Przemyslaw Marczak
adfc17bf09 usb:gadget:f_thor: code cleanup in function download_tail()
In thor's download_tail() function, dfu_get_entity() is called
before each dfu_write() call and the returned entity pointers
are the same. So dfu_get_entity() can be called just once and
this patch changes this.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-04-30 10:30:57 +02:00
Adrian Cox
ea42777567 usb: Add endian support macros to interrupt transfers in the EHCI driver.
Update the EHCI driver to support interrupt transfers on PowerPC.

Signed-off-by: Adrian Cox <adrian@humboldt.co.uk>
2014-04-30 10:30:56 +02:00
Nobuhiro Iwamatsu
ede4d5e387 usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs
The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-30 10:30:56 +02:00
Shaveta Leekha
a405764c1e drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte write
Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"

However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
        RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.

Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.

To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-04-29 07:10:58 +02:00
York Sun
dec1861be9 driver/mxc_i2c: Move static data structure to global_data
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
2014-04-29 07:10:27 +02:00
Tom Rini
080d897585 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-04-25 14:53:51 -04:00
Zhao Qiang
08ad9b068a ar8031: modify the config func of ar8031 to ar8021_config
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Prabhakar Kushwaha
1eaa742d85 driver: Add support of image load for MMC & SPI in SPL
Add support of loading image, binary for MMC and SPI during SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
e278ddcd7f driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.

During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.

Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
5abed9c546 driver/ifc: define nand_spl_load_image() for SPL
nand_spl_load_image() can also be used for non TPL framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Tang Yuantian
aade20046b mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
349689b802 drivers/ddr: Fix possible out of bounds error
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Priyanka Jain
2ee6c52e22 driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons

-On SoCs that have FMAN-v3H  like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.

So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.

This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Nikhil Badola
896720ceb2 fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Prabhakar Kushwaha
613ab32c47 driver/mmc: fix compile warnings
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Nikhil Badola
11856919f2 fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
        P1010 rev 1.0
        B4860 rev 1.0, 2.0
        P4080 rev 2.0, 3.0

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Codrin Ciubotariu
44afbbc0f0 net/phy: Fix PHY id for VSC8514
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
York Sun
e77224e2d8 driver/fsl_ifc: Add a function to finalize CS0 address binding
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-04-22 17:58:47 -07:00
Zhao Qiang
2a44efeb21 QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Zhao Qiang
dcf1d774bf QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Nikhil Badola
0ecb15c8e9 fsl/usb: Fix phy type for Second USB controller
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy

Signed-off-by: Nikhil Badola <B46172@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Albert ARIBAUD
c9aab0f9dd Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-04-21 21:01:35 +02:00
Albert ARIBAUD
94b972d366 Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2014-04-21 20:13:48 +02:00
Daniel Schwierzeck
538cf92c8c MIPS: drop incaip board
This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
2014-04-20 13:16:43 +02:00
David Müller (ELSOFT AG)
d2ff5e55c3 e1000: remove redundant assignment
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2014-04-18 16:14:10 -04:00
Paul Burton
6fb49e4aa0 pcnet: force ordering of descriptor accesses
The ordering of accesses to the rx & tx descriptors is important, yet
the send & recv functions accessed them via regular structure accesses.
This leaves the compiler with the opportunity to reorder those accesses
or to hoist them outside of loops. Prevent that from happening by using
readl & writel to access the descriptors. As a nice bonus, this removes
the need for the driver to care about endianness.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-18 10:42:30 -04:00
Paul Burton
a354ddc3d7 pcnet: align rx buffers for cache invalidation
The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-18 10:42:30 -04:00
Paul Burton
f1ae382dfd pcnet: access descriptor rings & init block uncached
The prior accesses to the descriptor rings & init block via cached
memory had a few issues:

  - The memory needs cache flushes or invalidation at the appropriate
    times, but was not necessarily aligned on cache line boundaries.
    This could lead to data being incorrectly lost or written back to
    RAM at the wrong time.

  - There are points where ordering of writes to the memory is
    important, but because it's cached memory the pcnet controller
    would see cache lines written back ordered by address. This could
    occasionally lead to hardware seeing descriptors in an incorrect
    state.

  - Flushing the cache constantly is inefficient.

So, to avoid all of those issues simply access the descriptors & init
block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is
used to do this (retrieving an address in kseg1) as I could see no
existing generic solution. Since the MIPS Malta board is the only user
of the pcnet driver, hopefully this doesn't matter.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-18 10:42:30 -04:00
Masahiro Yamada
36bf57b6fb arm: remove lubbock board support
Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/lubbock/*
 - Remove include/configs/lubbock.h
 - Cleanup defined(CONFIG_LUBBOCK)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:30 -04:00
Masahiro Yamada
4fb3925ff8 powerpc: remove RPXClassic, RPXlite boards support
Enough time has passed since these boards were moved to Orphan. Remove.

 - Remove board/RPXlite/*
 - Remove board/RPXClassic/*
 - Remove include/configs/RPXlite.h
 - Remove include/configs/RPXClassic.h
 - Clean-up defined(CONFIG_RPXCLASSIC)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:30 -04:00
Karicheri, Muralidharan
fc9a8e8d40 keystone2: net: add keystone ethernet driver
Ethernet driver configures the CPSW, SGMI and Phy and uses
the the Navigator APIs. The driver supports 4 Ethernet ports and
can work with only one port at a time.

Port configurations are defined in board.c.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
2014-04-17 17:24:39 -04:00
Karicheri, Muralidharan
2bcdf84d58 spi: davinci: add support for multiple bus and chip select
Currently davinci spi driver supports only bus 0 cs 0.
This patch allows driver to support bus 1 and bus 2 with
configurable number of chip selects. Also defaults are
selected in a way to avoid regression on other platforms
that uses davinci spi driver and has only one spi bus.

Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-04-17 17:24:39 -04:00
Vitaly Andrianov
ef509b9063 k2hk: add support for k2hk SOC and EVM
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.

This patch add support for keystone architecture and k2hk evm.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
2014-04-17 17:24:38 -04:00
Vitaly Andrianov
e8459dcc33 i2c, davinci: convert driver to new mutlibus/mutliadapter framework
- add davinci driver to new multibus/multiadpater support
    - adapted all config files, which uses this driver

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-04-17 17:24:38 -04:00
Karicheri, Muralidharan
356d15ebb2 i2c, davinci: move i2c_defs.h to the drivers/i2c directory
This patch moves the davinci i2c_defs.h file to drivers.i2c directory.
It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs.

Not used "git mv" command to move the file because small part of
it with definitions specific for Davinci SOCs has to remain in the
arch/arm/include/asm/arch-davinci.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:38 -04:00
Karicheri, Muralidharan
999d7d326d NAND: DaVinci: allow forced disable of subpage writes
This patch introduces a configurable mechanism to disable
subpage writes in the DaVinci NAND driver.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:38 -04:00
Tom Rini
fa1a73fa87 SPL:SPI: Add Falcon Mode support
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:37 -04:00
Poddar, Sourav
b545a98f5d spi: ti_qspi: Add delay for successful bulk erase.
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
2014-04-17 17:20:18 -04:00
Tom Rini
db60580649 mtd: Build nand_util.o for CONFIG_ENV_IS_IN_NAND in SPL
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 14:39:54 -04:00
Tom Rini
6dd3b56689 mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL
This mainly converts the am335x_spl_bch driver to the "normal" format
which means a slight change to nand_info within the driver.

Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 14:39:54 -04:00
Masahiro Yamada
dd649f1d00 mtd: delete unused files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-04-17 14:38:30 -04:00
Stefan Agner
8f9fd6caaf usb: tegra: combine header file
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stefan Agner
b1d615f3f1 usb: tegra: fix PHY configuration
On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.

Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stefan Agner
b03f4b3742 usb: tegra: fix USB2 powerdown for Tegra30 and later
Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stephen Warren
70ad375ee4 ARM: tegra: Tegra20 pinmux cleanup
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Tetsuyuki Kobayashi
7a65768903 i2c: sh_i2c: bugfix: i2c probe command does not work
This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework

Before commit 2035d77d, i2c probe command works properly on kzm9g board.

KZM-A9-GT# i2c probe
Valid chip addresses: 0C 12 1D 32 39 3D 40 60

After commit 2035d77d, i2c probe command does not work.

KZM-A9-GT# i2c probe
Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F

sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-14 17:41:48 +09:00
Albert ARIBAUD
519fdde9e6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	include/configs/trats.h
	include/configs/trats2.h
	include/mmc.h
2014-04-08 09:25:08 +02:00
Stefano Babic
1cad23c5f4 Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:35:30 +02:00
Roger Quadros
3f62971162 ahci: Fix data abort on multiple scsi resets.
Commit 2faf5fb82e introduced a regression that causes a data
abort when running scsi init followed by scsi reset.

There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.

Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.

Fixes: 2faf5fb82e (ahci: Fix cache align error messages)

Reported-by: Eli Nidam <elini@marvell.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
2014-04-02 15:44:40 -04:00
Haijun.Zhang
1336e2d343 mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
	Pantelis Antoniou <panto@antoniou-consulting.com>

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:25:01 +03:00
Andrew Gabbasov
8a573022c3 mmc: fsl_esdhc: add controller reset in case of data related errors too
The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:17:12 +03:00
Andrew Gabbasov
fb823981c5 mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:16:56 +03:00
Tom Rini
33ace362fd mmc: Add 'mmc rst-function' sub-command
Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value
in order for warm reset of the system to work.  Details on this being
required will be part of the eMMC datasheet.  Also add using this
command to the dra7xx README.

* Whitespace fix by panto

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:02:58 +03:00
Nobuhiro Iwamatsu
74c32ef58d mmc: sh_mmcif: Fix warning by unused variable
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 12:55:48 +03:00
Nobuhiro Iwamatsu
cd2bf4846c mmc: sh_mmcif: Fix compile error
BY commit "mmc: Split mmc struct, rework mmc initialization (v2)",
sh_mmcif has compile error. This fixes compile error.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Pantelis Antoniou <panto@antoniou-consulting.com>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 12:55:31 +03:00
Marek Vasut
a778aeae05 pci: mx6: Implement power callback
Implement a callback to toggle the slot power supply. The callback
can be overriden in case some more complex power supply for the slot
was implemented in hardware, yet for the usual case, one can define
a GPIO which toggles the power to the slot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
2014-03-31 18:28:50 +02:00
Marek Vasut
2bbcccf552 ARM: mxs: Add OCOTP driver
Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-03-31 18:28:50 +02:00
Masahiro Yamada
462d1883f7 drivers: i2c: delete an unused source file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
2014-03-31 07:30:55 +02:00
Tom Rini
0b2da7e209 blackfin: mmc: Correct mmc_host_is_spi and bfin_sdh.c
In the recent mmc cleanup, the mmc_host_is_spi macro was broken and
bfin_sdh.c had mmc->bus_width turned into mmc_bus_width(mmc), both of
which were incorrect.

Signed-off-by: Tom Rini <trini@ti.com>
2014-03-28 16:55:29 -04:00
Przemyslaw Marczak
0bd937248a drivers: crypto: ace_sha: add implementation of hardware based lib rand
This patch adds implementation of rand library based on hardware random
number generator of security subsystem in Exynos SOC.

This library includes:
- srand()  - used for seed hardware block
- rand()   - returns random number
- rand_r() - the same as above with given seed

which depends on CONFIG_EXYNOS_ACE_SHA and CONFIG_LIB_HW_RAND.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
cc: Akshay Saraswat <akshay.s@samsung.com>
cc: ARUN MANKUZHI <arun.m@samsung.com>
cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-28 15:06:31 -04:00
Alexey Brodkin
a7b26dbb49 net/designware: align DMA buffer descriptors to D$ line
It's important to have ability to flush/invalidate each DMA buffer descriptor
individually to prevent incoherency of adjacent BDs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
2014-03-28 15:06:30 -04:00
Tom Rini
82b9547387 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-03-28 08:24:01 -04:00
Albert ARIBAUD
ab6423cae0 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.

Conflicts:
	board/samsung/common/board.c
2014-03-25 10:53:15 +01:00
Łukasz Majewski
eea4e6fe82 dfu: mmc: Replace calls to u-boot commands with native mmc API
For some time we have been using the run_command() with properly crafted
string. Such approach turned to be unreliable and error prone.

Switch to "native" mmc subsystem API would allow better type checking and
shall improve speed.

Also, it seems that this API is changing less often than u-boot commands.
The approach similar to env operations on the eMMC has been reused.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-03-24 12:59:54 +02:00
Pantelis Antoniou
93bfd61677 mmc: Split mmc struct, rework mmc initialization (v2)
The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.

On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.

Typically the initialization got something like this in every driver.

	struct mmc *mmc = malloc(sizeof(struct mmc));
	memset(mmc, 0, sizeof(struct mmc);
	/* fill in fields of mmc struct */
	/* store private data pointer */
	mmc_register(mmc);

By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:

	struct mmc = mmc_create(&cfg, priv);

All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.

Changes since v1:

* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 12:58:56 +02:00
Pantelis Antoniou
22cb7d334e mmc: Convert mmc struct's name array to a pointer
Using an array is pointless; even more pointless (and scary) is using
sprintf to fill it without a format string.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 11:32:10 +02:00
Pantelis Antoniou
ab769f227f mmc: Remove ops from struct mmc and put in mmc_ops
Remove the in-structure ops and put them in mmc_ops with
a constant pointer to it.

This makes the mmc structure smaller as well as conserving
code space (in theory).

All in-tree drivers are converted as well; this is done in a
single patch in order to not break git bisect.

Changes since V1:
Fix compilation b0rked issue on omap platforms where OMAP_GPIO was
not set.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 11:32:10 +02:00
Łukasz Majewski
7d0b605abb dfu: mmc: Replace calls to u-boot commands with native mmc API
For some time we have been using the run_command() with properly crafted
string. Such approach turned to be unreliable and error prone.

Switch to "native" mmc subsystem API would allow better type checking and
shall improve speed.

Also, it seems that this API is changing less often than u-boot commands.
The approach similar to env operations on the eMMC has been reused.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-03-23 02:20:10 +01:00
Heiko Schocher
001a831986 usb: dfu: introduce dfuMANIFEST state
on nand flash using ubi, after the download of the new image into
the flash, the "rest" of the nand sectors get erased while flushing
the medium. With current u-boot version dfu-util may show:

Starting download: [##################################################] finished!
state(7) = dfuMANIFEST, status(0) = No error condition is present
unable to read DFU status

as get_status is not answered while erasing sectors, if erasing
needs some time.

So do the following changes to prevent this:

- introduce dfuManifest state
  According to dfu specification
  ( http://www.usb.org/developers/devclass_docs/usbdfu10.pdf ) section 7:
  "the device enters the dfuMANIFEST-SYNC state and awaits the solicitation
   of the status report by the host. Upon receipt of the anticipated
   DFU_GETSTATUS, the device enters the dfuMANIFEST state, where it
   completes its reprogramming operations."

- when stepping into dfuManifest state, sending a PollTimeout
  DFU_MANIFEST_POLL_TIMEOUT in ms, to the host, so the host
  (dfu-util) waits the PollTimeout before sending a get_status again.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-23 02:20:09 +01:00
Heiko Schocher
a2199afea1 usb, dfu: extract flush code into seperate function
move the flushing code into an extra function dfu_flush(),
so it can be used from other code.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-23 02:20:09 +01:00
Simon Glass
6e16d90aca sandbox: Add implementation of spi_setup_slave_fdt()
This function is needed when CONFIG_OF_SPI is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:50 -06:00
Simon Glass
ffb87905cb sandbox: Allow Ctrl-C to work in sandbox
It is useful for Cltl-C to be handled by U-Boot as it is on other boards.
But it is also useful to be able to terminate U-Boot with Ctrl-C.

Add an option to enable signals while in raw mode, and make this the
default. Add an option to leave the terminal cooked, which is useful for
redirecting output.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:49 -06:00
Simon Glass
a77bf70978 sound: Move Samsung-specific code into its own file
The i2s code is in fact Samsung-specific, but there might be other
implementation. Move this code into its own file. This makes it slightly
more obviously how to adjust the code to support another SoC, when someone
takes this task on.

Also drop non-FDT support, since it isn't used on Exynos 5.

Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:49 -06:00
Simon Glass
7d95f2a329 sandbox: Add LCD driver
Add a simple LCD driver which uses SDL to display the image. We update the
image regularly, while still providing for reasonable performance.

Adjust the common lcd code to support sandbox.

For command-line runs we do not want the LCD to be displayed, so add a
--show_lcd option to enable it.

Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:49 -06:00
Simon Glass
c34c0246a3 sandbox: Add a simple sound driver
Add a sound driver for sandbox, which uses SDL.

Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:48 -06:00
Simon Glass
b2a668b523 cros_ec: Implement I2C pass-through
The Chrome EC has a feature where you can access its I2C buses through a
pass-through arrangement. Add a command to support this, and export the
function for it also.

Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:48 -06:00
Simon Glass
df93d90aea cros_ec: sandbox: Add Chrome OS EC emulation
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
2ab83f0d75 cros_ec: Correct comparison between signed and unsigned numbers
Due to signed/unsigned comparison, '< sizeof(struct)' does not do the right
thing, since if ec_command() returns a -ve number we will consider this be
success.

Adjust all comparisons to avoid this problem.

This error was found with sandbox, which gives a segfault in this case. On
ARM we may instead silently fail.

We should also consider turning on -Wsign-compare to catch this sort of thing
in future.

Reviewed-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
2014-03-17 20:05:47 -06:00
Randall Spangler
a607028331 cros_ec: spi: Add support for EC protocol version 3
Protocol version 3 will be attempted first; if the EC doesn't support
it, u-boot will fall back to the old protocol version (2).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
2d8ede58ca cros_ec: Add base support for protocol v3
Protocol v2 was shipped with snow, link and spring. Protocol v3 is for
pit and is targetted at SPI operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Randall Spangler
e8c1266236 cros_ec: Clean up multiple EC protocol support
Version 1 protocols (without command version) were already no longer
supported in cros_ec.c.  This removes some dead code from the
cros_ec_i2c driver.

Version 2 protcols (with command version) are now called
protocol_version=2, instead of cmd_version_is_supported=1.

A subsequent change will introduce protocol version 3 for SPI.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
836bb6e827 cros_ec: Sync up with latest Chrome OS EC version
The EC messages have been expanded and some parts have been renamed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
1c266b9214 cros_ec: Move #ifdef to permit flash region access
Flash region access is not tied to having commands, so adjust the #ifdef
to reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Simon Glass
e0dd81e3aa cros_ec: Support systems with no EC interrupt
Some systems do not have an EC interrupt. Rather than assuming that the
interrupt is always present, and hanging forever waiting for more input,
handle the missing interrupt. This works by reading key scans only until
we get an identical one. This means the EC keyscan FIFO is empty.

Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Vadim Bendebury
4ff9b461a8 cros_ec: Drop old EC version support from EC driver
There is no need to support old style EC moving forward. Ultimately we
should get rid of the check_version() API. For now just return error
in case the EC does not seem to support the new API.

Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Tested-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Simon Glass
d7f25f35f4 cros_ec: Add a function for decoding the Chrome OS EC flashmap
In order to talk to the EC properly we need to be able to understand the
layout of its internal flash memory. This permits emulation of the EC
for sandbox, and also software update in a system with a real EC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Marek Vasut
bf64035a15 mtd: spi: Fix page size for S25FL032P,S25FL064P
The commit 6af8dc3ebc broke support for
S25FL032P and S25FL064P by carelessly removing the code handling special
page size for these two SPI NOR flashes and unifying the code under the
assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size.

Add special case handling for these two SPI NOR flashes.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:57 +05:30
Axel Lin
7dfc4dbd2d spi: atmel_dataflash: Simplify AT91F_SpiEnable implementation
Refactor the code a bit to make it better in readability.
Remove the comments because now the intention of the code is pretty clear.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:57 +05:30
Jagannadha Sutradharudu Teki
c6136aad91 sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-03-17 21:54:57 +05:30
Marek Vasut
cc56f13392 sf: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Marek Vasut
cfa90a636b sf: Add S25FL128S_256K IDs
Add IDs for this new chip.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Marek Vasut
c1f9325965 sf: Fix entries for S25FL256S_256K and S25FL512S_256K
Both of these chips have 256kB big sectors, thus the _256K suffix,
compared to their _64K counterparts, which have 64kB sectors. Also,
they have four times less sectors than their _64K counterparts.

Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:56 +05:30
Albert ARIBAUD
63f347ec4c Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-03-13 18:32:26 +01:00
Albert ARIBAUD
08798026f2 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-03-13 17:43:35 +01:00
Przemyslaw Marczak
b627eb461b usb: dfu: add static alt num count in dfu_config_entities()
Thanks to this multiple call of function dfu_config_entities()
gives continuous dfu alt numbering until call dfu_free_entities().

This allows to store dfu entities in multiple variables.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Łukasz Majewski <l.majewski@samsung.com>
Tested-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-13 10:30:56 +09:00
Gerhard Sittig
df4fb1c36d usb: net: introduce support for Moschip USB ethernet
introduce an 'mcs7830' driver for Moschip MCS7830 based (7730/7830/7832)
USB 2.0 Ethernet Devices

see "MCS7830 -- USB 2.0 to 10/100M Fast Ethernet Controller" at
http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=109;74;109

the driver was implemented based on the U-Boot Asix driver with
additional information gathered from the Moschip Linux driver,
development was done on "Delock 61147" and "Logilink UA0025C" dongles

Signed-off-by: Gerhard Sittig <gsi@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2014-03-12 17:04:31 -04:00
Ilya Ledvich
ef59bb7cc8 drivers: net: cpsw: init phy with gigabit features
CPSW ia a gigabit device. Use the PHY_GBIT_FEATURES macro to determine phy
supported features.
Tested on cm_t335.

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
2014-03-12 16:22:12 -04:00
Vasili Galka
ce6889a997 drivers/spi/omap3: Bug fix of premature write transfer completion
The logic determining SPI "write" transfer completion was faulty. At
certain conditions (e.g. slow SPI clock freq) the transfers were
interrupted before completion. Both EOT and TXS flags of channel
status registeer shall be checked to ensure that all data was
transferred. Tested on AM3359 chip.

Signed-off-by: Vasili Galka <vasili@visionmap.com>
2014-03-12 16:22:12 -04:00
Piotr Wilczek
3577fe8be9 drivers:mmc:sdhci: enable support for DT
This patch enables support for device tree for sdhci driver.
Non DT case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
1591ee7352 video:exynos_fb:fdt: add additional fdt data
This patch adds the new exynos_lcd_misc_init() function for optional
lcd specific initialisation.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
de461c526e video:mipidsim:fdt: Add DT support for mipi dsim driver
This patch enables parsing mipi data from device tree.
Non device tree case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Tom Rini
5495dae7aa Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-03-10 14:22:54 -04:00
Tom Rini
c0d297946f Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-03-10 14:06:51 -04:00
Stephen Warren
eb838e7d84 usb: create common header virtual root hub descriptors
Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.

Note that there were some very minor differences between the descriptors
in the various files, such as:

- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String content

I assume these aren't relevant.

Cc: Thomas Lange <thomas@corelatus.se>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Eric Millbrandt <emillbrandt@coldhaus.com>
Cc: Pierre Aubert <p.aubert@staubli.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Rodolfo Giometti <giometti@linux.it>
Cc: Zhang Wei <wei.zhang@freescale.com>
Cc: Mateusz Zalega <m.zalega@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Markus Klotzbuecher <mk@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: C Nauman <cnauman@diagraph.com>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Thomas Abraham <t-abraham@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Andrew Murray <amurray@embedded-bits.co.uk>
Cc: Matej Frančeškin <matej.franceskin@comtrade.com>
Cc: Cliff Cai <cliff.cai@analog.com>
Cc: Bryan Wu <cooloney@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-03-10 18:53:36 +01:00
Stephen Warren
8165e34bf4 usb: ehci: fully align interrupt QHs/QTDs
These data structures are passed to cache-flushing routines, and hence
must be conform to both the USB the cache-flusing alignment requirements.
That means aligning to USB_DMA_MINALIGN. This is important on systems
where cache lines are >32 bytes.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-10 18:53:36 +01:00
Stephen Warren
2456b97f0c ush: ehci: initialize altnext pointers in QH
Section 4.10.2 "Advance Queue" of ehci-specification-for-usb.pdf
specifies how an EHCI controller loads a new QTD for processing if the
QH is not already marked as active. It states:

=====
If the field Bytes to Transfer is not zero and the T-bit in the Alternate
Next qTD Pointer is set to zero, then the host controller uses the
Alternate Next qTD Pointer. Otherwise, the host controller uses the Next
qTD Pointer. If Next qTD Pointer’s T-bit is set to a one, then the host
controller exits this state and uses the horizontal pointer to the next
schedule data structure.
=====

Hence, we must ensure that the alternate next QTD pointer's T-bit
(TERMINATE) is set, so the EHCI controller knows to use the next QTD
pointer.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-10 18:53:36 +01:00
Eric Nelson
5ca05c8b03 cfb_console: align fields in gzipped .bmp files
.bmp files contain 32-bit integers aligned at offsets of +2, +6,
et cetera within the bmp_header structure (see include/bmp_layout.h).

Support for gzip-compressed .bmp files is present in the cfb_console
display subsystem by uncompressing them prior to use.

This patch forces the in-memory header to be aligned properly
for these compressed images by extracting them to a 2-byte
offset in the memory returned by malloc. Since malloc will always
return a 4-byte aligned value, this forces the .bmp header
fields to be naturally aligned on 4-byte addresses.

Refer to these files for more details:
	doc/README.displaying-bmps

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-03-10 13:50:31 -04:00
Ian Campbell
73545f75b6 ahci: wait longer for link.
I have observed timeouts on a cubietruck.

The increase to 40ms is completely arbitrary and Works For Me(tm). I
couldn't find a good reference for how long you are supposed to wait,
although googling around it seems like tens of ms rather than single
digits is more common. I don't think there is any harm in waiting a bit
longer.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2014-03-10 13:50:31 -04:00
Ian Campbell
c6f3d50b9b ahci-plat: Provide a weak scsi_init hook
This allow the platform to register the platform ahci device.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2014-03-10 13:50:31 -04:00
Bo Shen
0b0b4f5981 mtd: nand: atmel: prepare for nand spl boot support
Prepare for nand spl boot support. It supports nand software ECC and
hardware PMECC.
This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 19:19:06 +01:00
Stefan Roese
345b77baca ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.

This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2014-03-07 10:59:06 -05:00
Haijun.Zhang
dc116bd6c4 net/phy: Correct AR8021 phy_mask
There was wrong phy_mask for AR8021 device,
so the AR8021 can't be probed correctly.
Changed it from 0x4fffff to 0x4ffff0.

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
2014-03-07 10:59:06 -05:00
Stephen Warren
9a04a858eb net: asix: don't pad odd-length TX packets
For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that
they have an even size. Currently, asix_recv() does remove this padding,
and asic_send() adds equivalent padding in the TX path. However, the HW
does not appear to need this packing for TX packets in practical testing
with "ASIX Elec. Corp. AX88x72A 000001" Vendor: 0x0b95 Product 0x7720
Version 0.1. The Linux kernel does no such padding for the TX path.

Remove the padding from the TX path:

* For consistency with the Linux kernel.
* NVIDIA has a Tegra simulator which validates that the length of USB
  packets sent to an ASIX device matches the packet length value inside
  the packet data. Having U-Boot and the kernel do the same thing when
  creating the TX packets simplifies the simulator's validation.

Cc: Lucas Stach <dev@lynxeye.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-03-07 10:59:06 -05:00
Stefano Babic
1ad6364eeb Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-03-05 12:51:26 +01:00
Tim Harvey
91baa6f7ff power: add PFUZE100 PMIC driver
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-03-05 12:02:31 +01:00
Tom Rini
e4b87e5b1d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2014-03-04 21:23:42 -05:00
pekon gupta
2eda892f00 mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nand
omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
pekon gupta
6aff050988 mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nand
omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
pekon gupta
51d192c40d mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers into common omap_gpmc.h
Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related
defines and declarations scattered in SoC platform specific header files
like include/asm/arch-xx/cpu.h
However, GPMC hardware remains same across all platforms thus this patch merges
GPMC data scattered across different arch-xx specific header files into single
header file include/asm/arch/omap_gpmc.h

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-04 17:23:54 -06:00
Simon Glass
e2d8a714a7 sandbox: Convert GPIOs to use driver model
Convert sandbox over to use driver model GPIOs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-04 12:15:30 -05:00
Simon Glass
96495d90fe dm: Add GPIO support and tests
Add driver model support for GPIOs. Since existing GPIO drivers do not use
driver model, this feature must be enabled by CONFIG_DM_GPIO. After all
GPO drivers are converted over we can perhaps remove this config.

Tests are provided for the sandbox implementation, and are a sufficient
sanity check for basic operation.

The GPIO uclass understands the concept of named banks of GPIOs, with each
GPIO device providing a single bank. Within each bank the GPIOs are numbered
using an offset from 0 to n-1. For example a bank named 'b' with 20
offsets will provide GPIOs named b0 to b19.

Anonymous GPIO banks are also supported, and are just numbered without any
prefix.

Each time a GPIO driver is added to the uclass, the GPIOs are renumbered
accordinging, so there is always a global GPIO numbering order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com>
Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
2014-03-04 12:15:30 -05:00
Simon Glass
39f7611fec dm: Add a demonstration/example driver
As an example of how to write a uclass and a driver, provide a demo version
of each, accessible through the 'demo' command.

To use these with driver model, define CONFIG_CMD_DEMO and CONFIG_DM_DEMO.

The two demo drivers are enabled with CONFIG_DM_DEMO_SIMPLE and
CONFIG_DM_DEMO_SHAPE.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com>
Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
2014-03-04 12:15:29 -05:00
Simon Glass
6494d708bf dm: Add base driver model support
Add driver model functionality for generic board.

This includes data structures and base code for registering devices and
uclasses (groups of devices with the same purpose, e.g. all I2C ports will
be in the same uclass).

The feature is enabled with CONFIG_DM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com>
Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
2014-03-04 12:15:29 -05:00
Alexey Brodkin
1ace402239 sizes.h - consolidate for all architectures
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 12:15:01 -05:00
Mugunthan V N
9c653aad16 drivers: net: cpsw: add support to have phy address from cpsw platform data
Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335
pengwyn boards]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 09:41:53 -05:00
Michal Simek
c9416b9292 serial: zynq: Add OF initialization support
Add console selection from DTB which is enough to have
OF driven solution.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-04 09:27:36 -05:00
Michal Simek
345d3c0f01 mmc: zynq: Add OF initialization support
Enable initialize sdhci from DTB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-04 09:27:35 -05:00
Michal Simek
f88a6869a1 net: gem: Add OF initialization support
Gem can be directly initialized from DTB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-04 09:27:35 -05:00
Michal Simek
0c9c99a20b net: emaclite: Fix OF initialization
- Add xilinx_emaclite_of_init to netdev.h
- Remove global data pointer from the driver
- Add better handling for error state.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-04 09:27:32 -05:00
pekon gupta
6e562b1106 mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes
chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
	for ECC_BCH8 scheme using GPMC and ELM

This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
  known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
  omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
pekon gupta
71a7f95600 mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.

All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.

This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
  omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
				==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
pekon gupta
f5f1f614bd mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes
chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)

Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()

(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-03 20:09:03 -06:00
Tom Rini
eeb72e6761 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	arch/arm/cpu/armv7/config.mk
	board/ti/am43xx/mux.c
	include/configs/am43xx_evm.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-26 16:49:58 -05:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Nikhil Badola
91d7746df8 fsl/usb: Limit phy_type comparison to first four characters
Use first four characters for phy_type comparison. Strcmp() should not
be used to check the phy_type string which maybe parsed by hwconfig_subarg().
Hwconfig_subarg() returns part of hwconfig string starting from
phy_type value till the end of the string. Since phy_type could be
either "utmi" or "ulpi", strncmp() should be used so that a comparison
of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:57 -08:00
Zhao Qiang
e0d809647f ar8031/8033/phy:enable autonegotiation for ar8031/8033
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before
while "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033
to enable autonegotiation.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:41 -08:00
Łukasz Majewski
eae745379d power: fix: Do not execute pmic command when not all necessary parameters are passed
Lack of this check resulted in a data abort when CPU tried to execute the
following command (without further mandatory input): 'pmic MAX77686_PMIC'.

Only the 'pmic list' command requires one passed parameter.
Other require at least two valid parameters for correct operation.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-02-24 10:56:33 -05:00
Darwin Rambo
7a9d0ad009 mmc: kona: Add Kona mmc driver
Add support for the Kona SDHCI found on Broadcom mobile SoCs.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-22 19:30:41 +01:00
Darwin Rambo
4bded3a367 i2c: kona: Add Kona I2C driver
Add support for the Kona I2C controller found on Broadcom mobile SoCs.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-22 19:30:39 +01:00
Darwin Rambo
24e5219754 gpio: kona: Add Kona gpio driver
Add support for the Kona GPIO controller found on Broadcom mobile SoCs.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-22 19:30:27 +01:00
Bhupesh Sharma
ee456337c6 SMC91111: Fix compilation warnings
This patch fixes the following warning messages coming out of
'drivers/net/smc91111.h' when compiled for 'vexpress_aemv8a':

warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Currently this issue seems to surface when SMSC is compiled for 64-bit
ARMv8 platforms, so the change is protected under CONFIG_ARM64, so that
it doesn't break other existing platforms.

In addition this patch tries to fix some checkpatch errors and warnings
(others related to camel-casing and volatile usage will be addressed
by a later patch).

This fix has been tested on both ARMv8 foundation model v1 and v2.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-02-21 11:33:18 -05:00
York Sun
6b1e1254f3 driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
6b9e309a8a Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
4e5b1bd0df driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
Axel Lin
1cb8393a13 serial: arc: Convert to use default_serial_puts
Use default_serial_puts() instead of duplicating the implementation.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2014-02-21 09:50:12 -05:00
Tom Rini
4c89a369c7 Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-02-21 08:00:22 -05:00
Alexey Brodkin
94b5400e76 serial/serial_arc: switch from {read|write}l to {read|write}b accessors
This is required for proper functionality on big-endian targets.
Memory-mapped registres of ARC UART are not 32-bit words but 8-bit bytes
so on little-endian target either acessor (_l or _b) works fine.
On big-endian only _b accessors works as expected.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Noam Camus <noamc@ezchip.com>
Cc: Tom Rini <trini@ti.com>
2014-02-21 07:54:05 -05:00
Alexey Brodkin
1d568c7666 serial/serial_arc: add work-around of ISS bug
Explanation is in in-lined comment.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Noam Camus <noamc@ezchip.com>
Cc: Tom Rini <trini@ti.com>
2014-02-21 07:54:05 -05:00
Tom Rini
6853e6aa77 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-02-20 12:18:59 -05:00
Tom Rini
130fbeb1c5 blackfin: Add <asm/clock.h> to numerous drivers
With d6a320d we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include <asm/clock.h> in more drivers to
avoid warnings.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-02-20 12:00:27 -05:00
Lukasz Majewski
17eb1d8f57 dfu: mmc: fs: Fix format accepted by ext4write command
The commit:

"EXT4: Fix number base handling of "ext4write" command"
 SHA1: f7740f7712

Cleaned up the ext4write command format.

This commit shall be regarded as a follow up, since the DFU subsystem is
using those commands for its normal operation.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-02-20 12:00:27 -05:00
Albert ARIBAUD
3e11350255 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	Makefile
	drivers/net/npe/Makefile

These two conflicts arise from commit 0b2d3f20
("ARM: NET: Remove the IXP NPE ethernet driver") and are
resolved by deleting the drivers/net/npe/Makefile file
and removing the CONFIG_IXP4XX_NPE line from Makefile.
2014-02-20 13:16:05 +01:00
Alexey Brodkin
3d93f6959b designware_i2c: remove inclusion of <asm/arch/hardware.h>
As soon as all boards have their CONFIG_SYS_I2C_BASE defined in
configuration files instead of "asm/arch/hardware.h" it's safe to remove
the inclusion in question and make driver platform-independent.

Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Armando Visconti <armando.visconti@st.com>

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-20 06:49:09 +01:00
Hannes Petermaier
d5243359e1 OMAP24xx I2C: Add support for set-speed
Adds support for set-speed on the OMAP24xx I2C Adapter.

Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status.
Otherwise on a subsequent call the transfer of last byte from the
predecessor is aborted and therefore lost. For exmaple when
i2c_write(...) is followed by a i2c_setspeed(...) (which has to
deactivate and activate master for changing psc,...).

Minor cosmetical changes.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Heiko Schocher <hs@denx.de>
2014-02-20 06:48:23 +01:00
Marek Vasut
d22643e7e8 i2c: i2c-mxs: Wait for I2C to empty queue
Make sure the I2C write queue is empty before leaving the mxs_i2c_write().
If we start and I2C write and only wait for ACK, the MXS I2C IP block may
enter next operation while still processing the write aftermath internally.
This will in turn disrupt one or more subsequent transfer(s).

A testcase for this issue is as such. This testcase is also interesting because
the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command.
The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and
then uses I2C_READ to read data from the chip. After this command completes, the
'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The
problem is that the first I2C_WRITE disrupted the I2C IP block operation and
this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c
probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00,
even if this ACK was owned by the previous I2C_WRITE operation. Note that the
'i2c read' command must read from a valid I2C chip address.

Wrong:
> i2c probe
Valid chip addresses: 50 51
> i2c read 0x50 0x0.2 0x10 0x42000000
> i2c probe
Valid chip addresses: 00 50 51

With this patch
> i2c probe
Valid chip addresses: 50 51
> i2c read 0x50 0x0.2 0x10 0x42000000
> i2c probe
Valid chip addresses: 50 51

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
2014-02-20 06:46:57 +01:00
Chin Liang See
070cbaf821 designware_i2c: Enhance DesignWare I2C driver address support
Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.

Signed-off-by: Chin Liang See <clsee@altera.com>
Acked-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
cc: Armando Visconti <armando.visconti@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
2014-02-20 06:46:56 +01:00
Heiko Schocher
9e50c406c8 i2c, bootcount: add support for bootcounter on i2c devices
add support for bootcounter on an i2c device. And add a
README for all bootcounter options.

Signed-off-by: Heiko Schocher <hs@denx.de>
2014-02-20 06:46:56 +01:00
Scott Jiang
16c550274c blackfin: make i2c driver blackfin independant
The ADI twi peripheral is not binding to Blackfin processor only.
Access i2c registers by standard io functions.
Fix coding style.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20 06:46:56 +01:00
Sonic Zhang
86bdd70a09 blackfin: rename bfin-twi_i2c driver to adi_i2c
The ADI twi peripheral is not binding to Blackfin processor only.
Change to a generic name.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20 06:46:56 +01:00
Sonic Zhang
d6a320d5bb blackfin: add spi and i2c specific get clock functions
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20 06:46:56 +01:00
Sonic Zhang
bb0fad0ea0 blackfin: the sclk MHz in i2c driver should be divided by 1000 other than 1024
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20 06:46:55 +01:00
Michael Burr
18948632a9 i2c: zynq: Add support for the second i2c controller
Initialize the second i2c controller.

Signed-off-by: Michael Burr <michael.burr@logicpd.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-20 06:46:55 +01:00
Michael Burr
9e90107155 i2c: zynq: Support for 0-length register address
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read'
Further minor corrections:
- Write 'address' register before 'data' register.
- Write 'transfer_size' register before 'address' register.

Signed-off-by: Michael Burr <michael.burr@logicpd.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-20 06:46:55 +01:00
Masahiro Yamada
6825a95b0b kbuild: use Linux Kernel build scripts
Now we are ready to switch over to real Kbuild.

This commit disables temporary scripts:
  scripts/{Makefile.build.tmp, Makefile.host.tmp}
and enables real Kbuild scripts:
  scripts/{Makefile.build,Makefile.host,Makefile.lib}.

This switch is triggered by the line in scripts/Kbuild.include
  -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj
  +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj

We need to adjust some build scripts for U-Boot.
But smaller amount of modification is preferable.

Additionally, we need to fix compiler flags which are
locally added or removed.

In Kbuild, it is not allowed to change CFLAGS locally.
Instead, ccflags-y, asflags-y, cppflags-y,
CFLAGS_$(basetarget).o, CFLAGS_REMOVE_$(basetarget).o
are prepared for that purpose.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-02-19 11:07:50 -05:00
Masahiro Yamada
9e4140329e kbuild: change out-of-tree build
This commit changes the working directory
where the build process occurs.

Before this commit, build process occurred under the source
tree for both in-tree and out-of-tree build.

That's why we needed to add $(obj) prefix to all generated
files in makefiles like follows:
  $(obj)u-boot.bin:  $(obj)u-boot

Here, $(obj) is empty for in-tree build, whereas it points
to the output directory for out-of-tree build.

And our old build system changes the current working directory
with "make -C <sub-dir>" syntax when descending into the
sub-directories.

On the other hand, Kbuild uses a different idea
to handle out-of-tree build and directory descending.

The build process of Kbuild always occurs under the output tree.
When "O=dir/to/store/output/files" is given, the build system
changes the current working directory to that directory and
restarts the make.

Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>"
syntax for descending into sub-directories.
(We can write it like "make $(obj)=<sub-dir>" with a shorthand.)
This means the current working directory is always the top
of the output directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-02-19 11:07:50 -05:00
Heiko Schocher
9137d19bdd net, phy: atheros ar803x bug
commit 626ee1e3 "phylib: update atheros ar803x phy"

leads in failing ethernet on the pxm2 board.

Calling genphy_config() instead of ar8021_config(),
which seems for ar8021 phys not ar803x phys, make
it working again.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-02-19 10:47:33 -05:00
Albert ARIBAUD
e7538fee99 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-02-19 12:04:45 +01:00
Soren Brinkmann
19605e2e03 serial_zynq: Migrate to Zynq clock framework
Remove hard coded frequencies and use Zynq's clock framework to obtain
the UART clock frequency.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:22 +01:00
Soren Brinkmann
97598fcf10 net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Soren Brinkmann
1cd46ed2d3 net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Michal Simek
bf83495040 zynq: serial: Simplify serial driver initialization
Define both serial uarts in the driver and return
default uart based on board configuration.

- Move baseaddresses to hardware.h
- Define default baudrate and clock values

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Albert ARIBAUD
a87a0ce702 Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2014-02-19 07:15:01 +01:00
Sourav Poddar
bb7cd0ddf9 spi: ti_qspi: Add delay before xfer for am43xx
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.

Without this patch, device does not get probed also.
Here is the log.

U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0

While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
U-Boot# sf erase 0 0x80000
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 81000000 0xdededede 0x40000
U-Boot# sf write 81000000 0 0x40000
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 82000000 0 0x40000
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x82000000

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:41:09 +05:30
Sourav Poddar
570533b820 spi: ti_qspi: Add AM43xx specifics changes
Add AM43xx specific changes.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:41:09 +05:30
Markus Niebel
5d584ccec1 spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3
SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:29:26 +05:30
Michal Simek
999c39a45f spi: xilinx: Move timeout calculation out of the loop
Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:24:28 +05:30
Tom Rini
c4d376fd1c Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-02-17 14:22:02 -05:00
Tom Rini
b1ad03c242 Merge branch 'master' of git://git.denx.de/u-boot-nios 2014-02-17 14:21:03 -05:00
Tom Rini
18c83588bc Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-02-17 14:16:08 -05:00
Albert ARIBAUD
d53ccdb341 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-02-13 13:30:54 +01:00
Stefano Babic
17998eff90 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-02-11 12:55:32 +01:00
Markus Niebel
6ba45cc0f8 NET: fec_mxc: fix MDIO clock prescaler calculation
The prescaler value for MDC is calculated wrong for
MX6S. Implement the same logic as linux here which handles
ENET_MAC different then original FEC.

Tested on a custom board with i.MX6S and 100MBit PHY

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
2014-02-11 11:33:45 +01:00
Marek Vasut
bb01956344 pci: mx6: Implement reset callback
Add a callback so that a board can implement it's own specific routine to
toggle the port's #PERST line or #define a GPIO to do so.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-02-11 11:24:12 +01:00
Axel Lin
2d61e1bed2 serial: opencores_yanu: Avoid duplicate oc_serial_setbrg() implementation
The implementation of oc_serial_setbrg() for CONFIG_SYS_NIOS_FIXEDBAUD and
!CONFIG_SYS_NIOS_FIXEDBAUD are very similar.
Add a baudrate variable and set it to either CONFIG_BAUDRATE or gd->baudrate.
Then we can unify the code for both cases.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-02-11 15:49:19 +08:00
Axel Lin
18a6bcc139 serial: opencores_yanu: Fix build error
Fix build error due to missing include of serial.h and a trivial typo.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-02-11 15:49:19 +08:00
Alexey Brodkin
22a240c32c serial/serial_arc - add driver for ARC UART
Driver for non-standard on-chip UART, instantiated in the ARC (Synopsys)
FPGA Boards such as ARCAngel4/ML50x

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-02-07 12:55:07 -05:00
Tom Rini
614b2bf1c9 cmd_mmc.c: Drop open/close mmc sub-commands
The open and close mmc sub-commands implement a hard-coded set of values
specific to the SMDK5250 platform.  Remove these commands as what they
did can be done instead with a series of mmc dev / bootpart / bootbus
commands instead now.

Cc: Amar <amarendra.xt@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 18:17:49 +02:00
Tom Rini
5a99b9de1a cmd_mmc.c: Add bootbus mmc sub-command
Add a bootbus sub-command to the mmc command to allow for setting
the boot_bus_width, reset_boot_bus_width and boot_mode fields of
BOOT_BUS_WIDTH (EXT_CSD[177]).

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 18:17:49 +02:00
Tom Rini
792970b0a3 cmd_mmc.c: Add 'partconf' command to mmc
Add a partconf sub-command to the mmc command to allow for setting
the boot_ack, boot_partition and partition_access fields of
PARTITION_CONFIG (formerly BOOT_CONFIG, EXT_CSD[179]).  Part of this
requires changing the check for 'part' from an strncmp to a strcmp, like
the rest of the sub-commands.

Cc: Andy Fleming <afleming@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 18:17:49 +02:00
Siva Durga Prasad Paladugu
f9ec45d1d9 mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1B
As per the below commit
"mmc: sdhci: add the quirk for broken r1b response"
(sha1: 3a6383207b)
need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the
response type is R1b.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 17:47:19 +02:00
Rajeshwari S Shinde
d3e016cc28 MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)

Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.

This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 17:42:26 +02:00
Stephen Warren
def816a2ba mmc: set rca to 1 for MMC cards
U-Boot currently sets MMC cards' RCA register to 0. This value is
reserved according to the specification. Use a value of 1 instead, just
like the Linux kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07 17:34:06 +02:00
Alexey Brodkin
50b0df814b net/designware: make driver compatible with data cache
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:

 * Flush Tx/Rx buffer descriptors their modification
 * Invalidate Tx/Rx buffer descriptors before reading its values
 * Flush cache for data passed from CPU to GMAC
 * Invalidate cache for data passed from GMAC to CPU

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-07 09:17:05 -05:00