Commit graph

37540 commits

Author SHA1 Message Date
Chen-Yu Tsai
511992695d sunxi: Implement poweroff support for axp818 pmic
Adds poweroff support for axp818 pmic.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
9850e20148 sunxi: Enable AXP818 SW for Sinovoip BPI M3
The SW output of the PMIC supplies the ethernet PHY with power.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
15278ccb84 sunxi: power: axp818: Add support for switch SW
The AXP818 has a switchable output, SW. This is commonly used for
controlling power to the LCD backlight.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
a696253c1d power: axp818: Fix typo for fldo2 Kconfig description
Description said eldo2 instead of fldo2, a copy-paste error.

Fixes: 38491d9c65 ("power: axp818: Add support for FLDOs")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
aa23f539c8 power: axp221: Remove switch case to simplify axp_set_eldo
The ELDO enable bits and registers are contiguous for axp221. Instead
of a switch case testing against the index, just use the index to shift
the bit or register offset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
5af116b560 sunxi: Disable VIDEO for SoCs without display support
The newer chips use a newer display pipeline, which is not supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
acdab175c0 sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCs
A83T, H3, and A64 have a dedicated pin for card detect on the PF
pingroup. This is used in all designs. Set it as the default.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
a81b79950e sunxi: Sort SoC variants by family (sunXi) first, chip name second
In most other places, we sort SoC descriptions by family (sunXi) first,
then by the chip name (A20).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Chen-Yu Tsai
1a5f0de08e sunxi: make SoC variant choice mandatory
The user should always select an SoC variant to support. Not choosing
one doesn't make sense for a bootloader.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-05-25 17:52:39 +02:00
Tom Rini
fc15b9beed Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-05-24 13:42:03 -04:00
Tom Rini
2ee490a024 Merge branch 'master' of git://git.denx.de/u-boot-net
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/zynq_gem.c
2016-05-24 11:59:02 -04:00
Dan Murphy
0a71cd7729 net: phy: dp83867: Add SGMII helper for configuration
The code assumed that if the interface is not RGMII configured
then it must be SGMII configured.  This device has the ability
to support most of the MII interfaces.  Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:05 -05:00
Dan Murphy
3c221af3c3 net: phy: Add phy_interface_is_sgmii to phy.h
Add a helper to phy.h to identify whether the
phy is configured for SGMII all variables.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:05 -05:00
Dan Murphy
3ab72fe807 net: phy: Move is_rgmii helper to phy.h
Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.

This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:05 -05:00
Dan Murphy
085445ca41 net: phy: ti: Allow the driver to be more configurable
Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Dan Murphy
c7ba7bdc9d net: phy: dp83867: Add device tree bindings and documentation
Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Dan Murphy
20671a9896 net: zynq_gem: Add the passing of the phy-handle node
Add the ability to pass the phy-handle node offset
to the phy driver.  This allows the phy driver
to access the DT subnode's data and parse accordingly.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Dan Murphy
cb3862277b drivers: net: cpsw: Add reading of DT phy-handle node
Add the ability to read the phy-handle node of the
cpsw slave.  Upon reading this handle the phy-id
can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Mugunthan V N
641b936fa5 defconfig: dra74_evm: enable eth driver model
Enable eth driver model for dra74_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Mugunthan V N
bc705ea1cf defconfig: am437x_sk_evm: enable eth driver model
Enable eth driver model for am437x_sk_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
54e3ba993a defconfig: am437x_gp_evm: enable eth driver model
Enable eth driver model for am437x_gp_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
844f814478 arm: dts: dra7: fix ethernet name with proper device address
Fix typo error for cpsw device name with proper device address

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
d7dc888d60 arm: dts: dra7: add syscon node to cpsw to read mac address
Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
dcda79e119 arm: dts: am4372: add syscon node to cpsw to read mac address
Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
e4310566de drivers: net: cpsw: add support for reading mac address from efuse
Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.

The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:03 -05:00
Mugunthan V N
66e740cbbd drivers: net: cpsw: fix get mdio base and gmii_sel reg from DT
Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:02 -05:00
Mugunthan V N
70c5b7b37e ARM: omap5: add platform specific ethernet phy modes configurations
Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:02 -05:00
Mugunthan V N
b2003c5458 drivers: net: cpsw: fix cpsw dp parse when num slaves as 1
On some boards number of slaves can be 1 when only one port
ethernet is pinned out. So do not break when slave_index and
num slaves check fails, instead continue to parse the next
child.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:02 -05:00
Mugunthan V N
3d12e80495 ti_omap5_common: eth: do not define DM_ETH for spl
Since omap's spl doesn't support DM currently, do not define
DM_ETH for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:02 -05:00
Mugunthan V N
73443b9e4c drivers: core: device: add support to check dt compatible for a device/machine
Provide an api to check whether the given device or machine is
compatible with the given compat string which helps in making
decisions in drivers based on device or machine compatible.

Idea taken from Linux.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:02 -05:00
Kevin Smith
24ae3961f8 net: phy: Add PHY driver for mv88e61xx switches
The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:39:04 -05:00
Kevin Smith
83c05515d8 net: Remove unused mv88e61xx switch driver
No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-05-24 11:39:04 -05:00
Tom Rini
ec8fb48ce9 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-05-24 08:20:43 -04:00
Tom Rini
c98dc5a133 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-05-24 07:22:55 -04:00
Michal Simek
ad5b580126 ARM: zynq: Simplify zynq configuration
Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:22:50 +02:00
Michal Simek
1b008fdb06 phy: marvell: Do not reset phy after negotiation
The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c35)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:17:59 +02:00
Michal Simek
7a673f0b06 phy: Wire return value from phy_config()
Fix zynq_gem driver to handle error from phy_config correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:17:59 +02:00
Michal Simek
62afc60188 image: Add boot_get_fpga() to load fpga with bootm
Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove additional blankline in image.h
2016-05-24 13:17:59 +02:00
Michal Simek
b733c278d7 net: phy: Handle phy_startup() error codes properly
Propagate error code from genphy_update_link() to phy startup().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:59 +02:00
Michal Simek
ef5e821bd8 phy: Return correct error code when timeout happens
Return -ETIMEDOUT if timeout happens.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:59 +02:00
Michal Simek
55259e7cda net: xilinx: Handle error value from phy_startup()
Handle error returned by phy_startup() properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:55 +02:00
Michal Simek
ed0cea7c52 mkimage: Report information about fpga
Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-24 11:15:02 +02:00
Michal Simek
905bca6c2d fpga: Fix typo in function comment
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:02 +02:00
Michal Simek
293271cbc3 ARM64: zynqmp: Enable CLK framework
ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Michal Simek
e6a9ed04e7 ARM64: zynqmp: Add SPL support support
Support RAM and MMC boot mode in SPL also with SPL_FIT images.

In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
 aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
 mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
 -d bl31.bin atf.ub
 cp spl/boot.bin <sdcard fat partition>
 cp atf.ub <sdcard fat partition>
 cp u-boot.bin <sdcard fat partition>

2) Boot flow with full U-Boot(EL3):
 cp spl/boot.bin <sdcard>
 cp u-boot*.img <sdcard>

3) emmc boot mode
 dd if=/dev/zero of=sd.img bs=1024 count=1024
 parted sd.img mktable msdos
 parted sd.img mkpart p fat32 0% 100%
 kpartx -a sd.img
 mkfs.vfat /dev/mapper/loop0p1
 mount /dev/mapper/loop0p1 /mnt/
 cp spl/boot.bin /mnt
 cp u-boot.img /mnt
 cp u-boot.bin /mnt
 cp atf.ub /mnt
 umount /dev/mapper/loop0p1
 kpartx -d sd.img
 cp sd.img /tftpboot/

 and program it via u-boot
 tftpb 10000 sd.img
 mmcinfo
 mmc write 10000 0 $filesize
 mmc rescan
 mmc part
 ls mmc 0

psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.

The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Michal Simek
c9811e14cf ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI
Add missing u-boot,dm-pre-reloc to get IPs initialized.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Alexander Graf
0a8c4f67f3 ARM64: zynqmp: Align gic ranges for 64k in device tree
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.

This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Michal Simek
d9b58b3031 tools: zynqmpimage: Add Xilinx ZynqMP boot header generation
Add support for the zynqmpimage to mkimage.
Only basic functionality is supported without encryption and register
initialization with one partition which is filled by U-Boot SPL.
For more detail information look at Xilinx ZynqMP TRM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-24 11:15:01 +02:00
Michal Simek
8d16e1d593 SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode
Support loading FIT in SPL for RAM bootmode.
CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
in memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-05-24 11:15:01 +02:00
Michal Simek
f44e603f73 ARM: zynq: Call ps7_post_config() for SPL
If ps7_post_config() is defined call it. It is enabling for example
level shifters for PL bitstreams.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00