This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations:
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
SPI2_CS0 == 0: NAND (default)
SPI2_CS0 == 1: eMMC
am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various
configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)
Signed-off-by: Pekon Gupta <pekon@ti.com>
When we're using EMMC_BOOT that means we have environment on eMMC so
we can make use of CONFIG_SPL_ENV_SUPPORT within Falcon Mode.
Signed-off-by: Tom Rini <trini@ti.com>
In the case of SPL on these boards we only need environment for
SPL_USBETH, so it's safe to normally use ENV_IS_NOWHERE and SPL+NAND
does not support environment today.
Cc: Hannes Petermaier <oe5hpm@oevsv.at>
Signed-off-by: Tom Rini <trini@ti.com>
There are times where we may need more than a few kilobytes of stack
space. We also will not be using CONFIG_SPL_STACK location prior to DDR
being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick
a good location within DDR for this to be. Tested on
OMAP4/AM335x/OMAP5/DRA7xx.
Signed-off-by: Tom Rini <trini@ti.com>
On am335x_evm we only support USBETH for a networking SPL option so move
the rest of the defines under that area as that's the only time we need
(and want) environment support here.
Signed-off-by: Tom Rini <trini@ti.com>
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com
Signed-off-by: Andy Fleming <afleming@gmail.com>
The booting of the board is now protected by the CPU watchdog.
A failure during the boot phase will end up in board reset.
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
[York Sun: Add prototype in watchdog.h]
Reviewed-by: York Sun <yorksun@freescale.com>
Add callback with __weak annotation to allow setup of environment
partition number in runtime from a board file.
Propagate mmc_switch_part() return value into init_mmc_for_env() instead
of -1 in case of failure.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Add configuration register definition, this register only
exists on MCI IP version >= 0x300.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Specific USB EHCI settings to be set for sun5i if CONFIG_USB_EHCI is enabled.
Note we don't specify default VBUS gpio pins for sun5i since they vary too
much from board to board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Specific USB EHCI settings to be set for sun4i if CONFIG_USB_EHCI is enabled.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Specific USB EHCI settings to be set for sun7i if
CONFIG_USB_EHCI is enabled.
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Use SUNXI_GPH macro for SUNXI_USB_VBUS#_GPIO]
[hdegoede@redhat.com: Add #ifndef SUNXI_USB_VBUS#_GPIO to allow override of
the default pins from boards.cfg]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
General configuration settings to be set if CONFIG_USB_EHCI
is enabled for an Allwinner aka sunxi SoC.
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.
The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port. This is added under a
suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig.
Remove the redundant definition in config headers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit enables Kconfig.
Going forward, we use Kconfig for the board configuration.
mkconfig will never be used. Nor will include/config.mk be generated.
Kconfig must be adjusted for U-Boot because our situation is
a little more complicated than Linux Kernel.
We have to generate multiple boot images (Normal, SPL, TPL)
from one source tree.
Each image needs its own configuration input.
Usage:
Run "make <board>_defconfig" to do the board configuration.
It will create the .config file and additionally spl/.config, tpl/.config
if SPL, TPL is enabled, respectively.
You can use "make config", "make menuconfig" etc. to create
a new .config or modify the existing one.
Use "make spl/config", "make spl/menuconfig" etc. for spl/.config
and do likewise for tpl/.config file.
The generic syntax of configuration targets for SPL, TPL is:
<target_image>/<config_command>
Here, <target_image> is either 'spl' or 'tpl'
<config_command> is 'config', 'menuconfig', 'xconfig', etc.
When the configuration is done, run "make".
(Or "make <board>_defconfig all" will do the configuration and build
in one time.)
For futher information of how Kconfig works in U-Boot,
please read the comment block of scripts/multiconfig.py.
By the way, there is another item worth remarking here:
coexistence of Kconfig and board herder files.
Prior to Kconfig, we used C headers to define a set of configs.
We expect a very long term to migrate from C headers to Kconfig.
Two different infractructure must coexist in the interim.
In our former configuration scheme, include/autoconf.mk was generated
for use in makefiles.
It is still generated under include/, spl/include/, tpl/include/ directory
for the Normal, SPL, TPL image, respectively.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
We are about to switch to Kconfig in the next commit.
But there are something to get done beforehand.
In Kconfig, include/generated/autoconf.h defines boolean
CONFIG macros as 1.
CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1.
Otherwise, when switching to Kconfig, the build log
would be sprinkled with warning messages like this:
warning: "CONFIG_SPL" redefined [enabled by default]
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.
[maz: collapsed 3 patches into one, rewrote commit message]
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.
Following configs are affected in this patch:
CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>
This patch also updates documentation for few of above NAND configs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Fixes commit a0a37183bd
ARM: omap: merge GPMC initialization code for all platform
1) NAND device are not directly memory-mapped to CPU address-space, they are
indirectly accessed via following GPMC registers:
- GPMC_NAND_COMMAND_x
- GPMC_NAND_ADDRESS_x
- GPMC_NAND_DATA_x
Therefore from CPU's point of view, NAND address-map can be limited to just
above register addresses. But GPMC chip-select address-map can be configured
in granularity of 16MB only.
So this patch uses GPMC_SIZE_16M for all NAND devices.
2) NOR device are directly memory-mapped to CPU address-space, so its
address-map size depends on actual addressable region in NOR FLASH device.
So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
size configuration.
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch adds clock definitions and commands to support Keystone2
K2E SOC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.
Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.
The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.
The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.
Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
pekon gupta
Tom Rini
Albert ARIBAUD
Andy Fleming
Boschung, Rainer
Dmitry Lifshitz
Bo Shen
DrEagle
Marc Zyngier
Hans de Goede
Roman Byshko
Ian Campbell
Masahiro Yamada
Ma Haijun
Hao Zhang
Khoronzhuk, Ivan
Stefan Roese
Andreas Bießmann