- added framework port for TM4C with dummy flash driver.
- added demo bootloader for DK-TM4C123G board. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@72 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
parent
82acb8d718
commit
abfc06cef3
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@ -1,5 +1,5 @@
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[sci]
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port=3
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port=6
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baudrate=8
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[xcp]
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seedkey=
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Binary file not shown.
Binary file not shown.
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/**
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\defgroup Boot_ARMCM4_TM4C_DK_TM4C123G_IAR Bootloader
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\brief Bootloader.
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\ingroup ARMCM4_TM4C_DK_TM4C123G_IAR
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*/
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/************************************************************************************//**
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* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Boot\hooks.c
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* \brief Bootloader callback source file.
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* \ingroup Boot_ARMCM4_TM4C_DK_TM4C123G_IAR
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
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||||
*
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||||
*----------------------------------------------------------------------------------------
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||||
* L I C E N S E
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||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
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||||
*
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||||
* \endinternal
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||||
****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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#include <stdbool.h>
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#include <stdint.h>
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#if (BOOT_FILE_LOGGING_ENABLE > 0)
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "driverlib/uartlib.h"
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#endif
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/****************************************************************************************
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* B A C K D O O R E N T R Y H O O K F U N C T I O N S
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****************************************************************************************/
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||||
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
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/************************************************************************************//**
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** \brief Initializes the backdoor entry option.
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** \return none.
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||||
**
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||||
****************************************************************************************/
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void BackDoorInitHook(void)
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{
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} /*** end of BackDoorInitHook ***/
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/************************************************************************************//**
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** \brief Checks if a backdoor entry is requested.
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** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
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**
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****************************************************************************************/
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blt_bool BackDoorEntryHook(void)
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{
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/* default implementation always activates the bootloader after a reset */
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return BLT_TRUE;
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} /*** end of BackDoorEntryHook ***/
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#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
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||||
|
||||
|
||||
/****************************************************************************************
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* C P U D R I V E R H O O K F U N C T I O N S
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****************************************************************************************/
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|
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#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
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/************************************************************************************//**
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** \brief Callback that gets called when the bootloader is about to exit and
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** hand over control to the user program. This is the last moment that
|
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** some final checking can be performed and if necessary prevent the
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||||
** bootloader from activiting the user program.
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** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
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** keep the bootloader active.
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**
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****************************************************************************************/
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blt_bool CpuUserProgramStartHook(void)
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{
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/* okay to start the user program */
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return BLT_TRUE;
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} /*** end of CpuUserProgramStartHook ***/
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#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
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|
||||
|
||||
/****************************************************************************************
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||||
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
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||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the internal NVM driver
|
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** initialization routine.
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||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInitHook(void)
|
||||
{
|
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} /*** end of NvmInitHook ***/
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|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver write
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
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** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||
** been written yet.
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** \param addr Start address.
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** \param len Length in bytes.
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** \param data Pointer to the data buffer.
|
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** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
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** not within the supported memory range, or BLT_NVM_ERROR is the write
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** operation failed.
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**
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****************************************************************************************/
|
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blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
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{
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return BLT_NVM_NOT_IN_RANGE;
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} /*** end of NvmWriteHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver erase
|
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** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
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** hasn't been erased yet.
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** \param addr Start address.
|
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** \param len Length in bytes.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
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** not within the supported memory range, or BLT_NVM_ERROR is the erase
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||||
** operation failed.
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||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
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} /*** end of NvmEraseHook ***/
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||||
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||||
|
||||
/************************************************************************************//**
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||||
** \brief Callback that gets called at the end of the NVM programming session.
|
||||
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
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||||
**
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****************************************************************************************/
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blt_bool NvmDoneHook(void)
|
||||
{
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return BLT_TRUE;
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||||
} /*** end of NvmDoneHook ***/
|
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#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
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||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
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||||
**
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||||
****************************************************************************************/
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||||
blt_bool NvmVerifyChecksumHook(void)
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||||
{
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||||
return BLT_TRUE;
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if a valid user programming is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
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||||
**
|
||||
****************************************************************************************/
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||||
blt_bool NvmWriteChecksumHook(void)
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{
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return BLT_TRUE;
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}
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#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
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||||
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
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||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
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/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
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||||
** initialization routine. It can be used to configure and enable the
|
||||
** watchdog.
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||||
** \return none.
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||||
**
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****************************************************************************************/
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void CopInitHook(void)
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{
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} /*** end of CopInitHook ***/
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||||
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||||
|
||||
/************************************************************************************//**
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||||
** \brief Callback that gets called at the end of the internal COP driver
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** service routine. This gets called upon initialization and during
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** potential long lasting loops and routine. It can be used to service
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** the watchdog to prevent a watchdog reset.
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** \return none.
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**
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||||
****************************************************************************************/
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void CopServiceHook(void)
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{
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} /*** end of CopServiceHook ***/
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#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
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||||
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||||
|
||||
/****************************************************************************************
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||||
* F I L E S Y S T E M I N T E R F A C E H O O K F U N C T I O N S
|
||||
****************************************************************************************/
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||||
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||||
#if (BOOT_FILE_SYS_ENABLE > 0)
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||||
|
||||
/****************************************************************************************
|
||||
* Constant data declarations
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||||
****************************************************************************************/
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||||
/** \brief Firmware filename. */
|
||||
static const blt_char firmwareFilename[] = "/demoprog_ek_lm3s6965.srec";
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||||
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||||
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||||
/****************************************************************************************
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||||
* Local data declarations
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||||
****************************************************************************************/
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||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/** \brief Data structure for grouping log-file related information. */
|
||||
static struct
|
||||
{
|
||||
FIL handle; /**< FatFS handle to the log-file. */
|
||||
blt_bool canUse; /**< Flag to indicate if the log-file can be used. */
|
||||
} logfile;
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called to check whether a firmware update from
|
||||
** local file storage should be started. This could for example be when
|
||||
** a switch is pressed, when a certain file is found on the local file
|
||||
** storage, etc.
|
||||
** \return BLT_TRUE if a firmware update is requested, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FileIsFirmwareUpdateRequestedHook(void)
|
||||
{
|
||||
FILINFO fileInfoObject = { 0 }; /* needs to be zeroed according to f_stat docs */;
|
||||
|
||||
/* Current example implementation looks for a predetermined firmware file on the
|
||||
* SD-card. If the SD-card is accessible and the firmware file was found the firmware
|
||||
* update is started. When successfully completed, the firmware file is deleted.
|
||||
* During the firmware update, progress information is written to a file called
|
||||
* bootlog.txt and additionally outputted on UART @57600 bps for debugging purposes.
|
||||
*/
|
||||
/* check if firmware file is present and SD-card is accessible */
|
||||
if (f_stat(firmwareFilename, &fileInfoObject) == FR_OK)
|
||||
{
|
||||
/* check if the filesize is valid and that it is not a directory */
|
||||
if ( (fileInfoObject.fsize > 0) && (!(fileInfoObject.fattrib & AM_DIR)) )
|
||||
{
|
||||
/* all conditions are met to start a firmware update from local file storage */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
}
|
||||
/* still here so no firmware update request is pending */
|
||||
return BLT_FALSE;
|
||||
} /*** end of FileIsFirmwareUpdateRequestedHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback to obtain the filename of the firmware file that should be
|
||||
** used during the firmware update from the local file storage. This
|
||||
** hook function is called at the beginning of the firmware update from
|
||||
** local storage sequence.
|
||||
** \return valid firmware filename with full path or BLT_NULL.
|
||||
**
|
||||
****************************************************************************************/
|
||||
const blt_char *FileGetFirmwareFilenameHook(void)
|
||||
{
|
||||
return firmwareFilename;
|
||||
} /*** end of FileGetFirmwareFilenameHook ***/
|
||||
|
||||
|
||||
#if (BOOT_FILE_STARTED_HOOK_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called to inform the application that a firmware
|
||||
** update from local storage just started.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FileFirmwareUpdateStartedHook(void)
|
||||
{
|
||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/* create/overwrite the logfile */
|
||||
logfile.canUse = BLT_FALSE;
|
||||
if (f_open(&logfile.handle, "/bootlog.txt", FA_CREATE_ALWAYS | FA_WRITE) == FR_OK)
|
||||
{
|
||||
logfile.canUse = BLT_TRUE;
|
||||
}
|
||||
#endif
|
||||
} /*** end of FileFirmwareUpdateStartedHook ***/
|
||||
#endif /* BOOT_FILE_STARTED_HOOK_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_FILE_COMPLETED_HOOK_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called to inform the application that a firmware
|
||||
** update was successfully completed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FileFirmwareUpdateCompletedHook(void)
|
||||
{
|
||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/* close the log file */
|
||||
if (logfile.canUse == BLT_TRUE)
|
||||
{
|
||||
f_close(&logfile.handle);
|
||||
}
|
||||
/* wait for all logging related transmission to complete */
|
||||
while (UARTBusy(UART0_BASE) == true);
|
||||
#endif
|
||||
/* now delete the firmware file from the disk since the update was successful */
|
||||
f_unlink(firmwareFilename);
|
||||
} /*** end of FileFirmwareUpdateCompletedHook ***/
|
||||
#endif /* BOOT_FILE_COMPLETED_HOOK_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_FILE_ERROR_HOOK_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called in case an error occurred during a firmware
|
||||
** update. Refer to <file.h> for a list of available error codes.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FileFirmwareUpdateErrorHook(blt_int8u error_code)
|
||||
{
|
||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/* error detected which stops the firmware update, so close the log file */
|
||||
if (logfile.canUse == BLT_TRUE)
|
||||
{
|
||||
f_close(&logfile.handle);
|
||||
}
|
||||
#endif
|
||||
} /*** end of FileFirmwareUpdateErrorHook ***/
|
||||
#endif /* BOOT_FILE_ERROR_HOOK_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called each time new log information becomes
|
||||
** available during a firmware update.
|
||||
** \param info_string Pointer to a character array with the log entry info.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FileFirmwareUpdateLogHook(blt_char *info_string)
|
||||
{
|
||||
/* write the string to the log file */
|
||||
if (logfile.canUse == BLT_TRUE)
|
||||
{
|
||||
if (f_puts(info_string, &logfile.handle) < 0)
|
||||
{
|
||||
logfile.canUse = BLT_FALSE;
|
||||
f_close(&logfile.handle);
|
||||
}
|
||||
}
|
||||
/* echo all characters in the string on UART */
|
||||
while(*info_string != '\0')
|
||||
{
|
||||
/* write character to transmit holding register */
|
||||
UARTCharPutNonBlocking(UART0_BASE, *info_string);
|
||||
/* wait for tx holding register to be empty */
|
||||
while(UARTSpaceAvail(UART0_BASE) == false);
|
||||
/* point to the next character in the string */
|
||||
info_string++;
|
||||
}
|
||||
} /*** end of FileFirmwareUpdateLogHook ***/
|
||||
#endif /* BOOT_FILE_LOGGING_ENABLE > 0 */
|
||||
|
||||
|
||||
#endif /* BOOT_FILE_SYS_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of hooks.c ************************************/
|
|
@ -0,0 +1,4 @@
|
|||
Integrated Development Environment
|
||||
----------------------------------
|
||||
IAR Embedded Workbench for ARM v6.50 was used as the editor during the development of this software program. This directory contains
|
||||
the Embedded Workbench project and worksapce files. More info is available at: http://www.iar.com/
|
|
@ -0,0 +1,24 @@
|
|||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM
|
||||
@REM Read about available command line parameters in the C-SPY Debugging
|
||||
@REM Guide. Hints about additional command line parameters that may be
|
||||
@REM useful in specific cases:
|
||||
@REM --download_only Downloads a code image without starting a debug
|
||||
@REM session afterwards.
|
||||
@REM --silent Omits the sign-on message.
|
||||
@REM --timeout Limits the maximum allowed execution time.
|
||||
@REM
|
||||
|
||||
|
||||
"C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armlmiftdi.dll" %1 --plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\TexasInstruments\FlashTC4_H6.board" --backend -B "--endian=little" "--cpu=Cortex-M4" "--fpu=VFPv4" "-p" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\TexasInstruments\TM4C123GH6PGE.ddf" "--drv_verify_download" "--semihosting" "--device=TM4C123GH6PGE" "--lmiftdi_speed=500"
|
||||
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<Project>
|
||||
<Desktop>
|
||||
<Static>
|
||||
<Debug-Log>
|
||||
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TI TivaWare for C Series Source and Object Code Software License Agreement
|
||||
|
||||
IMPORTANT - PLEASE READ THE FOLLOWING LICENSE AGREEMENT CAREFULLY. THIS IS A
|
||||
LEGALLY BINDING AGREEMENT. AFTER YOU READ THIS LICENSE AGREEMENT, YOU WILL BE
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ASKED WHETHER YOU ACCEPT AND AGREE TO THE TERMS OF THIS LICENSE AGREEMENT. DO
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AGREE TO THE TERMS OF THIS LICENSE AGREEMENT ON BEHALF OF YOURSELF OR YOUR
|
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COMPANY (AS APPLICABLE); AND (2) YOU INTEND TO BE BOUND BY THE TERMS OF THIS
|
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LICENSE AGREEMENT ON BEHALF OF YOURSELF OR YOUR COMPANY (AS APPLICABLE).
|
||||
|
||||
Important - Read carefully: This Source and Object Code Software License
|
||||
Agreement ("Agreement") is a legal agreement between you (either an individual
|
||||
or legal entity) and Texas Instruments Incorporated ("TI"). The "Licensed
|
||||
Materials" subject to this Agreement include the software programs (in whole or
|
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|
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|
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documentation (in whole or in part) associated and provided with these software
|
||||
programs, as well as any updates or upgrades to such software programs and
|
||||
documentation, if any, provided to you at TI's sole discretion. The Licensed
|
||||
Materials are specifically designed and licensed for use solely and exclusively
|
||||
with semiconductor devices manufactured by or for TI ("TI Devices"). By
|
||||
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|
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abide by the provisions set forth herein. This Agreement is displayed for you
|
||||
to read prior to using the Licensed Materials. If you choose not to accept or
|
||||
agree with these provisions, do not download or install the Licensed Materials.
|
||||
|
||||
Note Regarding Possible Access to Open Source Software: The Licensed Materials
|
||||
may be bundled with Open Source Software. "Open Source Software" means any
|
||||
software licensed under terms requiring that (A) other software ("Proprietary
|
||||
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|
||||
developed using such software: (i) be disclosed or distributed in source code
|
||||
form; or (ii) otherwise be licensed on terms inconsistent with the terms of
|
||||
this Agreement, including but not limited to permitting use of the Proprietary
|
||||
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|
||||
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|
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Software and/or Proprietary Software incorporated, combined or distributed with
|
||||
such Open Source Software or developed using such Open Source Software.
|
||||
|
||||
By accepting this Agreement, you may gain access to Open Source Software, in
|
||||
which case such Open Source Software will be listed in the applicable software
|
||||
manifest (in whole or in part, the "Open Source Materials"). Your use of the
|
||||
Open Source Materials is subject to the separate licensing terms applicable to
|
||||
such Open Source Materials as specified in the applicable software manifest.
|
||||
For clarification, this Agreement does not limit your rights under, or grant
|
||||
you rights that supersede, the license terms of any applicable Open Source
|
||||
Materials license agreement. If any of the Open Source Materials have been
|
||||
provided to you in object code only, TI will provide to you, or show you where
|
||||
you can access, the source code versions of such Open Source Materials if you
|
||||
contact TI at Texas Instruments Incorporated, 12500 TI Boulevard, Mail Station
|
||||
8638, Dallas, Texas 75243, Attention: Contracts Manager, Embedded Processing.
|
||||
In the event you choose not to accept or agree with the terms in any applicable
|
||||
Open Source Materials license agreement, you must terminate this Agreement.
|
||||
|
||||
1. License Grant and Use Restrictions.
|
||||
|
||||
a. Licensed Materials License Grant. Subject to the terms of this Agreement, TI
|
||||
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|
||||
non-assignable, non-sub-licensable, fully paid-up and royalty-free license to:
|
||||
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(i). Limited Source Code License. make copies, prepare derivative works,
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||||
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|
||||
source code for the sole purpose of developing object and executable versions
|
||||
of such Licensed Materials, or any derivative thereof, that execute solely and
|
||||
exclusively on TI Devices, for end use in Licensee Products, and maintaining
|
||||
and supporting such Licensed Materials, or any derivative thereof, and Licensee
|
||||
Products. For purposes of this Agreement, "Licensee Product" means a product
|
||||
that consists of both hardware, including one or more TI Devices, and software
|
||||
components, including only executable versions of the Licensed Materials that
|
||||
execute solely and exclusively on such TI Devices.
|
||||
|
||||
(ii). Object Code Evaluation, Testing and Use License. make copies, display
|
||||
internally, distribute internally and use internally the Licensed Materials in
|
||||
object code for the sole purposes of evaluating and testing the Licensed
|
||||
Materials and designing and developing Licensee Products, and maintaining and
|
||||
supporting the Licensee Products;
|
||||
|
||||
(iii). Demonstration License. demonstrate to third parties the Licensed
|
||||
Materials executing solely and exclusively on TI Devices as they are used in
|
||||
Licensee Products, provided that such Licensed Materials are demonstrated in
|
||||
object or executable versions only and
|
||||
|
||||
(iv). Production and Distribution License. make, use, import, export and
|
||||
otherwise distribute the Licensed Materials as part of a Licensee Product,
|
||||
provided that such Licensee Products include only embedded executable copies of
|
||||
such Licensed Materials that execute solely and exclusively on TI Devices.
|
||||
|
||||
b. Contractors. The licenses granted to you hereunder shall include your
|
||||
on-site and off-site contractors (either an individual or entity), while such
|
||||
contractors are performing work for or providing services to you, provided that
|
||||
such contractors have executed work-for-hire agreements with you containing
|
||||
applicable terms and conditions consistent with the terms and conditions set
|
||||
forth in this Agreement and provided further that you shall be liable to TI for
|
||||
any breach by your contractors of this Agreement to the same extent as you
|
||||
would be if you had breached the Agreement yourself.
|
||||
|
||||
c. No Other License. Nothing in this Agreement shall be construed as a license
|
||||
to any intellectual property rights of TI other than those rights embodied in
|
||||
the Licensed Materials provided to you by TI. EXCEPT AS PROVIDED HEREIN, NO
|
||||
OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER TI
|
||||
INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREIN.
|
||||
|
||||
d. Covenant not to Sue. You agree not to assert a claim against TI or its
|
||||
licensees that the Licensed Materials infringe your intellectual property
|
||||
rights.
|
||||
|
||||
e. Restrictions. You shall maintain the source code versions of the Licensed
|
||||
Materials under password control protection and shall not disclose such source
|
||||
code versions of the Licensed Materials, to any person other than your
|
||||
employees and contractors whose job performance requires access. You shall not
|
||||
use the Licensed Materials with a processing device other than a TI Device, and
|
||||
you agree that any such unauthorized use of the Licensed Materials is a
|
||||
material breach of this Agreement. You shall not use the Licensed Materials for
|
||||
the purpose of analyzing or proving infringement of any of your patents by
|
||||
either TI or TI's customers. Except as expressly provided in this Agreement,
|
||||
you shall not copy, publish, disclose, display, provide, transfer or make
|
||||
available the Licensed Materials to any third party and you shall not
|
||||
sublicense, transfer, or assign the Licensed Materials or your rights under
|
||||
this Agreement to any third party. You shall not mortgage, pledge or encumber
|
||||
the Licensed Materials in any way. You may use the Licensed Materials with Open
|
||||
Source Software or with software developed using Open Source Software tools
|
||||
provided you do not incorporate, combine or distribute the Licensed Materials
|
||||
in a manner that subjects the Licensed Materials to any license obligations or
|
||||
any other intellectual property related terms of any license governing such
|
||||
Open Source Software.
|
||||
|
||||
f. Termination. This Agreement is effective on the date the Licensed Materials
|
||||
are delivered to you together with this Agreement and will remain in full force
|
||||
and effect until terminated. You may terminate this Agreement at any time by
|
||||
written notice to TI. Without prejudice to any other rights, if you fail to
|
||||
comply with the terms of this Agreement or you are acquired, TI may terminate
|
||||
your right to use the Licensed Materials upon written notice to you. Upon
|
||||
termination of this Agreement, you will destroy any and all copies of the
|
||||
Licensed Materials in your possession, custody or control and provide to TI a
|
||||
written statement signed by your authorized representative certifying such
|
||||
destruction. Except for Sections 1(a), 1(b) and 1(d), all provisions of this
|
||||
Agreement shall survive termination of this Agreement.
|
||||
|
||||
2. Licensed Materials Ownership. The Licensed Materials are licensed, not sold
|
||||
to you, and can only be used in accordance with the terms of this Agreement.
|
||||
Subject to the licenses granted to you pursuant to this Agreement, TI and its
|
||||
licensors own and shall continue to own all right, title and interest in and to
|
||||
the Licensed Materials, including all copies thereof. You agree that all fixes,
|
||||
modifications and improvements to the Licensed Materials conceived of or made
|
||||
by TI that are based, either in whole or in part, on your feedback, suggestions
|
||||
or recommendations are the exclusive property of TI and all right, title and
|
||||
interest in and to such fixes, modifications or improvements to the Licensed
|
||||
Materials will vest solely in TI. Moreover, you acknowledge and agree that when
|
||||
your independently developed software or hardware components are combined, in
|
||||
whole or in part, with the Licensed Materials, your right to use the combined
|
||||
work that includes the Licensed Materials remains subject to the terms and
|
||||
conditions of this Agreement.
|
||||
|
||||
3. Intellectual Property Rights.
|
||||
|
||||
a. The Licensed Materials contain copyrighted material, trade secrets and other
|
||||
proprietary information of TI and its licensors and are protected by copyright
|
||||
laws, international copyright treaties, and trade secret laws, as well as other
|
||||
intellectual property laws. To protect TI's and its licensors' rights in the
|
||||
Licensed Materials, you agree, except as specifically permitted by statute by a
|
||||
provision that cannot be waived by contract, not to "unlock", decompile,
|
||||
reverse engineer, disassemble or otherwise translate to a human-perceivable
|
||||
form any portions of the Licensed Materials provided to you in object code
|
||||
format only, nor permit any person or entity to do so. You shall not remove,
|
||||
alter, cover, or obscure any confidentiality, trade secret, trade mark, patent,
|
||||
copyright or other proprietary notice or other identifying marks or designs
|
||||
from any component of the Licensed Materials and you shall reproduce and
|
||||
include in all copies of the Licensed Materials the copyright notice(s) and
|
||||
proprietary legend(s) of TI and its licensors as they appear in the Licensed
|
||||
Materials. TI reserves all rights not specifically granted under this
|
||||
Agreement.
|
||||
|
||||
b. Certain Licensed Materials may be based on industry recognized standards or
|
||||
software programs published by industry recognized standards bodies and certain
|
||||
third parties may claim to own patents, copyrights, and other intellectual
|
||||
property rights that cover implementation of those standards. You acknowledge
|
||||
and agree that this Agreement does not convey a license to any such third party
|
||||
patents, copyrights, and other intellectual property rights and that you are
|
||||
solely responsible for any patent, copyright, or other intellectual property
|
||||
right claim that relates to your use or distribution of the Licensed Materials
|
||||
or your use or distribution of your products that include or incorporate the
|
||||
Licensed Materials. Moreover, you acknowledge that you are responsible for any
|
||||
fees or royalties that may be payable to any third party based on such third
|
||||
party's interests in the Licensed Materials or any intellectual property rights
|
||||
that cover implementation of any industry recognized standard, any software
|
||||
program published by any industry recognized standards bodies or any other
|
||||
proprietary technology.
|
||||
|
||||
4. Audit Right. At TI's request, and within thirty (30) calendar days after
|
||||
receiving written notice, you shall permit an internal or independent auditor
|
||||
selected by TI to have access, no more than once each calendar year (unless the
|
||||
immediately preceding audit revealed a discrepancy) and during your regular
|
||||
business hours, to all of your equipment, records, and documents as may contain
|
||||
information bearing upon the use of the Licensed Materials. You shall keep
|
||||
full, complete, clear and accurate records with respect to product sales and
|
||||
distributions for a period beginning with the then-current calendar year and
|
||||
going back three (3) years.
|
||||
|
||||
5. Confidential Information. You acknowledge and agree that the Licensed
|
||||
Materials contain trade secrets and other confidential information of TI and
|
||||
its licensors. You agree to use the Licensed Materials solely within the scope
|
||||
of the licenses set forth herein, to maintain the Licensed Materials in strict
|
||||
confidence, to use at least the same procedures and degree of care that you use
|
||||
to prevent disclosure of your own confidential information of like importance
|
||||
but in no instance less than reasonable care, and to prevent disclosure of the
|
||||
Licensed Materials to any third party, except as may be necessary and required
|
||||
in connection with your rights and obligations hereunder; provided, however,
|
||||
that you may not provide the Licensed Materials to any business organization or
|
||||
group within your company or to customers or contractors that design or
|
||||
manufacture semiconductors unless TI gives written consent. You agree to obtain
|
||||
executed confidentiality agreements with your employees and contractors having
|
||||
access to the Licensed Materials and to diligently take steps to enforce such
|
||||
agreements in this respect. TI may disclose your contact information to TI's
|
||||
licensors.
|
||||
|
||||
6. Warranties and Limitations. THE LICENSED MATERIALS ARE PROVIDED "AS IS".
|
||||
FURTHERMORE, YOU ACKNOWLEDGE AND AGREE THAT THE LICENSED MATERIALS HAVE NOT
|
||||
BEEN TESTED OR CERTIFIED BY ANY GOVERNMENT AGENCY OR INDUSTRY REGULATORY
|
||||
ORGANIZATION OR ANY OTHER THIRD PARTY ORGANIZATION. YOU AGREE THAT PRIOR TO
|
||||
USING, INCORPORATING OR DISTRIBUTING THE LICENSED MATERIALS IN OR WITH ANY
|
||||
COMMERCIAL PRODUCT THAT YOU WILL THOROUGHLY TEST THE PRODUCT AND THE
|
||||
FUNCTIONALITY OF THE LICENSED MATERIALS IN OR WITH THAT PRODUCT AND BE SOLELY
|
||||
RESPONSIBLE FOR ANY PROBLEMS OR FAILURES.
|
||||
|
||||
TI AND ITS LICENSORS MAKE NO WARRANTY OR REPRESENTATION, EITHER EXPRESS,
|
||||
IMPLIED OR STATUTORY, REGARDING THE LICENSED MATERIALS, INCLUDING BUT NOT
|
||||
LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
|
||||
PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS,
|
||||
TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. YOU AGREE TO USE YOUR
|
||||
INDEPENDENT JUDGMENT IN DEVELOPING YOUR PRODUCTS. NOTHING CONTAINED IN THIS
|
||||
AGREEMENT WILL BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY TI TO MAINTAIN
|
||||
PRODUCTION OF ANY TI SEMICONDUCTOR DEVICE OR OTHER HARDWARE OR SOFTWARE WITH
|
||||
WHICH THE LICENSED MATERIALS MAY BE USED.
|
||||
|
||||
IN NO EVENT SHALL TI OR ITS LICENSORS, BE LIABLE FOR ANY SPECIAL, INDIRECT,
|
||||
INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED, ON ANY THEORY OF
|
||||
LIABILITY, IN CONNECTION WITH OR ARISING OUT OF THIS AGREEMENT OR THE USE OF
|
||||
THE LICENSED MATERIALS REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO,
|
||||
COST OF REMOVAL OR REINSTALLATION, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF
|
||||
DATA, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF USE OR
|
||||
INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S OR ITS LICENSORS' AGGREGATE
|
||||
LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF YOUR USE OF THE LICENSED
|
||||
MATERIALS EXCEED FIVE HUNDRED U.S. DOLLARS (US$500).
|
||||
|
||||
Because some jurisdictions do not allow the exclusion or limitation of
|
||||
incidental or consequential damages or limitation on how long an implied
|
||||
warranty lasts, the above limitations or exclusions may not apply to you.
|
||||
|
||||
7. Indemnification Disclaimer. YOU ACKNOWLEDGE AND AGREE THAT TI SHALL NOT BE
|
||||
LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY THIRD PARTY
|
||||
INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON YOUR MANUFACTURE, USE, OR
|
||||
DISTRIBUTION OF THE LICENSED MATERIALS OR YOUR MANUFACTURE, USE, OFFER FOR
|
||||
SALE, SALE, IMPORTATION OR DISTRIBUTION OF YOUR PRODUCTS THAT INCLUDE OR
|
||||
INCORPORATE THE LICENSED MATERIALS.
|
||||
|
||||
You will defend and indemnify TI in the event of claim, liability or costs
|
||||
(including reasonable attorney's fees related to Your use of the Licensed
|
||||
Materials) relating in any way to Your violation of the terms of the License
|
||||
Grants set forth in Section 1, or any other violation of other terms and
|
||||
conditions of this Agreement.
|
||||
|
||||
8. No Technical Support. TI and its licensors are under no obligation to
|
||||
install, maintain or support the Licensed Materials.
|
||||
|
||||
9. Notices. All notices to TI hereunder shall be delivered to Texas Instruments
|
||||
Incorporated, 12500 TI Boulevard, Mail Station 8638, Dallas, Texas 75243,
|
||||
Attention: Contracts Manager - Embedded Processing, with a copy to Texas
|
||||
Instruments Incorporated, 13588 N. Central Expressway, Mail Station 3999,
|
||||
Dallas, Texas 75243, Attention: Law Department - Embedded Processing. All
|
||||
notices shall be deemed served when received by TI.
|
||||
|
||||
10. Export Control. The Licensed Materials are subject to export control under
|
||||
the U.S. Commerce Department's Export Administration Regulations ("EAR").
|
||||
Unless prior authorization is obtained from the U.S. Commerce Department,
|
||||
neither you nor your subsidiaries shall export, re-export, or release, directly
|
||||
or indirectly (including, without limitation, by permitting the Licensed
|
||||
Materials to be downloaded), any technology, software, or software source code,
|
||||
received from TI, or export, directly or indirectly, any direct product of such
|
||||
technology, software, or software source code, to any person, destination or
|
||||
country to which the export, re-export, or release of the technology, software,
|
||||
or software source code, or direct product is prohibited by the EAR. You
|
||||
represent and warrant that you (i) are not located in, or under the control of,
|
||||
a national or resident of Cuba, Iran, North Korea, Sudan and Syria or any other
|
||||
country subject to a U.S. goods embargo; (ii) are not on the U.S. Treasury
|
||||
Department's List of Specially Designated Nationals or the U.S. Commerce
|
||||
Department's Denied Persons List or Entity List; and (iii) will not use the
|
||||
Licensed Materials or transfer the Licensed Materials for use in any military,
|
||||
nuclear, chemical or biological weapons, or missile technology end-uses. Any
|
||||
software export classification made by TI shall not be construed as a
|
||||
representation or warranty regarding the proper export classification for such
|
||||
software or whether an export license or other documentation is required for
|
||||
the exportation of such software.
|
||||
|
||||
11. Governing Law and Severability; Waiver. This Agreement will be governed by
|
||||
and interpreted in accordance with the laws of the State of Texas, without
|
||||
reference to conflict of laws principles. If for any reason a court of
|
||||
competent jurisdiction finds any provision of the Agreement to be
|
||||
unenforceable, that provision will be enforced to the maximum extent possible
|
||||
to effectuate the intent of the parties, and the remainder of the Agreement
|
||||
shall continue in full force and effect. This Agreement shall not be governed
|
||||
by the United Nations Convention on Contracts for the International Sale of
|
||||
Goods, or by the Uniform Computer Information Transactions Act (UCITA). The
|
||||
parties agree that non-exclusive jurisdiction for any dispute arising out of or
|
||||
relating to this Agreement lies within the courts located in the State of
|
||||
Texas. Notwithstanding the foregoing, any judgment may be enforced in any
|
||||
United States or foreign court, and either party may seek injunctive relief in
|
||||
any United States or foreign court. Failure by TI to enforce any provision of
|
||||
this Agreement shall not be deemed a waiver of future enforcement of that or
|
||||
any other provision in this Agreement or any other agreement that may be in
|
||||
place between the parties.
|
||||
|
||||
12. PRC Provisions. If you are located in the People's Republic of China
|
||||
("PRC") or if the Licensed Materials will be sent to the PRC, the following
|
||||
provisions shall apply:
|
||||
|
||||
a. Registration Requirements. You shall be solely responsible for performing
|
||||
all acts and obtaining all approvals that may be required in connection with
|
||||
this Agreement by the government of the PRC, including but not limited to
|
||||
registering pursuant to, and otherwise complying with, the PRC Measures on the
|
||||
Administration of Software Products, Management Regulations on Technology
|
||||
Import-Export, and Technology Import and Export Contract Registration
|
||||
Management Rules. Upon receipt of such approvals from the government
|
||||
authorities, you shall forward evidence of all such approvals to TI for its
|
||||
records. In the event that you fail to obtain any such approval or
|
||||
registration, you shall be solely responsible for any and all losses, damages
|
||||
or costs resulting therefrom, and shall indemnify TI for all such losses,
|
||||
damages or costs.
|
||||
|
||||
b. Governing Language. This Agreement is written and executed in the English
|
||||
language and shall be authoritative and controlling, whether or not translated
|
||||
into a language other than English to comply with law or for reference
|
||||
purposes. If a translation of this Agreement is required for any purpose,
|
||||
including but not limited to registration of the Agreement pursuant to any
|
||||
governmental laws, regulations or rules, you shall be solely responsible for
|
||||
creating such translation.
|
||||
|
||||
13. Contingencies. TI shall not be in breach of this Agreement and shall not be
|
||||
liable for any non-performance or delay in performance if such non-performance
|
||||
or delay is due to a force majeure event or other circumstances beyond TI's
|
||||
reasonable control.
|
||||
|
||||
14. Entire Agreement. This is the entire agreement between you and TI and this
|
||||
Agreement supersedes any prior agreement between the parties related to the
|
||||
subject matter of this Agreement. Notwithstanding the foregoing, any signed and
|
||||
effective software license agreement relating to the subject matter hereof and
|
||||
stating expressly that such agreement shall control regardless of any
|
||||
subsequent click-wrap, shrink-wrap or web-wrap, shall supersede the terms of
|
||||
this Agreement. No amendment or modification of this Agreement will be
|
||||
effective unless in writing and signed by a duly authorized representative of
|
||||
TI. You hereby warrant and represent that you have obtained all authorizations
|
||||
and other applicable consents required empowering you to enter into this
|
||||
Agreement.
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,290 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// adc.h - ADC headers for using the ADC driver functions.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_ADC_H__
|
||||
#define __DRIVERLIB_ADC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceConfigure as the ui32Trigger
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
|
||||
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
|
||||
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
|
||||
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
|
||||
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
|
||||
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
|
||||
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
|
||||
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
|
||||
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
|
||||
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceStepConfigure as the ui32Config
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
|
||||
#define ADC_CTL_IE 0x00000040 // Interrupt enable
|
||||
#define ADC_CTL_END 0x00000020 // Sequence end select
|
||||
#define ADC_CTL_D 0x00000010 // Differential select
|
||||
#define ADC_CTL_CH0 0x00000000 // Input channel 0
|
||||
#define ADC_CTL_CH1 0x00000001 // Input channel 1
|
||||
#define ADC_CTL_CH2 0x00000002 // Input channel 2
|
||||
#define ADC_CTL_CH3 0x00000003 // Input channel 3
|
||||
#define ADC_CTL_CH4 0x00000004 // Input channel 4
|
||||
#define ADC_CTL_CH5 0x00000005 // Input channel 5
|
||||
#define ADC_CTL_CH6 0x00000006 // Input channel 6
|
||||
#define ADC_CTL_CH7 0x00000007 // Input channel 7
|
||||
#define ADC_CTL_CH8 0x00000008 // Input channel 8
|
||||
#define ADC_CTL_CH9 0x00000009 // Input channel 9
|
||||
#define ADC_CTL_CH10 0x0000000A // Input channel 10
|
||||
#define ADC_CTL_CH11 0x0000000B // Input channel 11
|
||||
#define ADC_CTL_CH12 0x0000000C // Input channel 12
|
||||
#define ADC_CTL_CH13 0x0000000D // Input channel 13
|
||||
#define ADC_CTL_CH14 0x0000000E // Input channel 14
|
||||
#define ADC_CTL_CH15 0x0000000F // Input channel 15
|
||||
#define ADC_CTL_CH16 0x00000100 // Input channel 16
|
||||
#define ADC_CTL_CH17 0x00000101 // Input channel 17
|
||||
#define ADC_CTL_CH18 0x00000102 // Input channel 18
|
||||
#define ADC_CTL_CH19 0x00000103 // Input channel 19
|
||||
#define ADC_CTL_CH20 0x00000104 // Input channel 20
|
||||
#define ADC_CTL_CH21 0x00000105 // Input channel 21
|
||||
#define ADC_CTL_CH22 0x00000106 // Input channel 22
|
||||
#define ADC_CTL_CH23 0x00000107 // Input channel 23
|
||||
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
|
||||
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
|
||||
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
|
||||
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
|
||||
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
|
||||
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
|
||||
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
|
||||
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCComparatorConfigure as part of the
|
||||
// ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
|
||||
#define ADC_COMP_TRIG_LOW_ALWAYS \
|
||||
0x00001000 // Trigger Low Always
|
||||
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
|
||||
#define ADC_COMP_TRIG_LOW_HALWAYS \
|
||||
0x00001200 // Trigger Low Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
|
||||
#define ADC_COMP_TRIG_MID_ALWAYS \
|
||||
0x00001400 // Trigger Mid Always
|
||||
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
|
||||
#define ADC_COMP_TRIG_HIGH_ALWAYS \
|
||||
0x00001C00 // Trigger High Always
|
||||
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
|
||||
#define ADC_COMP_TRIG_HIGH_HALWAYS \
|
||||
0x00001E00 // Trigger High Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_HIGH_HONCE \
|
||||
0x00001F00 // Trigger High Once (Hysteresis)
|
||||
|
||||
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
|
||||
#define ADC_COMP_INT_LOW_ALWAYS \
|
||||
0x00000010 // Interrupt Low Always
|
||||
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
|
||||
#define ADC_COMP_INT_LOW_HALWAYS \
|
||||
0x00000012 // Interrupt Low Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
|
||||
#define ADC_COMP_INT_MID_ALWAYS \
|
||||
0x00000014 // Interrupt Mid Always
|
||||
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
|
||||
#define ADC_COMP_INT_HIGH_ALWAYS \
|
||||
0x0000001C // Interrupt High Always
|
||||
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
|
||||
#define ADC_COMP_INT_HIGH_HALWAYS \
|
||||
0x0000001E // Interrupt High Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_HIGH_HONCE \
|
||||
0x0000001F // Interrupt High Once (Hysteresis)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be used to modify the sequence number passed to
|
||||
// ADCProcessorTrigger in order to get cross-module synchronous processor
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
|
||||
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and
|
||||
// returned from ADCPhaseDelayGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_PHASE_0 0x00000000 // 0 degrees
|
||||
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
|
||||
#define ADC_PHASE_45 0x00000002 // 45 degrees
|
||||
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
|
||||
#define ADC_PHASE_90 0x00000004 // 90 degrees
|
||||
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
|
||||
#define ADC_PHASE_135 0x00000006 // 135 degrees
|
||||
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
|
||||
#define ADC_PHASE_180 0x00000008 // 180 degrees
|
||||
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
|
||||
#define ADC_PHASE_225 0x0000000A // 225 degrees
|
||||
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
|
||||
#define ADC_PHASE_270 0x0000000C // 270 degrees
|
||||
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
|
||||
#define ADC_PHASE_315 0x0000000E // 315 degrees
|
||||
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCReferenceSet as the ui32Ref parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_REF_INT 0x00000000 // Internal reference
|
||||
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
|
||||
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
|
||||
// ADCIntClearEx() and ADCIntStatusEx().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_INT_SS0 0x00000001
|
||||
#define ADC_INT_SS1 0x00000002
|
||||
#define ADC_INT_SS2 0x00000004
|
||||
#define ADC_INT_SS3 0x00000008
|
||||
#define ADC_INT_DMA_SS0 0x00000100
|
||||
#define ADC_INT_DMA_SS1 0x00000200
|
||||
#define ADC_INT_DMA_SS2 0x00000400
|
||||
#define ADC_INT_DMA_SS3 0x00000800
|
||||
#define ADC_INT_DCON_SS0 0x00010000
|
||||
#define ADC_INT_DCON_SS1 0x00020000
|
||||
#define ADC_INT_DCON_SS2 0x00040000
|
||||
#define ADC_INT_DCON_SS3 0x00080000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum,
|
||||
bool bMasked);
|
||||
extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
|
||||
uint32_t ui32Trigger, uint32_t ui32Priority);
|
||||
extern void ADCSequenceStepConfigure(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum,
|
||||
uint32_t ui32Step, uint32_t ui32Config);
|
||||
extern int32_t ADCSequenceOverflow(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern void ADCSequenceOverflowClear(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern int32_t ADCSequenceUnderflow(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern void ADCSequenceUnderflowClear(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
|
||||
uint32_t *pui32Buffer);
|
||||
extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum);
|
||||
extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum,
|
||||
uint32_t ui32Factor);
|
||||
extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum,
|
||||
uint32_t ui32Step,
|
||||
uint32_t ui32Config);
|
||||
extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum,
|
||||
uint32_t *pui32Buffer,
|
||||
uint32_t ui32Count);
|
||||
extern void ADCHardwareOversampleConfigure(uint32_t ui32Base,
|
||||
uint32_t ui32Factor);
|
||||
extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
uint32_t ui32Config);
|
||||
extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
uint32_t ui32LowRef, uint32_t ui32HighRef);
|
||||
extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
bool bTrigger, bool bInterrupt);
|
||||
extern void ADCComparatorIntDisable(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern void ADCComparatorIntEnable(uint32_t ui32Base,
|
||||
uint32_t ui32SequenceNum);
|
||||
extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base);
|
||||
extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status);
|
||||
extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref);
|
||||
extern uint32_t ADCReferenceGet(uint32_t ui32Base);
|
||||
extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase);
|
||||
extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_ADC_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,451 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// can.h - Defines and Macros for the CAN controller.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_CAN_H__
|
||||
#define __DRIVERLIB_CAN_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup can_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Miscellaneous defines for Message ID Types
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These are the flags used by the tCANMsgObject.ui32Flags value when calling
|
||||
// the CANMessageSet() and CANMessageGet() functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//
|
||||
//! This indicates that transmit interrupts should be enabled, or are enabled.
|
||||
//
|
||||
#define MSG_OBJ_TX_INT_ENABLE 0x00000001
|
||||
|
||||
//
|
||||
//! This indicates that receive interrupts should be enabled, or are
|
||||
//! enabled.
|
||||
//
|
||||
#define MSG_OBJ_RX_INT_ENABLE 0x00000002
|
||||
|
||||
//
|
||||
//! This indicates that a message object will use or is using an extended
|
||||
//! identifier.
|
||||
//
|
||||
#define MSG_OBJ_EXTENDED_ID 0x00000004
|
||||
|
||||
//
|
||||
//! This indicates that a message object will use or is using filtering
|
||||
//! based on the object's message identifier.
|
||||
//
|
||||
#define MSG_OBJ_USE_ID_FILTER 0x00000008
|
||||
|
||||
//
|
||||
//! This indicates that new data was available in the message object.
|
||||
//
|
||||
#define MSG_OBJ_NEW_DATA 0x00000080
|
||||
|
||||
//
|
||||
//! This indicates that data was lost since this message object was last
|
||||
//! read.
|
||||
//
|
||||
#define MSG_OBJ_DATA_LOST 0x00000100
|
||||
|
||||
//
|
||||
//! This indicates that a message object will use or is using filtering
|
||||
//! based on the direction of the transfer. If the direction filtering is
|
||||
//! used, then ID filtering must also be enabled.
|
||||
//
|
||||
#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER)
|
||||
|
||||
//
|
||||
//! This indicates that a message object will use or is using message
|
||||
//! identifier filtering based on the extended identifier. If the extended
|
||||
//! identifier filtering is used, then ID filtering must also be enabled.
|
||||
//
|
||||
#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER)
|
||||
|
||||
//
|
||||
//! This indicates that a message object is a remote frame.
|
||||
//
|
||||
#define MSG_OBJ_REMOTE_FRAME 0x00000040
|
||||
|
||||
//
|
||||
//! This indicates that this message object is part of a FIFO structure and
|
||||
//! not the final message object in a FIFO.
|
||||
//
|
||||
#define MSG_OBJ_FIFO 0x00000200
|
||||
|
||||
//
|
||||
//! This indicates that a message object has no flags set.
|
||||
//
|
||||
#define MSG_OBJ_NO_FLAGS 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This define is used with the flag values to allow checking only status
|
||||
//! flags and not configuration flags.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! The structure used for encapsulating all the items associated with a CAN
|
||||
//! message object in the CAN controller.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef struct
|
||||
{
|
||||
//
|
||||
//! The CAN message identifier used for 11 or 29 bit identifiers.
|
||||
//
|
||||
uint32_t ui32MsgID;
|
||||
|
||||
//
|
||||
//! The message identifier mask used when identifier filtering is enabled.
|
||||
//
|
||||
uint32_t ui32MsgIDMask;
|
||||
|
||||
//
|
||||
//! This value holds various status flags and settings specified by
|
||||
//! tCANObjFlags.
|
||||
//
|
||||
uint32_t ui32Flags;
|
||||
|
||||
//
|
||||
//! This value is the number of bytes of data in the message object.
|
||||
//
|
||||
uint32_t ui32MsgLen;
|
||||
|
||||
//
|
||||
//! This is a pointer to the message object's data.
|
||||
//
|
||||
uint8_t *pui8MsgData;
|
||||
}
|
||||
tCANMsgObject;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This structure is used for encapsulating the values associated with setting
|
||||
//! up the bit timing for a CAN controller. The structure is used when calling
|
||||
//! the CANGetBitTiming and CANSetBitTiming functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef struct
|
||||
{
|
||||
//
|
||||
//! This value holds the sum of the Synchronization, Propagation, and Phase
|
||||
//! Buffer 1 segments, measured in time quanta. The valid values for this
|
||||
//! setting range from 2 to 16.
|
||||
//
|
||||
uint32_t ui32SyncPropPhase1Seg;
|
||||
|
||||
//
|
||||
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
|
||||
//! values for this setting range from 1 to 8.
|
||||
//
|
||||
uint32_t ui32Phase2Seg;
|
||||
|
||||
//
|
||||
//! This value holds the Resynchronization Jump Width in time quanta. The
|
||||
//! valid values for this setting range from 1 to 4.
|
||||
//
|
||||
uint32_t ui32SJW;
|
||||
|
||||
//
|
||||
//! This value holds the CAN_CLK divider used to determine time quanta.
|
||||
//! The valid values for this setting range from 1 to 1023.
|
||||
//
|
||||
uint32_t ui32QuantumPrescaler;
|
||||
}
|
||||
tCANBitClkParms;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This data type is used to identify the interrupt status register. This is
|
||||
//! used when calling the CANIntStatus() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//
|
||||
//! Read the CAN interrupt status information.
|
||||
//
|
||||
CAN_INT_STS_CAUSE,
|
||||
|
||||
//
|
||||
//! Read a message object's interrupt status.
|
||||
//
|
||||
CAN_INT_STS_OBJECT
|
||||
}
|
||||
tCANIntStsReg;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This data type is used to identify which of several status registers to
|
||||
//! read when calling the CANStatusGet() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//
|
||||
//! Read the full CAN controller status.
|
||||
//
|
||||
CAN_STS_CONTROL,
|
||||
|
||||
//
|
||||
//! Read the full 32-bit mask of message objects with a transmit request
|
||||
//! set.
|
||||
//
|
||||
CAN_STS_TXREQUEST,
|
||||
|
||||
//
|
||||
//! Read the full 32-bit mask of message objects with new data available.
|
||||
//
|
||||
CAN_STS_NEWDAT,
|
||||
|
||||
//
|
||||
//! Read the full 32-bit mask of message objects that are enabled.
|
||||
//
|
||||
CAN_STS_MSGVAL
|
||||
}
|
||||
tCANStsReg;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These definitions are used to specify interrupt sources to CANIntEnable()
|
||||
// and CANIntDisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This flag is used to allow a CAN controller to generate error
|
||||
//! interrupts.
|
||||
//
|
||||
#define CAN_INT_ERROR 0x00000008
|
||||
|
||||
//
|
||||
//! This flag is used to allow a CAN controller to generate status
|
||||
//! interrupts.
|
||||
//
|
||||
#define CAN_INT_STATUS 0x00000004
|
||||
|
||||
//
|
||||
//! This flag is used to allow a CAN controller to generate any CAN
|
||||
//! interrupts. If this is not set, then no interrupts will be generated
|
||||
//! by the CAN controller.
|
||||
//
|
||||
#define CAN_INT_MASTER 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This definition is used to determine the type of message object that will
|
||||
//! be set up via a call to the CANMessageSet() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
//
|
||||
//! Transmit message object.
|
||||
//
|
||||
MSG_OBJ_TYPE_TX,
|
||||
|
||||
//
|
||||
//! Transmit remote request message object
|
||||
//
|
||||
MSG_OBJ_TYPE_TX_REMOTE,
|
||||
|
||||
//
|
||||
//! Receive message object.
|
||||
//
|
||||
MSG_OBJ_TYPE_RX,
|
||||
|
||||
//
|
||||
//! Receive remote request message object.
|
||||
//
|
||||
MSG_OBJ_TYPE_RX_REMOTE,
|
||||
|
||||
//
|
||||
//! Remote frame receive remote, with auto-transmit message object.
|
||||
//
|
||||
MSG_OBJ_TYPE_RXTX_REMOTE
|
||||
}
|
||||
tMsgObjType;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following enumeration contains all error or status indicators that can
|
||||
// be returned when calling the CANStatusGet() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! CAN controller has entered a Bus Off state.
|
||||
//
|
||||
#define CAN_STATUS_BUS_OFF 0x00000080
|
||||
|
||||
//
|
||||
//! CAN controller error level has reached warning level.
|
||||
//
|
||||
#define CAN_STATUS_EWARN 0x00000040
|
||||
|
||||
//
|
||||
//! CAN controller error level has reached error passive level.
|
||||
//
|
||||
#define CAN_STATUS_EPASS 0x00000020
|
||||
|
||||
//
|
||||
//! A message was received successfully since the last read of this status.
|
||||
//
|
||||
#define CAN_STATUS_RXOK 0x00000010
|
||||
|
||||
//
|
||||
//! A message was transmitted successfully since the last read of this
|
||||
//! status.
|
||||
//
|
||||
#define CAN_STATUS_TXOK 0x00000008
|
||||
|
||||
//
|
||||
//! This is the mask for the last error code field.
|
||||
//
|
||||
#define CAN_STATUS_LEC_MSK 0x00000007
|
||||
|
||||
//
|
||||
//! There was no error.
|
||||
//
|
||||
#define CAN_STATUS_LEC_NONE 0x00000000
|
||||
|
||||
//
|
||||
//! A bit stuffing error has occurred.
|
||||
//
|
||||
#define CAN_STATUS_LEC_STUFF 0x00000001
|
||||
|
||||
//
|
||||
//! A formatting error has occurred.
|
||||
//
|
||||
#define CAN_STATUS_LEC_FORM 0x00000002
|
||||
|
||||
//
|
||||
//! An acknowledge error has occurred.
|
||||
//
|
||||
#define CAN_STATUS_LEC_ACK 0x00000003
|
||||
|
||||
//
|
||||
//! The bus remained a bit level of 1 for longer than is allowed.
|
||||
//
|
||||
#define CAN_STATUS_LEC_BIT1 0x00000004
|
||||
|
||||
//
|
||||
//! The bus remained a bit level of 0 for longer than is allowed.
|
||||
//
|
||||
#define CAN_STATUS_LEC_BIT0 0x00000005
|
||||
|
||||
//
|
||||
//! A CRC error has occurred.
|
||||
//
|
||||
#define CAN_STATUS_LEC_CRC 0x00000006
|
||||
|
||||
//
|
||||
//! This is the mask for the CAN Last Error Code (LEC).
|
||||
//
|
||||
#define CAN_STATUS_LEC_MASK 0x00000007
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
|
||||
extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
|
||||
extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
|
||||
uint32_t ui32BitRate);
|
||||
extern void CANDisable(uint32_t ui32Base);
|
||||
extern void CANEnable(uint32_t ui32Base);
|
||||
extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
|
||||
uint32_t *pui32TxCount);
|
||||
extern void CANInit(uint32_t ui32Base);
|
||||
extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
|
||||
extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
|
||||
extern void CANIntUnregister(uint32_t ui32Base);
|
||||
extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
|
||||
extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
|
||||
tCANMsgObject *psMsgObject, bool bClrPendingInt);
|
||||
extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
|
||||
tCANMsgObject *psMsgObject, tMsgObjType eMsgType);
|
||||
extern bool CANRetryGet(uint32_t ui32Base);
|
||||
extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
|
||||
extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_CAN_H__
|
|
@ -0,0 +1,452 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// comp.c - Driver for the analog comparator.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup comp_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_comp.h"
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/comp.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Configures a comparator.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator to configure.
|
||||
//! \param ui32Config is the configuration of the comparator.
|
||||
//!
|
||||
//! This function configures a comparator. The \e ui32Config parameter is the
|
||||
//! result of a logical OR operation between the \b COMP_TRIG_xxx,
|
||||
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
|
||||
//!
|
||||
//! The \b COMP_TRIG_xxx term can take on the following values:
|
||||
//!
|
||||
//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
|
||||
//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
|
||||
//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
|
||||
//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
|
||||
//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
|
||||
//! high.
|
||||
//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
|
||||
//! or high.
|
||||
//!
|
||||
//! The \b COMP_INT_xxx term can take on the following values:
|
||||
//!
|
||||
//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
|
||||
//! high.
|
||||
//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
|
||||
//! low.
|
||||
//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
|
||||
//! low.
|
||||
//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
|
||||
//! high.
|
||||
//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
|
||||
//! low or high.
|
||||
//!
|
||||
//! The \b COMP_ASRCP_xxx term can take on the following values:
|
||||
//!
|
||||
//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
|
||||
//! voltage.
|
||||
//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
|
||||
//! the same as \b COMP_ASRCP_PIN for the comparator 0).
|
||||
//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
|
||||
//! reference voltage.
|
||||
//!
|
||||
//! The \b COMP_OUTPUT_xxx term can take on the following values:
|
||||
//!
|
||||
//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
|
||||
//! to a device pin.
|
||||
//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
|
||||
//! a device pin.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Configure this comparator.
|
||||
//
|
||||
HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the internal reference voltage.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Ref is the desired reference voltage.
|
||||
//!
|
||||
//! This function sets the internal reference voltage value. The voltage is
|
||||
//! specified as one of the following values:
|
||||
//!
|
||||
//! - \b COMP_REF_OFF to turn off the reference voltage
|
||||
//! - \b COMP_REF_0V to set the reference voltage to 0 V
|
||||
//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
|
||||
//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
|
||||
//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
|
||||
//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
|
||||
//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
|
||||
//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
|
||||
//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
|
||||
//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
|
||||
//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
|
||||
//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
|
||||
//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
|
||||
//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
|
||||
//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
|
||||
//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
|
||||
//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
|
||||
//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
|
||||
//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
|
||||
//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
|
||||
//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
|
||||
//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
|
||||
//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
|
||||
//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
|
||||
//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
|
||||
//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
|
||||
//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
|
||||
//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
|
||||
//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
|
||||
//
|
||||
// Set the voltage reference voltage as requested.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current comparator output value.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//!
|
||||
//! This function retrieves the current value of the comparator output.
|
||||
//!
|
||||
//! \return Returns \b true if the comparator output is high and \b false if
|
||||
//! the comparator output is low.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Return the appropriate value based on the comparator's present output
|
||||
// value.
|
||||
//
|
||||
if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) &
|
||||
COMP_ACSTAT0_OVAL)
|
||||
{
|
||||
return(true);
|
||||
}
|
||||
else
|
||||
{
|
||||
return(false);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the comparator interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! comparator interrupt occurs.
|
||||
//!
|
||||
//! This function sets the handler to be called when the comparator interrupt
|
||||
//! occurs and enables the interrupt in the interrupt controller. It is the
|
||||
//! interrupt handler's responsibility to clear the interrupt source via
|
||||
//! ComparatorIntClear().
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
void (*pfnHandler)(void))
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Register the interrupt handler, returning an error if an error occurs.
|
||||
//
|
||||
IntRegister(INT_COMP0_BLIZZARD + ui32Comp, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the interrupt in the interrupt controller.
|
||||
//
|
||||
IntEnable(INT_COMP0_BLIZZARD + ui32Comp);
|
||||
|
||||
//
|
||||
// Enable the comparator interrupt.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters an interrupt handler for a comparator interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//!
|
||||
//! This function clears the handler to be called when a comparator interrupt
|
||||
//! occurs. This function also masks off the interrupt in the interrupt
|
||||
//! controller so that the interrupt handler no longer is called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Disable the comparator interrupt.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
|
||||
|
||||
//
|
||||
// Disable the interrupt in the interrupt controller.
|
||||
//
|
||||
IntDisable(INT_COMP0_BLIZZARD + ui32Comp);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(INT_COMP0_BLIZZARD + ui32Comp);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the comparator interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//!
|
||||
//! This function enables generation of an interrupt from the specified
|
||||
//! comparator. Only enabled comparator interrupts can be reflected
|
||||
//! to the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Enable the comparator interrupt.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the comparator interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//!
|
||||
//! This function disables generation of an interrupt from the specified
|
||||
//! comparator. Only enabled comparator interrupts can be reflected
|
||||
//! to the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Disable the comparator interrupt.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current interrupt status.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//! \param bMasked is \b false if the raw interrupt status is required and
|
||||
//! \b true if the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the interrupt status for the comparator. Either the
|
||||
//! raw or the masked interrupt status can be returned.
|
||||
//!
|
||||
//! \return \b true if the interrupt is asserted and \b false if it is not
|
||||
//! asserted.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true :
|
||||
false);
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true :
|
||||
false);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears a comparator interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the comparator module.
|
||||
//! \param ui32Comp is the index of the comparator.
|
||||
//!
|
||||
//! The comparator interrupt is cleared, so that it no longer asserts. This
|
||||
//! fucntion must be called in the interrupt handler to keep the handler from
|
||||
//! being called again immediately upon exit. Note that for a level-triggered
|
||||
//! interrupt, the interrupt cannot be cleared until it stops asserting.
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Base == COMP_BASE);
|
||||
ASSERT(ui32Comp < 3);
|
||||
|
||||
//
|
||||
// Clear the interrupt.
|
||||
//
|
||||
HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,141 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// comp.h - Prototypes for the analog comparator driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_COMP_H__
|
||||
#define __DRIVERLIB_COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorConfigure() as the ui32Config
|
||||
// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and
|
||||
// so on), one of the values may be selected and combined together with values
|
||||
// from the other groups via a logical OR.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
|
||||
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
|
||||
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
|
||||
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
|
||||
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
|
||||
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
|
||||
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
|
||||
#define COMP_INT_LOW 0x00000000 // Interrupt when low
|
||||
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
|
||||
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
|
||||
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
|
||||
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
|
||||
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
|
||||
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
|
||||
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
|
||||
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
|
||||
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
|
||||
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
|
||||
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
|
||||
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
|
||||
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
|
||||
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
|
||||
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
|
||||
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
|
||||
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
|
||||
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
|
||||
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
|
||||
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
|
||||
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
|
||||
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
|
||||
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
|
||||
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
|
||||
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
|
||||
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
|
||||
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
|
||||
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
|
||||
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
|
||||
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
|
||||
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
|
||||
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
|
||||
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
|
||||
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
|
||||
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
uint32_t ui32Config);
|
||||
extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref);
|
||||
extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp);
|
||||
extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp);
|
||||
extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp);
|
||||
extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp);
|
||||
extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp,
|
||||
bool bMasked);
|
||||
extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_COMP_H__
|
|
@ -0,0 +1,457 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// cpu.c - Instruction wrappers for special CPU instructions needed by the
|
||||
// drivers.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "driverlib/cpulib.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
|
||||
// on entry.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
uint32_t __attribute__((naked))
|
||||
CPUcpsid(void)
|
||||
{
|
||||
uint32_t ui32Ret;
|
||||
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsid i\n"
|
||||
" bx lr\n"
|
||||
: "=r" (ui32Ret));
|
||||
|
||||
//
|
||||
// The return is handled in the inline assembly, but the compiler will
|
||||
// still complain if there is not an explicit return here (despite the fact
|
||||
// that this does not result in any code being produced because of the
|
||||
// naked attribute).
|
||||
//
|
||||
return(ui32Ret);
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
uint32_t
|
||||
CPUcpsid(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsid i\n");
|
||||
|
||||
//
|
||||
// "Warning[Pe940]: missing return statement at end of non-void function"
|
||||
// is suppressed here to avoid putting a "bx lr" in the inline assembly
|
||||
// above and a superfluous return statement here.
|
||||
//
|
||||
#pragma diag_suppress=Pe940
|
||||
}
|
||||
#pragma diag_default=Pe940
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm uint32_t
|
||||
CPUcpsid(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
mrs r0, PRIMASK;
|
||||
cpsid i;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
uint32_t
|
||||
CPUcpsid(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsid i\n"
|
||||
" bx lr\n");
|
||||
|
||||
//
|
||||
// The following keeps the compiler happy, because it wants to see a
|
||||
// return value from this function. It will generate code to return
|
||||
// a zero. However, the real return is the "bx lr" above, so the
|
||||
// return(0) is never executed and the function returns with the value
|
||||
// you expect in R0.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function returning the state of PRIMASK (indicating whether
|
||||
// interrupts are enabled or disabled).
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
uint32_t __attribute__((naked))
|
||||
CPUprimask(void)
|
||||
{
|
||||
uint32_t ui32Ret;
|
||||
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" bx lr\n"
|
||||
: "=r" (ui32Ret));
|
||||
|
||||
//
|
||||
// The return is handled in the inline assembly, but the compiler will
|
||||
// still complain if there is not an explicit return here (despite the fact
|
||||
// that this does not result in any code being produced because of the
|
||||
// naked attribute).
|
||||
//
|
||||
return(ui32Ret);
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
uint32_t
|
||||
CPUprimask(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n");
|
||||
|
||||
//
|
||||
// "Warning[Pe940]: missing return statement at end of non-void function"
|
||||
// is suppressed here to avoid putting a "bx lr" in the inline assembly
|
||||
// above and a superfluous return statement here.
|
||||
//
|
||||
#pragma diag_suppress=Pe940
|
||||
}
|
||||
#pragma diag_default=Pe940
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm uint32_t
|
||||
CPUprimask(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
mrs r0, PRIMASK;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
uint32_t
|
||||
CPUprimask(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and disable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" bx lr\n");
|
||||
|
||||
//
|
||||
// The following keeps the compiler happy, because it wants to see a
|
||||
// return value from this function. It will generate code to return
|
||||
// a zero. However, the real return is the "bx lr" above, so the
|
||||
// return(0) is never executed and the function returns with the value
|
||||
// you expect in R0.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
|
||||
// on entry.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
uint32_t __attribute__((naked))
|
||||
CPUcpsie(void)
|
||||
{
|
||||
uint32_t ui32Ret;
|
||||
|
||||
//
|
||||
// Read PRIMASK and enable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsie i\n"
|
||||
" bx lr\n"
|
||||
: "=r" (ui32Ret));
|
||||
|
||||
//
|
||||
// The return is handled in the inline assembly, but the compiler will
|
||||
// still complain if there is not an explicit return here (despite the fact
|
||||
// that this does not result in any code being produced because of the
|
||||
// naked attribute).
|
||||
//
|
||||
return(ui32Ret);
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
uint32_t
|
||||
CPUcpsie(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and enable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsie i\n");
|
||||
|
||||
//
|
||||
// "Warning[Pe940]: missing return statement at end of non-void function"
|
||||
// is suppressed here to avoid putting a "bx lr" in the inline assembly
|
||||
// above and a superfluous return statement here.
|
||||
//
|
||||
#pragma diag_suppress=Pe940
|
||||
}
|
||||
#pragma diag_default=Pe940
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm uint32_t
|
||||
CPUcpsie(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and enable interrupts.
|
||||
//
|
||||
mrs r0, PRIMASK;
|
||||
cpsie i;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
uint32_t
|
||||
CPUcpsie(void)
|
||||
{
|
||||
//
|
||||
// Read PRIMASK and enable interrupts.
|
||||
//
|
||||
__asm(" mrs r0, PRIMASK\n"
|
||||
" cpsie i\n"
|
||||
" bx lr\n");
|
||||
|
||||
//
|
||||
// The following keeps the compiler happy, because it wants to see a
|
||||
// return value from this function. It will generate code to return
|
||||
// a zero. However, the real return is the "bx lr" above, so the
|
||||
// return(0) is never executed and the function returns with the value
|
||||
// you expect in R0.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function for the WFI instruction.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
void __attribute__((naked))
|
||||
CPUwfi(void)
|
||||
{
|
||||
//
|
||||
// Wait for the next interrupt.
|
||||
//
|
||||
__asm(" wfi\n"
|
||||
" bx lr\n");
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
void
|
||||
CPUwfi(void)
|
||||
{
|
||||
//
|
||||
// Wait for the next interrupt.
|
||||
//
|
||||
__asm(" wfi\n");
|
||||
}
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm void
|
||||
CPUwfi(void)
|
||||
{
|
||||
//
|
||||
// Wait for the next interrupt.
|
||||
//
|
||||
wfi;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
void
|
||||
CPUwfi(void)
|
||||
{
|
||||
//
|
||||
// Wait for the next interrupt.
|
||||
//
|
||||
__asm(" wfi\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function for writing the BASEPRI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
void __attribute__((naked))
|
||||
CPUbasepriSet(uint32_t ui32NewBasepri)
|
||||
{
|
||||
//
|
||||
// Set the BASEPRI register
|
||||
//
|
||||
__asm(" msr BASEPRI, r0\n"
|
||||
" bx lr\n");
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
void
|
||||
CPUbasepriSet(uint32_t ui32NewBasepri)
|
||||
{
|
||||
//
|
||||
// Set the BASEPRI register
|
||||
//
|
||||
__asm(" msr BASEPRI, r0\n");
|
||||
}
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm void
|
||||
CPUbasepriSet(uint32_t ui32NewBasepri)
|
||||
{
|
||||
//
|
||||
// Set the BASEPRI register
|
||||
//
|
||||
msr BASEPRI, r0;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
void
|
||||
CPUbasepriSet(uint32_t ui32NewBasepri)
|
||||
{
|
||||
//
|
||||
// Set the BASEPRI register
|
||||
//
|
||||
__asm(" msr BASEPRI, r0\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrapper function for reading the BASEPRI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
|
||||
uint32_t __attribute__((naked))
|
||||
CPUbasepriGet(void)
|
||||
{
|
||||
uint32_t ui32Ret;
|
||||
|
||||
//
|
||||
// Read BASEPRI
|
||||
//
|
||||
__asm(" mrs r0, BASEPRI\n"
|
||||
" bx lr\n"
|
||||
: "=r" (ui32Ret));
|
||||
|
||||
//
|
||||
// The return is handled in the inline assembly, but the compiler will
|
||||
// still complain if there is not an explicit return here (despite the fact
|
||||
// that this does not result in any code being produced because of the
|
||||
// naked attribute).
|
||||
//
|
||||
return(ui32Ret);
|
||||
}
|
||||
#endif
|
||||
#if defined(ewarm)
|
||||
uint32_t
|
||||
CPUbasepriGet(void)
|
||||
{
|
||||
//
|
||||
// Read BASEPRI
|
||||
//
|
||||
__asm(" mrs r0, BASEPRI\n");
|
||||
|
||||
//
|
||||
// "Warning[Pe940]: missing return statement at end of non-void function"
|
||||
// is suppressed here to avoid putting a "bx lr" in the inline assembly
|
||||
// above and a superfluous return statement here.
|
||||
//
|
||||
#pragma diag_suppress=Pe940
|
||||
}
|
||||
#pragma diag_default=Pe940
|
||||
#endif
|
||||
#if defined(rvmdk) || defined(__ARMCC_VERSION)
|
||||
__asm uint32_t
|
||||
CPUbasepriGet(void)
|
||||
{
|
||||
//
|
||||
// Read BASEPRI
|
||||
//
|
||||
mrs r0, BASEPRI;
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#if defined(ccs)
|
||||
uint32_t
|
||||
CPUbasepriGet(void)
|
||||
{
|
||||
//
|
||||
// Read BASEPRI
|
||||
//
|
||||
__asm(" mrs r0, BASEPRI\n"
|
||||
" bx lr\n");
|
||||
|
||||
//
|
||||
// The following keeps the compiler happy, because it wants to see a
|
||||
// return value from this function. It will generate code to return
|
||||
// a zero. However, the real return is the "bx lr" above, so the
|
||||
// return(0) is never executed and the function returns with the value
|
||||
// you expect in R0.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,75 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// cpu.h - Prototypes for the CPU instruction wrapper functions.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_CPU_H__
|
||||
#define __DRIVERLIB_CPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint32_t CPUcpsid(void);
|
||||
extern uint32_t CPUcpsie(void);
|
||||
extern uint32_t CPUprimask(void);
|
||||
extern void CPUwfi(void);
|
||||
extern uint32_t CPUbasepriGet(void);
|
||||
extern void CPUbasepriSet(uint32_t ui32NewBasepri);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_CPU_H__
|
|
@ -0,0 +1,70 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// debug.h - Macros for assisting debug of the driver library.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_DEBUG_H__
|
||||
#define __DRIVERLIB_DEBUG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(char *pcFilename, uint32_t ui32Line);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) do \
|
||||
{ \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
} \
|
||||
while(0)
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_DEBUG_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,279 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// eeprom.h - Prototypes for the EEPROM driver.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_EEPROM_H__
|
||||
#define __DRIVERLIB_EEPROM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup eeprom_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values returned by EEPROMInit.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//
|
||||
//! This value may be returned from a call to EEPROMInit(). It indicates that
|
||||
//! no previous write operations were interrupted by a reset event and that the
|
||||
//! EEPROM peripheral is ready for use.
|
||||
//
|
||||
#define EEPROM_INIT_OK 0
|
||||
|
||||
//
|
||||
//! This value may be returned from a call to EEPROMInit(). It indicates that
|
||||
//! a previous data or protection write operation was interrupted by a reset
|
||||
//! event. The EEPROM peripheral has recovered its state but the last write
|
||||
//! operation may have been lost. The application must check the validity of
|
||||
//! data it has written and retry any writes as required.
|
||||
//
|
||||
#define EEPROM_INIT_RETRY 1
|
||||
|
||||
//
|
||||
//! This value may be returned from a call to EEPROMInit(). It indicates that
|
||||
//! a previous data or protection write operation was interrupted by a reset
|
||||
//! event and that the EEPROM peripheral was unable to clean up after the
|
||||
//! problem. This situation may be resolved with another reset or may be fatal
|
||||
//! depending upon the cause of the problem. For example, if the voltage to
|
||||
//! the part is unstable, retrying once the voltage has stabilized may clear
|
||||
//! the error.
|
||||
//
|
||||
#define EEPROM_INIT_ERROR 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Error indicators returned by various EEPROM API calls. These will be ORed
|
||||
// together into the final return code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//
|
||||
//! This return code bit indicates that the EEPROM programming state machine
|
||||
//! failed to write a value due to the voltage level dropping below that
|
||||
//! required for EEPROM programming. The operation may be retried once the
|
||||
//! voltage stabilizes.
|
||||
//
|
||||
#define EEPROM_RC_INVPL 0x00000100
|
||||
|
||||
//
|
||||
//! This return code bit indicates that an attempt was made to read from
|
||||
//! the EEPROM while a write operation was in progress.
|
||||
//
|
||||
#define EEPROM_RC_WRBUSY 0x00000020
|
||||
|
||||
//
|
||||
//! This return code bit indicates that an attempt was made to write a
|
||||
//! value but the destination permissions disallow write operations. This
|
||||
//! may be due to the destination block being locked, access protection set
|
||||
//! to prohibit writes or an attempt to write a password when one is already
|
||||
//! written.
|
||||
//
|
||||
#define EEPROM_RC_NOPERM 0x00000010
|
||||
|
||||
//
|
||||
//! This return code bit indicates that the EEPROM programming state machine
|
||||
//! is currently copying to or from the internal copy buffer to make room for
|
||||
//! a newly written value. It is provided as a status indicator and does not
|
||||
//! indicate an error.
|
||||
//
|
||||
#define EEPROM_RC_WKCOPY 0x00000008
|
||||
|
||||
//
|
||||
//! This return code bit indicates that the EEPROM programming state machine
|
||||
//! is currently erasing the internal copy buffer. It is provided as a
|
||||
//! status indicator and does not indicate an error.
|
||||
//
|
||||
#define EEPROM_RC_WKERASE 0x00000004
|
||||
|
||||
//
|
||||
//! This return code bit indicates that the EEPROM programming state machine
|
||||
//! is currently working. No new write operations should be attempted until
|
||||
//! this bit is clear.
|
||||
//
|
||||
#define EEPROM_RC_WORKING 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect
|
||||
// parameter, and returned by EEPROMBlockProtectGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//
|
||||
//! This bit may be ORed with the protection option passed to
|
||||
//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It
|
||||
//! restricts EEPROM access to threads running in supervisor mode and prevents
|
||||
//! access to an EEPROM block when the CPU is in user mode.
|
||||
//
|
||||
#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
|
||||
|
||||
//
|
||||
//! This value may be passed to EEPROMBlockProtectSet() or returned from
|
||||
//! EEPROMBlockProtectGet(). It indicates that the block should offer
|
||||
//! read/write access when no password is set or when a password is set and
|
||||
//! the block is unlocked, and read-only access when a password is set but
|
||||
//! the block is locked.
|
||||
//
|
||||
#define EEPROM_PROT_RW_LRO_URW 0x00000000
|
||||
|
||||
//
|
||||
//! This value may be passed to EEPROMBlockProtectSet() or returned from
|
||||
//! EEPROMBlockProtectGet(). It indicates that the block should offer neither
|
||||
//! read nor write access unless it is protected by a password and unlocked.
|
||||
//
|
||||
#define EEPROM_PROT_NA_LNA_URW 0x00000001
|
||||
|
||||
//
|
||||
//! This value may be passed to EEPROMBlockProtectSet() or returned from
|
||||
//! EEPROMBlockProtectGet(). It indicates that the block should offer
|
||||
//! read-only access when no password is set or when a password is set and the
|
||||
//! block is unlocked. When a password is set and the block is locked, neither
|
||||
//! read nor write access is permitted.
|
||||
//
|
||||
#define EEPROM_PROT_RO_LNA_URO 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
|
||||
//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
|
||||
//! signaled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_INT_PROGRAM 0x00000004
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the EEPROM block number containing a given offset address.
|
||||
//!
|
||||
//! \param ui32Addr is the linear, byte address of the EEPROM location whose
|
||||
//! block number is to be returned. This is a zero-based offset from the start
|
||||
//! of the EEPROM storage.
|
||||
//!
|
||||
//! This macro may be used to translate an EEPROM address offset into a
|
||||
//! block number suitable for use in any of the driver's block protection
|
||||
//! functions. The address provided is expressed as a byte offset from the
|
||||
//! base of the EEPROM.
|
||||
//!
|
||||
//! \return Returns the zero-based block number which contains the passed
|
||||
//! address.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the offset address of the first word in an EEPROM block.
|
||||
//!
|
||||
//! \param ui32Block is the index of the EEPROM block whose first word address
|
||||
//! is to be returned.
|
||||
//!
|
||||
//! This macro may be used to determine the address of the first word in a
|
||||
//! given EEPROM block. The address returned is expressed as a byte offset
|
||||
//! from the base of EEPROM storage.
|
||||
//!
|
||||
//! \return Returns the address of the first word in the given EEPROM block.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint32_t EEPROMInit(void);
|
||||
extern uint32_t EEPROMSizeGet(void);
|
||||
extern uint32_t EEPROMBlockCountGet(void);
|
||||
extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address,
|
||||
uint32_t ui32Count);
|
||||
extern uint32_t EEPROMProgram(uint32_t *pui32Data,
|
||||
uint32_t ui32Address,
|
||||
uint32_t ui32Count);
|
||||
extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data,
|
||||
uint32_t ui32Address);
|
||||
extern uint32_t EEPROMStatusGet(void);
|
||||
extern uint32_t EEPROMMassErase(void);
|
||||
extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block);
|
||||
extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block,
|
||||
uint32_t ui32Protect);
|
||||
extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block,
|
||||
uint32_t *pui32Password,
|
||||
uint32_t ui32Count);
|
||||
extern uint32_t EEPROMBlockLock(uint32_t ui32Block);
|
||||
extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block,
|
||||
uint32_t *pui32Password,
|
||||
uint32_t ui32Count);
|
||||
extern void EEPROMBlockHide(uint32_t ui32Block);
|
||||
extern void EEPROMIntEnable(uint32_t ui32IntFlags);
|
||||
extern void EEPROMIntDisable(uint32_t ui32IntFlags);
|
||||
extern uint32_t EEPROMIntStatus(bool bMasked);
|
||||
extern void EEPROMIntClear(uint32_t ui32IntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_EEPROM_H__
|
|
@ -0,0 +1,782 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// flash.c - Driver for programming the on-chip flash.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup flash_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_flash.h"
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/flashlib.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// An array that maps the specified memory bank to the appropriate Flash
|
||||
// Memory Protection Program Enable (FMPPE) register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32FMPPERegs[] =
|
||||
{
|
||||
FLASH_FMPPE0,
|
||||
FLASH_FMPPE1,
|
||||
FLASH_FMPPE2,
|
||||
FLASH_FMPPE3
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// An array that maps the specified memory bank to the appropriate Flash
|
||||
// Memory Protection Read Enable (FMPRE) register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32FMPRERegs[] =
|
||||
{
|
||||
FLASH_FMPRE0,
|
||||
FLASH_FMPRE1,
|
||||
FLASH_FMPRE2,
|
||||
FLASH_FMPRE3
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Erases a block of flash.
|
||||
//!
|
||||
//! \param ui32Address is the start address of the flash block to be erased.
|
||||
//!
|
||||
//! This function erases a 1-kB block of the on-chip flash. After erasing,
|
||||
//! the block is filled with 0xFF bytes. Read-only and execute-only blocks
|
||||
//! cannot be erased.
|
||||
//!
|
||||
//! This function does not return until the block has been erased.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if an invalid block address was
|
||||
//! specified or the block is write-protected.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibErase(uint32_t ui32Address)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(!(ui32Address & (FLASH_ERASE_SIZE - 1)));
|
||||
|
||||
//
|
||||
// Clear the flash access and error interrupts.
|
||||
//
|
||||
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
|
||||
FLASH_FCMISC_ERMISC);
|
||||
|
||||
//
|
||||
// Erase the block.
|
||||
//
|
||||
HWREG(FLASH_FMA) = ui32Address;
|
||||
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
|
||||
|
||||
//
|
||||
// Wait until the block has been erased.
|
||||
//
|
||||
while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Return an error if an access violation or erase error occurred.
|
||||
//
|
||||
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
|
||||
FLASH_FCRIS_ERRIS))
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Programs flash.
|
||||
//!
|
||||
//! \param pui32Data is a pointer to the data to be programmed.
|
||||
//! \param ui32Address is the starting address in flash to be programmed. Must
|
||||
//! be a multiple of four.
|
||||
//! \param ui32Count is the number of bytes to be programmed. Must be a
|
||||
//! multiple of four.
|
||||
//!
|
||||
//! This function programs a sequence of words into the on-chip flash.
|
||||
//! Each word in a page of flash can only be programmed one time between an
|
||||
//! erase of that page; programming a word multiple times results in an
|
||||
//! unpredictable value in that word of flash.
|
||||
//!
|
||||
//! Because the flash is programmed one word at a time, the starting address
|
||||
//! and byte count must both be multiples of four. It is up to the caller to
|
||||
//! verify the programmed contents, if such verification is required.
|
||||
//!
|
||||
//! This function does not return until the data has been programmed.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if a programming error is encountered.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(!(ui32Address & 3));
|
||||
ASSERT(!(ui32Count & 3));
|
||||
|
||||
//
|
||||
// Clear the flash access and error interrupts.
|
||||
//
|
||||
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
|
||||
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
|
||||
|
||||
//
|
||||
// Loop over the words to be programmed.
|
||||
//
|
||||
while(ui32Count)
|
||||
{
|
||||
//
|
||||
// Set the address of this block of words.
|
||||
//
|
||||
HWREG(FLASH_FMA) = ui32Address & ~(0x7f);
|
||||
|
||||
//
|
||||
// Loop over the words in this 32-word block.
|
||||
//
|
||||
while(((ui32Address & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
|
||||
(ui32Count != 0))
|
||||
{
|
||||
//
|
||||
// Write this word into the write buffer.
|
||||
//
|
||||
HWREG(FLASH_FWBN + (ui32Address & 0x7c)) = *pui32Data++;
|
||||
ui32Address += 4;
|
||||
ui32Count -= 4;
|
||||
}
|
||||
|
||||
//
|
||||
// Program the contents of the write buffer into flash.
|
||||
//
|
||||
HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
|
||||
|
||||
//
|
||||
// Wait until the write buffer has been programmed.
|
||||
//
|
||||
while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Return an error if an access violation occurred.
|
||||
//
|
||||
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
|
||||
FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the protection setting for a block of flash.
|
||||
//!
|
||||
//! \param ui32Address is the start address of the flash block to be queried.
|
||||
//!
|
||||
//! This function gets the current protection for the specified 2-kB block
|
||||
//! of flash. Each block can be read/write, read-only, or execute-only.
|
||||
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
|
||||
//! blocks can be read and executed. Execute-only blocks can only be executed;
|
||||
//! processor and debugger data reads are not allowed.
|
||||
//!
|
||||
//! \return Returns the protection setting for this block. See
|
||||
//! FlashProtectSet() for possible values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
tFlashProtection
|
||||
FlashLibProtectGet(uint32_t ui32Address)
|
||||
{
|
||||
uint32_t ui32FMPRE, ui32FMPPE;
|
||||
uint32_t ui32Bank;
|
||||
|
||||
//
|
||||
// Check the argument.
|
||||
//
|
||||
ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1)));
|
||||
|
||||
//
|
||||
// Calculate the Flash Bank from Base Address, and mask off the Bank
|
||||
// from ui32Address for subsequent reference.
|
||||
//
|
||||
ui32Bank = (((ui32Address / FLASH_PROTECT_SIZE) / 32) % 4);
|
||||
ui32Address &= ((FLASH_PROTECT_SIZE * 32) - 1);
|
||||
|
||||
//
|
||||
// Read the appropriate flash protection registers for the specified
|
||||
// flash bank.
|
||||
//
|
||||
ui32FMPRE = HWREG(g_pui32FMPRERegs[ui32Bank]);
|
||||
ui32FMPPE = HWREG(g_pui32FMPPERegs[ui32Bank]);
|
||||
|
||||
//
|
||||
// Check the appropriate protection bits for the block of memory that
|
||||
// is specified by the address.
|
||||
//
|
||||
switch((((ui32FMPRE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1) << 1) |
|
||||
((ui32FMPPE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1))
|
||||
{
|
||||
//
|
||||
// This block is marked as execute only (that is, it can not be erased
|
||||
// or programmed, and the only reads allowed are via the instruction
|
||||
// fetch interface).
|
||||
//
|
||||
case 0:
|
||||
case 1:
|
||||
{
|
||||
return(FlashExecuteOnly);
|
||||
}
|
||||
|
||||
//
|
||||
// This block is marked as read only (that is, it can not be erased or
|
||||
// programmed).
|
||||
//
|
||||
case 2:
|
||||
{
|
||||
return(FlashReadOnly);
|
||||
}
|
||||
|
||||
//
|
||||
// This block is read/write; it can be read, erased, and programmed.
|
||||
//
|
||||
case 3:
|
||||
default:
|
||||
{
|
||||
return(FlashReadWrite);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the protection setting for a block of flash.
|
||||
//!
|
||||
//! \param ui32Address is the start address of the flash block to be protected.
|
||||
//! \param eProtect is the protection to be applied to the block. Can be one
|
||||
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
|
||||
//!
|
||||
//! This function sets the protection for the specified 2-kB block of
|
||||
//! flash. Blocks that are read/write can be made read-only or execute-only.
|
||||
//! Blocks that are read-only can be made execute-only. Blocks that are
|
||||
//! execute-only cannot have their protection modified. Attempts to make the
|
||||
//! block protection less stringent (that is, read-only to read/write)
|
||||
//! result in a failure (and are prevented by the hardware).
|
||||
//!
|
||||
//! Changes to the flash protection are maintained only until the next reset.
|
||||
//! This protocol allows the application to be executed in the desired flash
|
||||
//! protection environment to check for inappropriate flash access (via the
|
||||
//! flash interrupt). To make the flash protection permanent, use the
|
||||
//! FlashProtectSave() function.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
|
||||
//! protection was specified.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibProtectSet(uint32_t ui32Address, tFlashProtection eProtect)
|
||||
{
|
||||
uint32_t ui32ProtectRE, ui32ProtectPE;
|
||||
uint32_t ui32Bank;
|
||||
|
||||
//
|
||||
// Check the argument.
|
||||
//
|
||||
ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1)));
|
||||
ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
|
||||
(eProtect == FlashExecuteOnly));
|
||||
|
||||
//
|
||||
// Convert the address into a block number.
|
||||
//
|
||||
ui32Address /= FLASH_PROTECT_SIZE;
|
||||
|
||||
//
|
||||
// ui32Address contains a "raw" block number. Derive the Flash Bank from
|
||||
// the "raw" block number, and convert ui32Address to a "relative"
|
||||
// block number.
|
||||
//
|
||||
ui32Bank = ((ui32Address / 32) % 4);
|
||||
ui32Address %= 32;
|
||||
|
||||
//
|
||||
// Get the current protection for the specified flash bank.
|
||||
//
|
||||
ui32ProtectRE = HWREG(g_pui32FMPRERegs[ui32Bank]);
|
||||
ui32ProtectPE = HWREG(g_pui32FMPPERegs[ui32Bank]);
|
||||
|
||||
//
|
||||
// Set the protection based on the requested protection.
|
||||
//
|
||||
switch(eProtect)
|
||||
{
|
||||
//
|
||||
// Make this block execute only.
|
||||
//
|
||||
case FlashExecuteOnly:
|
||||
{
|
||||
//
|
||||
// Turn off the read and program bits for this block.
|
||||
//
|
||||
ui32ProtectRE &= ~(0x1 << ui32Address);
|
||||
ui32ProtectPE &= ~(0x1 << ui32Address);
|
||||
|
||||
//
|
||||
// We're done handling this protection.
|
||||
//
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Make this block read only.
|
||||
//
|
||||
case FlashReadOnly:
|
||||
{
|
||||
//
|
||||
// The block can not be made read only if it is execute only.
|
||||
//
|
||||
if(((ui32ProtectRE >> ui32Address) & 0x1) != 0x1)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//
|
||||
// Make this block read only.
|
||||
//
|
||||
ui32ProtectPE &= ~(0x1 << ui32Address);
|
||||
|
||||
//
|
||||
// We're done handling this protection.
|
||||
//
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Make this block read/write.
|
||||
//
|
||||
case FlashReadWrite:
|
||||
default:
|
||||
{
|
||||
//
|
||||
// The block can not be made read/write if it is not already
|
||||
// read/write.
|
||||
//
|
||||
if((((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) ||
|
||||
(((ui32ProtectPE >> ui32Address) & 0x1) != 0x1))
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//
|
||||
// The block is already read/write, so there is nothing to do.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Set the new protection for the specified flash bank.
|
||||
//
|
||||
HWREG(g_pui32FMPRERegs[ui32Bank]) = ui32ProtectRE;
|
||||
HWREG(g_pui32FMPPERegs[ui32Bank]) = ui32ProtectPE;
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Saves the flash protection settings.
|
||||
//!
|
||||
//! This function makes the currently programmed flash protection settings
|
||||
//! permanent. On some devices, this operation is non-reversible; a chip reset
|
||||
//! or power cycle does not change the flash protection.
|
||||
//!
|
||||
//! This function does not return until the protection has been saved.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibProtectSave(void)
|
||||
{
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// Save the entire bank of 8 flash protection registers.
|
||||
//
|
||||
for(ui32Temp = 0; ui32Temp < 8; ui32Temp++)
|
||||
{
|
||||
//
|
||||
// Tell the flash controller to write the flash protection register.
|
||||
//
|
||||
HWREG(FLASH_FMA) = ui32Temp;
|
||||
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
||||
|
||||
//
|
||||
// Wait until the write has completed.
|
||||
//
|
||||
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the user registers.
|
||||
//!
|
||||
//! \param pui32User0 is a pointer to the location to store USER Register 0.
|
||||
//! \param pui32User1 is a pointer to the location to store USER Register 1.
|
||||
//!
|
||||
//! This function reads the contents of user registers (0 and 1), and
|
||||
//! stores them in the specified locations.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibUserGet(uint32_t *pui32User0, uint32_t *pui32User1)
|
||||
{
|
||||
//
|
||||
// Verify that the pointers are valid.
|
||||
//
|
||||
ASSERT(pui32User0 != 0);
|
||||
ASSERT(pui32User1 != 0);
|
||||
|
||||
//
|
||||
// Get and store the current value of the user registers.
|
||||
//
|
||||
*pui32User0 = HWREG(FLASH_USERREG0);
|
||||
*pui32User1 = HWREG(FLASH_USERREG1);
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the user registers.
|
||||
//!
|
||||
//! \param ui32User0 is the value to store in USER Register 0.
|
||||
//! \param ui32User1 is the value to store in USER Register 1.
|
||||
//!
|
||||
//! This function sets the contents of the user registers (0 and 1) to
|
||||
//! the specified values.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibUserSet(uint32_t ui32User0, uint32_t ui32User1)
|
||||
{
|
||||
//
|
||||
// Save the new values into the user registers.
|
||||
//
|
||||
HWREG(FLASH_USERREG0) = ui32User0;
|
||||
HWREG(FLASH_USERREG1) = ui32User1;
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Saves the user registers.
|
||||
//!
|
||||
//! This function makes the currently programmed user register settings
|
||||
//! permanent. On some devices, this operation is non-reversible; a chip reset
|
||||
//! or power cycle does not change this setting.
|
||||
//!
|
||||
//! This function does not return until the protection has been saved.
|
||||
//!
|
||||
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
FlashLibUserSave(void)
|
||||
{
|
||||
//
|
||||
// Setting the MSB of FMA will trigger a permanent save of a USER
|
||||
// register. Bit 0 will indicate User 0 (0) or User 1 (1).
|
||||
//
|
||||
HWREG(FLASH_FMA) = 0x80000000;
|
||||
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
||||
|
||||
//
|
||||
// Wait until the write has completed.
|
||||
//
|
||||
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Tell the flash controller to write the USER1 Register.
|
||||
//
|
||||
HWREG(FLASH_FMA) = 0x80000001;
|
||||
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
|
||||
|
||||
//
|
||||
// Wait until the write has completed.
|
||||
//
|
||||
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Success.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the flash interrupt.
|
||||
//!
|
||||
//! \param pfnHandler is a pointer to the function to be called when the flash
|
||||
//! interrupt occurs.
|
||||
//!
|
||||
//! This function sets the handler to be called when the flash interrupt
|
||||
//! occurs. The flash controller can generate an interrupt when an invalid
|
||||
//! flash access occurs, such as trying to program or erase a read-only block,
|
||||
//! or trying to read from an execute-only block. It can also generate an
|
||||
//! interrupt when a program or erase operation has completed. The interrupt
|
||||
//! is automatically enabled when the handler is registered.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FlashLibIntRegister(void (*pfnHandler)(void))
|
||||
{
|
||||
//
|
||||
// Register the interrupt handler, returning an error if an error occurs.
|
||||
//
|
||||
IntRegister(INT_FLASH_BLIZZARD, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the flash interrupt.
|
||||
//
|
||||
IntEnable(INT_FLASH_BLIZZARD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters the interrupt handler for the flash interrupt.
|
||||
//!
|
||||
//! This function clears the handler to be called when the flash interrupt
|
||||
//! occurs. This function also masks off the interrupt in the interrupt
|
||||
//! controller so that the interrupt handler is no longer called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FlashLibIntUnregister(void)
|
||||
{
|
||||
//
|
||||
// Disable the interrupt.
|
||||
//
|
||||
IntDisable(INT_FLASH_BLIZZARD);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(INT_FLASH_BLIZZARD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables individual flash controller interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
|
||||
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
|
||||
//!
|
||||
//! This function enables the indicated flash controller interrupt sources.
|
||||
//! Only the sources that are enabled can be reflected to the processor
|
||||
//! interrupt; disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FlashLibIntEnable(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Enable the specified interrupts.
|
||||
//
|
||||
HWREG(FLASH_FCIM) |= ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables individual flash controller interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
|
||||
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
|
||||
//!
|
||||
//! This function disables the indicated flash controller interrupt sources.
|
||||
//! Only the sources that are enabled can be reflected to the processor
|
||||
//! interrupt; disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FlashLibIntDisable(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Disable the specified interrupts.
|
||||
//
|
||||
HWREG(FLASH_FCIM) &= ~(ui32IntFlags);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current interrupt status.
|
||||
//!
|
||||
//! \param bMasked is false if the raw interrupt status is required and true if
|
||||
//! the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the interrupt status for the flash controller.
|
||||
//! Either the raw interrupt status or the status of interrupts that are
|
||||
//! allowed to reflect to the processor can be returned.
|
||||
//!
|
||||
//! \return The current interrupt status, enumerated as a bit field of
|
||||
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
FlashLibIntStatus(bool bMasked)
|
||||
{
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(HWREG(FLASH_FCMISC));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(HWREG(FLASH_FCRIS));
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears flash controller interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared.
|
||||
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
|
||||
//!
|
||||
//! The specified flash controller interrupt sources are cleared, so that they
|
||||
//! no longer assert. This function must be called in the interrupt handler
|
||||
//! to keep the interrupt from being triggered again immediately upon exit.
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FlashLibIntClear(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Clear the flash interrupt.
|
||||
//
|
||||
HWREG(FLASH_FCMISC) = ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,113 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// flash.h - Prototypes for the flash driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_FLASH_H__
|
||||
#define __DRIVERLIB_FLASH_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FlashProtectSet(), and returned by
|
||||
// FlashProtectGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
FlashReadWrite, // Flash can be read and written
|
||||
FlashReadOnly, // Flash can only be read
|
||||
FlashExecuteOnly // Flash can only be executed
|
||||
}
|
||||
tFlashProtection;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
|
||||
// returned from FlashIntStatus().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
|
||||
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
|
||||
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
|
||||
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
|
||||
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
|
||||
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
|
||||
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern int32_t FlashLibErase(uint32_t ui32Address);
|
||||
extern int32_t FlashLibProgram(uint32_t *pui32Data, uint32_t ui32Address,
|
||||
uint32_t ui32Count);
|
||||
extern tFlashProtection FlashLibProtectGet(uint32_t ui32Address);
|
||||
extern int32_t FlashLibProtectSet(uint32_t ui32Address,
|
||||
tFlashProtection eProtect);
|
||||
extern int32_t FlashLibProtectSave(void);
|
||||
extern int32_t FlashLibUserGet(uint32_t *pui32User0, uint32_t *pui32User1);
|
||||
extern int32_t FlashLibUserSet(uint32_t ui32User0, uint32_t ui32User1);
|
||||
extern int32_t FlashLibUserSave(void);
|
||||
extern void FlashLibIntRegister(void (*pfnHandler)(void));
|
||||
extern void FlashLibIntUnregister(void);
|
||||
extern void FlashLibIntEnable(uint32_t ui32IntFlags);
|
||||
extern void FlashLibIntDisable(uint32_t ui32IntFlags);
|
||||
extern uint32_t FlashLibIntStatus(bool bMasked);
|
||||
extern void FlashLibIntClear(uint32_t ui32IntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_FLASH_H__
|
|
@ -0,0 +1,300 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
|
||||
// processor.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup fpu_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/fpu.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the floating-point unit.
|
||||
//!
|
||||
//! This function enables the floating-point unit, allowing the floating-point
|
||||
//! instructions to be executed. This function must be called prior to
|
||||
//! performing any hardware floating-point operations; failure to do so results
|
||||
//! in a NOCP usage fault.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable the coprocessors used by the floating-point unit.
|
||||
//
|
||||
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
|
||||
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
|
||||
NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the floating-point unit.
|
||||
//!
|
||||
//! This function disables the floating-point unit, preventing floating-point
|
||||
//! instructions from executing (generating a NOCP usage fault instead).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable the coprocessors used by the floating-point unit.
|
||||
//
|
||||
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
|
||||
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
|
||||
NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the stacking of floating-point registers.
|
||||
//!
|
||||
//! This function enables the stacking of floating-point registers s0-s15 when
|
||||
//! an interrupt is handled. When enabled, space is reserved on the stack for
|
||||
//! the floating-point context and the floating-point state is saved into this
|
||||
//! stack space. Upon return from the interrupt, the floating-point context is
|
||||
//! restored.
|
||||
//!
|
||||
//! If the floating-point registers are not stacked, floating-point
|
||||
//! instructions cannot be safely executed in an interrupt handler because the
|
||||
//! values of s0-s15 are not likely to be preserved for the interrupted code.
|
||||
//! On the other hand, stacking the floating-point registers increases the
|
||||
//! stacking operation from 8 words to 26 words, also increasing the interrupt
|
||||
//! response latency.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUStackingEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable automatic state preservation for the floating-point unit, and
|
||||
// disable lazy state preservation (meaning that the floating-point state
|
||||
// is always stacked when floating-point instructions are used).
|
||||
//
|
||||
HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the lazy stacking of floating-point registers.
|
||||
//!
|
||||
//! This function enables the lazy stacking of floating-point registers s0-s15
|
||||
//! when an interrupt is handled. When lazy stacking is enabled, space is
|
||||
//! reserved on the stack for the floating-point context, but the
|
||||
//! floating-point state is not saved. If a floating-point instruction is
|
||||
//! executed from within the interrupt context, the floating-point context is
|
||||
//! first saved into the space reserved on the stack. On completion of the
|
||||
//! interrupt handler, the floating-point context is only restored if it was
|
||||
//! saved (as the result of executing a floating-point instruction).
|
||||
//!
|
||||
//! This method provides a compromise between fast interrupt response (because
|
||||
//! the floating-point state is not saved on interrupt entry) and the ability
|
||||
//! to use floating-point in interrupt handlers (because the floating-point
|
||||
//! state is saved if floating-point instructions are used).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPULazyStackingEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable automatic and lazy state preservation for the floating-point
|
||||
// unit.
|
||||
//
|
||||
HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the stacking of floating-point registers.
|
||||
//!
|
||||
//! This function disables the stacking of floating-point registers s0-s15 when
|
||||
//! an interrupt is handled. When floating-point context stacking is disabled,
|
||||
//! floating-point operations performed in an interrupt handler destroy the
|
||||
//! floating-point context of the main thread of execution.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUStackingDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable automatic and lazy state preservation for the floating-point
|
||||
// unit.
|
||||
//
|
||||
HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Selects the format of half-precision floating-point values.
|
||||
//!
|
||||
//! \param ui32Mode is the format for half-precision floating-point value,
|
||||
//! which is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
|
||||
//!
|
||||
//! This function selects between the IEEE half-precision floating-point
|
||||
//! representation and the Cortex-M processor alternative representation. The
|
||||
//! alternative representation has a larger range but does not have a way to
|
||||
//! encode infinity (positive or negative) or NaN (quiet or signaling). The
|
||||
//! default setting is the IEEE format.
|
||||
//!
|
||||
//! \note Unless this function is called prior to executing any floating-point
|
||||
//! instructions, the default mode is used.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUHalfPrecisionModeSet(uint32_t ui32Mode)
|
||||
{
|
||||
//
|
||||
// Set the half-precision floating-point format.
|
||||
//
|
||||
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ui32Mode;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Selects the NaN mode.
|
||||
//!
|
||||
//! \param ui32Mode is the mode for NaN results; which is either
|
||||
//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
|
||||
//!
|
||||
//! This function selects the handling of NaN results during floating-point
|
||||
//! computations. NaNs can either propagate (the default), or they can return
|
||||
//! the default NaN.
|
||||
//!
|
||||
//! \note Unless this function is called prior to executing any floating-point
|
||||
//! instructions, the default mode is used.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUNaNModeSet(uint32_t ui32Mode)
|
||||
{
|
||||
//
|
||||
// Set the NaN mode.
|
||||
//
|
||||
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ui32Mode;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Selects the flush-to-zero mode.
|
||||
//!
|
||||
//! \param ui32Mode is the flush-to-zero mode; which is either
|
||||
//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
|
||||
//!
|
||||
//! This function enables or disables the flush-to-zero mode of the
|
||||
//! floating-point unit. When disabled (the default), the floating-point unit
|
||||
//! is fully IEEE compliant. When enabled, values close to zero are treated as
|
||||
//! zero, greatly improving the execution speed at the expense of some accuracy
|
||||
//! (as well as IEEE compliance).
|
||||
//!
|
||||
//! \note Unless this function is called prior to executing any floating-point
|
||||
//! instructions, the default mode is used.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPUFlushToZeroModeSet(uint32_t ui32Mode)
|
||||
{
|
||||
//
|
||||
// Set the flush-to-zero mode.
|
||||
//
|
||||
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ui32Mode;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Selects the rounding mode for floating-point results.
|
||||
//!
|
||||
//! \param ui32Mode is the rounding mode.
|
||||
//!
|
||||
//! This function selects the rounding mode for floating-point results. After
|
||||
//! a floating-point operation, the result is rounded toward the specified
|
||||
//! value. The default mode is \b FPU_ROUND_NEAREST.
|
||||
//!
|
||||
//! The following rounding modes are available (as specified by \e ui32Mode):
|
||||
//!
|
||||
//! - \b FPU_ROUND_NEAREST - round toward the nearest value
|
||||
//! - \b FPU_ROUND_POS_INF - round toward positive infinity
|
||||
//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
|
||||
//! - \b FPU_ROUND_ZERO - round toward zero
|
||||
//!
|
||||
//! \note Unless this function is called prior to executing any floating-point
|
||||
//! instructions, the default mode is used.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
FPURoundingModeSet(uint32_t ui32Mode)
|
||||
{
|
||||
//
|
||||
// Set the rounding mode.
|
||||
//
|
||||
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ui32Mode;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,113 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// fpu.h - Prototypes for the floatint point manipulation routines.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_FPU_H__
|
||||
#define __DRIVERLIB_FPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_HALF_IEEE 0x00000000
|
||||
#define FPU_HALF_ALTERNATE 0x04000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_NAN_PROPAGATE 0x00000000
|
||||
#define FPU_NAN_DEFAULT 0x02000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
|
||||
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_ROUND_NEAREST 0x00000000
|
||||
#define FPU_ROUND_POS_INF 0x00400000
|
||||
#define FPU_ROUND_NEG_INF 0x00800000
|
||||
#define FPU_ROUND_ZERO 0x00c00000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void FPUEnable(void);
|
||||
extern void FPUDisable(void);
|
||||
extern void FPUStackingEnable(void);
|
||||
extern void FPULazyStackingEnable(void);
|
||||
extern void FPUStackingDisable(void);
|
||||
extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode);
|
||||
extern void FPUNaNModeSet(uint32_t ui32Mode);
|
||||
extern void FPUFlushToZeroModeSet(uint32_t ui32Mode);
|
||||
extern void FPURoundingModeSet(uint32_t ui32Mode);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_FPU_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,190 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// gpio.h - Defines and Macros for GPIO API.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_GPIO_H__
|
||||
#define __DRIVERLIB_GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following values define the bit field for the ui8Pins argument to
|
||||
// several of the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
|
||||
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
|
||||
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
|
||||
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
|
||||
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
|
||||
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
|
||||
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
|
||||
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and
|
||||
// returned from GPIODirModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
|
||||
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
|
||||
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter,
|
||||
// and returned from GPIOIntTypeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
|
||||
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
|
||||
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
|
||||
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
|
||||
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
|
||||
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pui32Strength parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
|
||||
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
|
||||
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
|
||||
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pui32PadType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
|
||||
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
|
||||
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
|
||||
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
|
||||
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
|
||||
// in the ui32IntFlags parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_INT_PIN_0 0x00000001
|
||||
#define GPIO_INT_PIN_1 0x00000002
|
||||
#define GPIO_INT_PIN_2 0x00000004
|
||||
#define GPIO_INT_PIN_3 0x00000008
|
||||
#define GPIO_INT_PIN_4 0x00000010
|
||||
#define GPIO_INT_PIN_5 0x00000020
|
||||
#define GPIO_INT_PIN_6 0x00000040
|
||||
#define GPIO_INT_PIN_7 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,
|
||||
uint32_t ui32PinIO);
|
||||
extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin);
|
||||
extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
|
||||
uint32_t ui32IntType);
|
||||
extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin);
|
||||
extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,
|
||||
uint32_t ui32Strength, uint32_t ui32PadType);
|
||||
extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,
|
||||
uint32_t *pui32Strength, uint32_t *pui32PadType);
|
||||
extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags);
|
||||
extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags);
|
||||
extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked);
|
||||
extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags);
|
||||
extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void));
|
||||
extern void GPIOIntUnregister(uint32_t ui32Port);
|
||||
extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val);
|
||||
extern void GPIOPinConfigure(uint32_t ui32PinConfig);
|
||||
extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeFan(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypePECIRx(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypePECITx(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_GPIO_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,146 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hibernate.h - API definition for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_HIBERNATE_H__
|
||||
#define __DRIVERLIB_HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros need to configure wake events for HibernateWakeSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_WAKE_PIN 0x00000010
|
||||
#define HIBERNATE_WAKE_RTC 0x00000008
|
||||
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros needed to configure low battery detect for HibernateLowBatSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_LOW_BAT_DETECT \
|
||||
0x00000020
|
||||
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
|
||||
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
|
||||
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
|
||||
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
|
||||
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining interrupt source bits for the interrupt functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_INT_WR_COMPLETE \
|
||||
0x00000010
|
||||
#define HIBERNATE_INT_PIN_WAKE 0x00000008
|
||||
#define HIBERNATE_INT_LOW_BAT 0x00000004
|
||||
#define HIBERNATE_INT_RTC_MATCH_0 \
|
||||
0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining oscillator configuration options for the
|
||||
// HibernateClockConfig() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_OSC_LOWDRIVE 0x00000000
|
||||
#define HIBERNATE_OSC_HIGHDRIVE 0x00020000
|
||||
#define HIBERNATE_OSC_DISABLE 0x00010000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void HibernateGPIORetentionEnable(void);
|
||||
extern void HibernateGPIORetentionDisable(void);
|
||||
extern bool HibernateGPIORetentionGet(void);
|
||||
extern void HibernateEnableExpClk(uint32_t ui32HibClk);
|
||||
extern void HibernateDisable(void);
|
||||
extern void HibernateRTCEnable(void);
|
||||
extern void HibernateRTCDisable(void);
|
||||
extern void HibernateWakeSet(uint32_t ui32WakeFlags);
|
||||
extern uint32_t HibernateWakeGet(void);
|
||||
extern void HibernateLowBatSet(uint32_t ui32LowBatFlags);
|
||||
extern uint32_t HibernateLowBatGet(void);
|
||||
extern void HibernateRTCSet(uint32_t ui32RTCValue);
|
||||
extern uint32_t HibernateRTCGet(void);
|
||||
extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value);
|
||||
extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match);
|
||||
extern void HibernateRTCTrimSet(uint32_t ui32Trim);
|
||||
extern uint32_t HibernateRTCTrimGet(void);
|
||||
extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count);
|
||||
extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count);
|
||||
extern void HibernateRequest(void);
|
||||
extern void HibernateIntEnable(uint32_t ui32IntFlags);
|
||||
extern void HibernateIntDisable(uint32_t ui32IntFlags);
|
||||
extern void HibernateIntRegister(void (*pfnHandler)(void));
|
||||
extern void HibernateIntUnregister(void);
|
||||
extern uint32_t HibernateIntStatus(bool bMasked);
|
||||
extern void HibernateIntClear(uint32_t ui32IntFlags);
|
||||
extern uint32_t HibernateIsActive(void);
|
||||
extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value);
|
||||
extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match);
|
||||
extern uint32_t HibernateRTCSSGet(void);
|
||||
extern void HibernateClockConfig(uint32_t ui32Config);
|
||||
extern void HibernateBatCheckStart(void);
|
||||
extern uint32_t HibernateBatCheckDone(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_HIBERNATE_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,212 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// i2c.h - Prototypes for the I2C Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_I2C_H__
|
||||
#define __DRIVERLIB_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for the API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Interrupt defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_INT_MASTER 0x00000001
|
||||
#define I2C_INT_SLAVE 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master commands.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CMD_SINGLE_SEND \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_BURST_SEND_START \
|
||||
0x00000003
|
||||
#define I2C_MASTER_CMD_BURST_SEND_CONT \
|
||||
0x00000001
|
||||
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_SEND_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
|
||||
0x0000000b
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
|
||||
0x00000009
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_QUICK_COMMAND \
|
||||
0x00000027
|
||||
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
|
||||
0x00000013
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master error status.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_ERR_NONE 0
|
||||
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
|
||||
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
|
||||
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
|
||||
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave action requests
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_ACT_NONE 0
|
||||
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
|
||||
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
|
||||
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
|
||||
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
|
||||
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
|
||||
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Miscellaneous I2C driver definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
|
||||
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
|
||||
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
|
||||
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
|
||||
extern void I2CIntUnregister(uint32_t ui32Base);
|
||||
extern bool I2CMasterBusBusy(uint32_t ui32Base);
|
||||
extern bool I2CMasterBusy(uint32_t ui32Base);
|
||||
extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
|
||||
extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
|
||||
extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
|
||||
extern void I2CMasterDisable(uint32_t ui32Base);
|
||||
extern void I2CMasterEnable(uint32_t ui32Base);
|
||||
extern uint32_t I2CMasterErr(uint32_t ui32Base);
|
||||
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
|
||||
bool bFast);
|
||||
extern void I2CMasterIntClear(uint32_t ui32Base);
|
||||
extern void I2CMasterIntDisable(uint32_t ui32Base);
|
||||
extern void I2CMasterIntEnable(uint32_t ui32Base);
|
||||
extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void I2CMasterIntEnableEx(uint32_t ui32Base,
|
||||
uint32_t ui32IntFlags);
|
||||
extern void I2CMasterIntDisableEx(uint32_t ui32Base,
|
||||
uint32_t ui32IntFlags);
|
||||
extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
|
||||
bool bMasked);
|
||||
extern void I2CMasterIntClearEx(uint32_t ui32Base,
|
||||
uint32_t ui32IntFlags);
|
||||
extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
|
||||
extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
|
||||
extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
|
||||
extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
|
||||
extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
|
||||
uint8_t ui8SlaveAddr,
|
||||
bool bReceive);
|
||||
extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
|
||||
extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
|
||||
extern void I2CSlaveDisable(uint32_t ui32Base);
|
||||
extern void I2CSlaveEnable(uint32_t ui32Base);
|
||||
extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
|
||||
extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
|
||||
uint8_t ui8SlaveAddr);
|
||||
extern void I2CSlaveIntClear(uint32_t ui32Base);
|
||||
extern void I2CSlaveIntDisable(uint32_t ui32Base);
|
||||
extern void I2CSlaveIntEnable(uint32_t ui32Base);
|
||||
extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
|
||||
uint32_t ui32IntFlags);
|
||||
extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
|
||||
bool bMasked);
|
||||
extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_I2C_H__
|
|
@ -0,0 +1,880 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.c - Driver for the NVIC Interrupt Controller.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup interrupt_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/cpulib.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between priority grouping encodings and the number of
|
||||
// preemption priority bits.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32Priority[] =
|
||||
{
|
||||
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
|
||||
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
|
||||
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number and the register that contains
|
||||
// the priority encoding for that interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32Regs[] =
|
||||
{
|
||||
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
|
||||
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
|
||||
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
|
||||
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
|
||||
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
|
||||
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
|
||||
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt enable for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32EnRegs[] =
|
||||
{
|
||||
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt disable for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32Dii16Regs[] =
|
||||
{
|
||||
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt pend for that interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32PendRegs[] =
|
||||
{
|
||||
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt unpend for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32UnpendRegs[] =
|
||||
{
|
||||
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! The default interrupt handler.
|
||||
//!
|
||||
//! This is the default interrupt handler for all interrupts. It simply loops
|
||||
//! forever so that the system state is preserved for observation by a
|
||||
//! debugger. Since interrupts must be disabled before unregistering the
|
||||
//! corresponding handler, this should never be called during normal operation.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static void
|
||||
_IntDefaultHandler(void)
|
||||
{
|
||||
//
|
||||
// Go into an infinite loop.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The processor vector table.
|
||||
//
|
||||
// This contains a list of the handlers for the various interrupt sources in
|
||||
// the system. The layout of this list is defined by the hardware; assertion
|
||||
// of an interrupt causes the processor to start executing directly at the
|
||||
// address given in the corresponding location in this list.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Set the size of the vector table to the largest number of interrupts of
|
||||
// any device
|
||||
//
|
||||
#undef NUM_INTERRUPTS
|
||||
#define NUM_INTERRUPTS 155
|
||||
#if defined(ewarm)
|
||||
#pragma data_alignment=1024
|
||||
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
|
||||
#elif defined(sourcerygxx)
|
||||
static __attribute__((section(".cs3.region-head.ram")))
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
|
||||
#elif defined(ccs) || defined(DOXYGEN)
|
||||
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
|
||||
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
|
||||
#else
|
||||
static __attribute__((section("vtable")))
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024)));
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the processor interrupt.
|
||||
//!
|
||||
//! This function allows the processor to respond to interrupts. This function
|
||||
//! does not affect the set of interrupts enabled in the interrupt controller;
|
||||
//! it just gates the single interrupt from the controller to the processor.
|
||||
//!
|
||||
//! \note Previously, this function had no return value. As such, it was
|
||||
//! possible to include <tt>interrupt.h</tt> and call this function without
|
||||
//! having included <tt>hw_types.h</tt>. Now that the return is a
|
||||
//! <tt>bool</tt>, a compiler error occurs in this case. The solution
|
||||
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
|
||||
//!
|
||||
//! \return Returns \b true if interrupts were disabled when the function was
|
||||
//! called or \b false if they were initially enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
IntMasterEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable processor interrupts.
|
||||
//
|
||||
return(CPUcpsie());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the processor interrupt.
|
||||
//!
|
||||
//! This function prevents the processor from receiving interrupts. This
|
||||
//! function does not affect the set of interrupts enabled in the interrupt
|
||||
//! controller; it just gates the single interrupt from the controller to the
|
||||
//! processor.
|
||||
//!
|
||||
//! \note Previously, this function had no return value. As such, it was
|
||||
//! possible to include <tt>interrupt.h</tt> and call this function without
|
||||
//! having included <tt>hw_types.h</tt>. Now that the return is a
|
||||
//! <tt>bool</tt>, a compiler error occurs in this case. The solution
|
||||
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
|
||||
//!
|
||||
//! \return Returns \b true if interrupts were already disabled when the
|
||||
//! function was called or \b false if they were initially enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
IntMasterDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable processor interrupts.
|
||||
//
|
||||
return(CPUcpsid());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers a function to be called when an interrupt occurs.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt in question.
|
||||
//! \param pfnHandler is a pointer to the function to be called.
|
||||
//!
|
||||
//! This function is used to specify the handler function to be called when the
|
||||
//! given interrupt is asserted to the processor. When the interrupt occurs,
|
||||
//! if it is enabled (via IntEnable()), the handler function is called in
|
||||
//! interrupt context. Because the handler function can preempt other code,
|
||||
//! care must be taken to protect memory or peripherals that are accessed by
|
||||
//! the handler and other non-handler code.
|
||||
//!
|
||||
//! \note The use of this function (directly or indirectly via a peripheral
|
||||
//! driver interrupt register function) moves the interrupt vector table from
|
||||
//! flash to SRAM. Therefore, care must be taken when linking the application
|
||||
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
|
||||
//! otherwise the NVIC does not look in the correct portion of memory for the
|
||||
//! vector table (it requires the vector table be on a 1 kB memory alignment).
|
||||
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
|
||||
//! See the discussion of compile-time versus run-time interrupt handler
|
||||
//! registration in the introduction to this chapter.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
|
||||
{
|
||||
uint32_t ui32Idx, ui32Value;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Make sure that the RAM vector table is correctly aligned.
|
||||
//
|
||||
ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0);
|
||||
|
||||
//
|
||||
// See if the RAM vector table has been initialized.
|
||||
//
|
||||
if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
|
||||
{
|
||||
//
|
||||
// Copy the vector table from the beginning of FLASH to the RAM vector
|
||||
// table.
|
||||
//
|
||||
ui32Value = HWREG(NVIC_VTABLE);
|
||||
for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
|
||||
{
|
||||
g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
|
||||
ui32Value);
|
||||
}
|
||||
|
||||
//
|
||||
// Point the NVIC at the RAM vector table.
|
||||
//
|
||||
HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
|
||||
}
|
||||
|
||||
//
|
||||
// Save the interrupt handler.
|
||||
//
|
||||
g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters the function to be called when an interrupt occurs.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt in question.
|
||||
//!
|
||||
//! This function is used to indicate that no handler is called when the
|
||||
//! given interrupt is asserted to the processor. The interrupt source is
|
||||
//! automatically disabled (via IntDisable()) if necessary.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntUnregister(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Reset the interrupt handler.
|
||||
//
|
||||
g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority grouping of the interrupt controller.
|
||||
//!
|
||||
//! \param ui32Bits specifies the number of bits of preemptable priority.
|
||||
//!
|
||||
//! This function specifies the split between preemptable priority levels and
|
||||
//! sub-priority levels in the interrupt priority specification. The range of
|
||||
//! the grouping values are dependent upon the hardware implementation; on
|
||||
//! the Tiva C and E Series family, three bits are available for hardware
|
||||
//! interrupt prioritization and therefore priority grouping values of three
|
||||
//! through seven have the same effect.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPriorityGroupingSet(uint32_t ui32Bits)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Bits < NUM_PRIORITY);
|
||||
|
||||
//
|
||||
// Set the priority grouping.
|
||||
//
|
||||
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits];
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority grouping of the interrupt controller.
|
||||
//!
|
||||
//! This function returns the split between preemptable priority levels and
|
||||
//! sub-priority levels in the interrupt priority specification.
|
||||
//!
|
||||
//! \return The number of bits of preemptable priority.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
IntPriorityGroupingGet(void)
|
||||
{
|
||||
uint32_t ui32Loop, ui32Value;
|
||||
|
||||
//
|
||||
// Read the priority grouping.
|
||||
//
|
||||
ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
|
||||
|
||||
//
|
||||
// Loop through the priority grouping values.
|
||||
//
|
||||
for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
|
||||
{
|
||||
//
|
||||
// Stop looping if this value matches.
|
||||
//
|
||||
if(ui32Value == g_pui32Priority[ui32Loop])
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Return the number of priority bits.
|
||||
//
|
||||
return(ui32Loop);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority of an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt in question.
|
||||
//! \param ui8Priority specifies the priority of the interrupt.
|
||||
//!
|
||||
//! This function is used to set the priority of an interrupt. When multiple
|
||||
//! interrupts are asserted simultaneously, the ones with the highest priority
|
||||
//! are processed before the lower priority interrupts. Smaller numbers
|
||||
//! correspond to higher interrupt priorities; priority 0 is the highest
|
||||
//! interrupt priority.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Tiva C and E Series family), so any
|
||||
//! prioritization must be performed in those bits. The remaining bits can be
|
||||
//! used to sub-prioritize the interrupt sources, and may be used by the
|
||||
//! hardware priority mechanism on a future part. This arrangement allows
|
||||
//! priorities to migrate to different NVIC implementations without changing
|
||||
//! the gross prioritization of the interrupts.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority)
|
||||
{
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
|
||||
|
||||
//
|
||||
// Set the interrupt priority.
|
||||
//
|
||||
ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
|
||||
ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
|
||||
ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
|
||||
HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority of an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt in question.
|
||||
//!
|
||||
//! This function gets the priority of an interrupt. See IntPrioritySet() for
|
||||
//! a definition of the priority value.
|
||||
//!
|
||||
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
|
||||
//! specified.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
IntPriorityGet(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
|
||||
|
||||
//
|
||||
// Return the interrupt priority.
|
||||
//
|
||||
return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >>
|
||||
(8 * (ui32Interrupt & 3))) & 0xFF);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to be enabled.
|
||||
//!
|
||||
//! The specified interrupt is enabled in the interrupt controller. Other
|
||||
//! enables for the interrupt (such as at the peripheral level) are unaffected
|
||||
//! by this function.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntEnable(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to enable.
|
||||
//
|
||||
if(ui32Interrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Enable the MemManage interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Enable the bus fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Enable the usage fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Enable the System Tick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
else if(ui32Interrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Enable the general interrupt.
|
||||
//
|
||||
HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) =
|
||||
1 << ((ui32Interrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to be disabled.
|
||||
//!
|
||||
//! The specified interrupt is disabled in the interrupt controller. Other
|
||||
//! enables for the interrupt (such as at the peripheral level) are unaffected
|
||||
//! by this function.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntDisable(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to disable.
|
||||
//
|
||||
if(ui32Interrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Disable the MemManage interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Disable the bus fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Disable the usage fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Disable the System Tick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
|
||||
}
|
||||
else if(ui32Interrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Disable the general interrupt.
|
||||
//
|
||||
HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) =
|
||||
1 << ((ui32Interrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns if a peripheral interrupt is enabled.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to check.
|
||||
//!
|
||||
//! This function checks if the specified interrupt is enabled in the interrupt
|
||||
//! controller.
|
||||
//!
|
||||
//! \return A non-zero value if the interrupt is enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
IntIsEnabled(uint32_t ui32Interrupt)
|
||||
{
|
||||
uint32_t ui32Ret;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Initialize the return value.
|
||||
//
|
||||
ui32Ret = 0;
|
||||
|
||||
//
|
||||
// Determine the interrupt to disable.
|
||||
//
|
||||
if(ui32Interrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Check the MemManage interrupt.
|
||||
//
|
||||
ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Check the bus fault interrupt.
|
||||
//
|
||||
ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Check the usage fault interrupt.
|
||||
//
|
||||
ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Check the System Tick interrupt.
|
||||
//
|
||||
ui32Ret = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
else if(ui32Interrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Check the general interrupt.
|
||||
//
|
||||
ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) &
|
||||
(1 << ((ui32Interrupt - 16) & 31));
|
||||
}
|
||||
return(ui32Ret);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Pends an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to be pended.
|
||||
//!
|
||||
//! The specified interrupt is pended in the interrupt controller. Pending an
|
||||
//! interrupt causes the interrupt controller to execute the corresponding
|
||||
//! interrupt handler at the next available time, based on the current
|
||||
//! interrupt state priorities. For example, if called by a higher priority
|
||||
//! interrupt handler, the specified interrupt handler is not called until
|
||||
//! after the current interrupt handler has completed execution. The interrupt
|
||||
//! must have been enabled for it to be called.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPendSet(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to pend.
|
||||
//
|
||||
if(ui32Interrupt == FAULT_NMI)
|
||||
{
|
||||
//
|
||||
// Pend the NMI interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_PENDSV)
|
||||
{
|
||||
//
|
||||
// Pend the PendSV interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Pend the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
|
||||
}
|
||||
else if(ui32Interrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Pend the general interrupt.
|
||||
//
|
||||
HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) =
|
||||
1 << ((ui32Interrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Un-pends an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to be un-pended.
|
||||
//!
|
||||
//! The specified interrupt is un-pended in the interrupt controller. This
|
||||
//! causes any previously generated interrupts that have not been handled
|
||||
//! yet (due to higher priority interrupts or the interrupt not having been
|
||||
//! enabled yet) to be discarded.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPendClear(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to unpend.
|
||||
//
|
||||
if(ui32Interrupt == FAULT_PENDSV)
|
||||
{
|
||||
//
|
||||
// Unpend the PendSV interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
|
||||
}
|
||||
else if(ui32Interrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Unpend the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
|
||||
}
|
||||
else if(ui32Interrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Unpend the general interrupt.
|
||||
//
|
||||
HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) =
|
||||
1 << ((ui32Interrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority masking level
|
||||
//!
|
||||
//! \param ui32PriorityMask is the priority level that is masked.
|
||||
//!
|
||||
//! This function sets the interrupt priority masking level so that all
|
||||
//! interrupts at the specified or lesser priority level are masked. Masking
|
||||
//! interrupts can be used to globally disable a set of interrupts with
|
||||
//! priority below a predetermined threshold. A value of 0 disables priority
|
||||
//! masking.
|
||||
//!
|
||||
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
||||
//! a priority level mask of 4 allows interrupts of priority level 0-3,
|
||||
//! and interrupts with a numerical priority of 4 and greater are blocked.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Tiva C and E Series family), so any
|
||||
//! prioritization must be performed in those bits.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPriorityMaskSet(uint32_t ui32PriorityMask)
|
||||
{
|
||||
//
|
||||
// Set the priority mask.
|
||||
//
|
||||
CPUbasepriSet(ui32PriorityMask);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority masking level
|
||||
//!
|
||||
//! This function gets the current setting of the interrupt priority masking
|
||||
//! level. The value returned is the priority level such that all interrupts
|
||||
//! of that and lesser priority are masked. A value of 0 means that priority
|
||||
//! masking is disabled.
|
||||
//!
|
||||
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
||||
//! a priority level mask of 4 allows interrupts of priority level 0-3,
|
||||
//! and interrupts with a numerical priority of 4 and greater are blocked.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Tiva C and E Series family), so any
|
||||
//! prioritization must be performed in those bits.
|
||||
//!
|
||||
//! \return Returns the value of the interrupt priority level mask.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
IntPriorityMaskGet(void)
|
||||
{
|
||||
//
|
||||
// Return the current priority mask.
|
||||
//
|
||||
return(CPUbasepriGet());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Triggers an interrupt.
|
||||
//!
|
||||
//! \param ui32Interrupt specifies the interrupt to be triggered.
|
||||
//!
|
||||
//! This function performs a software trigger of an interrupt. The interrupt
|
||||
//! controller behaves as if the corresponding interrupt line was asserted, and
|
||||
//! the interrupt is handled in the same manner (meaning that it must be
|
||||
//! enabled in order to be processed, and the processing is based on its
|
||||
//! priority with respect to other unhandled interrupts).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntTrigger(uint32_t ui32Interrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS));
|
||||
|
||||
//
|
||||
// Trigger this interrupt.
|
||||
//
|
||||
HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,94 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_INTERRUPT_H__
|
||||
#define __DRIVERLIB_INTERRUPT_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to generate an interrupt priority mask based on the number of bits
|
||||
// of priority supported by the hardware.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern bool IntMasterEnable(void);
|
||||
extern bool IntMasterDisable(void);
|
||||
extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
|
||||
extern void IntUnregister(uint32_t ui32Interrupt);
|
||||
extern void IntPriorityGroupingSet(uint32_t ui32Bits);
|
||||
extern uint32_t IntPriorityGroupingGet(void);
|
||||
extern void IntPrioritySet(uint32_t ui32Interrupt,
|
||||
uint8_t ui8Priority);
|
||||
extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
|
||||
extern void IntEnable(uint32_t ui32Interrupt);
|
||||
extern void IntDisable(uint32_t ui32Interrupt);
|
||||
extern uint32_t IntIsEnabled(uint32_t ui32Interrupt);
|
||||
extern void IntPendSet(uint32_t ui32Interrupt);
|
||||
extern void IntPendClear(uint32_t ui32Interrupt);
|
||||
extern void IntPriorityMaskSet(uint32_t ui32PriorityMask);
|
||||
extern uint32_t IntPriorityMaskGet(void);
|
||||
extern void IntTrigger(uint32_t ui32Interrupt);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_INTERRUPT_H__
|
|
@ -0,0 +1,459 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup mpu_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
#include "driverlib/mpu.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables and configures the MPU for use.
|
||||
//!
|
||||
//! \param ui32MPUConfig is the logical OR of the possible configurations.
|
||||
//!
|
||||
//! This function enables the Cortex-M memory protection unit. It also
|
||||
//! configures the default behavior when in privileged mode and while handling
|
||||
//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
|
||||
//! be set by calling MPURegionSet() or else by enabling the default region for
|
||||
//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
|
||||
//! MPUEnable(). Once the MPU is enabled, a memory management fault is
|
||||
//! generated for memory access violations.
|
||||
//!
|
||||
//! The \e ui32MPUConfig parameter should be the logical OR of any of the
|
||||
//! following:
|
||||
//!
|
||||
//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
|
||||
//! privileged mode and when no other regions are defined. If this option
|
||||
//! is not enabled, then there must be at least one valid region already
|
||||
//! defined when the MPU is enabled.
|
||||
//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
|
||||
//! exception handler. If this option is not enabled, then the MPU is
|
||||
//! disabled while in one of these exception handlers and the default
|
||||
//! memory map is applied.
|
||||
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
|
||||
//! no default memory map is provided in privileged mode, and the MPU is not
|
||||
//! enabled in the fault handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPUEnable(uint32_t ui32MPUConfig)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
|
||||
MPU_CONFIG_HARDFLT_NMI)));
|
||||
|
||||
//
|
||||
// Set the MPU control bits according to the flags passed by the user,
|
||||
// and also set the enable bit.
|
||||
//
|
||||
HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the MPU for use.
|
||||
//!
|
||||
//! This function disables the Cortex-M memory protection unit. When the
|
||||
//! MPU is disabled, the default memory map is used and memory management
|
||||
//! faults are not generated.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPUDisable(void)
|
||||
{
|
||||
//
|
||||
// Turn off the MPU enable bit.
|
||||
//
|
||||
HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the count of regions supported by the MPU.
|
||||
//!
|
||||
//! This function is used to get the total number of regions that are supported
|
||||
//! by the MPU, including regions that are already programmed.
|
||||
//!
|
||||
//! \return The number of memory protection regions that are available
|
||||
//! for programming using MPURegionSet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
MPURegionCountGet(void)
|
||||
{
|
||||
//
|
||||
// Read the DREGION field of the MPU type register and mask off
|
||||
// the bits of interest to get the count of regions.
|
||||
//
|
||||
return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >>
|
||||
NVIC_MPU_TYPE_DREGION_S);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables a specific region.
|
||||
//!
|
||||
//! \param ui32Region is the region number to enable.
|
||||
//!
|
||||
//! This function is used to enable a memory protection region. The region
|
||||
//! should already be configured with the MPURegionSet() function. Once
|
||||
//! enabled, the memory protection rules of the region are applied and access
|
||||
//! violations cause a memory management fault.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPURegionEnable(uint32_t ui32Region)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Region < 8);
|
||||
|
||||
//
|
||||
// Select the region to modify.
|
||||
//
|
||||
HWREG(NVIC_MPU_NUMBER) = ui32Region;
|
||||
|
||||
//
|
||||
// Modify the enable bit in the region attributes.
|
||||
//
|
||||
HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables a specific region.
|
||||
//!
|
||||
//! \param ui32Region is the region number to disable.
|
||||
//!
|
||||
//! This function is used to disable a previously enabled memory protection
|
||||
//! region. The region remains configured if it is not overwritten with
|
||||
//! another call to MPURegionSet(), and can be enabled again by calling
|
||||
//! MPURegionEnable().
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPURegionDisable(uint32_t ui32Region)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Region < 8);
|
||||
|
||||
//
|
||||
// Select the region to modify.
|
||||
//
|
||||
HWREG(NVIC_MPU_NUMBER) = ui32Region;
|
||||
|
||||
//
|
||||
// Modify the enable bit in the region attributes.
|
||||
//
|
||||
HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets up the access rules for a specific region.
|
||||
//!
|
||||
//! \param ui32Region is the region number to set up.
|
||||
//! \param ui32Addr is the base address of the region. It must be aligned
|
||||
//! according to the size of the region specified in ui32Flags.
|
||||
//! \param ui32Flags is a set of flags to define the attributes of the region.
|
||||
//!
|
||||
//! This function sets up the protection rules for a region. The region has
|
||||
//! a base address and a set of attributes including the size. The base
|
||||
//! address parameter, \e ui32Addr, must be aligned according to the size, and
|
||||
//! the size must be a power of 2.
|
||||
//!
|
||||
//! The \e ui32Flags parameter is the logical OR of all of the attributes
|
||||
//! of the region. It is a combination of choices for region size,
|
||||
//! execute permission, read/write permissions, disabled sub-regions,
|
||||
//! and a flag to determine if the region is enabled.
|
||||
//!
|
||||
//! The size flag determines the size of a region and must be one of the
|
||||
//! following:
|
||||
//!
|
||||
//! - \b MPU_RGN_SIZE_32B
|
||||
//! - \b MPU_RGN_SIZE_64B
|
||||
//! - \b MPU_RGN_SIZE_128B
|
||||
//! - \b MPU_RGN_SIZE_256B
|
||||
//! - \b MPU_RGN_SIZE_512B
|
||||
//! - \b MPU_RGN_SIZE_1K
|
||||
//! - \b MPU_RGN_SIZE_2K
|
||||
//! - \b MPU_RGN_SIZE_4K
|
||||
//! - \b MPU_RGN_SIZE_8K
|
||||
//! - \b MPU_RGN_SIZE_16K
|
||||
//! - \b MPU_RGN_SIZE_32K
|
||||
//! - \b MPU_RGN_SIZE_64K
|
||||
//! - \b MPU_RGN_SIZE_128K
|
||||
//! - \b MPU_RGN_SIZE_256K
|
||||
//! - \b MPU_RGN_SIZE_512K
|
||||
//! - \b MPU_RGN_SIZE_1M
|
||||
//! - \b MPU_RGN_SIZE_2M
|
||||
//! - \b MPU_RGN_SIZE_4M
|
||||
//! - \b MPU_RGN_SIZE_8M
|
||||
//! - \b MPU_RGN_SIZE_16M
|
||||
//! - \b MPU_RGN_SIZE_32M
|
||||
//! - \b MPU_RGN_SIZE_64M
|
||||
//! - \b MPU_RGN_SIZE_128M
|
||||
//! - \b MPU_RGN_SIZE_256M
|
||||
//! - \b MPU_RGN_SIZE_512M
|
||||
//! - \b MPU_RGN_SIZE_1G
|
||||
//! - \b MPU_RGN_SIZE_2G
|
||||
//! - \b MPU_RGN_SIZE_4G
|
||||
//!
|
||||
//! The execute permission flag must be one of the following:
|
||||
//!
|
||||
//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
|
||||
//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
|
||||
//!
|
||||
//! The read/write access permissions are applied separately for the
|
||||
//! privileged and user modes. The read/write access flags must be one
|
||||
//! of the following:
|
||||
//!
|
||||
//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
|
||||
//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
|
||||
//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
|
||||
//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
|
||||
//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
|
||||
//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
|
||||
//!
|
||||
//! The region is automatically divided into 8 equally-sized sub-regions by
|
||||
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
|
||||
//! or larger. Any of these 8 sub-regions can be disabled, allowing for
|
||||
//! creation of ``holes'' in a region which can be left open, or overlaid
|
||||
//! by another region with different attributes. Any of the 8 sub-regions
|
||||
//! can be disabled with a logical OR of any of the following flags:
|
||||
//!
|
||||
//! - \b MPU_SUB_RGN_DISABLE_0
|
||||
//! - \b MPU_SUB_RGN_DISABLE_1
|
||||
//! - \b MPU_SUB_RGN_DISABLE_2
|
||||
//! - \b MPU_SUB_RGN_DISABLE_3
|
||||
//! - \b MPU_SUB_RGN_DISABLE_4
|
||||
//! - \b MPU_SUB_RGN_DISABLE_5
|
||||
//! - \b MPU_SUB_RGN_DISABLE_6
|
||||
//! - \b MPU_SUB_RGN_DISABLE_7
|
||||
//!
|
||||
//! Finally, the region can be initially enabled or disabled with one of
|
||||
//! the following flags:
|
||||
//!
|
||||
//! - \b MPU_RGN_ENABLE
|
||||
//! - \b MPU_RGN_DISABLE
|
||||
//!
|
||||
//! As an example, to set a region with the following attributes: size of
|
||||
//! 32 KB, execution enabled, read-only for both privileged and user, one
|
||||
//! sub-region disabled, and initially enabled; the \e ui32Flags parameter
|
||||
//! would have the following value:
|
||||
//!
|
||||
//! <code>
|
||||
//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
|
||||
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
|
||||
//! </code>
|
||||
//!
|
||||
//! \note This function writes to multiple registers and is not protected
|
||||
//! from interrupts. It is possible that an interrupt which accesses a
|
||||
//! region may occur while that region is in the process of being changed.
|
||||
//! The safest way to handle this is to disable a region before changing it.
|
||||
//! Refer to the discussion of this in the API Detailed Description section.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Region < 8);
|
||||
ASSERT(ui32Addr ==
|
||||
(ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)));
|
||||
|
||||
//
|
||||
// Program the base address, use the region field to select the
|
||||
// region at the same time.
|
||||
//
|
||||
HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID;
|
||||
|
||||
//
|
||||
// Program the region attributes. Set the TEX field and the S, C,
|
||||
// and B bits to fixed values that are suitable for all Tiva C and
|
||||
// E Series memory.
|
||||
//
|
||||
HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M |
|
||||
NVIC_MPU_ATTR_CACHEABLE)) |
|
||||
NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current settings for a specific region.
|
||||
//!
|
||||
//! \param ui32Region is the region number to get.
|
||||
//! \param pui32Addr points to storage for the base address of the region.
|
||||
//! \param pui32Flags points to the attribute flags for the region.
|
||||
//!
|
||||
//! This function retrieves the configuration of a specific region. The
|
||||
//! meanings and format of the parameters is the same as that of the
|
||||
//! MPURegionSet() function.
|
||||
//!
|
||||
//! This function can be used to save the configuration of a region for later
|
||||
//! use with the MPURegionSet() function. The region's enable state is
|
||||
//! preserved in the attributes that are saved.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ui32Region < 8);
|
||||
ASSERT(pui32Addr);
|
||||
ASSERT(pui32Flags);
|
||||
|
||||
//
|
||||
// Select the region to get.
|
||||
//
|
||||
HWREG(NVIC_MPU_NUMBER) = ui32Region;
|
||||
|
||||
//
|
||||
// Read and store the base address for the region.
|
||||
//
|
||||
*pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M;
|
||||
|
||||
//
|
||||
// Read and store the region attributes.
|
||||
//
|
||||
*pui32Flags = HWREG(NVIC_MPU_ATTR);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the memory management fault.
|
||||
//!
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! memory management fault occurs.
|
||||
//!
|
||||
//! This function sets and enables the handler to be called when the MPU
|
||||
//! generates a memory management fault due to a protection region access
|
||||
//! violation.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPUIntRegister(void (*pfnHandler)(void))
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(pfnHandler);
|
||||
|
||||
//
|
||||
// Register the interrupt handler.
|
||||
//
|
||||
IntRegister(FAULT_MPU, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the memory management fault.
|
||||
//
|
||||
IntEnable(FAULT_MPU);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters an interrupt handler for the memory management fault.
|
||||
//!
|
||||
//! This function disables and clears the handler to be called when a
|
||||
//! memory management fault occurs.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
MPUIntUnregister(void)
|
||||
{
|
||||
//
|
||||
// Disable the interrupt.
|
||||
//
|
||||
IntDisable(FAULT_MPU);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(FAULT_MPU);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,162 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// mpu.h - Defines and Macros for the memory protection unit.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_MPU_H__
|
||||
#define __DRIVERLIB_MPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags that can be passed to MPUEnable.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MPU_CONFIG_PRIV_DEFAULT 4
|
||||
#define MPU_CONFIG_HARDFLT_NMI 2
|
||||
#define MPU_CONFIG_NONE 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags for the region size to be passed to MPURegionSet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MPU_RGN_SIZE_32B (4 << 1)
|
||||
#define MPU_RGN_SIZE_64B (5 << 1)
|
||||
#define MPU_RGN_SIZE_128B (6 << 1)
|
||||
#define MPU_RGN_SIZE_256B (7 << 1)
|
||||
#define MPU_RGN_SIZE_512B (8 << 1)
|
||||
|
||||
#define MPU_RGN_SIZE_1K (9 << 1)
|
||||
#define MPU_RGN_SIZE_2K (10 << 1)
|
||||
#define MPU_RGN_SIZE_4K (11 << 1)
|
||||
#define MPU_RGN_SIZE_8K (12 << 1)
|
||||
#define MPU_RGN_SIZE_16K (13 << 1)
|
||||
#define MPU_RGN_SIZE_32K (14 << 1)
|
||||
#define MPU_RGN_SIZE_64K (15 << 1)
|
||||
#define MPU_RGN_SIZE_128K (16 << 1)
|
||||
#define MPU_RGN_SIZE_256K (17 << 1)
|
||||
#define MPU_RGN_SIZE_512K (18 << 1)
|
||||
|
||||
#define MPU_RGN_SIZE_1M (19 << 1)
|
||||
#define MPU_RGN_SIZE_2M (20 << 1)
|
||||
#define MPU_RGN_SIZE_4M (21 << 1)
|
||||
#define MPU_RGN_SIZE_8M (22 << 1)
|
||||
#define MPU_RGN_SIZE_16M (23 << 1)
|
||||
#define MPU_RGN_SIZE_32M (24 << 1)
|
||||
#define MPU_RGN_SIZE_64M (25 << 1)
|
||||
#define MPU_RGN_SIZE_128M (26 << 1)
|
||||
#define MPU_RGN_SIZE_256M (27 << 1)
|
||||
#define MPU_RGN_SIZE_512M (28 << 1)
|
||||
|
||||
#define MPU_RGN_SIZE_1G (29 << 1)
|
||||
#define MPU_RGN_SIZE_2G (30 << 1)
|
||||
#define MPU_RGN_SIZE_4G (31 << 1)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags for the permissions to be passed to MPURegionSet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MPU_RGN_PERM_EXEC 0x00000000
|
||||
#define MPU_RGN_PERM_NOEXEC 0x10000000
|
||||
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
|
||||
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
|
||||
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
|
||||
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
|
||||
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
|
||||
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags for the sub-region to be passed to MPURegionSet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MPU_SUB_RGN_DISABLE_0 0x00000100
|
||||
#define MPU_SUB_RGN_DISABLE_1 0x00000200
|
||||
#define MPU_SUB_RGN_DISABLE_2 0x00000400
|
||||
#define MPU_SUB_RGN_DISABLE_3 0x00000800
|
||||
#define MPU_SUB_RGN_DISABLE_4 0x00001000
|
||||
#define MPU_SUB_RGN_DISABLE_5 0x00002000
|
||||
#define MPU_SUB_RGN_DISABLE_6 0x00004000
|
||||
#define MPU_SUB_RGN_DISABLE_7 0x00008000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags to enable or disable a region, to be passed to MPURegionSet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MPU_RGN_ENABLE 1
|
||||
#define MPU_RGN_DISABLE 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void MPUEnable(uint32_t ui32MPUConfig);
|
||||
extern void MPUDisable(void);
|
||||
extern uint32_t MPURegionCountGet(void);
|
||||
extern void MPURegionEnable(uint32_t ui32Region);
|
||||
extern void MPURegionDisable(uint32_t ui32Region);
|
||||
extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr,
|
||||
uint32_t ui32Flags);
|
||||
extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr,
|
||||
uint32_t *pui32Flags);
|
||||
extern void MPUIntRegister(void (*pfnHandler)(void));
|
||||
extern void MPUIntUnregister(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_MPU_H__
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,295 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_PWM_H__
|
||||
#define __DRIVERLIB_PWM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines are passed to PWMGenConfigure() as the ui32Config
|
||||
// parameter and specify the configuration of the PWM generator.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
|
||||
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
|
||||
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
|
||||
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
|
||||
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
|
||||
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
|
||||
#define PWM_GEN_MODE_FAULT_LATCHED \
|
||||
0x00040000 // Fault is latched
|
||||
#define PWM_GEN_MODE_FAULT_UNLATCHED \
|
||||
0x00000000 // Fault is not latched
|
||||
#define PWM_GEN_MODE_FAULT_MINPER \
|
||||
0x00020000 // Enable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_NO_MINPER \
|
||||
0x00000000 // Disable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
|
||||
#define PWM_GEN_MODE_FAULT_LEGACY \
|
||||
0x00000000 // Disable extended fault support
|
||||
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
|
||||
0x0000A800 // Deadband updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
|
||||
0x0000FC00 // Deadband updates globally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_NO_SYNC \
|
||||
0x00000000 // Generator mode updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
|
||||
0x00000280 // Generator mode updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
|
||||
0x000003C0 // Generator mode updates globally
|
||||
// synchronized
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM generator interrupts and
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
|
||||
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
|
||||
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
|
||||
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
|
||||
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
|
||||
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
|
||||
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
|
||||
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
|
||||
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
|
||||
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the generators within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
|
||||
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
|
||||
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
|
||||
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
|
||||
|
||||
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
|
||||
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
|
||||
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
|
||||
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
|
||||
|
||||
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
|
||||
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
|
||||
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
|
||||
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the outputs within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
|
||||
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
|
||||
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
|
||||
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
|
||||
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
|
||||
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
|
||||
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
|
||||
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
|
||||
|
||||
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
|
||||
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
|
||||
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
|
||||
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
|
||||
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
|
||||
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
|
||||
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
|
||||
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_0 0
|
||||
|
||||
#define PWM_FAULT_FAULT0 0x00000001
|
||||
#define PWM_FAULT_FAULT1 0x00000002
|
||||
#define PWM_FAULT_FAULT2 0x00000004
|
||||
#define PWM_FAULT_FAULT3 0x00000008
|
||||
#define PWM_FAULT_ACMP0 0x00010000
|
||||
#define PWM_FAULT_ACMP1 0x00020000
|
||||
#define PWM_FAULT_ACMP2 0x00040000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_1.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_1 1
|
||||
|
||||
#define PWM_FAULT_DCMP0 0x00000001
|
||||
#define PWM_FAULT_DCMP1 0x00000002
|
||||
#define PWM_FAULT_DCMP2 0x00000004
|
||||
#define PWM_FAULT_DCMP3 0x00000008
|
||||
#define PWM_FAULT_DCMP4 0x00000010
|
||||
#define PWM_FAULT_DCMP5 0x00000020
|
||||
#define PWM_FAULT_DCMP6 0x00000040
|
||||
#define PWM_FAULT_DCMP7 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the sense of each of the external FAULTn signals
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT0_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT0_SENSE_LOW 0x00000001
|
||||
#define PWM_FAULT1_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT1_SENSE_LOW 0x00000002
|
||||
#define PWM_FAULT2_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT2_SENSE_LOW 0x00000004
|
||||
#define PWM_FAULT3_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT3_SENSE_LOW 0x00000008
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32Config);
|
||||
extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32Period);
|
||||
extern uint32_t PWMGenPeriodGet(uint32_t ui32Base,
|
||||
uint32_t ui32Gen);
|
||||
extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen);
|
||||
extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen);
|
||||
extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut,
|
||||
uint32_t ui32Width);
|
||||
extern uint32_t PWMPulseWidthGet(uint32_t ui32Base,
|
||||
uint32_t ui32PWMOut);
|
||||
extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint16_t ui16Rise, uint16_t ui16Fall);
|
||||
extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen);
|
||||
extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits);
|
||||
extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits);
|
||||
extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits,
|
||||
bool bEnable);
|
||||
extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits,
|
||||
bool bInvert);
|
||||
extern void PWMOutputFaultLevel(uint32_t ui32Base,
|
||||
uint32_t ui32PWMOutBits,
|
||||
bool bDriveHigh);
|
||||
extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits,
|
||||
bool bFaultSuppress);
|
||||
extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen);
|
||||
extern void PWMFaultIntRegister(uint32_t ui32Base,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMFaultIntUnregister(uint32_t ui32Base);
|
||||
extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32IntTrig);
|
||||
extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32IntTrig);
|
||||
extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
bool bMasked);
|
||||
extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32Ints);
|
||||
extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault);
|
||||
extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault);
|
||||
extern void PWMFaultIntClear(uint32_t ui32Base);
|
||||
extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void PWMFaultIntClearExt(uint32_t ui32Base,
|
||||
uint32_t ui32FaultInts);
|
||||
extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32MinFaultPeriod,
|
||||
uint32_t ui32FaultSenses);
|
||||
extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32Group,
|
||||
uint32_t ui32FaultTriggers);
|
||||
extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base,
|
||||
uint32_t ui32Gen,
|
||||
uint32_t ui32Group);
|
||||
extern uint32_t PWMGenFaultStatus(uint32_t ui32Base,
|
||||
uint32_t ui32Gen,
|
||||
uint32_t ui32Group);
|
||||
extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen,
|
||||
uint32_t ui32Group,
|
||||
uint32_t ui32FaultTriggers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_PWM_H__
|
|
@ -0,0 +1,682 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// qei.c - Driver for the Quadrature Encoder with Index.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup qei_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_qei.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
#include "driverlib/qei.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the quadrature encoder.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function enables operation of the quadrature encoder module. The
|
||||
//! module must be configured before it is enabled.
|
||||
//!
|
||||
//! \sa QEIConfigure()
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Enable the QEI module.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the quadrature encoder.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function disables operation of the quadrature encoder module.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIDisable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Disable the QEI module.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Configures the quadrature encoder.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32Config is the configuration for the quadrature encoder. See
|
||||
//! below for a description of this parameter.
|
||||
//! \param ui32MaxPosition specifies the maximum position value.
|
||||
//!
|
||||
//! This function configures the operation of the quadrature encoder. The
|
||||
//! \e ui32Config parameter provides the configuration of the encoder and is
|
||||
//! the logical OR of several values:
|
||||
//!
|
||||
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges
|
||||
//! on channel A or on both channels A and B should be counted by the
|
||||
//! position integrator and velocity accumulator.
|
||||
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the
|
||||
//! position integrator should be reset when the index pulse is detected.
|
||||
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if
|
||||
//! quadrature signals are being provided on ChA and ChB, or if a direction
|
||||
//! signal and a clock are being provided instead.
|
||||
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
|
||||
//! provided on ChA and ChB should be swapped before being processed.
|
||||
//!
|
||||
//! \e ui32MaxPosition is the maximum value of the position integrator and is
|
||||
//! the value used to reset the position capture when in index reset mode and
|
||||
//! moving in the reverse (negative) direction.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
|
||||
uint32_t ui32MaxPosition)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Write the new configuration to the hardware.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) &
|
||||
~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
|
||||
QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
|
||||
ui32Config);
|
||||
|
||||
//
|
||||
// Set the maximum position.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_MAXPOS) = ui32MaxPosition;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current encoder position.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function returns the current position of the encoder. Depending upon
|
||||
//! the configuration of the encoder, and the incident of an index pulse, this
|
||||
//! value may or may not contain the expected data (that is, if in reset on
|
||||
//! index mode, if an index pulse has not been encountered, the position
|
||||
//! counter is not yet aligned with the index pulse).
|
||||
//!
|
||||
//! \return The current position of the encoder.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
QEIPositionGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Return the current position counter.
|
||||
//
|
||||
return(HWREG(ui32Base + QEI_O_POS));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the current encoder position.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32Position is the new position for the encoder.
|
||||
//!
|
||||
//! This function sets the current position of the encoder; the encoder
|
||||
//! position is then measured relative to this value.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Set the position counter.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_POS) = ui32Position;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current direction of rotation.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function returns the current direction of rotation. In this case,
|
||||
//! current means the most recently detected direction of the encoder; it may
|
||||
//! not be presently moving but this is the direction it last moved before it
|
||||
//! stopped.
|
||||
//!
|
||||
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
|
||||
//! reverse direction.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
QEIDirectionGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Return the direction of rotation.
|
||||
//
|
||||
return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the encoder error indicator.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function returns the error indicator for the quadrature encoder. It
|
||||
//! is an error for both of the signals of the quadrature input to change at
|
||||
//! the same time.
|
||||
//!
|
||||
//! \return Returns \b true if an error has occurred and \b false otherwise.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
QEIErrorGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Return the error indicator.
|
||||
//
|
||||
return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the velocity capture.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function enables operation of the velocity capture in the quadrature
|
||||
//! encoder module. The module must be configured before velocity capture is
|
||||
//! enabled.
|
||||
//!
|
||||
//! \sa QEIVelocityConfigure() and QEIEnable()
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIVelocityEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Enable the velocity capture.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_VELEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the velocity capture.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function disables operation of the velocity capture in the quadrature
|
||||
//! encoder module.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIVelocityDisable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Disable the velocity capture.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Configures the velocity capture.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32PreDiv specifies the predivider applied to the input quadrature
|
||||
//! signal before it is counted; can be one of \b QEI_VELDIV_1,
|
||||
//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
|
||||
//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
|
||||
//! \param ui32Period specifies the number of clock ticks over which to measure
|
||||
//! the velocity; must be non-zero.
|
||||
//!
|
||||
//! This function configures the operation of the velocity capture portion of
|
||||
//! the quadrature encoder. The position increment signal is predivided as
|
||||
//! specified by \e ui32PreDiv before being accumulated by the velocity
|
||||
//! capture. The divided signal is accumulated over \e ui32Period system clock
|
||||
//! before being saved and resetting the accumulator.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
|
||||
uint32_t ui32Period)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
ASSERT(!(ui32PreDiv & ~(QEI_CTL_VELDIV_M)));
|
||||
ASSERT(ui32Period != 0);
|
||||
|
||||
//
|
||||
// Set the velocity predivider.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) &
|
||||
~(QEI_CTL_VELDIV_M)) | ui32PreDiv);
|
||||
|
||||
//
|
||||
// Set the timer period.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_LOAD) = ui32Period - 1;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current encoder speed.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function returns the current speed of the encoder. The value returned
|
||||
//! is the number of pulses detected in the specified time period; this number
|
||||
//! can be multiplied by the number of time periods per second and divided by
|
||||
//! the number of pulses per revolution to obtain the number of revolutions per
|
||||
//! second.
|
||||
//!
|
||||
//! \return Returns the number of pulses captured in the given time period.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
QEIVelocityGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Return the speed capture value.
|
||||
//
|
||||
return(HWREG(ui32Base + QEI_O_SPEED));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the quadrature encoder interrupt number.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the selected quadrature encoder
|
||||
//!
|
||||
//! This function returns the interrupt number for the quadrature encoder with
|
||||
//! the base address passed in the \e ui32Base parameter.
|
||||
//!
|
||||
//! \return Returns a quadrature encoder interrupt number or 0 if the interrupt
|
||||
//! does not exist.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static uint32_t
|
||||
_QEIIntNumberGet(uint32_t ui32Base)
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Find the valid interrupt number for this quadrature encoder.
|
||||
//
|
||||
if(CLASS_IS_BLIZZARD)
|
||||
{
|
||||
if(ui32Base == QEI0_BASE)
|
||||
{
|
||||
ui32Int = INT_QEI0_BLIZZARD;
|
||||
}
|
||||
else
|
||||
{
|
||||
ui32Int = INT_QEI1_BLIZZARD;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ui32Int = 0;
|
||||
}
|
||||
|
||||
return(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the quadrature encoder interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! quadrature encoder interrupt occurs.
|
||||
//!
|
||||
//! This function registers the handler to be called when a quadrature encoder
|
||||
//! interrupt occurs. This function enables the global interrupt in the
|
||||
//! interrupt controller; specific quadrature encoder interrupts must be
|
||||
//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility
|
||||
//! to clear the interrupt source via QEIIntClear().
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Determine the interrupt number based on the QEI module.
|
||||
//
|
||||
ui32Int = _QEIIntNumberGet(ui32Base);
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Register the interrupt handler, returning an error if an error occurs.
|
||||
//
|
||||
IntRegister(ui32Int, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the quadrature encoder interrupt.
|
||||
//
|
||||
IntEnable(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters an interrupt handler for the quadrature encoder interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//!
|
||||
//! This function unregisters the handler to be called when a quadrature
|
||||
//! encoder interrupt occurs. This function also masks off the interrupt in
|
||||
//! the interrupt controller so that the interrupt handler no longer is called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIIntUnregister(uint32_t ui32Base)
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Determine the interrupt number based on the QEI module.
|
||||
//
|
||||
ui32Int = _QEIIntNumberGet(ui32Base);
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Disable the interrupt.
|
||||
//
|
||||
IntDisable(ui32Int);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables individual quadrature encoder interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
|
||||
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
|
||||
//! \b QEI_INTINDEX values.
|
||||
//!
|
||||
//! This function enables the indicated quadrature encoder interrupt sources.
|
||||
//! Only the sources that are enabled can be reflected to the processor
|
||||
//! interrupt; disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Enable the specified interrupts.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_INTEN) |= ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables individual quadrature encoder interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
|
||||
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
|
||||
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
|
||||
//!
|
||||
//! This function disables the indicated quadrature encoder interrupt sources.
|
||||
//! Only the sources that are enabled can be reflected to the processor
|
||||
//! interrupt; disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Disable the specified interrupts.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_INTEN) &= ~(ui32IntFlags);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current interrupt status.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param bMasked is false if the raw interrupt status is required and true if
|
||||
//! the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the interrupt status for the quadrature encoder
|
||||
//! module. Either the raw interrupt status or the status of interrupts that
|
||||
//! are allowed to reflect to the processor can be returned.
|
||||
//!
|
||||
//! \return Returns the current interrupt status, enumerated as a bit field of
|
||||
//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
QEIIntStatus(uint32_t ui32Base, bool bMasked)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(HWREG(ui32Base + QEI_O_ISC));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(HWREG(ui32Base + QEI_O_RIS));
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears quadrature encoder interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the quadrature encoder module.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
|
||||
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
|
||||
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
|
||||
//!
|
||||
//! The specified quadrature encoder interrupt sources are cleared, so that
|
||||
//! they no longer assert. This function must be called in the interrupt
|
||||
//! handler to keep the interrupt from being triggered again immediately upon
|
||||
//! exit.
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
|
||||
|
||||
//
|
||||
// Clear the requested interrupt sources.
|
||||
//
|
||||
HWREG(ui32Base + QEI_O_ISC) = ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,128 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// qei.h - Prototypes for the Quadrature Encoder Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_QEI_H__
|
||||
#define __DRIVERLIB_QEI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to QEIConfigure as the ui32Config paramater.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
|
||||
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
|
||||
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
|
||||
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
|
||||
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
|
||||
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
|
||||
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
|
||||
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
|
||||
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
|
||||
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
|
||||
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
|
||||
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
|
||||
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
|
||||
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
|
||||
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
|
||||
// as the ui32IntFlags parameter, and returned by QEIGetIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_INTERROR 0x00000008 // Phase error detected
|
||||
#define QEI_INTDIR 0x00000004 // Direction change
|
||||
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
|
||||
#define QEI_INTINDEX 0x00000001 // Index pulse detected
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void QEIEnable(uint32_t ui32Base);
|
||||
extern void QEIDisable(uint32_t ui32Base);
|
||||
extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
|
||||
uint32_t ui32MaxPosition);
|
||||
extern uint32_t QEIPositionGet(uint32_t ui32Base);
|
||||
extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position);
|
||||
extern int32_t QEIDirectionGet(uint32_t ui32Base);
|
||||
extern bool QEIErrorGet(uint32_t ui32Base);
|
||||
extern void QEIVelocityEnable(uint32_t ui32Base);
|
||||
extern void QEIVelocityDisable(uint32_t ui32Base);
|
||||
extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
|
||||
uint32_t ui32Period);
|
||||
extern uint32_t QEIVelocityGet(uint32_t ui32Base);
|
||||
extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern void QEIIntUnregister(uint32_t ui32Base);
|
||||
extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_QEI_H__
|
|
@ -0,0 +1,36 @@
|
|||
This project will build the TivaWare Peripheral Driver Library.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
Software License Agreement
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
Neither the name of Texas Instruments Incorporated nor the names of
|
||||
its contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,108 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// rtos_bindings.h - Macros intended to aid porting of TivaWare modules
|
||||
// for use with an RTOS.
|
||||
//
|
||||
// Copyright (c) 2012-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_RTOS_BINDINGS_H__
|
||||
#define __DRIVERLIB_RTOS_BINDINGS_H__
|
||||
|
||||
#ifdef USE_RTOS
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If an RTOS is in use, implement a header file called "tiva_rtos.h"
|
||||
// which contains RTOS-specific versions of each of the macros defined below
|
||||
// and make sure it appears on the include path set when you build your
|
||||
// project.
|
||||
//
|
||||
// Note that there is no default implementation of this header file included
|
||||
// in TivaWare - it is your responsibility to create it specifically for
|
||||
// your RTOS.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#include "tiva_rtos.h"
|
||||
|
||||
#else
|
||||
//*****************************************************************************
|
||||
//
|
||||
// When no RTOS is in use, the follow macros compile to either nothing or a
|
||||
// minimal implementation that works in a bare-metal environment.
|
||||
//
|
||||
// Each of these macros must be redefined in tiva_rtos.h if you are using
|
||||
// TivaWare under an RTOS.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// A simple macro used to yield within polling loops. In the default, non-RTOS
|
||||
// implementation, this compiles to nothing.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define OS_YIELD()
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// A simple macro around the SysCtlDelay function. The parameter is the number
|
||||
// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS
|
||||
// implementation, this could be replaced with an OS delay call with
|
||||
// appropriate parameter scaling.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Wrappers around low level interrupt control functions. For information
|
||||
// on each of these functions, please see the appropriate API documentation
|
||||
// for the DriverLib Interrupt driver.
|
||||
//
|
||||
// The macros defined here represent interrupt-control functions that may be
|
||||
// called from within TivaWare code. It is expected that application
|
||||
// code will use RTOS-specific functions to control interrupt priority, to
|
||||
// pend interrupts and to perform runtime vector manipulation. As a result,
|
||||
// no macros are defined to wrap any of these functions from interrupt.c.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
|
||||
#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
|
||||
#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID)
|
||||
#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID)
|
||||
|
||||
#endif // USE_RTOS
|
||||
|
||||
#endif // __DRIVERLIB_RTOS_BINDINGS_H__
|
|
@ -0,0 +1,879 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// ssi.c - Driver for Synchronous Serial Interface.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup ssi_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_ssi.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
#include "driverlib/ssi.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// A mapping of timer base address to interrupt number.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_ppui32SSIIntMap[][2] =
|
||||
{
|
||||
{ SSI0_BASE, INT_SSI0_BLIZZARD },
|
||||
{ SSI1_BASE, INT_SSI1_BLIZZARD },
|
||||
{ SSI2_BASE, INT_SSI2_BLIZZARD },
|
||||
{ SSI3_BASE, INT_SSI3_BLIZZARD },
|
||||
};
|
||||
static const uint_fast8_t g_ui8SSIIntMapRows =
|
||||
sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! Checks an SSI base address.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//!
|
||||
//! This function determines if a SSI module base address is valid.
|
||||
//!
|
||||
//! \return Returns \b true if the base address is valid and \b false
|
||||
//! otherwise.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
static bool
|
||||
_SSIBaseValid(uint32_t ui32Base)
|
||||
{
|
||||
return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) ||
|
||||
(ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE));
|
||||
}
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the interrupt number of SSI module .
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI module.
|
||||
//!
|
||||
//! This function returns the interrupt number for the SSI module with the base
|
||||
//! address passed in the \e ui32Base parameter.
|
||||
//!
|
||||
//! \return Returns an SSI interrupt number, or 0 if the interrupt does not
|
||||
//! exist.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static uint32_t
|
||||
_SSIIntNumberGet(uint32_t ui32Base)
|
||||
{
|
||||
uint_fast8_t ui8Idx, ui8Rows;
|
||||
const uint32_t (*ppui32SSIIntMap)[2];
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
ppui32SSIIntMap = g_ppui32SSIIntMap;
|
||||
ui8Rows = g_ui8SSIIntMapRows;
|
||||
|
||||
//
|
||||
// Loop through the table that maps SSI base addresses to interrupt
|
||||
// numbers.
|
||||
//
|
||||
for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
|
||||
{
|
||||
//
|
||||
// See if this base address matches.
|
||||
//
|
||||
if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
|
||||
{
|
||||
//
|
||||
// Return the corresponding interrupt number.
|
||||
//
|
||||
return(ppui32SSIIntMap[ui8Idx][1]);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// The base address could not be found, so return an error.
|
||||
//
|
||||
return(0);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Configures the synchronous serial interface.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32SSIClk is the rate of the clock supplied to the SSI module.
|
||||
//! \param ui32Protocol specifies the data transfer protocol.
|
||||
//! \param ui32Mode specifies the mode of operation.
|
||||
//! \param ui32BitRate specifies the clock rate.
|
||||
//! \param ui32DataWidth specifies number of bits transferred per frame.
|
||||
//!
|
||||
//! This function configures the synchronous serial interface. It sets
|
||||
//! the SSI protocol, mode of operation, bit rate, and data width.
|
||||
//!
|
||||
//! The \e ui32Protocol parameter defines the data frame format. The
|
||||
//! \e ui32Protocol parameter can be one of the following values:
|
||||
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
|
||||
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
|
||||
//! frame formats encode the following polarity and phase configurations:
|
||||
//!
|
||||
//! <pre>
|
||||
//! Polarity Phase Mode
|
||||
//! 0 0 SSI_FRF_MOTO_MODE_0
|
||||
//! 0 1 SSI_FRF_MOTO_MODE_1
|
||||
//! 1 0 SSI_FRF_MOTO_MODE_2
|
||||
//! 1 1 SSI_FRF_MOTO_MODE_3
|
||||
//! </pre>
|
||||
//!
|
||||
//! The \e ui32Mode parameter defines the operating mode of the SSI module.
|
||||
//! The SSI module can operate as a master or slave; if it is a slave, the SSI
|
||||
//! can be configured to disable output on its serial output line. The
|
||||
//! \e ui32Mode parameter can be one of the following values:
|
||||
//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
|
||||
//!
|
||||
//! The \e ui32BitRate parameter defines the bit rate for the SSI. This bit
|
||||
//! rate must satisfy the following clock ratio criteria:
|
||||
//!
|
||||
//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz.
|
||||
//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the
|
||||
//! capability of the specific microcontroller
|
||||
//!
|
||||
//! where FSSI is the frequency of the clock supplied to the SSI module.
|
||||
//!
|
||||
//! The \e ui32DataWidth parameter defines the width of the data transfers and
|
||||
//! can be a value between 4 and 16, inclusive.
|
||||
//!
|
||||
//! The peripheral clock is the same as the processor clock. This value is
|
||||
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
|
||||
//! constant and known (to save the code/execution overhead of a call to
|
||||
//! SysCtlClockGet()).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
|
||||
uint32_t ui32Protocol, uint32_t ui32Mode,
|
||||
uint32_t ui32BitRate, uint32_t ui32DataWidth)
|
||||
{
|
||||
uint32_t ui32MaxBitRate;
|
||||
uint32_t ui32RegVal;
|
||||
uint32_t ui32PreDiv;
|
||||
uint32_t ui32SCR;
|
||||
uint32_t ui32SPH_SPO;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) ||
|
||||
(ui32Protocol == SSI_FRF_MOTO_MODE_1) ||
|
||||
(ui32Protocol == SSI_FRF_MOTO_MODE_2) ||
|
||||
(ui32Protocol == SSI_FRF_MOTO_MODE_3) ||
|
||||
(ui32Protocol == SSI_FRF_TI) ||
|
||||
(ui32Protocol == SSI_FRF_NMW));
|
||||
ASSERT((ui32Mode == SSI_MODE_MASTER) ||
|
||||
(ui32Mode == SSI_MODE_SLAVE) ||
|
||||
(ui32Mode == SSI_MODE_SLAVE_OD));
|
||||
ASSERT(((ui32Mode == SSI_MODE_MASTER) &&
|
||||
(ui32BitRate <= (ui32SSIClk / 2))) ||
|
||||
((ui32Mode != SSI_MODE_MASTER) &&
|
||||
(ui32BitRate <= (ui32SSIClk / 12))));
|
||||
ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256));
|
||||
ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16));
|
||||
|
||||
//
|
||||
// Set the mode.
|
||||
//
|
||||
ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
|
||||
ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
|
||||
HWREG(ui32Base + SSI_O_CR1) = ui32RegVal;
|
||||
|
||||
//
|
||||
// Set the clock predivider.
|
||||
//
|
||||
ui32MaxBitRate = ui32SSIClk / ui32BitRate;
|
||||
ui32PreDiv = 0;
|
||||
do
|
||||
{
|
||||
ui32PreDiv += 2;
|
||||
ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1;
|
||||
}
|
||||
while(ui32SCR > 255);
|
||||
HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv;
|
||||
|
||||
//
|
||||
// Set protocol and clock rate.
|
||||
//
|
||||
ui32SPH_SPO = (ui32Protocol & 3) << 6;
|
||||
ui32Protocol &= SSI_CR0_FRF_M;
|
||||
ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol |
|
||||
(ui32DataWidth - 1);
|
||||
HWREG(ui32Base + SSI_O_CR0) = ui32RegVal;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the synchronous serial interface.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//!
|
||||
//! This function enables operation of the synchronous serial interface. The
|
||||
//! synchronous serial interface must be configured before it is enabled.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Read-modify-write the enable bit.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the synchronous serial interface.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//!
|
||||
//! This function disables operation of the synchronous serial interface.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIDisable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Read-modify-write the enable bit.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the synchronous serial interface.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! synchronous serial interface interrupt occurs.
|
||||
//!
|
||||
//! This function registers the handler to be called when an SSI interrupt
|
||||
//! occurs. This function enables the global interrupt in the interrupt
|
||||
//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If
|
||||
//! necessary, it is the interrupt handler's responsibility to clear the
|
||||
//! interrupt source via SSIIntClear().
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Determine the interrupt number based on the SSI port.
|
||||
//
|
||||
ui32Int = _SSIIntNumberGet(ui32Base);
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Register the interrupt handler, returning an error if an error occurs.
|
||||
//
|
||||
IntRegister(ui32Int, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the synchronous serial interface interrupt.
|
||||
//
|
||||
IntEnable(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters an interrupt handler for the synchronous serial interface.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//!
|
||||
//! This function clears the handler to be called when an SSI interrupt
|
||||
//! occurs. This function also masks off the interrupt in the interrupt
|
||||
//! controller so that the interrupt handler no longer is called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIIntUnregister(uint32_t ui32Base)
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Determine the interrupt number based on the SSI port.
|
||||
//
|
||||
ui32Int = _SSIIntNumberGet(ui32Base);
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Disable the interrupt.
|
||||
//
|
||||
IntDisable(ui32Int);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables individual SSI interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
|
||||
//!
|
||||
//! This function enables the indicated SSI interrupt sources. Only the
|
||||
//! sources that are enabled can be reflected to the processor interrupt;
|
||||
//! disabled sources have no effect on the processor. The \e ui32IntFlags
|
||||
//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
|
||||
//! \b SSI_RXOR values.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Enable the specified interrupts.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables individual SSI interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
|
||||
//!
|
||||
//! This function disables the indicated SSI interrupt sources. The
|
||||
//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
|
||||
//! \b SSI_RXTO, or \b SSI_RXOR values.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Disable the specified interrupts.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current interrupt status.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param bMasked is \b false if the raw interrupt status is required or
|
||||
//! \b true if the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the interrupt status for the SSI module. Either the
|
||||
//! raw interrupt status or the status of interrupts that are allowed to
|
||||
//! reflect to the processor can be returned.
|
||||
//!
|
||||
//! \return The current interrupt status, enumerated as a bit field of
|
||||
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
SSIIntStatus(uint32_t ui32Base, bool bMasked)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(HWREG(ui32Base + SSI_O_MIS));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(HWREG(ui32Base + SSI_O_RIS));
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears SSI interrupt sources.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
|
||||
//!
|
||||
//! This function clears the specified SSI interrupt sources so that they no
|
||||
//! longer assert. This function must be called in the interrupt handler to
|
||||
//! keep the interrupts from being triggered again immediately upon exit. The
|
||||
//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and
|
||||
//! \b SSI_RXOR values.
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Clear the requested interrupt sources.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Puts a data element into the SSI transmit FIFO.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32Data is the data to be transmitted over the SSI interface.
|
||||
//!
|
||||
//! This function places the supplied data into the transmit FIFO of the
|
||||
//! specified SSI module. If there is no space available in the transmit FIFO,
|
||||
//! this function waits until there is space available before returning.
|
||||
//!
|
||||
//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
|
||||
//! where N is the data width as configured by SSIConfigSetExpClk(). For
|
||||
//! example, if the interface is configured for 8-bit data width, the upper 24
|
||||
//! bits of \e ui32Data are discarded.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIDataPut(uint32_t ui32Base, uint32_t ui32Data)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
|
||||
SSI_CR0_DSS_M))) == 0);
|
||||
|
||||
//
|
||||
// Wait until there is space.
|
||||
//
|
||||
while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF))
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Write the data to the SSI.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_DR) = ui32Data;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Puts a data element into the SSI transmit FIFO.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param ui32Data is the data to be transmitted over the SSI interface.
|
||||
//!
|
||||
//! This function places the supplied data into the transmit FIFO of the
|
||||
//! specified SSI module. If there is no space in the FIFO, then this function
|
||||
//! returns a zero.
|
||||
//!
|
||||
//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
|
||||
//! where N is the data width as configured by SSIConfigSetExpClk(). For
|
||||
//! example, if the interface is configured for 8-bit data width, the upper 24
|
||||
//! bits of \e ui32Data are discarded.
|
||||
//!
|
||||
//! \return Returns the number of elements written to the SSI transmit FIFO.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
|
||||
SSI_CR0_DSS_M))) == 0);
|
||||
|
||||
//
|
||||
// Check for space to write.
|
||||
//
|
||||
if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)
|
||||
{
|
||||
HWREG(ui32Base + SSI_O_DR) = ui32Data;
|
||||
return(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets a data element from the SSI receive FIFO.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param pui32Data is a pointer to a storage location for data that was
|
||||
//! received over the SSI interface.
|
||||
//!
|
||||
//! This function gets received data from the receive FIFO of the specified
|
||||
//! SSI module and places that data into the location specified by the
|
||||
//! \e pui32Data parameter. If there is no data available, this function waits
|
||||
//! until data is received before returning.
|
||||
//!
|
||||
//! \note Only the lower N bits of the value written to \e pui32Data contain
|
||||
//! valid data, where N is the data width as configured by
|
||||
//! SSIConfigSetExpClk(). For example, if the interface is configured for
|
||||
//! 8-bit data width, only the lower 8 bits of the value written to
|
||||
//! \e pui32Data contain valid data.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Wait until there is data to be read.
|
||||
//
|
||||
while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE))
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Read data from SSI.
|
||||
//
|
||||
*pui32Data = HWREG(ui32Base + SSI_O_DR);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets a data element from the SSI receive FIFO.
|
||||
//!
|
||||
//! \param ui32Base specifies the SSI module base address.
|
||||
//! \param pui32Data is a pointer to a storage location for data that was
|
||||
//! received over the SSI interface.
|
||||
//!
|
||||
//! This function gets received data from the receive FIFO of the specified SSI
|
||||
//! module and places that data into the location specified by the \e ui32Data
|
||||
//! parameter. If there is no data in the FIFO, then this function returns a
|
||||
//! zero.
|
||||
//!
|
||||
//! \note Only the lower N bits of the value written to \e pui32Data contain
|
||||
//! valid data, where N is the data width as configured by
|
||||
//! SSIConfigSetExpClk(). For example, if the interface is configured for
|
||||
//! 8-bit data width, only the lower 8 bits of the value written to
|
||||
//! \e pui32Data contain valid data.
|
||||
//!
|
||||
//! \return Returns the number of elements read from the SSI receive FIFO.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int32_t
|
||||
SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Check for data to read.
|
||||
//
|
||||
if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)
|
||||
{
|
||||
*pui32Data = HWREG(ui32Base + SSI_O_DR);
|
||||
return(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables SSI DMA operation.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI port.
|
||||
//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
|
||||
//!
|
||||
//! This function enables the specified SSI DMA features. The SSI can be
|
||||
//! configured to use DMA for transmit and/or receive data transfers.
|
||||
//! The \e ui32DMAFlags parameter is the logical OR of any of the following
|
||||
//! values:
|
||||
//!
|
||||
//! - SSI_DMA_RX - enable DMA for receive
|
||||
//! - SSI_DMA_TX - enable DMA for transmit
|
||||
//!
|
||||
//! \note The uDMA controller must also be set up before DMA can be used
|
||||
//! with the SSI.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Set the requested bits in the SSI DMA control register.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables SSI DMA operation.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI port.
|
||||
//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
|
||||
//!
|
||||
//! This function is used to disable SSI DMA features that were enabled
|
||||
//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
|
||||
//! \e ui32DMAFlags parameter is the logical OR of any of the following values:
|
||||
//!
|
||||
//! - SSI_DMA_RX - disable DMA for receive
|
||||
//! - SSI_DMA_TX - disable DMA for transmit
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Clear the requested bits in the SSI DMA control register.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Determines whether the SSI transmitter is busy or not.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI port.
|
||||
//!
|
||||
//! This function allows the caller to determine whether all transmitted bytes
|
||||
//! have cleared the transmitter hardware. If \b false is returned, then the
|
||||
//! transmit FIFO is empty and all bits of the last transmitted word have left
|
||||
//! the hardware shift register.
|
||||
//!
|
||||
//! \return Returns \b true if the SSI is transmitting or \b false if all
|
||||
//! transmissions are complete.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
SSIBusy(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Determine if the SSI is busy.
|
||||
//
|
||||
return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the data clock source for the specified SSI peripheral.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI port.
|
||||
//! \param ui32Source is the baud clock source for the SSI.
|
||||
//!
|
||||
//! This function allows the baud clock source for the SSI to be selected.
|
||||
//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
|
||||
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
|
||||
//!
|
||||
//! Changing the baud clock source changes the data rate generated by the
|
||||
//! SSI. Therefore, the data rate should be reconfigured after any change to
|
||||
//! the SSI clock source.
|
||||
//!
|
||||
//! \note The ability to specify the SSI baud clock source varies with the
|
||||
//! Tiva part and SSI in use. Please consult the data sheet for the part
|
||||
//! in use to determine whether this support is available.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
ASSERT((ui32Source == SSI_CLOCK_SYSTEM) ||
|
||||
(ui32Source == SSI_CLOCK_PIOSC));
|
||||
|
||||
//
|
||||
// Set the SSI clock source.
|
||||
//
|
||||
HWREG(ui32Base + SSI_O_CC) = ui32Source;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the data clock source for the specified SSI peripheral.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the SSI port.
|
||||
//!
|
||||
//! This function returns the data clock source for the specified SSI.
|
||||
//!
|
||||
//! \note The ability to specify the SSI data clock source varies with the
|
||||
//! Tiva part and SSI in use. Please consult the data sheet for the part
|
||||
//! in use to determine whether this support is available.
|
||||
//!
|
||||
//! \return Returns the current clock source, which will be either
|
||||
//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
SSIClockSourceGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(_SSIBaseValid(ui32Base));
|
||||
|
||||
//
|
||||
// Return the SSI clock source.
|
||||
//
|
||||
return(HWREG(ui32Base + SSI_O_CC));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,135 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_SSI_H__
|
||||
#define __DRIVERLIB_SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
|
||||
// as the ui32IntFlags parameter, and returned by SSIIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
|
||||
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
|
||||
#define SSI_RXTO 0x00000002 // RX timeout
|
||||
#define SSI_RXOR 0x00000001 // RX overrun
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIConfigSetExpClk.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
|
||||
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
|
||||
#define SSI_FRF_TI 0x00000010 // TI frame format
|
||||
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
|
||||
|
||||
#define SSI_MODE_MASTER 0x00000000 // SSI master
|
||||
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
|
||||
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIClockSourceSet() or returned from
|
||||
// SSIClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CLOCK_SYSTEM 0x00000000
|
||||
#define SSI_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
|
||||
uint32_t ui32Protocol, uint32_t ui32Mode,
|
||||
uint32_t ui32BitRate,
|
||||
uint32_t ui32DataWidth);
|
||||
extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
|
||||
extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base,
|
||||
uint32_t *pui32Data);
|
||||
extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
|
||||
extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
|
||||
extern void SSIDisable(uint32_t ui32Base);
|
||||
extern void SSIEnable(uint32_t ui32Base);
|
||||
extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void SSIIntUnregister(uint32_t ui32Base);
|
||||
extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
|
||||
extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
|
||||
extern bool SSIBusy(uint32_t ui32Base);
|
||||
extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
|
||||
extern uint32_t SSIClockSourceGet(uint32_t ui32Base);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_SSI_H__
|
|
@ -0,0 +1,770 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sw_crc.c - Software CRC functions.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup sw_crc_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "driverlib/sw_crc.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT).
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint8_t g_pui8Crc8CCITT[256] =
|
||||
{
|
||||
0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
|
||||
0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
|
||||
0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
|
||||
0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
|
||||
0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
|
||||
0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
|
||||
0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
|
||||
0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
|
||||
0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
|
||||
0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
|
||||
0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
|
||||
0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
|
||||
0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
|
||||
0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
|
||||
0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
|
||||
0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
|
||||
0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
|
||||
0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
|
||||
0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
|
||||
0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
|
||||
0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
|
||||
0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
|
||||
0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
|
||||
0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
|
||||
0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
|
||||
0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
|
||||
0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
|
||||
0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
|
||||
0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
|
||||
0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
|
||||
0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
|
||||
0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard
|
||||
// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI).
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint16_t g_pui16Crc16[256] =
|
||||
{
|
||||
0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
|
||||
0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
|
||||
0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
|
||||
0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
|
||||
0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
|
||||
0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
|
||||
0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
|
||||
0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
|
||||
0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
|
||||
0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
|
||||
0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
|
||||
0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
|
||||
0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
|
||||
0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
|
||||
0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
|
||||
0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
|
||||
0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
|
||||
0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
|
||||
0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
|
||||
0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
|
||||
0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
|
||||
0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
|
||||
0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
|
||||
0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
|
||||
0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
|
||||
0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
|
||||
0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
|
||||
0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
|
||||
0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
|
||||
0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
|
||||
0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
|
||||
0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 +
|
||||
// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard
|
||||
// CRC32 as used in Ethernet, MPEG-2, PNG, etc.).
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const uint32_t g_pui32Crc32[] =
|
||||
{
|
||||
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
|
||||
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
|
||||
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
|
||||
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
|
||||
0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
|
||||
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
|
||||
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
|
||||
0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
|
||||
0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
|
||||
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
|
||||
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
|
||||
0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
|
||||
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
|
||||
0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
|
||||
0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
|
||||
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
|
||||
0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
|
||||
0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
|
||||
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
|
||||
0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
|
||||
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
|
||||
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
|
||||
0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
|
||||
0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
|
||||
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
|
||||
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
|
||||
0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
|
||||
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
|
||||
0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
|
||||
0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
|
||||
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
|
||||
0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
|
||||
0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
|
||||
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
|
||||
0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
|
||||
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
|
||||
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
|
||||
0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
|
||||
0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
|
||||
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
|
||||
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
|
||||
0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
|
||||
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
|
||||
0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
|
||||
0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
|
||||
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
|
||||
0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
|
||||
0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
|
||||
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
|
||||
0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
|
||||
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
|
||||
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
|
||||
0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
|
||||
0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
|
||||
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
|
||||
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
|
||||
0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
|
||||
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
|
||||
0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
|
||||
0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
|
||||
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
|
||||
0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
|
||||
0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
|
||||
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This macro executes one iteration of the CRC-8-CCITT.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CRC8_ITER(crc, data) g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This macro executes one iteration of the CRC-16.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CRC16_ITER(crc, data) (((crc) >> 8) ^ \
|
||||
g_pui16Crc16[(uint8_t)((crc) ^ (data))])
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This macro executes one iteration of the CRC-32.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CRC32_ITER(crc, data) (((crc) >> 8) ^ \
|
||||
g_pui32Crc32[(uint8_t)((crc & 0xFF) ^ \
|
||||
(data))])
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Calculates the CRC-8-CCITT of an array of bytes.
|
||||
//!
|
||||
//! \param ui8Crc is the starting CRC-8-CCITT value.
|
||||
//! \param pui8Data is a pointer to the data buffer.
|
||||
//! \param ui32Count is the number of bytes in the data buffer.
|
||||
//!
|
||||
//! This function is used to calculate the CRC-8-CCITT of the input buffer.
|
||||
//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire
|
||||
//! data block that is to have its CRC-8-CCITT computed does not need to be
|
||||
//! supplied all at once. If the input buffer contains the entire block of
|
||||
//! data, then \b ui8Crc should be set to 0. If, however, the entire block of
|
||||
//! data is not available, then \b ui8Crc should be set to 0 for the first
|
||||
//! portion of the data, and then the returned value should be passed back in
|
||||
//! as \b ui8Crc for the next portion of the data.
|
||||
//!
|
||||
//! For example, to compute the CRC-8-CCITT of a block that has been split into
|
||||
//! three pieces, use the following:
|
||||
//!
|
||||
//! \verbatim
|
||||
//! ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1);
|
||||
//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2);
|
||||
//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3);
|
||||
//! \endverbatim
|
||||
//!
|
||||
//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the
|
||||
//! data is arriving via a serial link (for example) and is therefore not all
|
||||
//! available at one time.
|
||||
//!
|
||||
//! \return The CRC-8-CCITT of the input data.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint8_t
|
||||
Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count)
|
||||
{
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// If the data buffer is not 16 bit-aligned, then perform a single step of
|
||||
// the CRC to make it 16 bit-aligned.
|
||||
//
|
||||
if((uint32_t)pui8Data & 1)
|
||||
{
|
||||
//
|
||||
// Perform the CRC on this input byte.
|
||||
//
|
||||
ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
|
||||
|
||||
//
|
||||
// Skip this input byte.
|
||||
//
|
||||
pui8Data++;
|
||||
ui32Count--;
|
||||
}
|
||||
|
||||
//
|
||||
// If the data buffer is not word-aligned and there are at least two bytes
|
||||
// of data left, then perform two steps of the CRC to make it word-aligned.
|
||||
//
|
||||
if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
|
||||
{
|
||||
//
|
||||
// Read the next 16 bits.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// While there is at least a word remaining in the data buffer, perform
|
||||
// four steps of the CRC to consume a word.
|
||||
//
|
||||
while(ui32Count > 3)
|
||||
{
|
||||
//
|
||||
// Read the next word.
|
||||
//
|
||||
ui32Temp = *(uint32_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these four bytes.
|
||||
//
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16);
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 4;
|
||||
ui32Count -= 4;
|
||||
}
|
||||
|
||||
//
|
||||
// If there are 16 bits left in the input buffer, then perform two steps of
|
||||
// the CRC.
|
||||
//
|
||||
if(ui32Count > 1)
|
||||
{
|
||||
//
|
||||
// Read the 16 bits.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
|
||||
ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// If there is a final byte remaining in the input buffer, then perform a
|
||||
// single step of the CRC.
|
||||
//
|
||||
if(ui32Count != 0)
|
||||
{
|
||||
ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
|
||||
}
|
||||
|
||||
//
|
||||
// Return the resulting CRC-8-CCITT value.
|
||||
//
|
||||
return(ui8Crc);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Calculates the CRC-16 of an array of bytes.
|
||||
//!
|
||||
//! \param ui16Crc is the starting CRC-16 value.
|
||||
//! \param pui8Data is a pointer to the data buffer.
|
||||
//! \param ui32Count is the number of bytes in the data buffer.
|
||||
//!
|
||||
//! This function is used to calculate the CRC-16 of the input buffer. The
|
||||
//! CRC-16 is computed in a running fashion, meaning that the entire data block
|
||||
//! that is to have its CRC-16 computed does not need to be supplied all at
|
||||
//! once. If the input buffer contains the entire block of data, then
|
||||
//! \b ui16Crc should be set to 0. If, however, the entire block of data is
|
||||
//! not available, then \b ui16Crc should be set to 0 for the first portion of
|
||||
//! the data, and then the returned value should be passed back in as
|
||||
//! \b ui16Crc for the next portion of the data.
|
||||
//!
|
||||
//! For example, to compute the CRC-16 of a block that has been split into
|
||||
//! three pieces, use the following:
|
||||
//!
|
||||
//! \verbatim
|
||||
//! ui16Crc = Crc16(0, pui8Data1, ui32Len1);
|
||||
//! ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2);
|
||||
//! ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3);
|
||||
//! \endverbatim
|
||||
//!
|
||||
//! Computing a CRC-16 in a running fashion is useful in cases where the data
|
||||
//! is arriving via a serial link (for example) and is therefore not all
|
||||
//! available at one time.
|
||||
//!
|
||||
//! \return The CRC-16 of the input data.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint16_t
|
||||
Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count)
|
||||
{
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// If the data buffer is not 16 bit-aligned, then perform a single step of
|
||||
// the CRC to make it 16 bit-aligned.
|
||||
//
|
||||
if((uint32_t)pui8Data & 1)
|
||||
{
|
||||
//
|
||||
// Perform the CRC on this input byte.
|
||||
//
|
||||
ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
|
||||
|
||||
//
|
||||
// Skip this input byte.
|
||||
//
|
||||
pui8Data++;
|
||||
ui32Count--;
|
||||
}
|
||||
|
||||
//
|
||||
// If the data buffer is not word-aligned and there are at least two bytes
|
||||
// of data left, then perform two steps of the CRC to make it word-aligned.
|
||||
//
|
||||
if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
|
||||
{
|
||||
//
|
||||
// Read the next 16 bits.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// While there is at least a word remaining in the data buffer, perform
|
||||
// four steps of the CRC to consume a word.
|
||||
//
|
||||
while(ui32Count > 3)
|
||||
{
|
||||
//
|
||||
// Read the next word.
|
||||
//
|
||||
ui32Temp = *(uint32_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these four bytes.
|
||||
//
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 4;
|
||||
ui32Count -= 4;
|
||||
}
|
||||
|
||||
//
|
||||
// If there are two bytes left in the input buffer, then perform two steps
|
||||
// of the CRC.
|
||||
//
|
||||
if(ui32Count > 1)
|
||||
{
|
||||
//
|
||||
// Read the two bytes.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// If there is a final byte remaining in the input buffer, then perform a
|
||||
// single step of the CRC.
|
||||
//
|
||||
if(ui32Count != 0)
|
||||
{
|
||||
ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
|
||||
}
|
||||
|
||||
//
|
||||
// Return the resulting CRC-16 value.
|
||||
//
|
||||
return(ui16Crc);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Calculates the CRC-16 of an array of words.
|
||||
//!
|
||||
//! \param ui32WordLen is the length of the array in words (the number of bytes
|
||||
//! divided by 4).
|
||||
//! \param pui32Data is a pointer to the data buffer.
|
||||
//!
|
||||
//! This function is a wrapper around the running CRC-16 function, providing
|
||||
//! the CRC-16 for a single block of data.
|
||||
//!
|
||||
//! \return The CRC-16 of the input data.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint16_t
|
||||
Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data)
|
||||
{
|
||||
//
|
||||
// Calculate and return the CRC-16 of this array of words.
|
||||
//
|
||||
return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Calculates three CRC-16s of an array of words.
|
||||
//!
|
||||
//! \param ui32WordLen is the length of the array in words (the number of bytes
|
||||
//! divided by 4).
|
||||
//! \param pui32Data is a pointer to the data buffer.
|
||||
//! \param pui16Crc3 is a pointer to an array in which to place the three
|
||||
//! CRC-16 values.
|
||||
//!
|
||||
//! This function is used to calculate three CRC-16s of the input buffer; the
|
||||
//! first uses every byte from the array, the second uses only the even-index
|
||||
//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third
|
||||
//! uses only the odd-index bytes from the array (in other words, bytes 1, 3,
|
||||
//! 5, etc.).
|
||||
//!
|
||||
//! \return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
|
||||
uint16_t *pui16Crc3)
|
||||
{
|
||||
uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even;
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// Initialize the CRC values to zero.
|
||||
//
|
||||
ui16Crc = 0;
|
||||
ui16Cri8Odd = 0;
|
||||
ui16Cri8Even = 0;
|
||||
|
||||
//
|
||||
// Loop while there are more words in the data buffer.
|
||||
//
|
||||
while(ui32WordLen--)
|
||||
{
|
||||
//
|
||||
// Read the next word.
|
||||
//
|
||||
ui32Temp = *pui32Data++;
|
||||
|
||||
//
|
||||
// Perform the first CRC on all four data bytes.
|
||||
//
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
|
||||
ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
|
||||
|
||||
//
|
||||
// Perform the second CRC on only the even-index data bytes.
|
||||
//
|
||||
ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp);
|
||||
ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16);
|
||||
|
||||
//
|
||||
// Perform the third CRC on only the odd-index data bytes.
|
||||
//
|
||||
ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8);
|
||||
ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24);
|
||||
}
|
||||
|
||||
//
|
||||
// Return the resulting CRC-16 values.
|
||||
//
|
||||
pui16Crc3[0] = ui16Crc;
|
||||
pui16Crc3[1] = ui16Cri8Even;
|
||||
pui16Crc3[2] = ui16Cri8Odd;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Calculates the CRC-32 of an array of bytes.
|
||||
//!
|
||||
//! \param ui32Crc is the starting CRC-32 value.
|
||||
//! \param pui8Data is a pointer to the data buffer.
|
||||
//! \param ui32Count is the number of bytes in the data buffer.
|
||||
//!
|
||||
//! This function is used to calculate the CRC-32 of the input buffer. The
|
||||
//! CRC-32 is computed in a running fashion, meaning that the entire data block
|
||||
//! that is to have its CRC-32 computed does not need to be supplied all at
|
||||
//! once. If the input buffer contains the entire block of data, then
|
||||
//! \b ui32Crc should be set to 0xFFFFFFFF. If, however, the entire block of
|
||||
//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the
|
||||
//! first portion of the data, and then the returned value should be passed
|
||||
//! back in as \b ui32Crc for the next portion of the data. Once all data has
|
||||
//! been passed to the function, the final CRC-32 can be obtained by inverting
|
||||
//! the last returned value.
|
||||
//!
|
||||
//! For example, to compute the CRC-32 of a block that has been split into
|
||||
//! three pieces, use the following:
|
||||
//!
|
||||
//! \verbatim
|
||||
//! ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1);
|
||||
//! ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2);
|
||||
//! ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3);
|
||||
//! ui32Crc ^= 0xFFFFFFFF;
|
||||
//! \endverbatim
|
||||
//!
|
||||
//! Computing a CRC-32 in a running fashion is useful in cases where the data
|
||||
//! is arriving via a serial link (for example) and is therefore not all
|
||||
//! available at one time.
|
||||
//!
|
||||
//! \return The accumulated CRC-32 of the input data.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count)
|
||||
{
|
||||
uint32_t ui32Temp;
|
||||
|
||||
//
|
||||
// If the data buffer is not 16 bit-aligned, then perform a single step
|
||||
// of the CRC to make it 16 bit-aligned.
|
||||
//
|
||||
if((uint32_t)pui8Data & 1)
|
||||
{
|
||||
//
|
||||
// Perform the CRC on this input byte.
|
||||
//
|
||||
ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
|
||||
|
||||
//
|
||||
// Skip this input byte.
|
||||
//
|
||||
pui8Data++;
|
||||
ui32Count--;
|
||||
}
|
||||
|
||||
//
|
||||
// If the data buffer is not word-aligned and there are at least two bytes
|
||||
// of data left, then perform two steps of the CRC to make it word-aligned.
|
||||
//
|
||||
if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
|
||||
{
|
||||
//
|
||||
// Read the next int16_t.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// While there is at least a word remaining in the data buffer, perform
|
||||
// four steps of the CRC to consume a word.
|
||||
//
|
||||
while(ui32Count > 3)
|
||||
{
|
||||
//
|
||||
// Read the next word.
|
||||
//
|
||||
ui32Temp = *(uint32_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these four bytes.
|
||||
//
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16);
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 4;
|
||||
ui32Count -= 4;
|
||||
}
|
||||
|
||||
//
|
||||
// If there are 16 bits left in the input buffer, then perform two steps of
|
||||
// the CRC.
|
||||
//
|
||||
if(ui32Count > 1)
|
||||
{
|
||||
//
|
||||
// Read the two bytes.
|
||||
//
|
||||
ui32Temp = *(uint16_t *)pui8Data;
|
||||
|
||||
//
|
||||
// Perform the CRC on these two bytes.
|
||||
//
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
|
||||
ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
|
||||
|
||||
//
|
||||
// Skip these input bytes.
|
||||
//
|
||||
pui8Data += 2;
|
||||
ui32Count -= 2;
|
||||
}
|
||||
|
||||
//
|
||||
// If there is a final byte remaining in the input buffer, then perform a
|
||||
// single step of the CRC.
|
||||
//
|
||||
if(ui32Count != 0)
|
||||
{
|
||||
ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
|
||||
}
|
||||
|
||||
//
|
||||
// Return the resulting CRC-32 value.
|
||||
//
|
||||
return(ui32Crc);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,78 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sw_crc.h - Prototypes for the software CRC functions.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_SW_CRC_H__
|
||||
#define __DRIVERLIB_SW_CRC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data,
|
||||
uint32_t ui32Count);
|
||||
extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data,
|
||||
uint32_t ui32Count);
|
||||
extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data);
|
||||
extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
|
||||
uint16_t *pui16Crc3);
|
||||
extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data,
|
||||
uint32_t ui32Count);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_SW_CRC_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,527 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sysctl.h - Prototypes for the system control driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_SYSCTL_H__
|
||||
#define __DRIVERLIB_SYSCTL_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
|
||||
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
|
||||
// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble
|
||||
// is 3) can only be used with the SysCtlPeripheralPresent() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0
|
||||
#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1
|
||||
#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0
|
||||
#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1
|
||||
#define SYSCTL_PERIPH_CAN2 0xf0003402 // CAN 2
|
||||
#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog comparator 0
|
||||
#define SYSCTL_PERIPH_COMP1 0xf0003c01 // Analog comparator 1
|
||||
#define SYSCTL_PERIPH_COMP2 0xf0003c02 // Analog comparator 2
|
||||
#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A
|
||||
#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B
|
||||
#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C
|
||||
#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D
|
||||
#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E
|
||||
#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F
|
||||
#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G
|
||||
#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H
|
||||
#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J
|
||||
#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module
|
||||
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
|
||||
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
|
||||
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
|
||||
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
|
||||
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
|
||||
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
|
||||
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
|
||||
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
|
||||
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
|
||||
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
|
||||
#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0
|
||||
#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1
|
||||
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
|
||||
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
|
||||
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
|
||||
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
|
||||
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
|
||||
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
|
||||
#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0
|
||||
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
|
||||
#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0
|
||||
#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1
|
||||
#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0
|
||||
#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1
|
||||
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
|
||||
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
|
||||
#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0
|
||||
#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1
|
||||
#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2
|
||||
#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3
|
||||
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
|
||||
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
|
||||
#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0
|
||||
#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1
|
||||
#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2
|
||||
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
|
||||
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
|
||||
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
|
||||
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
|
||||
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
|
||||
#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA
|
||||
#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0
|
||||
#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0
|
||||
#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1
|
||||
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
|
||||
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
|
||||
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
|
||||
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
|
||||
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
|
||||
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlIntEnable(),
|
||||
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
|
||||
// by the SysCtlIntStatus() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
|
||||
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
|
||||
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
|
||||
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
|
||||
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
|
||||
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
|
||||
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
|
||||
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
|
||||
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlResetCauseClear()
|
||||
// API or returned by the SysCtlResetCauseGet() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
|
||||
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
|
||||
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
|
||||
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
|
||||
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
|
||||
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
|
||||
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
|
||||
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
|
||||
// API as the ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
|
||||
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlPWMClockSet() API
|
||||
// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet()
|
||||
// API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
|
||||
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
|
||||
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
|
||||
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
|
||||
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
|
||||
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
|
||||
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlADCSpeedSet() API
|
||||
// as the ui32Speed parameter, and can be returned by the SysCtlADCSpeedGet()
|
||||
// API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlClockSet() API as
|
||||
// the ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
|
||||
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
|
||||
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
|
||||
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
|
||||
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
|
||||
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
|
||||
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
|
||||
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
|
||||
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
|
||||
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
|
||||
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
|
||||
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
|
||||
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
|
||||
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
|
||||
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
|
||||
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
|
||||
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
|
||||
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
|
||||
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
|
||||
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
|
||||
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
|
||||
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
|
||||
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
|
||||
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
|
||||
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
|
||||
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
|
||||
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
|
||||
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
|
||||
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
|
||||
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
|
||||
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
|
||||
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
|
||||
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
|
||||
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
|
||||
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
|
||||
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
|
||||
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
|
||||
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
|
||||
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
|
||||
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
|
||||
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
|
||||
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
|
||||
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
|
||||
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
|
||||
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
|
||||
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
|
||||
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
|
||||
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
|
||||
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
|
||||
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
|
||||
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
|
||||
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
|
||||
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
|
||||
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
|
||||
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
|
||||
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
|
||||
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
|
||||
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
|
||||
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
|
||||
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
|
||||
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
|
||||
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
|
||||
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
|
||||
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
|
||||
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
|
||||
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
|
||||
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
|
||||
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
|
||||
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
|
||||
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
|
||||
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
|
||||
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
|
||||
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
|
||||
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
|
||||
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
|
||||
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
|
||||
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
|
||||
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
|
||||
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
|
||||
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
|
||||
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
|
||||
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
|
||||
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
|
||||
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
|
||||
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
|
||||
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
|
||||
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
|
||||
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
|
||||
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
|
||||
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
|
||||
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
|
||||
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
|
||||
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
|
||||
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
|
||||
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
|
||||
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
|
||||
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
|
||||
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
|
||||
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
|
||||
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
|
||||
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
|
||||
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
|
||||
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
|
||||
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
|
||||
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
|
||||
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
|
||||
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
|
||||
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
|
||||
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
|
||||
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
|
||||
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
|
||||
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
|
||||
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
|
||||
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
|
||||
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
|
||||
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
|
||||
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
|
||||
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
|
||||
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
|
||||
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
|
||||
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
|
||||
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
|
||||
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
|
||||
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
|
||||
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
|
||||
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
|
||||
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
|
||||
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
|
||||
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
|
||||
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
|
||||
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
|
||||
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
|
||||
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
|
||||
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
|
||||
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
|
||||
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
|
||||
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
|
||||
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
|
||||
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
|
||||
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
|
||||
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
|
||||
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
|
||||
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
|
||||
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
|
||||
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
|
||||
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
|
||||
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
|
||||
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
|
||||
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
|
||||
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
|
||||
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
|
||||
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
|
||||
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
|
||||
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
|
||||
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
|
||||
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
|
||||
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
|
||||
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
|
||||
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
|
||||
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
|
||||
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
|
||||
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
|
||||
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
|
||||
// API as the ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
|
||||
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
|
||||
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
|
||||
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
|
||||
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
|
||||
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
|
||||
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
|
||||
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
|
||||
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
|
||||
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
|
||||
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
|
||||
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
|
||||
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
|
||||
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
|
||||
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
|
||||
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
|
||||
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
|
||||
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
|
||||
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
|
||||
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
|
||||
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
|
||||
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
|
||||
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
|
||||
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
|
||||
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
|
||||
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
|
||||
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
|
||||
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
|
||||
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
|
||||
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
|
||||
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
|
||||
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
|
||||
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
|
||||
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
|
||||
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
|
||||
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
|
||||
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
|
||||
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
|
||||
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
|
||||
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
|
||||
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
|
||||
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
|
||||
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
|
||||
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
|
||||
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
|
||||
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
|
||||
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
|
||||
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
|
||||
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
|
||||
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
|
||||
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
|
||||
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
|
||||
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
|
||||
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
|
||||
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
|
||||
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
|
||||
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
|
||||
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
|
||||
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
|
||||
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
|
||||
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
|
||||
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
|
||||
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
|
||||
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
|
||||
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
|
||||
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
|
||||
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
|
||||
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
|
||||
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlPIOSCCalibrate()
|
||||
// API as the ui32Type parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
|
||||
#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
|
||||
#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlMOSCConfigSet() API
|
||||
// as the ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
|
||||
#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
|
||||
#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint32_t SysCtlSRAMSizeGet(void);
|
||||
extern uint32_t SysCtlFlashSizeGet(void);
|
||||
extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
|
||||
extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
|
||||
extern void SysCtlPeripheralClockGating(bool bEnable);
|
||||
extern void SysCtlIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysCtlIntUnregister(void);
|
||||
extern void SysCtlIntEnable(uint32_t ui32Ints);
|
||||
extern void SysCtlIntDisable(uint32_t ui32Ints);
|
||||
extern void SysCtlIntClear(uint32_t ui32Ints);
|
||||
extern uint32_t SysCtlIntStatus(bool bMasked);
|
||||
extern void SysCtlLDOConfigSet(uint32_t ui32Config);
|
||||
extern void SysCtlReset(void);
|
||||
extern void SysCtlSleep(void);
|
||||
extern void SysCtlDeepSleep(void);
|
||||
extern uint32_t SysCtlResetCauseGet(void);
|
||||
extern void SysCtlResetCauseClear(uint32_t ui32Causes);
|
||||
extern void SysCtlBrownOutConfigSet(uint32_t ui32Config,
|
||||
uint32_t ui32Delay);
|
||||
extern void SysCtlDelay(uint32_t ui32Count);
|
||||
extern void SysCtlMOSCConfigSet(uint32_t ui32Config);
|
||||
extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type);
|
||||
extern void SysCtlClockSet(uint32_t ui32Config);
|
||||
extern uint32_t SysCtlClockGet(void);
|
||||
extern void SysCtlDeepSleepClockSet(uint32_t ui32Config);
|
||||
extern void SysCtlPWMClockSet(uint32_t ui32Config);
|
||||
extern uint32_t SysCtlPWMClockGet(void);
|
||||
extern void SysCtlADCSpeedSet(uint32_t ui32Speed);
|
||||
extern uint32_t SysCtlADCSpeedGet(void);
|
||||
extern void SysCtlIOSCVerificationSet(bool bEnable);
|
||||
extern void SysCtlMOSCVerificationSet(bool bEnable);
|
||||
extern void SysCtlPLLVerificationSet(bool bEnable);
|
||||
extern void SysCtlClkVerificationClear(void);
|
||||
extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral);
|
||||
extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral);
|
||||
extern void SysCtlUSBPLLEnable(void);
|
||||
extern void SysCtlUSBPLLDisable(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_SYSCTL_H__
|
|
@ -0,0 +1,307 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sysexc.c - Routines for the System Exception Module.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup sysexc_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "inc/hw_sysexc.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns the interrupt number for a system exception.
|
||||
//!
|
||||
//! This function returns the interrupt number for a system exception.
|
||||
//!
|
||||
//! \return Returns the system exception interrupt number.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static uint32_t
|
||||
_SysExcIntNumberGet(void)
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Get the interrupt number based on the class.
|
||||
//
|
||||
if(CLASS_IS_BLIZZARD)
|
||||
{
|
||||
ui32Int = INT_SYSEXC_BLIZZARD;
|
||||
}
|
||||
else
|
||||
{
|
||||
ui32Int = 0;
|
||||
}
|
||||
return(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the system exception interrupt.
|
||||
//!
|
||||
//! \param pfnHandler is a pointer to the function to be called when the system
|
||||
//! exception interrupt occurs.
|
||||
//!
|
||||
//! This function places the address of the system exception interrupt handler
|
||||
//! into the interrupt vector table in SRAM. This function also enables the
|
||||
//! global interrupt in the interrupt controller; specific system exception
|
||||
//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt
|
||||
//! handler's responsibility to clear the interrupt source.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysExcIntRegister(void (*pfnHandler)(void))
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Get the system exception interrupt number.
|
||||
//
|
||||
ui32Int = _SysExcIntNumberGet();
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Register the interrupt handler.
|
||||
//
|
||||
IntRegister(ui32Int, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the system exception interrupt.
|
||||
//
|
||||
IntEnable(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters the system exception interrupt handler.
|
||||
//!
|
||||
//! This function removes the system exception interrupt handler from the
|
||||
//! vector table in SRAM. This function also masks off the system exception
|
||||
//! interrupt in the interrupt controller so that the interrupt handler is no
|
||||
//! longer called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysExcIntUnregister(void)
|
||||
{
|
||||
uint32_t ui32Int;
|
||||
|
||||
//
|
||||
// Get the system exception interrupt number.
|
||||
//
|
||||
ui32Int = _SysExcIntNumberGet();
|
||||
|
||||
ASSERT(ui32Int != 0);
|
||||
|
||||
//
|
||||
// Disable the system exception interrupt.
|
||||
//
|
||||
IntDisable(ui32Int);
|
||||
|
||||
//
|
||||
// Unregister the system exception interrupt handler.
|
||||
//
|
||||
IntUnregister(ui32Int);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables individual system exception interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
|
||||
//!
|
||||
//! This function enables the indicated system exception interrupt sources.
|
||||
//! Only the sources that are enabled can be reflected to the processor
|
||||
//! interrupt; disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
|
||||
//!
|
||||
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
|
||||
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysExcIntEnable(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Enable the specified interrupts.
|
||||
//
|
||||
HWREG(SYSEXC_IM) |= ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables individual system exception interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is the bit mask of the interrupt sources to be
|
||||
//! disabled.
|
||||
//!
|
||||
//! This function disables the indicated system exception interrupt sources.
|
||||
//! Only sources that are enabled can be reflected to the processor interrupt;
|
||||
//! disabled sources have no effect on the processor.
|
||||
//!
|
||||
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
|
||||
//!
|
||||
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
|
||||
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysExcIntDisable(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Disable the specified interrupts.
|
||||
//
|
||||
HWREG(SYSEXC_IM) &= ~(ui32IntFlags);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current system exception interrupt status.
|
||||
//!
|
||||
//! \param bMasked is \b false if the raw interrupt status is required and
|
||||
//! \b true if the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the system exception interrupt status. Either the
|
||||
//! raw interrupt status or the status of interrupts that are allowed to
|
||||
//! reflect to the processor can be returned.
|
||||
//!
|
||||
//! \return Returns the current system exception interrupt status, enumerated
|
||||
//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC,
|
||||
//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and
|
||||
//! \b SYSEXC_INT_FP_IDC.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
SysExcIntStatus(bool bMasked)
|
||||
{
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(HWREG(SYSEXC_MIS));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(HWREG(SYSEXC_RIS));
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears system exception interrupt sources.
|
||||
//!
|
||||
//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
|
||||
//!
|
||||
//! This function clears the specified system exception interrupt sources, so
|
||||
//! that they no longer assert. This function must be called in the interrupt
|
||||
//! handler to keep the interrupt from being recognized again immediately upon
|
||||
//! exit.
|
||||
//!
|
||||
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
|
||||
//!
|
||||
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
|
||||
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
|
||||
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysExcIntClear(uint32_t ui32IntFlags)
|
||||
{
|
||||
//
|
||||
// Clear the requested interrupt sources.
|
||||
//
|
||||
HWREG(SYSEXC_IC) = ui32IntFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,89 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sysexc.h - Prototypes for the System Exception Module routines.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_SYSEXC_H__
|
||||
#define __DRIVERLIB_SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
|
||||
// SysExcIntClear as the ui32IntFlags parameter, and returned from
|
||||
// SysExcIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
|
||||
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
|
||||
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
|
||||
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
|
||||
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
|
||||
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysExcIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysExcIntUnregister(void);
|
||||
extern void SysExcIntEnable(uint32_t ui32IntFlags);
|
||||
extern void SysExcIntDisable(uint32_t ui32IntFlags);
|
||||
extern uint32_t SysExcIntStatus(bool bMasked);
|
||||
extern void SysExcIntClear(uint32_t ui32IntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_SYSEXC_H__
|
|
@ -0,0 +1,277 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// systick.c - Driver for the SysTick timer in NVIC.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup systick_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
#include "driverlib/systick.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the SysTick counter.
|
||||
//!
|
||||
//! This function starts the SysTick counter. If an interrupt handler has been
|
||||
//! registered, it is called when the SysTick counter rolls over.
|
||||
//!
|
||||
//! \note Calling this function causes the SysTick counter to (re)commence
|
||||
//! counting from its current value. The counter is not automatically reloaded
|
||||
//! with the period as specified in a previous call to SysTickPeriodSet(). If
|
||||
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
|
||||
//! written to force the reload. Any write to this register clears the SysTick
|
||||
//! counter to 0 and causes a reload with the supplied period on the next
|
||||
//! clock.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable SysTick.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the SysTick counter.
|
||||
//!
|
||||
//! This function stops the SysTick counter. If an interrupt handler has been
|
||||
//! registered, it is not called until SysTick is restarted.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable SysTick.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the SysTick interrupt.
|
||||
//!
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! SysTick interrupt occurs.
|
||||
//!
|
||||
//! This function registers the handler to be called when a SysTick interrupt
|
||||
//! occurs.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickIntRegister(void (*pfnHandler)(void))
|
||||
{
|
||||
//
|
||||
// Register the interrupt handler, returning an error if an error occurs.
|
||||
//
|
||||
IntRegister(FAULT_SYSTICK, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters the interrupt handler for the SysTick interrupt.
|
||||
//!
|
||||
//! This function unregisters the handler to be called when a SysTick interrupt
|
||||
//! occurs.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickIntUnregister(void)
|
||||
{
|
||||
//
|
||||
// Disable the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(FAULT_SYSTICK);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the SysTick interrupt.
|
||||
//!
|
||||
//! This function enables the SysTick interrupt, allowing it to be
|
||||
//! reflected to the processor.
|
||||
//!
|
||||
//! \note The SysTick interrupt handler is not required to clear the SysTick
|
||||
//! interrupt source because it is cleared automatically by the NVIC when the
|
||||
//! interrupt handler is called.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickIntEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the SysTick interrupt.
|
||||
//!
|
||||
//! This function disables the SysTick interrupt, preventing it from being
|
||||
//! reflected to the processor.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickIntDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the period of the SysTick counter.
|
||||
//!
|
||||
//! \param ui32Period is the number of clock ticks in each period of the
|
||||
//! SysTick counter and must be between 1 and 16,777,216, inclusive.
|
||||
//!
|
||||
//! This function sets the rate at which the SysTick counter wraps, which
|
||||
//! equates to the number of processor clocks between interrupts.
|
||||
//!
|
||||
//! \note Calling this function does not cause the SysTick counter to reload
|
||||
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
|
||||
//! register must be written. Any write to this register clears the SysTick
|
||||
//! counter to 0 and causes a reload with the \e ui32Period supplied here on
|
||||
//! the next clock after SysTick is enabled.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
SysTickPeriodSet(uint32_t ui32Period)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
|
||||
|
||||
//
|
||||
// Set the period of the SysTick counter.
|
||||
//
|
||||
HWREG(NVIC_ST_RELOAD) = ui32Period - 1;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the period of the SysTick counter.
|
||||
//!
|
||||
//! This function returns the rate at which the SysTick counter wraps, which
|
||||
//! equates to the number of processor clocks between interrupts.
|
||||
//!
|
||||
//! \return Returns the period of the SysTick counter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
SysTickPeriodGet(void)
|
||||
{
|
||||
//
|
||||
// Return the period of the SysTick counter.
|
||||
//
|
||||
return(HWREG(NVIC_ST_RELOAD) + 1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current value of the SysTick counter.
|
||||
//!
|
||||
//! This function returns the current value of the SysTick counter, which is
|
||||
//! a value between the period - 1 and zero, inclusive.
|
||||
//!
|
||||
//! \return Returns the current value of the SysTick counter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
SysTickValueGet(void)
|
||||
{
|
||||
//
|
||||
// Return the current value of the SysTick counter.
|
||||
//
|
||||
return(HWREG(NVIC_ST_CURRENT));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,78 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// systick.h - Prototypes for the SysTick driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_SYSTICK_H__
|
||||
#define __DRIVERLIB_SYSTICK_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysTickEnable(void);
|
||||
extern void SysTickDisable(void);
|
||||
extern void SysTickIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysTickIntUnregister(void);
|
||||
extern void SysTickIntEnable(void);
|
||||
extern void SysTickIntDisable(void);
|
||||
extern void SysTickPeriodSet(uint32_t ui32Period);
|
||||
extern uint32_t SysTickPeriodGet(void);
|
||||
extern uint32_t SysTickValueGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_SYSTICK_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,208 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// timer.h - Prototypes for the timer module
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_TIMER_H__
|
||||
#define __DRIVERLIB_TIMER_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerConfigure as the ui32Config parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
|
||||
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
|
||||
// timer
|
||||
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
|
||||
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
|
||||
// timer
|
||||
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
|
||||
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
|
||||
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
|
||||
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
|
||||
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
|
||||
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
|
||||
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
|
||||
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
|
||||
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
|
||||
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
|
||||
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
|
||||
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
|
||||
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
|
||||
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
|
||||
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
|
||||
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
|
||||
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
|
||||
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
|
||||
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
|
||||
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
|
||||
// TimerIntClear as the ui32IntFlags parameter, and returned from
|
||||
// TimerIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
|
||||
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
|
||||
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
|
||||
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
|
||||
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
|
||||
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
|
||||
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
|
||||
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
|
||||
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerControlEvent as the ui32Event parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
|
||||
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
|
||||
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to most of the timer APIs as the ui32Timer
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_A 0x000000ff // Timer A
|
||||
#define TIMER_B 0x0000ff00 // Timer B
|
||||
#define TIMER_BOTH 0x0000ffff // Timer Both
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerSynchronize as the ui32Timers parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
|
||||
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
|
||||
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
|
||||
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
|
||||
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
|
||||
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
|
||||
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
|
||||
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
|
||||
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
|
||||
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
|
||||
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
|
||||
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
|
||||
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
|
||||
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
|
||||
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
|
||||
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
|
||||
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
|
||||
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
|
||||
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
|
||||
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
|
||||
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
|
||||
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
|
||||
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
|
||||
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
|
||||
extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
bool bInvert);
|
||||
extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
bool bEnable);
|
||||
extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
uint32_t ui32Event);
|
||||
extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
bool bStall);
|
||||
extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
bool bWait);
|
||||
extern void TimerRTCEnable(uint32_t ui32Base);
|
||||
extern void TimerRTCDisable(uint32_t ui32Base);
|
||||
extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
uint32_t ui32Value);
|
||||
extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
uint32_t ui32Value);
|
||||
extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
uint32_t ui32Value);
|
||||
extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value);
|
||||
extern uint64_t TimerLoadGet64(uint32_t ui32Base);
|
||||
extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern uint64_t TimerValueGet64(uint32_t ui32Base);
|
||||
extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
uint32_t ui32Value);
|
||||
extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value);
|
||||
extern uint64_t TimerMatchGet64(uint32_t ui32Base);
|
||||
extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
|
||||
void (*pfnHandler)(void));
|
||||
extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer);
|
||||
extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_TIMER_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,253 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// uart.h - Defines and Macros for the UART.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_UART_H__
|
||||
#define __DRIVERLIB_UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
|
||||
// as the ui32IntFlags parameter, and returned from UARTIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
|
||||
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
|
||||
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
|
||||
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
|
||||
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
|
||||
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
|
||||
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
|
||||
#define UART_INT_RX 0x010 // Receive Interrupt Mask
|
||||
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
|
||||
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
|
||||
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
|
||||
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter
|
||||
// and returned by UARTConfigGetExpClk in the pui32Config parameter.
|
||||
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
|
||||
// UARTParityModeSet as the ui32Parity parameter, and are returned by
|
||||
// UARTParityModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
|
||||
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
|
||||
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
|
||||
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
|
||||
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
|
||||
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
|
||||
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
|
||||
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
|
||||
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
|
||||
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
|
||||
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
|
||||
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
|
||||
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
|
||||
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter
|
||||
// and returned by UARTFIFOLevelGet in the pui32TxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
|
||||
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
|
||||
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
|
||||
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
|
||||
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter
|
||||
// and returned by UARTFIFOLevelGet in the pui32RxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
|
||||
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
|
||||
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
|
||||
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
|
||||
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
|
||||
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values returned from UARTRxErrorGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RXERROR_OVERRUN 0x00000008
|
||||
#define UART_RXERROR_BREAK 0x00000004
|
||||
#define UART_RXERROR_PARITY 0x00000002
|
||||
#define UART_RXERROR_FRAMING 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
|
||||
// UARTHandshakeOutputGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_OUTPUT_RTS 0x00000800
|
||||
#define UART_OUTPUT_DTR 0x00000400
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be returned from UARTHandshakeInputsGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INPUT_RI 0x00000100
|
||||
#define UART_INPUT_DCD 0x00000004
|
||||
#define UART_INPUT_DSR 0x00000002
|
||||
#define UART_INPUT_CTS 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFlowControl() or returned from
|
||||
// UARTFlowControlGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FLOWCONTROL_TX 0x00008000
|
||||
#define UART_FLOWCONTROL_RX 0x00004000
|
||||
#define UART_FLOWCONTROL_NONE 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTTxIntModeSet() or returned from
|
||||
// UARTTxIntModeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_TXINT_MODE_FIFO 0x00000000
|
||||
#define UART_TXINT_MODE_EOT 0x00000010
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTClockSourceSet() or returned from
|
||||
// UARTClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CLOCK_SYSTEM 0x00000000
|
||||
#define UART_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity);
|
||||
extern uint32_t UARTParityModeGet(uint32_t ui32Base);
|
||||
extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
|
||||
uint32_t ui32RxLevel);
|
||||
extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
|
||||
uint32_t *pui32RxLevel);
|
||||
extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
|
||||
uint32_t ui32Baud, uint32_t ui32Config);
|
||||
extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
|
||||
uint32_t *pui32Baud, uint32_t *pui32Config);
|
||||
extern void UARTEnable(uint32_t ui32Base);
|
||||
extern void UARTDisable(uint32_t ui32Base);
|
||||
extern void UARTFIFOEnable(uint32_t ui32Base);
|
||||
extern void UARTFIFODisable(uint32_t ui32Base);
|
||||
extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower);
|
||||
extern void UARTDisableSIR(uint32_t ui32Base);
|
||||
extern bool UARTCharsAvail(uint32_t ui32Base);
|
||||
extern bool UARTSpaceAvail(uint32_t ui32Base);
|
||||
extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base);
|
||||
extern int32_t UARTCharGet(uint32_t ui32Base);
|
||||
extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData);
|
||||
extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData);
|
||||
extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState);
|
||||
extern bool UARTBusy(uint32_t ui32Base);
|
||||
extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern void UARTIntUnregister(uint32_t ui32Base);
|
||||
extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
|
||||
extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
|
||||
extern uint32_t UARTRxErrorGet(uint32_t ui32Base);
|
||||
extern void UARTRxErrorClear(uint32_t ui32Base);
|
||||
extern void UARTSmartCardEnable(uint32_t ui32Base);
|
||||
extern void UARTSmartCardDisable(uint32_t ui32Base);
|
||||
extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control);
|
||||
extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control);
|
||||
extern uint32_t UARTModemControlGet(uint32_t ui32Base);
|
||||
extern uint32_t UARTModemStatusGet(uint32_t ui32Base);
|
||||
extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode);
|
||||
extern uint32_t UARTFlowControlGet(uint32_t ui32Base);
|
||||
extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode);
|
||||
extern uint32_t UARTTxIntModeGet(uint32_t ui32Base);
|
||||
extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
|
||||
extern uint32_t UARTClockSourceGet(uint32_t ui32Base);
|
||||
extern void UART9BitEnable(uint32_t ui32Base);
|
||||
extern void UART9BitDisable(uint32_t ui32Base);
|
||||
extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
|
||||
uint8_t ui8Mask);
|
||||
extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_UART_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,757 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// udma.h - Prototypes and macros for the uDMA controller.
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_UDMA_H__
|
||||
#define __DRIVERLIB_UDMA_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup udma_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// A structure that defines an entry in the channel control table. These
|
||||
// fields are used by the uDMA controller and normally it is not necessary for
|
||||
// software to directly read or write fields in the table.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef struct
|
||||
{
|
||||
//
|
||||
// The ending source address of the data transfer.
|
||||
//
|
||||
volatile void *pvSrcEndAddr;
|
||||
|
||||
//
|
||||
// The ending destination address of the data transfer.
|
||||
//
|
||||
volatile void *pvDstEndAddr;
|
||||
|
||||
//
|
||||
// The channel control mode.
|
||||
//
|
||||
volatile uint32_t ui32Control;
|
||||
|
||||
//
|
||||
// An unused location.
|
||||
//
|
||||
volatile uint32_t ui32Spare;
|
||||
}
|
||||
tDMAControlTable;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! A helper macro for building scatter-gather task table entries.
|
||||
//!
|
||||
//! \param ui32TransferCount is the count of items to transfer for this task.
|
||||
//! \param ui32ItemSize is the bit size of the items to transfer for this task.
|
||||
//! \param ui32SrcIncrement is the bit size increment for source data.
|
||||
//! \param pvSrcAddr is the starting address of the data to transfer.
|
||||
//! \param ui32DstIncrement is the bit size increment for destination data.
|
||||
//! \param pvDstAddr is the starting address of the destination data.
|
||||
//! \param ui32ArbSize is the arbitration size to use for the transfer task.
|
||||
//! \param ui32Mode is the transfer mode for this task.
|
||||
//!
|
||||
//! This macro is intended to be used to help populate a table of uDMA tasks
|
||||
//! for a scatter-gather transfer. This macro will calculate the values for
|
||||
//! the fields of a task structure entry based on the input parameters.
|
||||
//!
|
||||
//! There are specific requirements for the values of each parameter. No
|
||||
//! checking is done so it is up to the caller to ensure that correct values
|
||||
//! are used for the parameters.
|
||||
//!
|
||||
//! The \e ui32TransferCount parameter is the number of items that will be
|
||||
//! transferred by this task. It must be in the range 1-1024.
|
||||
//!
|
||||
//! The \e ui32ItemSize parameter is the bit size of the transfer data. It
|
||||
//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
|
||||
//!
|
||||
//! The \e ui32SrcIncrement parameter is the increment size for the source
|
||||
//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
|
||||
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
|
||||
//!
|
||||
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
|
||||
//! data.
|
||||
//!
|
||||
//! The \e ui32DstIncrement parameter is the increment size for the destination
|
||||
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
|
||||
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
|
||||
//!
|
||||
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
|
||||
//! location where the data will be transferred.
|
||||
//!
|
||||
//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and
|
||||
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
|
||||
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
|
||||
//! powers of 2, from 1 to 1024.
|
||||
//!
|
||||
//! The \e ui32Mode parameter is the mode to use for this transfer task. It
|
||||
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
|
||||
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
|
||||
//! that normally all tasks will be one of the scatter-gather modes while the
|
||||
//! last task is a task list will be AUTO or BASIC.
|
||||
//!
|
||||
//! This macro is intended to be used to initialize individual entries of
|
||||
//! a structure of tDMAControlTable type, like this:
|
||||
//!
|
||||
//! \verbatim
|
||||
//! tDMAControlTable MyTaskList[] =
|
||||
//! {
|
||||
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
|
||||
//! UDMA_SRC_INC_8, MySourceBuf,
|
||||
//! UDMA_DST_INC_8, MyDestBuf,
|
||||
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
|
||||
//! uDMATaskStructEntry(Task2Count, ...),
|
||||
//! }
|
||||
//! \endverbatim
|
||||
//!
|
||||
//! \return Nothing; this is not a function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define uDMATaskStructEntry(ui32TransferCount, \
|
||||
ui32ItemSize, \
|
||||
ui32SrcIncrement, \
|
||||
pvSrcAddr, \
|
||||
ui32DstIncrement, \
|
||||
pvDstAddr, \
|
||||
ui32ArbSize, \
|
||||
ui32Mode) \
|
||||
{ \
|
||||
(((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
|
||||
((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
|
||||
((ui32SrcIncrement) >> 26)) - 1]))), \
|
||||
(((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\
|
||||
((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
|
||||
((ui32DstIncrement) >> 30)) - 1]))), \
|
||||
(ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
|
||||
(ui32ArbSize) | \
|
||||
(((ui32TransferCount) - 1) << 4) | \
|
||||
((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
|
||||
((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
|
||||
(ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags that can be passed to uDMAChannelAttributeEnable(),
|
||||
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ATTR_USEBURST 0x00000001
|
||||
#define UDMA_ATTR_ALTSELECT 0x00000002
|
||||
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
|
||||
#define UDMA_ATTR_REQMASK 0x00000008
|
||||
#define UDMA_ATTR_ALL 0x0000000F
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// DMA control modes that can be passed to uDMAModeSet() and returned
|
||||
// uDMAModeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_MODE_STOP 0x00000000
|
||||
#define UDMA_MODE_BASIC 0x00000001
|
||||
#define UDMA_MODE_AUTO 0x00000002
|
||||
#define UDMA_MODE_PINGPONG 0x00000003
|
||||
#define UDMA_MODE_MEM_SCATTER_GATHER \
|
||||
0x00000004
|
||||
#define UDMA_MODE_PER_SCATTER_GATHER \
|
||||
0x00000006
|
||||
#define UDMA_MODE_ALT_SELECT 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Channel configuration values that can be passed to uDMAControlSet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_DST_INC_8 0x00000000
|
||||
#define UDMA_DST_INC_16 0x40000000
|
||||
#define UDMA_DST_INC_32 0x80000000
|
||||
#define UDMA_DST_INC_NONE 0xc0000000
|
||||
#define UDMA_SRC_INC_8 0x00000000
|
||||
#define UDMA_SRC_INC_16 0x04000000
|
||||
#define UDMA_SRC_INC_32 0x08000000
|
||||
#define UDMA_SRC_INC_NONE 0x0c000000
|
||||
#define UDMA_SIZE_8 0x00000000
|
||||
#define UDMA_SIZE_16 0x11000000
|
||||
#define UDMA_SIZE_32 0x22000000
|
||||
#define UDMA_DST_PROT_PRIV 0x00200000
|
||||
#define UDMA_SRC_PROT_PRIV 0x00040000
|
||||
#define UDMA_ARB_1 0x00000000
|
||||
#define UDMA_ARB_2 0x00004000
|
||||
#define UDMA_ARB_4 0x00008000
|
||||
#define UDMA_ARB_8 0x0000c000
|
||||
#define UDMA_ARB_16 0x00010000
|
||||
#define UDMA_ARB_32 0x00014000
|
||||
#define UDMA_ARB_64 0x00018000
|
||||
#define UDMA_ARB_128 0x0001c000
|
||||
#define UDMA_ARB_256 0x00020000
|
||||
#define UDMA_ARB_512 0x00024000
|
||||
#define UDMA_ARB_1024 0x00028000
|
||||
#define UDMA_NEXT_USEBURST 0x00000008
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Channel numbers to be passed to API functions that require a channel number
|
||||
// ID.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHANNEL_USBEP1RX 0
|
||||
#define UDMA_CHANNEL_USBEP1TX 1
|
||||
#define UDMA_CHANNEL_USBEP2RX 2
|
||||
#define UDMA_CHANNEL_USBEP2TX 3
|
||||
#define UDMA_CHANNEL_USBEP3RX 4
|
||||
#define UDMA_CHANNEL_USBEP3TX 5
|
||||
#define UDMA_CHANNEL_ETH0RX 6
|
||||
#define UDMA_CHANNEL_ETH0TX 7
|
||||
#define UDMA_CHANNEL_UART0RX 8
|
||||
#define UDMA_CHANNEL_UART0TX 9
|
||||
#define UDMA_CHANNEL_SSI0RX 10
|
||||
#define UDMA_CHANNEL_SSI0TX 11
|
||||
#define UDMA_CHANNEL_ADC0 14
|
||||
#define UDMA_CHANNEL_ADC1 15
|
||||
#define UDMA_CHANNEL_ADC2 16
|
||||
#define UDMA_CHANNEL_ADC3 17
|
||||
#define UDMA_CHANNEL_TMR0A 18
|
||||
#define UDMA_CHANNEL_TMR0B 19
|
||||
#define UDMA_CHANNEL_TMR1A 20
|
||||
#define UDMA_CHANNEL_TMR1B 21
|
||||
#define UDMA_CHANNEL_UART1RX 22
|
||||
#define UDMA_CHANNEL_UART1TX 23
|
||||
#define UDMA_CHANNEL_SSI1RX 24
|
||||
#define UDMA_CHANNEL_SSI1TX 25
|
||||
#define UDMA_CHANNEL_I2S0RX 28
|
||||
#define UDMA_CHANNEL_I2S0TX 29
|
||||
#define UDMA_CHANNEL_SW 30
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
|
||||
// control structure should be used.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_PRI_SELECT 0x00000000
|
||||
#define UDMA_ALT_SELECT 0x00000020
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
|
||||
// uDMAIntUnregister().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_INT_SW 62
|
||||
#define UDMA_INT_ERR 63
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Channel numbers to be passed to API functions that require a channel number
|
||||
// ID. These are for secondary peripheral assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_SEC_CHANNEL_UART2RX_0 \
|
||||
0
|
||||
#define UDMA_SEC_CHANNEL_UART2TX_1 \
|
||||
1
|
||||
#define UDMA_SEC_CHANNEL_TMR3A 2
|
||||
#define UDMA_SEC_CHANNEL_TMR3B 3
|
||||
#define UDMA_SEC_CHANNEL_TMR2A_4 \
|
||||
4
|
||||
#define UDMA_SEC_CHANNEL_TMR2B_5 \
|
||||
5
|
||||
#define UDMA_SEC_CHANNEL_TMR2A_6 \
|
||||
6
|
||||
#define UDMA_SEC_CHANNEL_TMR2B_7 \
|
||||
7
|
||||
#define UDMA_SEC_CHANNEL_UART1RX \
|
||||
8
|
||||
#define UDMA_SEC_CHANNEL_UART1TX \
|
||||
9
|
||||
#define UDMA_SEC_CHANNEL_SSI1RX 10
|
||||
#define UDMA_SEC_CHANNEL_SSI1TX 11
|
||||
#define UDMA_SEC_CHANNEL_UART2RX_12 \
|
||||
12
|
||||
#define UDMA_SEC_CHANNEL_UART2TX_13 \
|
||||
13
|
||||
#define UDMA_SEC_CHANNEL_TMR2A_14 \
|
||||
14
|
||||
#define UDMA_SEC_CHANNEL_TMR2B_15 \
|
||||
15
|
||||
#define UDMA_SEC_CHANNEL_TMR1A 18
|
||||
#define UDMA_SEC_CHANNEL_TMR1B 19
|
||||
#define UDMA_SEC_CHANNEL_EPI0RX 20
|
||||
#define UDMA_SEC_CHANNEL_EPI0TX 21
|
||||
#define UDMA_SEC_CHANNEL_ADC10 24
|
||||
#define UDMA_SEC_CHANNEL_ADC11 25
|
||||
#define UDMA_SEC_CHANNEL_ADC12 26
|
||||
#define UDMA_SEC_CHANNEL_ADC13 27
|
||||
#define UDMA_SEC_CHANNEL_SW 30
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// uDMA default/secondary peripheral selections, to be passed to
|
||||
// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
|
||||
0x00000001
|
||||
#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
|
||||
0x00000002
|
||||
#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
|
||||
0x00000004
|
||||
#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
|
||||
0x00000008
|
||||
#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
|
||||
0x00000010
|
||||
#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
|
||||
0x00000020
|
||||
#define UDMA_DEF_ETH0RX_SEC_TMR2A \
|
||||
0x00000040
|
||||
#define UDMA_DEF_ETH0TX_SEC_TMR2B \
|
||||
0x00000080
|
||||
#define UDMA_DEF_UART0RX_SEC_UART1RX \
|
||||
0x00000100
|
||||
#define UDMA_DEF_UART0TX_SEC_UART1TX \
|
||||
0x00000200
|
||||
#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
|
||||
0x00000400
|
||||
#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
|
||||
0x00000800
|
||||
#define UDMA_DEF_RESERVED_SEC_UART2RX \
|
||||
0x00001000
|
||||
#define UDMA_DEF_RESERVED_SEC_UART2TX \
|
||||
0x00002000
|
||||
#define UDMA_DEF_ADC00_SEC_TMR2A \
|
||||
0x00004000
|
||||
#define UDMA_DEF_ADC01_SEC_TMR2B \
|
||||
0x00008000
|
||||
#define UDMA_DEF_ADC02_SEC_RESERVED \
|
||||
0x00010000
|
||||
#define UDMA_DEF_ADC03_SEC_RESERVED \
|
||||
0x00020000
|
||||
#define UDMA_DEF_TMR0A_SEC_TMR1A \
|
||||
0x00040000
|
||||
#define UDMA_DEF_TMR0B_SEC_TMR1B \
|
||||
0x00080000
|
||||
#define UDMA_DEF_TMR1A_SEC_EPI0RX \
|
||||
0x00100000
|
||||
#define UDMA_DEF_TMR1B_SEC_EPI0TX \
|
||||
0x00200000
|
||||
#define UDMA_DEF_UART1RX_SEC_RESERVED \
|
||||
0x00400000
|
||||
#define UDMA_DEF_UART1TX_SEC_RESERVED \
|
||||
0x00800000
|
||||
#define UDMA_DEF_SSI1RX_SEC_ADC10 \
|
||||
0x01000000
|
||||
#define UDMA_DEF_SSI1TX_SEC_ADC11 \
|
||||
0x02000000
|
||||
#define UDMA_DEF_RESERVED_SEC_ADC12 \
|
||||
0x04000000
|
||||
#define UDMA_DEF_RESERVED_SEC_ADC13 \
|
||||
0x08000000
|
||||
#define UDMA_DEF_I2S0RX_SEC_RESERVED \
|
||||
0x10000000
|
||||
#define UDMA_DEF_I2S0TX_SEC_RESERVED \
|
||||
0x20000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to uDMAChannelAssign() to select peripheral
|
||||
// mapping for each channel. The channels named RESERVED may be assigned
|
||||
// to a peripheral in future parts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Channel 0
|
||||
//
|
||||
#define UDMA_CH0_USB0EP1RX 0x00000000
|
||||
#define UDMA_CH0_UART2RX 0x00010000
|
||||
#define UDMA_CH0_RESERVED2 0x00020000
|
||||
#define UDMA_CH0_TIMER4A 0x00030000
|
||||
#define UDMA_CH0_RESERVED4 0x00040000
|
||||
|
||||
//
|
||||
// Channel 1
|
||||
//
|
||||
#define UDMA_CH1_USB0EP1TX 0x00000001
|
||||
#define UDMA_CH1_UART2TX 0x00010001
|
||||
#define UDMA_CH1_RESERVED2 0x00020001
|
||||
#define UDMA_CH1_TIMER4B 0x00030001
|
||||
#define UDMA_CH1_RESERVED4 0x00040001
|
||||
|
||||
//
|
||||
// Channel 2
|
||||
//
|
||||
#define UDMA_CH2_USB0EP2RX 0x00000002
|
||||
#define UDMA_CH2_TIMER3A 0x00010002
|
||||
#define UDMA_CH2_RESERVED2 0x00020002
|
||||
#define UDMA_CH2_RESERVED3 0x00030002
|
||||
#define UDMA_CH2_RESERVED4 0x00040002
|
||||
|
||||
//
|
||||
// Channel 3
|
||||
//
|
||||
#define UDMA_CH3_USB0EP2TX 0x00000003
|
||||
#define UDMA_CH3_TIMER3B 0x00010003
|
||||
#define UDMA_CH3_RESERVED2 0x00020003
|
||||
#define UDMA_CH3_LPC0_3 0x00030003
|
||||
#define UDMA_CH3_RESERVED4 0x00040003
|
||||
|
||||
//
|
||||
// Channel 4
|
||||
//
|
||||
#define UDMA_CH4_USB0EP3RX 0x00000004
|
||||
#define UDMA_CH4_TIMER2A 0x00010004
|
||||
#define UDMA_CH4_RESERVED2 0x00020004
|
||||
#define UDMA_CH4_GPIOA 0x00030004
|
||||
#define UDMA_CH4_RESERVED4 0x00040004
|
||||
|
||||
//
|
||||
// Channel 5
|
||||
//
|
||||
#define UDMA_CH5_USB0EP3TX 0x00000005
|
||||
#define UDMA_CH5_TIMER2B 0x00010005
|
||||
#define UDMA_CH5_RESERVED2 0x00020005
|
||||
#define UDMA_CH5_GPIOB 0x00030005
|
||||
#define UDMA_CH5_RESERVED4 0x00040005
|
||||
|
||||
//
|
||||
// Channel 6
|
||||
//
|
||||
#define UDMA_CH6_RESERVED0 0x00000006
|
||||
#define UDMA_CH6_TIMER2A 0x00010006
|
||||
#define UDMA_CH6_UART5RX 0x00020006
|
||||
#define UDMA_CH6_GPIOC 0x00030006
|
||||
#define UDMA_CH6_I2C0RX 0x00040006
|
||||
|
||||
//
|
||||
// Channel 7
|
||||
//
|
||||
#define UDMA_CH7_RESERVED0 0x00000007
|
||||
#define UDMA_CH7_TIMER2B 0x00010007
|
||||
#define UDMA_CH7_UART5TX 0x00020007
|
||||
#define UDMA_CH7_GPIOD 0x00030007
|
||||
#define UDMA_CH7_I2C0TX 0x00040007
|
||||
|
||||
//
|
||||
// Channel 8
|
||||
//
|
||||
#define UDMA_CH8_UART0RX 0x00000008
|
||||
#define UDMA_CH8_UART1RX 0x00010008
|
||||
#define UDMA_CH8_RESERVED2 0x00020008
|
||||
#define UDMA_CH8_TIMER5A 0x00030008
|
||||
#define UDMA_CH8_I2C1RX 0x00040008
|
||||
|
||||
//
|
||||
// Channel 9
|
||||
//
|
||||
#define UDMA_CH9_UART0TX 0x00000009
|
||||
#define UDMA_CH9_UART1TX 0x00010009
|
||||
#define UDMA_CH9_RESERVED2 0x00020009
|
||||
#define UDMA_CH9_TIMER5B 0x00030009
|
||||
#define UDMA_CH9_I2C1TX 0x00040009
|
||||
|
||||
//
|
||||
// Channel 10
|
||||
//
|
||||
#define UDMA_CH10_SSI0RX 0x0000000A
|
||||
#define UDMA_CH10_SSI1RX 0x0001000A
|
||||
#define UDMA_CH10_UART6RX 0x0002000A
|
||||
#define UDMA_CH10_WTIMER0A 0x0003000A
|
||||
#define UDMA_CH10_I2C2RX 0x0004000A
|
||||
|
||||
//
|
||||
// Channel 11
|
||||
//
|
||||
#define UDMA_CH11_SSI0TX 0x0000000B
|
||||
#define UDMA_CH11_SSI1TX 0x0001000B
|
||||
#define UDMA_CH11_UART6TX 0x0002000B
|
||||
#define UDMA_CH11_WTIMER0B 0x0003000B
|
||||
#define UDMA_CH11_I2C2TX 0x0004000B
|
||||
|
||||
//
|
||||
// Channel 12
|
||||
//
|
||||
#define UDMA_CH12_RESERVED0 0x0000000C
|
||||
#define UDMA_CH12_UART2RX 0x0001000C
|
||||
#define UDMA_CH12_SSI2RX 0x0002000C
|
||||
#define UDMA_CH12_WTIMER1A 0x0003000C
|
||||
#define UDMA_CH12_GPIOK 0x0004000C
|
||||
|
||||
//
|
||||
// Channel 13
|
||||
//
|
||||
#define UDMA_CH13_RESERVED0 0x0000000D
|
||||
#define UDMA_CH13_UART2TX 0x0001000D
|
||||
#define UDMA_CH13_SSI2TX 0x0002000D
|
||||
#define UDMA_CH13_WTIMER1B 0x0003000D
|
||||
#define UDMA_CH13_GPIOL 0x0004000D
|
||||
|
||||
//
|
||||
// Channel 14
|
||||
//
|
||||
#define UDMA_CH14_ADC0_0 0x0000000E
|
||||
#define UDMA_CH14_TIMER2A 0x0001000E
|
||||
#define UDMA_CH14_SSI3RX 0x0002000E
|
||||
#define UDMA_CH14_GPIOE 0x0003000E
|
||||
#define UDMA_CH14_GPIOM 0x0004000E
|
||||
|
||||
//
|
||||
// Channel 15
|
||||
//
|
||||
#define UDMA_CH15_ADC0_1 0x0000000F
|
||||
#define UDMA_CH15_TIMER2B 0x0001000F
|
||||
#define UDMA_CH15_SSI3TX 0x0002000F
|
||||
#define UDMA_CH15_GPIOF 0x0003000F
|
||||
#define UDMA_CH15_GPION 0x0004000F
|
||||
|
||||
//
|
||||
// Channel 16
|
||||
//
|
||||
#define UDMA_CH16_ADC0_2 0x00000010
|
||||
#define UDMA_CH16_RESERVED1 0x00010010
|
||||
#define UDMA_CH16_UART3RX 0x00020010
|
||||
#define UDMA_CH16_WTIMER2A 0x00030010
|
||||
#define UDMA_CH16_GPIOP 0x00040010
|
||||
|
||||
//
|
||||
// Channel 17
|
||||
//
|
||||
#define UDMA_CH17_ADC0_3 0x00000011
|
||||
#define UDMA_CH17_RESERVED1 0x00010011
|
||||
#define UDMA_CH17_UART3TX 0x00020011
|
||||
#define UDMA_CH17_WTIMER2B 0x00030011
|
||||
#define UDMA_CH17_RESERVED4 0x00040011
|
||||
|
||||
//
|
||||
// Channel 18
|
||||
//
|
||||
#define UDMA_CH18_TIMER0A 0x00000012
|
||||
#define UDMA_CH18_TIMER1A 0x00010012
|
||||
#define UDMA_CH18_UART4RX 0x00020012
|
||||
#define UDMA_CH18_GPIOB 0x00030012
|
||||
#define UDMA_CH18_I2C3RX 0x00040012
|
||||
|
||||
//
|
||||
// Channel 19
|
||||
//
|
||||
#define UDMA_CH19_TIMER0B 0x00000013
|
||||
#define UDMA_CH19_TIMER1B 0x00010013
|
||||
#define UDMA_CH19_UART4TX 0x00020013
|
||||
#define UDMA_CH19_GPIOG 0x00030013
|
||||
#define UDMA_CH19_I2C3TX 0x00040013
|
||||
|
||||
//
|
||||
// Channel 20
|
||||
//
|
||||
#define UDMA_CH20_TIMER1A 0x00000014
|
||||
#define UDMA_CH20_RESERVED1 0x00010014
|
||||
#define UDMA_CH20_UART7RX 0x00020014
|
||||
#define UDMA_CH20_GPIOH 0x00030014
|
||||
#define UDMA_CH20_I2C4RX 0x00040014
|
||||
|
||||
//
|
||||
// Channel 21
|
||||
//
|
||||
#define UDMA_CH21_TIMER1B 0x00000015
|
||||
#define UDMA_CH21_RESERVED1 0x00010015
|
||||
#define UDMA_CH21_UART7TX 0x00020015
|
||||
#define UDMA_CH21_GPIOJ 0x00030015
|
||||
#define UDMA_CH21_I2C4TX 0x00040015
|
||||
|
||||
//
|
||||
// Channel 22
|
||||
//
|
||||
#define UDMA_CH22_UART1RX 0x00000016
|
||||
#define UDMA_CH22_RESERVED1 0x00010016
|
||||
#define UDMA_CH22_RESERVED2 0x00020016
|
||||
#define UDMA_CH22_LPC0_2 0x00030016
|
||||
#define UDMA_CH22_I2C5RX 0x00040016
|
||||
|
||||
//
|
||||
// Channel 23
|
||||
//
|
||||
#define UDMA_CH23_UART1TX 0x00000017
|
||||
#define UDMA_CH23_RESERVED1 0x00010017
|
||||
#define UDMA_CH23_RESERVED2 0x00020017
|
||||
#define UDMA_CH23_LPC0_1 0x00030017
|
||||
#define UDMA_CH23_I2C5TX 0x00040017
|
||||
|
||||
//
|
||||
// Channel 24
|
||||
//
|
||||
#define UDMA_CH24_SSI1RX 0x00000018
|
||||
#define UDMA_CH24_ADC1_0 0x00010018
|
||||
#define UDMA_CH24_RESERVED2 0x00020018
|
||||
#define UDMA_CH24_WTIMER3A 0x00030018
|
||||
#define UDMA_CH24_GPIOQ 0x00040018
|
||||
|
||||
//
|
||||
// Channel 25
|
||||
//
|
||||
#define UDMA_CH25_SSI1TX 0x00000019
|
||||
#define UDMA_CH25_ADC1_1 0x00010019
|
||||
#define UDMA_CH25_RESERVED2 0x00020019
|
||||
#define UDMA_CH25_WTIMER3B 0x00030019
|
||||
#define UDMA_CH25_RESERVED4 0x00040019
|
||||
|
||||
//
|
||||
// Channel 26
|
||||
//
|
||||
#define UDMA_CH26_RESERVED0 0x0000001A
|
||||
#define UDMA_CH26_ADC1_2 0x0001001A
|
||||
#define UDMA_CH26_RESERVED2 0x0002001A
|
||||
#define UDMA_CH26_WTIMER4A 0x0003001A
|
||||
#define UDMA_CH26_RESERVED4 0x0004001A
|
||||
|
||||
//
|
||||
// Channel 27
|
||||
//
|
||||
#define UDMA_CH27_RESERVED0 0x0000001B
|
||||
#define UDMA_CH27_ADC1_3 0x0001001B
|
||||
#define UDMA_CH27_RESERVED2 0x0002001B
|
||||
#define UDMA_CH27_WTIMER4B 0x0003001B
|
||||
#define UDMA_CH27_RESERVED4 0x0004001B
|
||||
|
||||
//
|
||||
// Channel 28
|
||||
//
|
||||
#define UDMA_CH28_RESERVED0 0x0000001C
|
||||
#define UDMA_CH28_RESERVED1 0x0001001C
|
||||
#define UDMA_CH28_RESERVED2 0x0002001C
|
||||
#define UDMA_CH28_WTIMER5A 0x0003001C
|
||||
#define UDMA_CH28_RESERVED4 0x0004001C
|
||||
|
||||
//
|
||||
// Channel 29
|
||||
//
|
||||
#define UDMA_CH29_RESERVED0 0x0000001D
|
||||
#define UDMA_CH29_RESERVED1 0x0001001D
|
||||
#define UDMA_CH29_RESERVED2 0x0002001D
|
||||
#define UDMA_CH29_WTIMER5B 0x0003001D
|
||||
#define UDMA_CH29_RESERVED4 0x0004001D
|
||||
|
||||
//
|
||||
// Channel 30
|
||||
//
|
||||
#define UDMA_CH30_SW 0x0000001E
|
||||
#define UDMA_CH30_RESERVED1 0x0001001E
|
||||
#define UDMA_CH30_RESERVED2 0x0002001E
|
||||
#define UDMA_CH30_RESERVED3 0x0003001E
|
||||
#define UDMA_CH30_RESERVED4 0x0004001E
|
||||
|
||||
//
|
||||
// Channel 31
|
||||
//
|
||||
#define UDMA_CH31_RESERVED0 0x0000001F
|
||||
#define UDMA_CH31_RESERVED1 0x0001001F
|
||||
#define UDMA_CH31_RESERVED2 0x0002001F
|
||||
#define UDMA_CH31_LPC0_0 0x0003001F
|
||||
#define UDMA_CH31_RESERVED4 0x0004001F
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void uDMAEnable(void);
|
||||
extern void uDMADisable(void);
|
||||
extern uint32_t uDMAErrorStatusGet(void);
|
||||
extern void uDMAErrorStatusClear(void);
|
||||
extern void uDMAChannelEnable(uint32_t ui32ChannelNum);
|
||||
extern void uDMAChannelDisable(uint32_t ui32ChannelNum);
|
||||
extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum);
|
||||
extern void uDMAControlBaseSet(void *pControlTable);
|
||||
extern void *uDMAControlBaseGet(void);
|
||||
extern void *uDMAControlAlternateBaseGet(void);
|
||||
extern void uDMAChannelRequest(uint32_t ui32ChannelNum);
|
||||
extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum,
|
||||
uint32_t ui32Attr);
|
||||
extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum,
|
||||
uint32_t ui32Attr);
|
||||
extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum);
|
||||
extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex,
|
||||
uint32_t ui32Control);
|
||||
extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex,
|
||||
uint32_t ui32Mode, void *pvSrcAddr,
|
||||
void *pvDstAddr, uint32_t ui32TransferSize);
|
||||
extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum,
|
||||
uint32_t ui32TaskCount,
|
||||
void *pvTaskList,
|
||||
uint32_t ui32IsPeriphSG);
|
||||
extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex);
|
||||
extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex);
|
||||
extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void));
|
||||
extern void uDMAIntUnregister(uint32_t ui32IntChannel);
|
||||
extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs);
|
||||
extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs);
|
||||
extern uint32_t uDMAIntStatus(void);
|
||||
extern void uDMAIntClear(uint32_t ui32ChanMask);
|
||||
extern void uDMAChannelAssign(uint32_t ui32Mapping);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_UDMA_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,481 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// usb.h - Prototypes for the USB Interface Driver.
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_USB_H__
|
||||
#define __DRIVERLIB_USB_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBIntEnableControl() and
|
||||
// USBIntDisableControl() as the ui32Flags parameter, and are returned from
|
||||
// USBIntStatusControl().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources
|
||||
#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts
|
||||
#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error
|
||||
#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected
|
||||
#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected
|
||||
#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected
|
||||
#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected
|
||||
#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected
|
||||
#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled
|
||||
#define USB_INTCTRL_RESET 0x00000004 // Reset signaled
|
||||
#define USB_INTCTRL_RESUME 0x00000002 // Resume detected
|
||||
#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected
|
||||
#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid
|
||||
#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBIntEnableEndpoint() and
|
||||
// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from
|
||||
// USBIntStatusEndpoint().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts
|
||||
#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts
|
||||
#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt
|
||||
#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt
|
||||
|
||||
#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts
|
||||
#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt
|
||||
#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt
|
||||
|
||||
#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts
|
||||
#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt
|
||||
#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt
|
||||
|
||||
#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts
|
||||
#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt
|
||||
#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt
|
||||
|
||||
#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that are returned from USBSpeedGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
|
||||
#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
|
||||
#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that are returned from USBEndpointStatus(). The
|
||||
// USB_HOST_* values are used when the USB controller is in host mode and the
|
||||
// USB_DEV_* values are used when the USB controller is in device mode.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts
|
||||
#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received
|
||||
#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond
|
||||
#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
|
||||
#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
|
||||
// (ISOC Mode)
|
||||
#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
|
||||
// specified timeout period
|
||||
#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
|
||||
// device
|
||||
#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
|
||||
#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
|
||||
#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts
|
||||
#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
|
||||
// specified timeout period
|
||||
#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
|
||||
// (ISOC mode)
|
||||
#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
|
||||
#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
|
||||
// device
|
||||
#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
|
||||
#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
|
||||
#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
|
||||
// specified timeout period
|
||||
#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
|
||||
#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
|
||||
// device
|
||||
#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
|
||||
#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
|
||||
#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous
|
||||
// transfer
|
||||
#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
|
||||
#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
|
||||
#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
|
||||
// a full FIFO
|
||||
#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
|
||||
#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
|
||||
#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
|
||||
// to come
|
||||
#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
|
||||
#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
|
||||
#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
|
||||
#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
|
||||
#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
|
||||
// Data End seen
|
||||
#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
|
||||
#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
|
||||
#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBHostEndpointConfig() and
|
||||
// USBDevEndpointConfigSet() as the ui32Flags parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
|
||||
#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
|
||||
#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
|
||||
#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
|
||||
#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
|
||||
#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
|
||||
#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
|
||||
#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
|
||||
#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
|
||||
#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
|
||||
#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
|
||||
#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
|
||||
#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint
|
||||
#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
|
||||
#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
|
||||
#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBHostPwrConfig() as the
|
||||
// ui32Flags parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_HOST_PWRFLT_LOW 0x00000010
|
||||
#define USB_HOST_PWRFLT_HIGH 0x00000030
|
||||
#define USB_HOST_PWRFLT_EP_NONE 0x00000000
|
||||
#define USB_HOST_PWRFLT_EP_TRI 0x00000140
|
||||
#define USB_HOST_PWRFLT_EP_LOW 0x00000240
|
||||
#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
|
||||
#define USB_HOST_PWREN_MAN_LOW 0x00000000
|
||||
#define USB_HOST_PWREN_MAN_HIGH 0x00000001
|
||||
#define USB_HOST_PWREN_AUTOLOW 0x00000002
|
||||
#define USB_HOST_PWREN_AUTOHIGH 0x00000003
|
||||
#define USB_HOST_PWREN_FILTER 0x00010000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are special values that can be passed to
|
||||
// USBHostEndpointConfig() as the ui32NAKPollInterval parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MAX_NAK_LIMIT 31 // Maximum NAK interval
|
||||
#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This value specifies the maximum size of transfers on endpoint 0 as 64
|
||||
// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define MAX_PACKET_SIZE_EP0 64
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These values are used to indicate which endpoint to access.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_EP_0 0x00000000 // Endpoint 0
|
||||
#define USB_EP_1 0x00000010 // Endpoint 1
|
||||
#define USB_EP_2 0x00000020 // Endpoint 2
|
||||
#define USB_EP_3 0x00000030 // Endpoint 3
|
||||
#define USB_EP_4 0x00000040 // Endpoint 4
|
||||
#define USB_EP_5 0x00000050 // Endpoint 5
|
||||
#define USB_EP_6 0x00000060 // Endpoint 6
|
||||
#define USB_EP_7 0x00000070 // Endpoint 7
|
||||
#define NUM_USB_EP 8 // Number of supported endpoints
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These macros allow conversion between 0-based endpoint indices and the
|
||||
// USB_EP_x values required when calling various USB APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define IndexToUSBEP(x) ((x) << 4)
|
||||
#define USBEPToIndex(x) ((x) >> 4)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBFIFOConfigSet() as the
|
||||
// ui32FIFOSize parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
|
||||
#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
|
||||
#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
|
||||
#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
|
||||
#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
|
||||
#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
|
||||
#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
|
||||
#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
|
||||
#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This macro allow conversion from a FIFO size label as defined above to
|
||||
// a number of bytes
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USBFIFOSizeToBytes(x) (8 << (x))
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to USBEndpointDataSend() as the
|
||||
// ui32TransType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
|
||||
#define USB_TRANS_IN 0x00000102 // Normal IN transaction
|
||||
#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
|
||||
// endpoint 0 in device mode)
|
||||
#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
|
||||
// 0)
|
||||
#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
|
||||
// 0)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values are returned by the USBModeGet function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
|
||||
// mode.
|
||||
#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
|
||||
// Device mode.
|
||||
#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
|
||||
// set.
|
||||
#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of
|
||||
// the cable Session Valid.
|
||||
#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of
|
||||
// the cable A valid.
|
||||
#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
|
||||
// the cable.
|
||||
#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint32_t USBDevAddrGet(uint32_t ui32Base);
|
||||
extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address);
|
||||
extern void USBDevConnect(uint32_t ui32Base);
|
||||
extern void USBDevDisconnect(uint32_t ui32Base);
|
||||
extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32MaxPacketSize,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t *pui32MaxPacketSize,
|
||||
uint32_t *pui32Flags);
|
||||
extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
bool bIsLastPacket);
|
||||
extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint);
|
||||
extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Config);
|
||||
extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint8_t *pui8Data, uint32_t *pui32Size);
|
||||
extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint8_t *pui8Data, uint32_t ui32Size);
|
||||
extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32TransType);
|
||||
extern void USBEndpointDataToggleClear(uint32_t ui32Base,
|
||||
uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Count);
|
||||
extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint);
|
||||
extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint);
|
||||
extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t *pui32FIFOAddress,
|
||||
uint32_t *pui32FIFOSize, uint32_t ui32Flags);
|
||||
extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern uint32_t USBFrameNumberGet(uint32_t ui32Base);
|
||||
extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Addr, uint32_t ui32Flags);
|
||||
extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32MaxPacketSize,
|
||||
uint32_t ui32NAKPollInterval,
|
||||
uint32_t ui32TargetEndpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBHostEndpointDataAck(uint32_t ui32Base,
|
||||
uint32_t ui32Endpoint);
|
||||
extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
bool bDataToggle, uint32_t ui32Flags);
|
||||
extern void USBHostEndpointStatusClear(uint32_t ui32Base,
|
||||
uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Flags);
|
||||
extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Addr, uint32_t ui32Flags);
|
||||
extern void USBHostPwrDisable(uint32_t ui32Base);
|
||||
extern void USBHostPwrEnable(uint32_t ui32Base);
|
||||
extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags);
|
||||
extern void USBHostPwrFaultDisable(uint32_t ui32Base);
|
||||
extern void USBHostPwrFaultEnable(uint32_t ui32Base);
|
||||
extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint);
|
||||
extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint);
|
||||
extern void USBHostRequestStatus(uint32_t ui32Base);
|
||||
extern void USBHostReset(uint32_t ui32Base, bool bStart);
|
||||
extern void USBHostResume(uint32_t ui32Base, bool bStart);
|
||||
extern uint32_t USBHostSpeedGet(uint32_t ui32Base);
|
||||
extern void USBHostSuspend(uint32_t ui32Base);
|
||||
extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern uint32_t USBIntStatusControl(uint32_t ui32Base);
|
||||
extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
|
||||
extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base);
|
||||
extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern void USBIntUnregister(uint32_t ui32Base);
|
||||
extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart);
|
||||
extern uint32_t USBModeGet(uint32_t ui32Base);
|
||||
extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
|
||||
uint32_t ui32Channel);
|
||||
extern void USBHostMode(uint32_t ui32Base);
|
||||
extern void USBDevMode(uint32_t ui32Base);
|
||||
extern void USBOTGMode(uint32_t ui32Base);
|
||||
extern void USBPHYPowerOff(uint32_t ui32Base);
|
||||
extern void USBPHYPowerOn(uint32_t ui32Base);
|
||||
extern uint32_t USBNumEndpointsGet(uint32_t ui32Base);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_USB_H__
|
|
@ -0,0 +1,618 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// watchdog.c - Driver for the Watchdog Timer Module.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup watchdog_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "inc/hw_watchdog.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
#include "driverlib/watchdog.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Determines if the watchdog timer is enabled.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function checks to see if the watchdog timer is enabled.
|
||||
//!
|
||||
//! \return Returns \b true if the watchdog timer is enabled and \b false
|
||||
//! if it is not.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
WatchdogRunning(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// See if the watchdog timer module is enabled, and return.
|
||||
//
|
||||
return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the watchdog timer.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function enables the watchdog timer counter and interrupt.
|
||||
//!
|
||||
//! \note This function has no effect if the watchdog timer has been locked.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Enable the watchdog timer module.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the watchdog timer reset.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function enables the capability of the watchdog timer to issue a reset
|
||||
//! to the processor after a second timeout condition.
|
||||
//!
|
||||
//! \note This function has no effect if the watchdog timer has been locked.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogResetEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Enable the watchdog reset.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the watchdog timer reset.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function disables the capability of the watchdog timer to issue a
|
||||
//! reset to the processor after a second timeout condition.
|
||||
//!
|
||||
//! \note This function has no effect if the watchdog timer has been locked.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogResetDisable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Disable the watchdog reset.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the watchdog timer lock mechanism.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function locks out write access to the watchdog timer configuration
|
||||
//! registers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogLock(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
|
||||
// register causes the lock to go into effect.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the watchdog timer lock mechanism.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function enables write access to the watchdog timer configuration
|
||||
//! registers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogUnlock(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Unlock watchdog register writes.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the state of the watchdog timer lock mechanism.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function returns the lock state of the watchdog timer registers.
|
||||
//!
|
||||
//! \return Returns \b true if the watchdog timer registers are locked, and
|
||||
//! \b false if they are not locked.
|
||||
//
|
||||
//*****************************************************************************
|
||||
bool
|
||||
WatchdogLockState(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Get the lock state.
|
||||
//
|
||||
return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the watchdog timer reload value.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//! \param ui32LoadVal is the load value for the watchdog timer.
|
||||
//!
|
||||
//! This function configures the value to load into the watchdog timer when the
|
||||
//! count reaches zero for the first time; if the watchdog timer is running
|
||||
//! when this function is called, then the value is immediately loaded into the
|
||||
//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an
|
||||
//! interrupt is immediately generated.
|
||||
//!
|
||||
//! \note This function has no effect if the watchdog timer has been locked.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Set the load register.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the watchdog timer reload value.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function gets the value that is loaded into the watchdog timer when
|
||||
//! the count reaches zero for the first time.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
WatchdogReloadGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Get the load register.
|
||||
//
|
||||
return(HWREG(ui32Base + WDT_O_LOAD));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current watchdog timer value.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function reads the current value of the watchdog timer.
|
||||
//!
|
||||
//! \return Returns the current value of the watchdog timer.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
WatchdogValueGet(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Get the current watchdog timer register value.
|
||||
//
|
||||
return(HWREG(ui32Base + WDT_O_VALUE));
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers an interrupt handler for the watchdog timer interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//! \param pfnHandler is a pointer to the function to be called when the
|
||||
//! watchdog timer interrupt occurs.
|
||||
//!
|
||||
//! This function does the actual registering of the interrupt handler. This
|
||||
//! function also enables the global interrupt in the interrupt controller; the
|
||||
//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the
|
||||
//! interrupt handler's responsibility to clear the interrupt source via
|
||||
//! WatchdogIntClear().
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \note For parts with a watchdog timer module that has the ability to
|
||||
//! generate an NMI instead of a standard interrupt, this function registers
|
||||
//! the standard watchdog interrupt handler. To register the NMI watchdog
|
||||
//! handler, use IntRegister() to register the handler for the
|
||||
//! \b FAULT_NMI interrupt.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Register the interrupt handler.
|
||||
//
|
||||
IntRegister(INT_WATCHDOG_BLIZZARD, pfnHandler);
|
||||
|
||||
//
|
||||
// Enable the watchdog timer interrupt.
|
||||
//
|
||||
IntEnable(INT_WATCHDOG_BLIZZARD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters an interrupt handler for the watchdog timer interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function does the actual unregistering of the interrupt handler. This
|
||||
//! function clears the handler to be called when a watchdog timer interrupt
|
||||
//! occurs. This function also masks off the interrupt in the interrupt
|
||||
//! controller so that the interrupt handler no longer is called.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \note For parts with a watchdog timer module that has the ability to
|
||||
//! generate an NMI instead of a standard interrupt, this function unregisters
|
||||
//! the standard watchdog interrupt handler. To unregister the NMI watchdog
|
||||
//! handler, use IntUnregister() to unregister the handler for the
|
||||
//! \b FAULT_NMI interrupt.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogIntUnregister(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Disable the interrupt.
|
||||
//
|
||||
IntDisable(INT_WATCHDOG_BLIZZARD);
|
||||
|
||||
//
|
||||
// Unregister the interrupt handler.
|
||||
//
|
||||
IntUnregister(INT_WATCHDOG_BLIZZARD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the watchdog timer interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function enables the watchdog timer interrupt.
|
||||
//!
|
||||
//! \note This function has no effect if the watchdog timer has been locked.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogIntEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Enable the watchdog interrupt.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the current watchdog timer interrupt status.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//! \param bMasked is \b false if the raw interrupt status is required and
|
||||
//! \b true if the masked interrupt status is required.
|
||||
//!
|
||||
//! This function returns the interrupt status for the watchdog timer module.
|
||||
//! Either the raw interrupt status or the status of interrupt that is allowed
|
||||
//! to reflect to the processor can be returned.
|
||||
//!
|
||||
//! \return Returns the current interrupt status, where a 1 indicates that the
|
||||
//! watchdog interrupt is active, and a 0 indicates that it is not active.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
WatchdogIntStatus(uint32_t ui32Base, bool bMasked)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Return either the interrupt status or the raw interrupt status as
|
||||
// requested.
|
||||
//
|
||||
if(bMasked)
|
||||
{
|
||||
return(HWREG(ui32Base + WDT_O_MIS));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(HWREG(ui32Base + WDT_O_RIS));
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Clears the watchdog timer interrupt.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! The watchdog timer interrupt source is cleared, so that it no longer
|
||||
//! asserts.
|
||||
//!
|
||||
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||||
//! take several clock cycles before the interrupt source is actually cleared.
|
||||
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||||
//! the interrupt handler (as opposed to the very last action) to avoid
|
||||
//! returning from the interrupt handler before the interrupt source is
|
||||
//! actually cleared. Failure to do so may result in the interrupt handler
|
||||
//! being immediately reentered (because the interrupt controller still sees
|
||||
//! the interrupt source asserted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogIntClear(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Clear the interrupt source.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the type of interrupt generated by the watchdog.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//! \param ui32Type is the type of interrupt to generate.
|
||||
//!
|
||||
//! This function sets the type of interrupt that is generated if the watchdog
|
||||
//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to
|
||||
//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
|
||||
//! generate a non-maskable interrupt (NMI).
|
||||
//!
|
||||
//! When configured to generate an NMI, the watchdog interrupt must still be
|
||||
//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
|
||||
//! NMI handler with WatchdogIntClear().
|
||||
//!
|
||||
//! \note The ability to select an NMI interrupt varies with the Tiva part
|
||||
//! in use. Please consult the datasheet for the part you are using to
|
||||
//! determine whether this support is available.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) ||
|
||||
(ui32Type == WATCHDOG_INT_TYPE_NMI));
|
||||
|
||||
//
|
||||
// Set the interrupt type.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) &
|
||||
~WDT_CTL_INTTYPE) | ui32Type;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables stalling of the watchdog timer during debug events.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function allows the watchdog timer to stop counting when the processor
|
||||
//! is stopped by the debugger. By doing so, the watchdog is prevented from
|
||||
//! expiring (typically almost immediately from a human time perspective) and
|
||||
//! resetting the system (if reset is enabled). The watchdog instead expires
|
||||
//! after the appropriate number of processor cycles have been executed while
|
||||
//! debugging (or at the appropriate time after the processor has been
|
||||
//! restarted).
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogStallEnable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Enable timer stalling.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables stalling of the watchdog timer during debug events.
|
||||
//!
|
||||
//! \param ui32Base is the base address of the watchdog timer module.
|
||||
//!
|
||||
//! This function disables the debug mode stall of the watchdog timer. By
|
||||
//! doing so, the watchdog timer continues to count regardless of the processor
|
||||
//! debug state.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
WatchdogStallDisable(uint32_t ui32Base)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||||
|
||||
//
|
||||
// Disable timer stalling.
|
||||
//
|
||||
HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
|
@ -0,0 +1,95 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// watchdog.h - Prototypes for the Watchdog Timer API
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DRIVERLIB_WATCHDOG_H__
|
||||
#define __DRIVERLIB_WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The type of interrupt that can be generated by the watchdog.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_INT_TYPE_INT 0x00000000
|
||||
#define WATCHDOG_INT_TYPE_NMI 0x00000004
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern bool WatchdogRunning(uint32_t ui32Base);
|
||||
extern void WatchdogEnable(uint32_t ui32Base);
|
||||
extern void WatchdogResetEnable(uint32_t ui32Base);
|
||||
extern void WatchdogResetDisable(uint32_t ui32Base);
|
||||
extern void WatchdogLock(uint32_t ui32Base);
|
||||
extern void WatchdogUnlock(uint32_t ui32Base);
|
||||
extern bool WatchdogLockState(uint32_t ui32Base);
|
||||
extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal);
|
||||
extern uint32_t WatchdogReloadGet(uint32_t ui32Base);
|
||||
extern uint32_t WatchdogValueGet(uint32_t ui32Base);
|
||||
extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
|
||||
extern void WatchdogIntUnregister(uint32_t ui32Base);
|
||||
extern void WatchdogIntEnable(uint32_t ui32Base);
|
||||
extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked);
|
||||
extern void WatchdogIntClear(uint32_t ui32Base);
|
||||
extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type);
|
||||
extern void WatchdogStallEnable(uint32_t ui32Base);
|
||||
extern void WatchdogStallDisable(uint32_t ui32Base);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRIVERLIB_WATCHDOG_H__
|
|
@ -0,0 +1,227 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ASMDEFS_H__
|
||||
#define __ASMDEFS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for code_red.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef codered
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // codered
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for EW-ARM.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef ewarm
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ module
|
||||
#define __TEXT__ rseg CODE:CODE(2)
|
||||
#define __DATA__ rseg DATA:DATA(2)
|
||||
#define __BSS__ rseg DATA:DATA(2)
|
||||
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ alignrom 2
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__ thumb
|
||||
#define __WORD__ dcd
|
||||
#define __INLINE_DATA__ data
|
||||
|
||||
#endif // ewarm
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for GCC.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(gcc)
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // gcc
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for RV-MDK.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef rvmdk
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
thumb
|
||||
require8
|
||||
preserve8
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ ;
|
||||
#define __TEXT__ area ||.text||, code, readonly, align=2
|
||||
#define __DATA__ area ||.data||, data, align=2
|
||||
#define __BSS__ area ||.bss||, noinit, align=2
|
||||
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ align 4
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__
|
||||
#define __WORD__ dcd
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // rvmdk
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for Sourcery G++.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(sourcerygxx)
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // sourcerygxx
|
||||
|
||||
#endif // __ASMDEF_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,462 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_can.h - Defines and macros used when accessing the CAN controllers.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_CAN_H__
|
||||
#define __HW_CAN_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the CAN register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_O_CTL 0x00000000 // CAN Control
|
||||
#define CAN_O_STS 0x00000004 // CAN Status
|
||||
#define CAN_O_ERR 0x00000008 // CAN Error Counter
|
||||
#define CAN_O_BIT 0x0000000C // CAN Bit Timing
|
||||
#define CAN_O_INT 0x00000010 // CAN Interrupt
|
||||
#define CAN_O_TST 0x00000014 // CAN Test
|
||||
#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
|
||||
// Extension
|
||||
#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
|
||||
#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
|
||||
#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
|
||||
#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
|
||||
#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
|
||||
#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
|
||||
#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
|
||||
#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
|
||||
#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
|
||||
#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
|
||||
#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
|
||||
#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
|
||||
#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
|
||||
#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
|
||||
#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
|
||||
#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
|
||||
#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
|
||||
#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
|
||||
#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
|
||||
#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
|
||||
#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
|
||||
#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
|
||||
#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
|
||||
#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
|
||||
#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
|
||||
#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
|
||||
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
|
||||
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
|
||||
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
|
||||
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
|
||||
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
|
||||
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
|
||||
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
|
||||
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
|
||||
#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
|
||||
#define CAN_CTL_INIT 0x00000001 // Initialization
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_STS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
|
||||
#define CAN_STS_EWARN 0x00000040 // Warning Status
|
||||
#define CAN_STS_EPASS 0x00000020 // Error Passive
|
||||
#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
|
||||
#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
|
||||
// Successfully
|
||||
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
|
||||
#define CAN_STS_LEC_NONE 0x00000000 // No Error
|
||||
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
|
||||
#define CAN_STS_LEC_FORM 0x00000002 // Format Error
|
||||
#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
|
||||
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
|
||||
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
|
||||
#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
|
||||
#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_ERR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_ERR_RP 0x00008000 // Received Error Passive
|
||||
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
|
||||
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
|
||||
#define CAN_ERR_REC_S 8
|
||||
#define CAN_ERR_TEC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_BIT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
|
||||
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
|
||||
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
|
||||
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
|
||||
#define CAN_BIT_TSEG2_S 12
|
||||
#define CAN_BIT_TSEG1_S 8
|
||||
#define CAN_BIT_SJW_S 6
|
||||
#define CAN_BIT_BRP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
|
||||
#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
|
||||
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TST_RX 0x00000080 // Receive Observation
|
||||
#define CAN_TST_TX_M 0x00000060 // Transmit Control
|
||||
#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
|
||||
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
|
||||
#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
|
||||
#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
|
||||
#define CAN_TST_LBACK 0x00000010 // Loopback Mode
|
||||
#define CAN_TST_SILENT 0x00000008 // Silent Mode
|
||||
#define CAN_TST_BASIC 0x00000004 // Basic Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_BRPE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
|
||||
#define CAN_BRPE_BRPE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
|
||||
#define CAN_IF1CRQ_MNUM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
|
||||
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
|
||||
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
|
||||
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
|
||||
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
|
||||
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
|
||||
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
|
||||
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
|
||||
#define CAN_IF1MSK1_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
|
||||
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
|
||||
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
|
||||
#define CAN_IF1MSK2_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
|
||||
#define CAN_IF1ARB1_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
|
||||
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
|
||||
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
|
||||
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
|
||||
#define CAN_IF1ARB2_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
|
||||
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
|
||||
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
|
||||
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
|
||||
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
|
||||
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
|
||||
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
|
||||
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
|
||||
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
|
||||
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
|
||||
#define CAN_IF1MCTL_DLC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DA1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DA2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DB1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DB2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
|
||||
#define CAN_IF2CRQ_MNUM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
|
||||
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
|
||||
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
|
||||
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
|
||||
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
|
||||
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
|
||||
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
|
||||
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
|
||||
#define CAN_IF2MSK1_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
|
||||
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
|
||||
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
|
||||
#define CAN_IF2MSK2_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
|
||||
#define CAN_IF2ARB1_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
|
||||
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
|
||||
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
|
||||
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
|
||||
#define CAN_IF2ARB2_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
|
||||
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
|
||||
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
|
||||
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
|
||||
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
|
||||
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
|
||||
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
|
||||
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
|
||||
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
|
||||
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
|
||||
#define CAN_IF2MCTL_DLC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DA1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DA2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DB1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DB2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||||
#define CAN_TXRQ1_TXRQST_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||||
#define CAN_TXRQ2_TXRQST_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
|
||||
#define CAN_NWDA1_NEWDAT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
|
||||
#define CAN_NWDA2_NEWDAT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||||
#define CAN_MSG1INT_INTPND_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||||
#define CAN_MSG2INT_INTPND_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||||
#define CAN_MSG1VAL_MSGVAL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||||
#define CAN_MSG2VAL_MSGVAL_S 0
|
||||
|
||||
#endif // __HW_CAN_H__
|
|
@ -0,0 +1,213 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_comp.h - Macros used when accessing the comparator hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_COMP_H__
|
||||
#define __HW_COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Comparator register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
|
||||
// Interrupt Status
|
||||
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
|
||||
// Status
|
||||
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
|
||||
// Enable
|
||||
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
|
||||
// Voltage Control
|
||||
#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
|
||||
#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
|
||||
#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
|
||||
#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
|
||||
#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
|
||||
#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
|
||||
#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
|
||||
// Properties
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
|
||||
// Status
|
||||
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
|
||||
// Status
|
||||
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
|
||||
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
|
||||
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
|
||||
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
|
||||
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACREFCTL
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
|
||||
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
|
||||
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
|
||||
#define COMP_ACREFCTL_VREF_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
// (VIREF)
|
||||
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
// (VIREF)
|
||||
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
|
||||
#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
|
||||
#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
|
||||
#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
|
||||
#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
|
||||
#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
|
||||
|
||||
#endif // __HW_COMP_H__
|
|
@ -0,0 +1,220 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_eeprom.h - Macros used when accessing the EEPROM controller.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_EEPROM_H__
|
||||
#define __HW_EEPROM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the EEPROM register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
|
||||
#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
|
||||
#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
|
||||
#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
|
||||
#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
|
||||
#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
|
||||
#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
|
||||
// Status
|
||||
#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
|
||||
#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
|
||||
#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
|
||||
#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
|
||||
#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
|
||||
#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
|
||||
#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
|
||||
#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
|
||||
#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EESIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
|
||||
#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
|
||||
#define EEPROM_EESIZE_WORDCNT_S 0
|
||||
#define EEPROM_EESIZE_BLKCNT_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
|
||||
#define EEPROM_EEBLOCK_BLOCK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEOFFSET
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEOFFSET_OFFSET_M \
|
||||
0x0000000F // Current Address Offset
|
||||
#define EEPROM_EEOFFSET_OFFSET_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EERDWR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
|
||||
#define EEPROM_EERDWR_VALUE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EERDWRINC
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EERDWRINC_VALUE_M \
|
||||
0xFFFFFFFF // EEPROM Read or Write Data with
|
||||
// Increment
|
||||
#define EEPROM_EERDWRINC_VALUE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEDONE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
|
||||
#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
|
||||
#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
|
||||
#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
|
||||
#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
|
||||
#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EESUPP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESUPP_START 0x00000001 // Start Erase
|
||||
#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
|
||||
#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
|
||||
#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEUNLOCK
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEUNLOCK_UNLOCK_M \
|
||||
0xFFFFFFFF // EEPROM Unlock
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPROT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
|
||||
#define EEPROM_EEPROT_PROT_RWNPW \
|
||||
0x00000000 // This setting is the default. If
|
||||
// there is no password, the block
|
||||
// is not protected and is readable
|
||||
// and writable
|
||||
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
|
||||
// block is readable or writable
|
||||
// only when unlocked
|
||||
#define EEPROM_EEPROT_PROT_RONPW \
|
||||
0x00000002 // If there is no password, the
|
||||
// block is readable, not writable
|
||||
#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS0_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS1_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS2_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEINT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEHIDE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEDBGME register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
|
||||
#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
|
||||
#define EEPROM_EEDBGME_KEY_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
|
||||
#define EEPROM_PP_SIZE_S 0
|
||||
|
||||
#endif // __HW_EEPROM_H__
|
|
@ -0,0 +1,49 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_fan.h - Macros used when accessing the fan control hardware.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_FAN_H__
|
||||
#define __HW_FAN_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Fan Control register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#endif // __HW_FAN_H__
|
|
@ -0,0 +1,298 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_flash.h - Macros used when accessing the flash controller.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_FLASH_H__
|
||||
#define __HW_FLASH_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the FLASH register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMA 0x400FD000 // Flash Memory Address
|
||||
#define FLASH_FMD 0x400FD004 // Flash Memory Data
|
||||
#define FLASH_FMC 0x400FD008 // Flash Memory Control
|
||||
#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
|
||||
#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
|
||||
// Interrupt Status and Clear
|
||||
#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
|
||||
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
|
||||
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
|
||||
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
|
||||
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
|
||||
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
|
||||
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
|
||||
#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
|
||||
#define FLASH_USERREG0 0x400FE1E0 // User Register 0
|
||||
#define FLASH_USERREG1 0x400FE1E4 // User Register 1
|
||||
#define FLASH_USERREG2 0x400FE1E8 // User Register 2
|
||||
#define FLASH_USERREG3 0x400FE1EC // User Register 3
|
||||
#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
|
||||
// Enable 0
|
||||
#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
|
||||
// Enable 1
|
||||
#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
|
||||
// Enable 2
|
||||
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
|
||||
// Enable 3
|
||||
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
|
||||
// Enable 0
|
||||
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
|
||||
// Enable 1
|
||||
#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
|
||||
// Enable 2
|
||||
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
|
||||
// Enable 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
|
||||
#define FLASH_FMA_OFFSET_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
|
||||
#define FLASH_FMD_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
|
||||
#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
|
||||
#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
|
||||
#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
|
||||
#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
|
||||
#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
|
||||
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
|
||||
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
|
||||
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
|
||||
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
|
||||
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
|
||||
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
|
||||
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
|
||||
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
|
||||
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
|
||||
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCMISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
|
||||
// Status and Clear
|
||||
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
|
||||
// Clear
|
||||
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
|
||||
// Status and Clear
|
||||
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
|
||||
// and Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMC2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
|
||||
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FWBVAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FWBN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FSIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
|
||||
#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_SSIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
|
||||
#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_RMCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_BOOTCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
|
||||
#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
|
||||
#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
|
||||
#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
|
||||
#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
|
||||
#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
|
||||
#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
|
||||
#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
|
||||
#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
|
||||
#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
|
||||
#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
|
||||
#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
|
||||
#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
|
||||
#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
|
||||
#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
|
||||
#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
|
||||
#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
|
||||
#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
|
||||
#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
|
||||
#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
|
||||
#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
|
||||
#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
|
||||
#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
|
||||
#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG0_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG3_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the erase size of the FLASH block that is
|
||||
// erased by an erase operation, and the protect size is the size of the FLASH
|
||||
// block that is protected by each protection register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_PROTECT_SIZE 0x00000800
|
||||
#define FLASH_ERASE_SIZE 0x00000400
|
||||
|
||||
#endif // __HW_FLASH_H__
|
|
@ -0,0 +1,125 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_GPIO_H__
|
||||
#define __HW_GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the GPIO register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_DATA 0x00000000 // GPIO Data
|
||||
#define GPIO_O_DIR 0x00000400 // GPIO Direction
|
||||
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
|
||||
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
|
||||
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
|
||||
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
|
||||
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
|
||||
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
|
||||
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
|
||||
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
|
||||
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
|
||||
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
|
||||
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
|
||||
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
|
||||
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
|
||||
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
|
||||
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
|
||||
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
|
||||
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
|
||||
#define GPIO_O_CR 0x00000524 // GPIO Commit
|
||||
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
|
||||
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
|
||||
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
|
||||
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
|
||||
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
|
||||
#define GPIO_IM_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
|
||||
#define GPIO_RIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
|
||||
#define GPIO_MIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
|
||||
#define GPIO_ICR_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
|
||||
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
|
||||
// and may be modified
|
||||
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
|
||||
// and may not be modified
|
||||
#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_SI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
|
||||
|
||||
#endif // __HW_GPIO_H__
|
|
@ -0,0 +1,188 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_hibernate.h - Defines and Macros for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_HIBERNATE_H__
|
||||
#define __HW_HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Hibernation module register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
|
||||
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
|
||||
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
|
||||
#define HIB_CTL 0x400FC010 // Hibernation Control
|
||||
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
|
||||
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
|
||||
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
|
||||
// Status
|
||||
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
|
||||
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
|
||||
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
|
||||
#define HIB_DATA 0x400FC030 // Hibernation Data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
|
||||
#define HIB_RTCC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
|
||||
#define HIB_RTCM0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCLD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
|
||||
#define HIB_RTCLD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
|
||||
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
|
||||
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
|
||||
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
|
||||
// Comparator
|
||||
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
|
||||
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
|
||||
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
|
||||
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
|
||||
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
|
||||
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
|
||||
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
|
||||
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
|
||||
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
|
||||
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
|
||||
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
|
||||
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
|
||||
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
|
||||
// Interrupt Mask
|
||||
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
|
||||
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
|
||||
// Mask
|
||||
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
|
||||
// Status
|
||||
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
|
||||
#define HIB_RTCT_TRIM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
|
||||
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
|
||||
#define HIB_RTCSS_RTCSSM_S 16
|
||||
#define HIB_RTCSS_RTCSSC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_DATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
|
||||
#define HIB_DATA_RTD_S 0
|
||||
|
||||
#endif // __HW_HIBERNATE_H__
|
|
@ -0,0 +1,293 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_I2C_H__
|
||||
#define __HW_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
|
||||
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
|
||||
#define I2C_O_MDR 0x00000008 // I2C Master Data
|
||||
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
|
||||
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
|
||||
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
|
||||
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
|
||||
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
|
||||
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
|
||||
// Count
|
||||
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
|
||||
#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2
|
||||
#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
|
||||
#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
|
||||
#define I2C_O_SDR 0x00000808 // I2C Slave Data
|
||||
#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
|
||||
#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
|
||||
#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
|
||||
#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
|
||||
#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
|
||||
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
|
||||
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MSA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
|
||||
#define I2C_MSA_RS 0x00000001 // Receive not send
|
||||
#define I2C_MSA_SA_S 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
|
||||
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
|
||||
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
|
||||
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
|
||||
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
|
||||
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
|
||||
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
|
||||
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
|
||||
#define I2C_MCS_STOP 0x00000004 // Generate STOP
|
||||
#define I2C_MCS_ERROR 0x00000002 // Error
|
||||
#define I2C_MCS_START 0x00000002 // Generate START
|
||||
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
|
||||
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
|
||||
#define I2C_MDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MTPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
|
||||
#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
|
||||
#define I2C_MTPR_TPR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
|
||||
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
|
||||
// Status
|
||||
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
|
||||
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
|
||||
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
|
||||
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
|
||||
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
|
||||
#define I2C_MCLKOCNT_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBMON register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
|
||||
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
|
||||
#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
|
||||
#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
|
||||
#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
|
||||
#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
|
||||
#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
|
||||
#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
|
||||
#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
|
||||
#define I2C_MCR2_GFPW_32 0x00000070 // 32 clocks
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
|
||||
#define I2C_SOAR_OAR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SCSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
|
||||
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
|
||||
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
|
||||
#define I2C_SCSR_DA 0x00000001 // Device Active
|
||||
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
|
||||
#define I2C_SDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
|
||||
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
|
||||
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
|
||||
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
|
||||
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
|
||||
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
|
||||
#define I2C_SOAR2_OAR2_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
|
||||
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PP_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PC_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
#endif // __HW_I2C_H__
|
|
@ -0,0 +1,344 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
|
||||
// MCUs.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Blizzard Class Interrupts
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA_BLIZZARD 16 // GPIO Port A
|
||||
#define INT_GPIOB_BLIZZARD 17 // GPIO Port B
|
||||
#define INT_GPIOC_BLIZZARD 18 // GPIO Port C
|
||||
#define INT_GPIOD_BLIZZARD 19 // GPIO Port D
|
||||
#define INT_GPIOE_BLIZZARD 20 // GPIO Port E
|
||||
#define INT_UART0_BLIZZARD 21 // UART0
|
||||
#define INT_UART1_BLIZZARD 22 // UART1
|
||||
#define INT_SSI0_BLIZZARD 23 // SSI0
|
||||
#define INT_I2C0_BLIZZARD 24 // I2C0
|
||||
#define INT_PWM0_FAULT_BLIZZARD 25 // PWM0 Fault
|
||||
#define INT_PWM0_0_BLIZZARD 26 // PWM0 Generator 0
|
||||
#define INT_PWM0_1_BLIZZARD 27 // PWM0 Generator 1
|
||||
#define INT_PWM0_2_BLIZZARD 28 // PWM0 Generator 2
|
||||
#define INT_QEI0_BLIZZARD 29 // QEI0
|
||||
#define INT_ADC0SS0_BLIZZARD 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1_BLIZZARD 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2_BLIZZARD 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3_BLIZZARD 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG_BLIZZARD 34 // Watchdog Timers 0 and 1
|
||||
#define INT_TIMER0A_BLIZZARD 35 // 16/32-Bit Timer 0A
|
||||
#define INT_TIMER0B_BLIZZARD 36 // 16/32-Bit Timer 0B
|
||||
#define INT_TIMER1A_BLIZZARD 37 // 16/32-Bit Timer 1A
|
||||
#define INT_TIMER1B_BLIZZARD 38 // 16/32-Bit Timer 1B
|
||||
#define INT_TIMER2A_BLIZZARD 39 // 16/32-Bit Timer 2A
|
||||
#define INT_TIMER2B_BLIZZARD 40 // 16/32-Bit Timer 2B
|
||||
#define INT_COMP0_BLIZZARD 41 // Analog Comparator 0
|
||||
#define INT_COMP1_BLIZZARD 42 // Analog Comparator 1
|
||||
#define INT_COMP2_BLIZZARD 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL_BLIZZARD 44 // System Control
|
||||
#define INT_FLASH_BLIZZARD 45 // Flash Memory Control and EEPROM
|
||||
// Control
|
||||
#define INT_GPIOF_BLIZZARD 46 // GPIO Port F
|
||||
#define INT_GPIOG_BLIZZARD 47 // GPIO Port G
|
||||
#define INT_GPIOH_BLIZZARD 48 // GPIO Port H
|
||||
#define INT_UART2_BLIZZARD 49 // UART2
|
||||
#define INT_SSI1_BLIZZARD 50 // SSI1
|
||||
#define INT_TIMER3A_BLIZZARD 51 // Timer 3A
|
||||
#define INT_TIMER3B_BLIZZARD 52 // Timer 3B
|
||||
#define INT_I2C1_BLIZZARD 53 // I2C1
|
||||
#define INT_QEI1_BLIZZARD 54 // QEI1
|
||||
#define INT_CAN0_BLIZZARD 55 // CAN0
|
||||
#define INT_CAN1_BLIZZARD 56 // CAN1
|
||||
#define INT_HIBERNATE_BLIZZARD 59 // Hibernation Module
|
||||
#define INT_USB0_BLIZZARD 60 // USB
|
||||
#define INT_PWM0_3_BLIZZARD 61 // PWM Generator 3
|
||||
#define INT_UDMA_BLIZZARD 62 // uDMA Software
|
||||
#define INT_UDMAERR_BLIZZARD 63 // uDMA Error
|
||||
#define INT_ADC1SS0_BLIZZARD 64 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1_BLIZZARD 65 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2_BLIZZARD 66 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3_BLIZZARD 67 // ADC1 Sequence 3
|
||||
#define INT_GPIOJ_BLIZZARD 70 // GPIO Port J
|
||||
#define INT_GPIOK_BLIZZARD 71 // GPIO Port K
|
||||
#define INT_GPIOL_BLIZZARD 72 // GPIO Port L
|
||||
#define INT_SSI2_BLIZZARD 73 // SSI2
|
||||
#define INT_SSI3_BLIZZARD 74 // SSI3
|
||||
#define INT_UART3_BLIZZARD 75 // UART3
|
||||
#define INT_UART4_BLIZZARD 76 // UART4
|
||||
#define INT_UART5_BLIZZARD 77 // UART5
|
||||
#define INT_UART6_BLIZZARD 78 // UART6
|
||||
#define INT_UART7_BLIZZARD 79 // UART7
|
||||
#define INT_I2C2_BLIZZARD 84 // I2C2
|
||||
#define INT_I2C3_BLIZZARD 85 // I2C3
|
||||
#define INT_TIMER4A_BLIZZARD 86 // 16/32-Bit Timer 4A
|
||||
#define INT_TIMER4B_BLIZZARD 87 // 16/32-Bit Timer 4B
|
||||
#define INT_TIMER5A_BLIZZARD 108 // 16/32-Bit Timer 5A
|
||||
#define INT_TIMER5B_BLIZZARD 109 // 16/32-Bit Timer 5B
|
||||
#define INT_WTIMER0A_BLIZZARD 110 // 32/64-Bit Timer 0A
|
||||
#define INT_WTIMER0B_BLIZZARD 111 // 32/64-Bit Timer 0B
|
||||
#define INT_WTIMER1A_BLIZZARD 112 // 32/64-Bit Timer 1A
|
||||
#define INT_WTIMER1B_BLIZZARD 113 // 32/64-Bit Timer 1B
|
||||
#define INT_WTIMER2A_BLIZZARD 114 // 32/64-Bit Timer 2A
|
||||
#define INT_WTIMER2B_BLIZZARD 115 // 32/64-Bit Timer 2B
|
||||
#define INT_WTIMER3A_BLIZZARD 116 // 32/64-Bit Timer 3A
|
||||
#define INT_WTIMER3B_BLIZZARD 117 // 32/64-Bit Timer 3B
|
||||
#define INT_WTIMER4A_BLIZZARD 118 // 32/64-Bit Timer 4A
|
||||
#define INT_WTIMER4B_BLIZZARD 119 // 32/64-Bit Timer 4B
|
||||
#define INT_WTIMER5A_BLIZZARD 120 // 32/64-Bit Timer 5A
|
||||
#define INT_WTIMER5B_BLIZZARD 121 // 32/64-Bit Timer 5B
|
||||
#define INT_SYSEXC_BLIZZARD 122 // System Exception (imprecise)
|
||||
#define INT_PECI0_BLIZZARD 123 // PECI 0
|
||||
#define INT_LPC0_BLIZZARD 124 // LPC 0
|
||||
#define INT_I2C4_BLIZZARD 125 // I2C4
|
||||
#define INT_I2C5_BLIZZARD 126 // I2C5
|
||||
#define INT_GPIOM_BLIZZARD 127 // GPIO Port M
|
||||
#define INT_GPION_BLIZZARD 128 // GPIO Port N
|
||||
#define INT_FAN0_BLIZZARD 130 // FAN 0
|
||||
#define INT_GPIOP0_BLIZZARD 132 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1_BLIZZARD 133 // GPIO Port P1
|
||||
#define INT_GPIOP2_BLIZZARD 134 // GPIO Port P2
|
||||
#define INT_GPIOP3_BLIZZARD 135 // GPIO Port P3
|
||||
#define INT_GPIOP4_BLIZZARD 136 // GPIO Port P4
|
||||
#define INT_GPIOP5_BLIZZARD 137 // GPIO Port P5
|
||||
#define INT_GPIOP6_BLIZZARD 138 // GPIO Port P6
|
||||
#define INT_GPIOP7_BLIZZARD 139 // GPIO Port P7
|
||||
#define INT_GPIOQ0_BLIZZARD 140 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1_BLIZZARD 141 // GPIO Port Q1
|
||||
#define INT_GPIOQ2_BLIZZARD 142 // GPIO Port Q2
|
||||
#define INT_GPIOQ3_BLIZZARD 143 // GPIO Port Q3
|
||||
#define INT_GPIOQ4_BLIZZARD 144 // GPIO Port Q4
|
||||
#define INT_GPIOQ5_BLIZZARD 145 // GPIO Port Q5
|
||||
#define INT_GPIOQ6_BLIZZARD 146 // GPIO Port Q6
|
||||
#define INT_GPIOQ7_BLIZZARD 147 // GPIO Port Q7
|
||||
#define INT_PWM1_0_BLIZZARD 150 // PWM1 Generator 0
|
||||
#define INT_PWM1_1_BLIZZARD 151 // PWM1 Generator 1
|
||||
#define INT_PWM1_2_BLIZZARD 152 // PWM1 Generator 2
|
||||
#define INT_PWM1_3_BLIZZARD 153 // PWM1 Generator 3
|
||||
#define INT_PWM1_FAULT_BLIZZARD 154 // PWM1 Fault
|
||||
#define NUM_INTERRUPTS_BLIZZARD 155
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Blizzard Interrupt Class Definition
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(TARGET_IS_BLIZZARD_RA1) || defined(TARGET_IS_BLIZZARD_RA2) || \
|
||||
defined(TARGET_IS_BLIZZARD_RA3) || defined(TARGET_IS_BLIZZARD_RB0) || \
|
||||
defined(TARGET_IS_BLIZZARD_RB1) || defined(PART_TM4C1230C3PM) || \
|
||||
defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
|
||||
defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
|
||||
defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
|
||||
defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
|
||||
defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
|
||||
defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
|
||||
defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
|
||||
defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
|
||||
defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
|
||||
defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
|
||||
defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
|
||||
defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
|
||||
defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
|
||||
defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
|
||||
defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
|
||||
defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
|
||||
defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
|
||||
defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
|
||||
defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
|
||||
defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
|
||||
defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
|
||||
defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
|
||||
defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
|
||||
defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
|
||||
defined(PART_TM4C123GH6ZRB)
|
||||
#define INT_RESOLVE(intname, class) intname##BLIZZARD
|
||||
#else
|
||||
#define INT_DEVICE_CLASS "UNKNOWN"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
|
||||
#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
|
||||
#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
|
||||
#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
|
||||
#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
|
||||
#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
|
||||
#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
|
||||
#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
|
||||
#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
|
||||
#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
|
||||
#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
|
||||
#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
|
||||
#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
|
||||
#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
|
||||
#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
|
||||
#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
|
||||
#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
|
||||
#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
|
||||
#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
|
||||
#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
|
||||
#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
|
||||
#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
#endif // __HW_INTS_H__
|
|
@ -0,0 +1,49 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_lpc.h - Macros used when accessing the LPC hardware.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_LPC_H__
|
||||
#define __HW_LPC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the LPC register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#endif // __HW_LPC_H__
|
|
@ -0,0 +1,129 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of the device.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
|
||||
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI0_BASE 0x40008000 // SSI0
|
||||
#define SSI1_BASE 0x40009000 // SSI1
|
||||
#define SSI2_BASE 0x4000A000 // SSI2
|
||||
#define SSI3_BASE 0x4000B000 // SSI3
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define UART2_BASE 0x4000E000 // UART2
|
||||
#define UART3_BASE 0x4000F000 // UART3
|
||||
#define UART4_BASE 0x40010000 // UART4
|
||||
#define UART5_BASE 0x40011000 // UART5
|
||||
#define UART6_BASE 0x40012000 // UART6
|
||||
#define UART7_BASE 0x40013000 // UART7
|
||||
#define I2C0_BASE 0x40020000 // I2C0
|
||||
#define I2C1_BASE 0x40021000 // I2C1
|
||||
#define I2C2_BASE 0x40022000 // I2C2
|
||||
#define I2C3_BASE 0x40023000 // I2C3
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
|
||||
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
|
||||
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
|
||||
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
|
||||
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
|
||||
#define QEI0_BASE 0x4002C000 // QEI0
|
||||
#define QEI1_BASE 0x4002D000 // QEI1
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define TIMER3_BASE 0x40033000 // Timer3
|
||||
#define TIMER4_BASE 0x40034000 // Timer4
|
||||
#define TIMER5_BASE 0x40035000 // Timer5
|
||||
#define WTIMER0_BASE 0x40036000 // Wide Timer0
|
||||
#define WTIMER1_BASE 0x40037000 // Wide Timer1
|
||||
#define ADC0_BASE 0x40038000 // ADC0
|
||||
#define ADC1_BASE 0x40039000 // ADC1
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
|
||||
#define CAN0_BASE 0x40040000 // CAN0
|
||||
#define CAN1_BASE 0x40041000 // CAN1
|
||||
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
|
||||
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
|
||||
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
|
||||
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
|
||||
#define USB0_BASE 0x40050000 // USB 0 Controller
|
||||
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
|
||||
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
|
||||
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
|
||||
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
|
||||
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
|
||||
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
|
||||
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
|
||||
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
|
||||
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
|
||||
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
|
||||
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
|
||||
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
|
||||
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
|
||||
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
|
||||
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
|
||||
#define EEPROM_BASE 0x400AF000 // EEPROM memory
|
||||
#define I2C4_BASE 0x400C0000 // I2C4
|
||||
#define I2C5_BASE 0x400C1000 // I2C5
|
||||
#define SYSEXC_BASE 0x400F9000 // System Exception Module
|
||||
#define HIB_BASE 0x400FC000 // Hibernation Module
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define UDMA_BASE 0x400FF000 // uDMA Controller
|
||||
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
|
||||
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
|
||||
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
|
||||
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,49 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_peci.h - Macros used when accessing the PECI hardware.
|
||||
//
|
||||
// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_PECI_H__
|
||||
#define __HW_PECI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the PECI register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#endif // __HW_PECI_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,178 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_qei.h - Macros used when accessing the QEI hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_QEI_H__
|
||||
#define __HW_QEI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the QEI register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_O_CTL 0x00000000 // QEI Control
|
||||
#define QEI_O_STAT 0x00000004 // QEI Status
|
||||
#define QEI_O_POS 0x00000008 // QEI Position
|
||||
#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
|
||||
#define QEI_O_LOAD 0x00000010 // QEI Timer Load
|
||||
#define QEI_O_TIME 0x00000014 // QEI Timer
|
||||
#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
|
||||
#define QEI_O_SPEED 0x0000001C // QEI Velocity
|
||||
#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
|
||||
#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
|
||||
#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
|
||||
#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
|
||||
#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
|
||||
#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
|
||||
#define QEI_CTL_INVB 0x00000400 // Invert PhB
|
||||
#define QEI_CTL_INVA 0x00000200 // Invert PhA
|
||||
#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
|
||||
#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
|
||||
#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
|
||||
#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
|
||||
#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
|
||||
#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
|
||||
#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
|
||||
#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
|
||||
#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
|
||||
#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
|
||||
#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
|
||||
#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
|
||||
#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
|
||||
#define QEI_CTL_SWAP 0x00000002 // Swap Signals
|
||||
#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
|
||||
#define QEI_CTL_FILTCNT_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
|
||||
#define QEI_STAT_ERROR 0x00000001 // Error Detected
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_POS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
|
||||
// Value
|
||||
#define QEI_POS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_MAXPOS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
|
||||
// Value
|
||||
#define QEI_MAXPOS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_LOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
|
||||
#define QEI_LOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_TIME register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
|
||||
#define QEI_TIME_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_COUNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
|
||||
#define QEI_COUNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_SPEED register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_SPEED_M 0xFFFFFFFF // Velocity
|
||||
#define QEI_SPEED_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_INTEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
|
||||
#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
|
||||
// Enable
|
||||
#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
|
||||
#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
|
||||
// Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
|
||||
#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
|
||||
#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
|
||||
#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the QEI_O_ISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
|
||||
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
|
||||
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
|
||||
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
|
||||
|
||||
#endif // __HW_QEI_H__
|
|
@ -0,0 +1,197 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_ssi.h - Macros used when accessing the SSI hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SSI_H__
|
||||
#define __HW_SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the SSI register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_O_CR0 0x00000000 // SSI Control 0
|
||||
#define SSI_O_CR1 0x00000004 // SSI Control 1
|
||||
#define SSI_O_DR 0x00000008 // SSI Data
|
||||
#define SSI_O_SR 0x0000000C // SSI Status
|
||||
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
|
||||
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
|
||||
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
|
||||
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
|
||||
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
|
||||
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
|
||||
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
|
||||
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
|
||||
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
|
||||
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
|
||||
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
|
||||
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
|
||||
// Serial Frame Format
|
||||
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
|
||||
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
|
||||
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
|
||||
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
|
||||
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
|
||||
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
|
||||
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
|
||||
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
|
||||
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
|
||||
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
|
||||
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
|
||||
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
|
||||
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
|
||||
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
|
||||
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
|
||||
#define SSI_CR0_SCR_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR1_EOT 0x00000010 // End of Transmission
|
||||
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
|
||||
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
|
||||
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
|
||||
// Enable
|
||||
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
|
||||
#define SSI_DR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_SR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
|
||||
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
|
||||
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
|
||||
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
|
||||
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CPSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
|
||||
#define SSI_CPSR_CPSDVSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
|
||||
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
|
||||
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Mask
|
||||
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
|
||||
// Interrupt Status
|
||||
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Clear
|
||||
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
|
||||
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
|
||||
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
|
||||
// PLL bypass is in effect) or the
|
||||
// PLL output (default)
|
||||
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
|
||||
|
||||
#endif // __HW_SSI_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,132 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_sysexc.h - Macros used when accessing the system exception module.
|
||||
//
|
||||
// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SYSEXC_H__
|
||||
#define __HW_SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the System Exception Module register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
|
||||
// Status
|
||||
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
|
||||
#define SYSEXC_MIS 0x400F9008 // System Exception Masked
|
||||
// Interrupt Status
|
||||
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Clear
|
||||
|
||||
#endif // __HW_SYSEXC_H__
|
|
@ -0,0 +1,587 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_timer.h - Defines and macros used when accessing the timer.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TIMER_H__
|
||||
#define __HW_TIMER_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Timer register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
|
||||
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
|
||||
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
|
||||
#define TIMER_O_CTL 0x0000000C // GPTM Control
|
||||
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
|
||||
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
|
||||
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
|
||||
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
|
||||
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
|
||||
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
|
||||
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
|
||||
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
|
||||
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
|
||||
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
|
||||
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
|
||||
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
|
||||
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
|
||||
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
|
||||
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
|
||||
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
|
||||
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
|
||||
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
|
||||
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
|
||||
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
|
||||
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
|
||||
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
|
||||
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
|
||||
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
|
||||
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
|
||||
// counter configuration
|
||||
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
|
||||
// function is controlled by bits
|
||||
// 1:0 of GPTMTAMR and GPTMTBMR
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
|
||||
// Operation
|
||||
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
|
||||
// Update
|
||||
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
|
||||
// Enable
|
||||
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
|
||||
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
|
||||
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
|
||||
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
|
||||
// Enable
|
||||
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
|
||||
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
|
||||
// Select
|
||||
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
|
||||
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
|
||||
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
|
||||
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
|
||||
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
|
||||
// Operation
|
||||
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
|
||||
// Update
|
||||
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
|
||||
// Enable
|
||||
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
|
||||
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
|
||||
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
|
||||
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
|
||||
// Enable
|
||||
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
|
||||
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
|
||||
// Select
|
||||
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
|
||||
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
|
||||
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
|
||||
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
|
||||
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
|
||||
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
|
||||
// Enable
|
||||
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
|
||||
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
|
||||
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
|
||||
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
|
||||
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
|
||||
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
|
||||
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
|
||||
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
|
||||
// Enable
|
||||
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
|
||||
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
|
||||
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
|
||||
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
|
||||
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
|
||||
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
|
||||
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_SYNC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 5
|
||||
#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 5 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 5 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 5 is triggered
|
||||
#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 4
|
||||
#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 4 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 4 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 4 is triggered
|
||||
#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 3
|
||||
#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 3 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 3 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 3 is triggered
|
||||
#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 2
|
||||
#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 2 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 2 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 2 is triggered
|
||||
#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 1
|
||||
#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 1 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 1 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 1 is triggered
|
||||
#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
|
||||
// 0
|
||||
#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
|
||||
// GPTM 32/64-Bit Timer 0 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
|
||||
// GPTM 32/64-Bit Timer 0 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 32/64-Bit
|
||||
// Timer 0 is triggered
|
||||
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
|
||||
// 5
|
||||
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 5 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 5 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 5 is triggered
|
||||
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
|
||||
// 4
|
||||
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 4 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 4 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 4 is triggered
|
||||
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
|
||||
// 3
|
||||
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 3 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 3 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 3 is triggered
|
||||
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
|
||||
// 2
|
||||
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 2 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 2 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 2 is triggered
|
||||
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
|
||||
// 1
|
||||
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 1 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 1 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 1 is triggered
|
||||
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
|
||||
// 0
|
||||
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
|
||||
// affected
|
||||
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
|
||||
// GPTM 16/32-Bit Timer 0 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
|
||||
// GPTM 16/32-Bit Timer 0 is
|
||||
// triggered
|
||||
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
|
||||
// and Timer B of GPTM 16/32-Bit
|
||||
// Timer 0 is triggered
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_IMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
|
||||
// Interrupt Mask
|
||||
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
|
||||
// Mask
|
||||
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
|
||||
// Interrupt Mask
|
||||
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
|
||||
// Interrupt Mask
|
||||
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
|
||||
// Mask
|
||||
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
|
||||
// Mask
|
||||
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
|
||||
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
|
||||
// Interrupt Mask
|
||||
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
|
||||
// Interrupt Mask
|
||||
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
|
||||
// Interrupt
|
||||
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
|
||||
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
|
||||
// Raw Interrupt
|
||||
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
|
||||
// Raw Interrupt
|
||||
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
|
||||
// Interrupt
|
||||
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
|
||||
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
|
||||
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
|
||||
// Raw Interrupt
|
||||
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
|
||||
// Raw Interrupt
|
||||
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
|
||||
// Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
|
||||
// Interrupt
|
||||
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
|
||||
// Interrupt
|
||||
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
|
||||
// Masked Interrupt
|
||||
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
|
||||
// Masked Interrupt
|
||||
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
|
||||
// Interrupt
|
||||
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
|
||||
// Interrupt
|
||||
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
|
||||
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
|
||||
// Masked Interrupt
|
||||
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
|
||||
// Masked Interrupt
|
||||
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
|
||||
// Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
|
||||
// Error Interrupt Clear
|
||||
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
|
||||
// Clear
|
||||
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
|
||||
// Interrupt Clear
|
||||
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
|
||||
// Interrupt Clear
|
||||
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
|
||||
// Clear
|
||||
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
|
||||
// Clear
|
||||
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
|
||||
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
|
||||
// Interrupt Clear
|
||||
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
|
||||
// Interrupt Clear
|
||||
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
|
||||
// Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAILR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
|
||||
// Register
|
||||
#define TIMER_TAILR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBILR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
|
||||
// Register
|
||||
#define TIMER_TBILR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
|
||||
#define TIMER_TAMATCHR_TAMR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
|
||||
#define TIMER_TBMATCHR_TBMR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
|
||||
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
|
||||
#define TIMER_TAPR_TAPSRH_S 8
|
||||
#define TIMER_TAPR_TAPSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
|
||||
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
|
||||
#define TIMER_TBPR_TBPSRH_S 8
|
||||
#define TIMER_TBPR_TBPSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
|
||||
// Byte
|
||||
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
|
||||
#define TIMER_TAPMR_TAPSMRH_S 8
|
||||
#define TIMER_TAPMR_TAPSMR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
|
||||
// Byte
|
||||
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
|
||||
#define TIMER_TBPMR_TBPSMRH_S 8
|
||||
#define TIMER_TBPMR_TBPSMR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
|
||||
#define TIMER_TAR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
|
||||
#define TIMER_TBR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAV register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
|
||||
#define TIMER_TAV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBV register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
|
||||
#define TIMER_TBV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
|
||||
#define TIMER_RTCPD_RTCPD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAPS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
|
||||
#define TIMER_TAPS_PSS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBPS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
|
||||
#define TIMER_TBPS_PSS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TAPV register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
|
||||
#define TIMER_TAPV_PSV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_TBPV register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
|
||||
#define TIMER_TBPV_PSV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the TIMER_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
|
||||
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
|
||||
// 16 bits each with an 8-bit
|
||||
// prescale counter
|
||||
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
|
||||
// 32 bits each with a 16-bit
|
||||
// prescale counter
|
||||
|
||||
#endif // __HW_TIMER_H__
|
|
@ -0,0 +1,128 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_types.h - Common types and macros.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TYPES_H__
|
||||
#define __HW_TYPES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros for hardware access, both direct and via the bit-band region.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HWREG(x) \
|
||||
(*((volatile uint32_t *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile uint16_t *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile uint8_t *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Helper Macros for determining silicon revisions, etc.
|
||||
//
|
||||
// These macros will be used by Driverlib at "run-time" to create necessary
|
||||
// conditional code blocks that will allow a single version of the Driverlib
|
||||
// "binary" code to support multiple(all) Tiva silicon revisions.
|
||||
//
|
||||
// It is expected that these macros will be used inside of a standard 'C'
|
||||
// conditional block of code, e.g.
|
||||
//
|
||||
// if(CLASS_IS_BLIZZARD)
|
||||
// {
|
||||
// do some Blizzard-class specific code here.
|
||||
// }
|
||||
//
|
||||
// By default, these macros will be defined as run-time checks of the
|
||||
// appropriate register(s) to allow creation of run-time conditional code
|
||||
// blocks for a common DriverLib across the entire Tiva family.
|
||||
//
|
||||
// However, if code-space optimization is required, these macros can be "hard-
|
||||
// coded" for a specific version of Tiva silicon. Many compilers will then
|
||||
// detect the "hard-coded" conditionals, and appropriately optimize the code
|
||||
// blocks, eliminating any "unreachable" code. This would result in a smaller
|
||||
// Driverlib, thus producing a smaller final application size, but at the cost
|
||||
// of limiting the Driverlib binary to a specific Tiva silicon revision.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef CLASS_IS_BLIZZARD
|
||||
#define CLASS_IS_BLIZZARD \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A0
|
||||
#define REVISION_IS_A0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A1
|
||||
#define REVISION_IS_A1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A2
|
||||
#define REVISION_IS_A2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B0
|
||||
#define REVISION_IS_B0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B1
|
||||
#define REVISION_IS_B1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#endif // __HW_TYPES_H__
|
|
@ -0,0 +1,345 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_uart.h - Macros and defines used when accessing the UART hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_UART_H__
|
||||
#define __HW_UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the UART register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_O_DR 0x00000000 // UART Data
|
||||
#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
|
||||
#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
|
||||
#define UART_O_FR 0x00000018 // UART Flag
|
||||
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
|
||||
#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
|
||||
#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
|
||||
// Divisor
|
||||
#define UART_O_LCRH 0x0000002C // UART Line Control
|
||||
#define UART_O_CTL 0x00000030 // UART Control
|
||||
#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
|
||||
#define UART_O_IM 0x00000038 // UART Interrupt Mask
|
||||
#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
|
||||
#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
|
||||
#define UART_O_ICR 0x00000044 // UART Interrupt Clear
|
||||
#define UART_O_DMACTL 0x00000048 // UART DMA Control
|
||||
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
|
||||
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
|
||||
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
|
||||
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_DR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DR_OE 0x00000800 // UART Overrun Error
|
||||
#define UART_DR_BE 0x00000400 // UART Break Error
|
||||
#define UART_DR_PE 0x00000200 // UART Parity Error
|
||||
#define UART_DR_FE 0x00000100 // UART Framing Error
|
||||
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
|
||||
#define UART_DR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_RSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RSR_OE 0x00000008 // UART Overrun Error
|
||||
#define UART_RSR_BE 0x00000004 // UART Break Error
|
||||
#define UART_RSR_PE 0x00000002 // UART Parity Error
|
||||
#define UART_RSR_FE 0x00000001 // UART Framing Error
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ECR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ECR_DATA_M 0x000000FF // Error Clear
|
||||
#define UART_ECR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_FR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FR_RI 0x00000100 // Ring Indicator
|
||||
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
|
||||
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
|
||||
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
|
||||
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
|
||||
#define UART_FR_BUSY 0x00000008 // UART Busy
|
||||
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
|
||||
#define UART_FR_DSR 0x00000002 // Data Set Ready
|
||||
#define UART_FR_CTS 0x00000001 // Clear To Send
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ILPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
|
||||
#define UART_ILPR_ILPDVSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IBRD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
|
||||
#define UART_IBRD_DIVINT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_FBRD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
|
||||
#define UART_FBRD_DIVFRAC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_LCRH register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
|
||||
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
|
||||
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
|
||||
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
|
||||
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
|
||||
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
|
||||
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
|
||||
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
|
||||
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
|
||||
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
|
||||
#define UART_LCRH_BRK 0x00000001 // UART Send Break
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
|
||||
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
|
||||
#define UART_CTL_RTS 0x00000800 // Request to Send
|
||||
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
|
||||
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
|
||||
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
|
||||
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
|
||||
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
|
||||
#define UART_CTL_EOT 0x00000010 // End of Transmission
|
||||
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
|
||||
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
|
||||
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
|
||||
#define UART_CTL_UARTEN 0x00000001 // UART Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IFLS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
|
||||
// Level Select
|
||||
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
|
||||
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
|
||||
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
|
||||
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
|
||||
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
|
||||
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
|
||||
// Level Select
|
||||
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
|
||||
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
|
||||
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
|
||||
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
|
||||
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
|
||||
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
|
||||
// Mask
|
||||
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
|
||||
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
|
||||
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
|
||||
// Mask
|
||||
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
|
||||
// Mask
|
||||
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
|
||||
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
|
||||
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
|
||||
// Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
|
||||
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Raw Interrupt Status
|
||||
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Masked Interrupt Status
|
||||
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
|
||||
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
|
||||
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
|
||||
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
|
||||
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
|
||||
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
|
||||
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
|
||||
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
|
||||
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
|
||||
// Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
|
||||
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
|
||||
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_9BITADDR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
|
||||
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
|
||||
#define UART_9BITADDR_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_9BITAMASK
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
|
||||
#define UART_9BITAMASK_MASK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_PP_NB 0x00000002 // 9-Bit Support
|
||||
#define UART_PP_SC 0x00000001 // Smart Card Support
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
|
||||
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
|
||||
#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
|
||||
|
||||
#endif // __HW_UART_H__
|
|
@ -0,0 +1,412 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_udma.h - Macros for use in accessing the UDMA registers.
|
||||
//
|
||||
// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_UDMA_H__
|
||||
#define __HW_UDMA_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Micro Direct Memory Access register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_STAT 0x400FF000 // DMA Status
|
||||
#define UDMA_CFG 0x400FF004 // DMA Configuration
|
||||
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
|
||||
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
|
||||
// Base Pointer
|
||||
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
|
||||
// Status
|
||||
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
|
||||
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
|
||||
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
|
||||
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
|
||||
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
|
||||
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
|
||||
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
|
||||
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
|
||||
// Set
|
||||
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
|
||||
// Clear
|
||||
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
|
||||
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
|
||||
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
|
||||
#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
|
||||
#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
|
||||
#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
|
||||
#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
|
||||
#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
|
||||
#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
|
||||
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
|
||||
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
|
||||
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
|
||||
#define UDMA_STAT_STATE_RD_SRCENDP \
|
||||
0x00000020 // Reading source end pointer
|
||||
#define UDMA_STAT_STATE_RD_DSTENDP \
|
||||
0x00000030 // Reading destination end pointer
|
||||
#define UDMA_STAT_STATE_RD_SRCDAT \
|
||||
0x00000040 // Reading source data
|
||||
#define UDMA_STAT_STATE_WR_DSTDAT \
|
||||
0x00000050 // Writing destination data
|
||||
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
|
||||
// clear
|
||||
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
|
||||
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
|
||||
#define UDMA_STAT_STATE_DONE 0x00000090 // Done
|
||||
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
|
||||
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
|
||||
#define UDMA_STAT_DMACHANS_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CTLBASE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
|
||||
#define UDMA_CTLBASE_ADDR_S 10
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ALTBASE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
|
||||
// Pointer
|
||||
#define UDMA_ALTBASE_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_SWREQ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_USEBURSTSET
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_REQMASKSET
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_REQMASKCLR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ENASET register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ENACLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ALTSET register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ALTCLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_PRIOSET register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_ERRCLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHASGN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
|
||||
#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
|
||||
// assignment
|
||||
#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
|
||||
// assignment
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
|
||||
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
|
||||
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
|
||||
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
|
||||
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
|
||||
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
|
||||
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
|
||||
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
|
||||
#define UDMA_CHMAP0_CH7SEL_S 28
|
||||
#define UDMA_CHMAP0_CH6SEL_S 24
|
||||
#define UDMA_CHMAP0_CH5SEL_S 20
|
||||
#define UDMA_CHMAP0_CH4SEL_S 16
|
||||
#define UDMA_CHMAP0_CH3SEL_S 12
|
||||
#define UDMA_CHMAP0_CH2SEL_S 8
|
||||
#define UDMA_CHMAP0_CH1SEL_S 4
|
||||
#define UDMA_CHMAP0_CH0SEL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
|
||||
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
|
||||
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
|
||||
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
|
||||
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
|
||||
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
|
||||
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
|
||||
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
|
||||
#define UDMA_CHMAP1_CH15SEL_S 28
|
||||
#define UDMA_CHMAP1_CH14SEL_S 24
|
||||
#define UDMA_CHMAP1_CH13SEL_S 20
|
||||
#define UDMA_CHMAP1_CH12SEL_S 16
|
||||
#define UDMA_CHMAP1_CH11SEL_S 12
|
||||
#define UDMA_CHMAP1_CH10SEL_S 8
|
||||
#define UDMA_CHMAP1_CH9SEL_S 4
|
||||
#define UDMA_CHMAP1_CH8SEL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
|
||||
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
|
||||
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
|
||||
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
|
||||
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
|
||||
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
|
||||
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
|
||||
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
|
||||
#define UDMA_CHMAP2_CH23SEL_S 28
|
||||
#define UDMA_CHMAP2_CH22SEL_S 24
|
||||
#define UDMA_CHMAP2_CH21SEL_S 20
|
||||
#define UDMA_CHMAP2_CH20SEL_S 16
|
||||
#define UDMA_CHMAP2_CH19SEL_S 12
|
||||
#define UDMA_CHMAP2_CH18SEL_S 8
|
||||
#define UDMA_CHMAP2_CH17SEL_S 4
|
||||
#define UDMA_CHMAP2_CH16SEL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
|
||||
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
|
||||
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
|
||||
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
|
||||
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
|
||||
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
|
||||
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
|
||||
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
|
||||
#define UDMA_CHMAP3_CH31SEL_S 28
|
||||
#define UDMA_CHMAP3_CH30SEL_S 24
|
||||
#define UDMA_CHMAP3_CH29SEL_S 20
|
||||
#define UDMA_CHMAP3_CH28SEL_S 16
|
||||
#define UDMA_CHMAP3_CH27SEL_S 12
|
||||
#define UDMA_CHMAP3_CH26SEL_S 8
|
||||
#define UDMA_CHMAP3_CH25SEL_S 4
|
||||
#define UDMA_CHMAP3_CH24SEL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
|
||||
// Pointer
|
||||
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
|
||||
// End Pointer
|
||||
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
|
||||
#define UDMA_SRCENDP_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
|
||||
#define UDMA_DSTENDP_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
|
||||
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
|
||||
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
|
||||
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
|
||||
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
|
||||
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
|
||||
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
|
||||
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
|
||||
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
|
||||
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
|
||||
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
|
||||
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
|
||||
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
|
||||
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
|
||||
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
|
||||
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
|
||||
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
|
||||
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
|
||||
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
|
||||
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
|
||||
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
|
||||
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
|
||||
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
|
||||
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
|
||||
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
|
||||
#define UDMA_CHCTL_XFERMODE_STOP \
|
||||
0x00000000 // Stop
|
||||
#define UDMA_CHCTL_XFERMODE_BASIC \
|
||||
0x00000001 // Basic
|
||||
#define UDMA_CHCTL_XFERMODE_AUTO \
|
||||
0x00000002 // Auto-Request
|
||||
#define UDMA_CHCTL_XFERMODE_PINGPONG \
|
||||
0x00000003 // Ping-Pong
|
||||
#define UDMA_CHCTL_XFERMODE_MEM_SG \
|
||||
0x00000004 // Memory Scatter-Gather
|
||||
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
|
||||
0x00000005 // Alternate Memory Scatter-Gather
|
||||
#define UDMA_CHCTL_XFERMODE_PER_SG \
|
||||
0x00000006 // Peripheral Scatter-Gather
|
||||
#define UDMA_CHCTL_XFERMODE_PER_SGA \
|
||||
0x00000007 // Alternate Peripheral
|
||||
// Scatter-Gather
|
||||
#define UDMA_CHCTL_XFERSIZE_S 4
|
||||
|
||||
#endif // __HW_UDMA_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,122 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 1.1 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_WATCHDOG_H__
|
||||
#define __HW_WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Watchdog Timer register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_O_LOAD 0x00000000 // Watchdog Load
|
||||
#define WDT_O_VALUE 0x00000004 // Watchdog Value
|
||||
#define WDT_O_CTL 0x00000008 // Watchdog Control
|
||||
#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
|
||||
#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
|
||||
#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
|
||||
#define WDT_O_TEST 0x00000418 // Watchdog Test
|
||||
#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
|
||||
#define WDT_LOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_VALUE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
|
||||
#define WDT_VALUE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_CTL_WRC 0x80000000 // Write Complete
|
||||
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
|
||||
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
|
||||
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
|
||||
#define WDT_ICR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_TEST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
|
||||
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
|
||||
#define WDT_LOCK_LOCKED 0x00000001 // Locked
|
||||
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
|
||||
|
||||
#endif // __HW_WATCHDOG_H__
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,109 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Boot\main.c
|
||||
* \brief Bootloader application source file.
|
||||
* \ingroup Boot_ARMCM4_TM4C_DK_TM4C123G_IAR
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_memmap.h"
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_sysctl.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/sysctl.h"
|
||||
#include "driverlib/gpio.h"
|
||||
#if (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
#include "driverlib/uartlib.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader */
|
||||
BootInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* run the bootloader task */
|
||||
BootTask();
|
||||
}
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
/* set the clocking to run at 50MHz from the PLL */
|
||||
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||
/* enable and configure UART0 related peripherals and pins */
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
|
||||
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
|
||||
#endif
|
||||
#elif (BOOT_FILE_LOGGING_ENABLE > 0)
|
||||
/* log info strings to UART during firmware updates from local file storage */
|
||||
/* enable and configure UART0 related peripherals and pins */
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
|
||||
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
|
||||
/* enable the UART0 peripheral */
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
|
||||
/* configure the UART0 baudrate and communication parameters */
|
||||
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 57600,
|
||||
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
|
||||
UART_CONFIG_PAR_NONE));
|
||||
#endif
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
Binary file not shown.
|
@ -1,171 +1,308 @@
|
|||
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|
||||
S1132FB001D4206801E05FF0FF3010BD00C0004084
|
||||
S1132FC000D0004000E0004000F00040000001405C
|
||||
S1132FD0001001400020014000300140D0310000C9
|
||||
S1132FE0FEFCFFFF0E48006850F005000C49086025
|
||||
S1132FF070470B48006850F00200094908607047A8
|
||||
S113300010B50400002C02D0B4F1807F03D9E22172
|
||||
S11330100448FFF780FC601E0349086010BD0000EF
|
||||
S113302010E000E01431000014E000E080B500F08E
|
||||
S113303007F8002801D0012000E00020C0B202BD42
|
||||
S1133040EFF3108062B6704740420F0000201C006E
|
||||
S113305080841E0000802500999E360000403800C0
|
||||
S113306000093D0000803E0000004B00404B4C0036
|
||||
S113307000204E00808D5B0000C05D000080700069
|
||||
S113308000127A0000007D0080969800001BB700B3
|
||||
S11330900080BB00C0E8CE00647ADA000024F400AB
|
||||
S11330A00000FA0080A81201002D310100366E01E3
|
||||
S11330B040787D01433A5C576F726B5C736F667442
|
||||
S11330C0776172655C4F70656E424C545C546172FA
|
||||
S11330D06765745C44656D6F5C41524D434D345F6C
|
||||
S11330E0544D34435F444B5F544D34433132334782
|
||||
S11330F05F4941525C50726F675C6C69625C6472D8
|
||||
S1133100697665726C69625C73797363746C2E633F
|
||||
S113311000000000433A5C576F726B5C736F667417
|
||||
S1133120776172655C4F70656E424C545C54617299
|
||||
S11331306765745C44656D6F5C41524D434D345F0B
|
||||
S1133140544D34435F444B5F544D34433132334721
|
||||
S11331505F4941525C50726F675C6C69625C647277
|
||||
S1133160697665726C69625C7379737469636B2EDA
|
||||
S113317063000000433A5C576F726B5C736F667454
|
||||
S1133180776172655C4F70656E424C545C54617239
|
||||
S11331906765745C44656D6F5C41524D434D345FAB
|
||||
S11331A0544D34435F444B5F544D344331323347C1
|
||||
S11331B05F4941525C50726F675C6C69625C647217
|
||||
S11331C0697665726C69625C6770696F2E63000072
|
||||
S11331D0433A5C576F726B5C736F667477617265A8
|
||||
S11331E05C4F70656E424C545C5461726765745CEC
|
||||
S11331F044656D6F5C41524D434D345F544D3443CF
|
||||
S11332005F444B5F544D3443313233475F4941523D
|
||||
S11332105C50726F675C6C69625C6472697665723B
|
||||
S11332206C69625C756172742E63000010B50749A5
|
||||
S113323079441831064C7C44163404E00A68081DAD
|
||||
S1133240511888470146A142F8D110BD2C00000056
|
||||
S11332503800000050F8041B61B150F8042BD30768
|
||||
S113326044BFA9F101039A18002342F8043B091F43
|
||||
S1133270FAD1EFE770470000DDFFFFFF58000000C0
|
||||
S1133280000000200000000080B50448006850F4ED
|
||||
S113329070000249086000F005F801BD88ED00E007
|
||||
S11332A0FEE70000034B9D46C046C04600F004F80C
|
||||
S11332B000F010F8580400204EF68851CEF20001B8
|
||||
S11332C0086840F4700008604FF00070E1EE100AE6
|
||||
S11332D07047000000F009F8002801D0FFF7A6FFAE
|
||||
S11332E00020FFF701FB00F002F80120704700F016
|
||||
S11332F001B800000746384600F002F8FBE700007A
|
||||
S113330080B5C046C046024A11001820ABBEFBE798
|
||||
S1073310260002008D
|
||||
S90332A525
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
<Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1395</ColumnWidth1><ColumnWidth2>372</ColumnWidth2><ColumnWidth3>93</ColumnWidth3></Build><Find-All-Declarations><ColumnWidth0>142</ColumnWidth0><ColumnWidth1>20</ColumnWidth1><ColumnWidth2>243</ColumnWidth2></Find-All-Declarations><TerminalIO/><Debug-Log><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>371</ColumnWidth1></Debug-Log></Static>
|
||||
<Windows>
|
||||
|
||||
<Wnd2>
|
||||
<Wnd0>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-23736-13759</Identity>
|
||||
|
@ -29,20 +29,20 @@
|
|||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-11003-23003</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-13665-29690</Identity><TabName>Find All Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab><Tab><Identity>TabID-2562-1429</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
|
||||
<SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-11003-23003</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-13665-29690</Identity><TabName>Find All Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab><Tab><Identity>TabID-2562-1429</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>
|
||||
<Editor>
|
||||
|
||||
|
||||
|
||||
|
||||
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>759</SelStart2><SelEnd2>759</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\boot.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>94</YPos2><SelStart2>5540</SelStart2><SelEnd2>5540</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\vectors.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>41</YPos2><SelStart2>3165</SelStart2><SelEnd2>3165</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
|
||||
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>759</SelStart2><SelEnd2>759</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
|
||||
<Positions>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<Top><Row0><Sizes><Toolbar-014efc58><key>iaridepm.enu1</key></Toolbar-014efc58></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>579</Bottom><Right>418</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>218750</sizeVertCX><sizeVertCY>576389</sizeVertCY></Rect></Wnd2><Wnd3><Rect><Top>0</Top><Left>0</Left><Bottom>0</Bottom><Right>7</Right><x>-2</x><y>577</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>218750</sizeVertCX><sizeVertCY>382937</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes/></Row0></Bottom><Float><Sizes/></Float></Positions>
|
||||
<Top><Row0><Sizes><Toolbar-02a0fc58><key>iaridepm.enu1</key></Toolbar-02a0fc58></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>579</Bottom><Right>418</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>218750</sizeVertCX><sizeVertCY>576389</sizeVertCY></Rect></Wnd0><Wnd1><Rect><Top>0</Top><Left>0</Left><Bottom>50135048</Bottom><Right>53788952</Right><x>-2</x><y>577</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>218750</sizeVertCX><sizeVertCY>382937</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes/></Row0></Bottom><Float><Sizes/></Float></Positions>
|
||||
</Desktop>
|
||||
</Workspace>
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue