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Refs #288. Added XMC1400 Boot Kit Dave4/GCC demo programs. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@216 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2017-04-24 10:59:23 +00:00
parent 52c9a8d11b
commit ae71ecce13
180 changed files with 155178 additions and 1 deletions
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124
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Boot/.cproject Normal file
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Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Boot/.project Normal file
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14
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Boot/.settings/com.dave.mbs.xc800.prefs Normal file
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13
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163
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.1
* @date 30. January 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.1
* @date 25. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifndef CMSIS_NVIC_VIRTUAL
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#endif /* CMSIS_NVIC_VIRTUAL */
#ifndef CMSIS_VECTAB_VIRTUAL
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*********************************************************************************************************************
* @file XMC1000_RomFunctionTable.h
* @brief ROM functions prototypes for the XMC1400-Series
* @version V1.0
* @date 03 Sep 2015
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history *********************************
* V1.0, 03 Sep 2015, JFT : Initial version
*****************************************************************************
* @endcond
*/
#ifndef ROM_FUNCTION_TABLE_H
#define ROM_FUNCTION_TABLE_H
#ifdef __cplusplus
extern "C" {
#endif
/* ***************************************************************************
******************************* Constants *******************************
*************************************************************************** */
/* Start address of the ROM function table */
#define ROM_FUNCTION_TABLE_START (0x00000100U)
/* Pointer to Erase Flash Page routine */
#define _NvmErase (ROM_FUNCTION_TABLE_START + 0x00U)
/* Pointer to Erase, Program & Verify Flash Page routine */
#define _NvmProgVerify (ROM_FUNCTION_TABLE_START + 0x04U)
/* Pointer to Request BMI installation routine */
#define _BmiInstallationReq (ROM_FUNCTION_TABLE_START + 0x08U)
/* ***************************************************************************
******************************** Enumerations ********************************
*************************************************************************** */
typedef enum TagNVMStatus
{
/* The function succeeded */
NVM_PASS = (int32_t)0x00010000U,
/* Generic error code */
NVM_E_FAIL = (int32_t)0x80010001U,
/* Source data not in RAM */
NVM_E_SRC_AREA_EXCCEED = (int32_t)0x80010003U,
/* Source data is not 4 byte aligned */
NVM_E_SRC_ALIGNMENT = (int32_t)0x80010004U,
/* NVM module cannot be physically accessed */
NVM_E_NVM_FAIL = (int32_t)0x80010005U,
/* Verification of written page not successful */
NVM_E_VERIFY = (int32_t)0x80010006U,
/* Destination data is not (completely) located in NVM */
NVM_E_DST_AREA_EXCEED = (int32_t)0x80010009U,
/* Destination data is not properly aligned */
NVM_E_DST_ALIGNMENT = (int32_t)0x80010010U,
} NVM_STATUS;
/* ***************************************************************************
*********************************** Macros ***********************************
*************************************************************************** */
/* ***************************************************************************
Description: Erase granularity = 1 Page of 16 blocks of 16 Bytes
= Equivalent to 256 Bytes using this routine.
Input parameters:
– Logical address of the Flash Page to be erased which must be page aligned
and in NVM address range
Return status:
– OK (NVM_PASS)
– Invalid address (NVM_E_DST_ALIGNMENT or NVM_E_DST_AREA_EXCEED)
– Operation failed (Error during low level NVM programming driver):
NVM_E_FAIL
NVM_E_VERIFY
NVM_E_NVM_FAIL
Prototype:
NVM_STATUS XMC1000_NvmErasePage(uint32_t *pageAddr)
*************************************************************************** */
#define XMC1000_NvmErasePage (*((NVM_STATUS (**) (uint32_t * )) \
_NvmErase))
/* ***************************************************************************
Description: This procedure performs erase (skipped if not necessary), program
and verify of selected Flash page.
Input parameter:
– Logical address of the target Flash Page, must be page aligned and in NVM
address range
– Address in SRAM where the data starts, must be 4-byte aligned
Return status:
– OK (NVM_PASS)
– Invalid addresses
NVM_E_DST_ALIGNMENT
NVM_E_SRC_ALIGNMENT
NVM_E_DST_AREA_EXCEED
NVM_E_SRC_AREA_EXCCEED
– Operation failed (Error during low level NVM programming driver):
NVM_E_FAIL
NVM_E_VERIFY
NVM_E_NVM_FAIL
Prototype:
NVM_STATUS XMC1000_NvmProgVerify(const uint32_t *srcAddr, uint32_t *dstAddr)
*************************************************************************** */
#define XMC1000_NvmProgVerify (*((NVM_STATUS (**) (const uint32_t * ,\
uint32_t * ))\
_NvmProgVerify))
/* ***************************************************************************
Description: This procedure initiates installation of a new BMI value. In
particular, it can be used as well as to restore the state upon delivery for a
device already in User Productive mode.
Input parameter:
– BMI value to be installed
Return status:
– wrong input BMI value (0x01) - only upon error, if OK the procedure triggers
a reset respectively does not return to calling routine !
Prototype:
unsigned long XMC1000_BmiInstallationReq(unsigned short requestedBmiValue)
**************************************************************************** */
#define XMC1000_BmiInstallationReq (*((uint32_t (**) (uint16_t)) \
_BmiInstallationReq))
#ifdef __cplusplus
}
#endif
#endif /* ROM_FUNCTION_TABLE_H */

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/*********************************************************************************************************************
* @file system_XMC1400.h
* @brief Device specific initialization for the XMC1400-Series according to CMSIS
* @version V1.0
* @date 03 Sep 2015
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history *********************************
* V1.0, 03 Sep 2015, JFT : Initial version
*****************************************************************************
* @endcond
*/
#ifndef SYSTEM_XMC1400_H
#define SYSTEM_XMC1400_H
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
extern uint32_t SystemCoreClock;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the system
*
*/
void SystemInit(void);
/**
* @brief Initialize CPU settings
*
*/
void SystemCoreSetup(void);
/**
* @brief Initialize clock
*
*/
void SystemCoreClockSetup(void);
/**
* @brief Update SystemCoreClock variable
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Returns frequency of the high performace oscillator
* User needs to overload this function to return the correct oscillator frequency
*/
uint32_t OSCHP_GetFrequency(void);
#ifdef __cplusplus
}
#endif
#endif

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/*********************************************************************************************************************
* @file syscalls.c
* @brief Newlib stubs
* @version V1.6
* @date 20 Apr 2017
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* *************************** Change history ********************************
* V0.1 : Initial version
* V0.2 : Label updates
* V1.0 : Made _sbrk device agnostic
* V1.1 : C++ support
* V1.2 : Restored compatibility with old project files
* V1.3 Jan 2014, PKB : Encapsulating everything in this file for use only with GCC
* V1.4 11 Dec 2015, JFT : Fix heap overflow
* V1.5 09 Mar 2016, JFT : Add dso_handle to support destructors call at exit
* V1.6 20 Apr 2017, JFT : Foward declaration of __sbrk to fix link time optimization (-flto) compilation errors
* @endcond
*/
/*
* This file contains stubs for standard C library functionality that must
* typically be provided for the underlying platform.
*
*/
#if defined ( __GNUC__ )
#include <stdint.h>
#include <errno.h>
#include <sys/types.h>
/* Forward prototypes. */
caddr_t _sbrk(int nbytes) __attribute__((externally_visible));
void _init(void) __attribute__((externally_visible));
/* c++ destructor dynamic shared object needed if -fuse-cxa-atexit is used*/
void *__dso_handle __attribute__ ((weak));
// defined in linker script
extern caddr_t Heap_Bank1_Start;
extern caddr_t Heap_Bank1_End;
caddr_t _sbrk(int nbytes)
{
static caddr_t heap_ptr = NULL;
caddr_t base;
if (heap_ptr == NULL) {
heap_ptr = (caddr_t)&Heap_Bank1_Start;
}
base = heap_ptr;
/* heap word alignment */
nbytes = (nbytes + 3) & ~0x3U;
if ((caddr_t)&Heap_Bank1_End > (heap_ptr + nbytes))
{
heap_ptr += nbytes;
return (base);
}
else
{
/* Heap overflow */
errno = ENOMEM;
return ((caddr_t)-1);
}
}
/* Init */
void _init(void)
{}
#endif /* __GNUC__ */

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/**
* @file xmc1_flash.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial <br>
* 2015-02-20:
* - Updated for Documentation related changes<br>
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#ifndef XMC1_FLASH_H
#define XMC1_FLASH_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC1
#include <XMC1000_RomFunctionTable.h>
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup FLASH
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_FLASH_PAGES_PER_SECTOR (16U) /**< Number of pages in a sector. A page consists of 16 blocks.*/
#define XMC_FLASH_BLOCKS_PER_PAGE (16U) /**< Number of blocks in a page. A block consists of 4 words(16 bytes).*/
#define XMC_FLASH_BYTES_PER_SECTOR (4096U) /**< Number of bytes in a sector. (16 pages * 256 bytes = 4096 bytes)*/
#define XMC_FLASH_BYTES_PER_PAGE (256U) /**< Number of bytes in a page. (16 blocks * 16 bytes = 256 bytes)*/
#define XMC_FLASH_BYTES_PER_BLOCK (16U) /**< Number of bytes in a block. (128 bits = 16 bytes)*/
#define XMC_FLASH_WORDS_PER_SECTOR (1024U) /**< Number of words in a sector. (16 pages * 64 words = 1024 words)*/
#define XMC_FLASH_WORDS_PER_PAGE (64U) /**< Number of words in a page. (16 blocks * 4 words = 64 words) */
#define XMC_FLASH_WORDS_PER_BLOCK (4U) /**< Number of words in a block. (128 bit / 32 bit = 4 words) */
#define FLASH_BLOCK_ADDR_MASK (15U) /* Bitwise AND with block address is done to check the address alignment.
Applicable to XMC_FLASH_WriteBlocks() and XMC_FLASH_VerifyBlocks()
APIs.*/
#define FLASH_PAGE_ADDR_MASK (255U) /* Bitwise AND with page address is done to check the address alignment.
Applicable to XMC_FLASH_ErasePages() API.*/
#define FLASH_SECTOR_ADDR_MASK (4095U) /* Bitwise AND with sector address is done to check the address alignment.
Applicable to XMC_FLASH_EraseSector API.*/
#define XMC_FLASH_BASE (0x10001000U) /**< Starting address of flash for XMC1 family of microcontrollers*/
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines the status of flash, to verify the flash related API calls. Use type \a XMC_FLASH_STATUS_t for this enum.
* The members defines the respective masked status bits of \a NVMSTATUS register.
*/
typedef enum XMC_FLASH_STATUS
{
XMC_FLASH_STATUS_OK = 0U, /**< Flash related operation was successfully
completed*/
XMC_FLASH_STATUS_BUSY = NVM_NVMSTATUS_BUSY_Msk , /**< Cannot execute the flash request because
another operation is in progress*/
XMC_FLASH_STATUS_SLEEP_MODE = NVM_NVMSTATUS_SLEEP_Msk , /**< Flash is in sleep mode*/
XMC_FLASH_STATUS_VERIFY_ERROR = NVM_NVMSTATUS_VERR_Msk , /**< Flash reported a verification failure*/
XMC_FLASH_STATUS_ECC1_READ_ERROR = NVM_NVMSTATUS_ECC1READ_Msk, /**< Flash reports a single bit failure, and it
is automatically corrected.*/
XMC_FLASH_STATUS_ECC2_READ_ERROR = NVM_NVMSTATUS_ECC2READ_Msk, /**< Flash reported at least two bit failure*/
XMC_FLASH_STATUS_WRITE_PROTOCOL_ERROR = NVM_NVMSTATUS_WRPERR_Msk , /**< Write/Verify operation on a block is
failed due to protocol violations or write
protected sectors*/
} XMC_FLASH_STATUS_t;
/**
* Defines NVM ready interrupt event. Use type \a XMC_FLASH_EVENT_t for this enum.
*/
typedef enum XMC_FLASH_EVENT
{
XMC_FLASH_EVENT_READY = NVM_NVMCONF_INT_ON_Msk /**< Generates the NVM ready interrupts on flash sequence completion*/
} XMC_FLASH_EVENT_t;
/**
* Defines hard read levels for strict data verification. Use type \a XMC_FLASH_HARDREAD_LEVEL_t for this enum.
* These \a hardread levels provide some margin to ensure that the data is really programmed with suitably distinct
* levels for written and erased bits.
*/
typedef enum XMC_FLASH_HARDREAD_LEVEL
{
XMC_FLASH_HARDREAD_LEVEL_NORMAL = (uint16_t)0x0, /**< No \a hardread level verification enabled (Normal read)*/
XMC_FLASH_HARDREAD_LEVEL_WRITTEN = (uint16_t)0x1, /**< Enables strict margin compare for written data cells*/
XMC_FLASH_HARDREAD_LEVEL_ERASED = (uint16_t)0x2 /**< Enables strict margin compare for erased data cells*/
} XMC_FLASH_HARDREAD_LEVEL_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param address Pointer to the starting address of the flash page from where the erase starts
* @param num_pages Number of pages to be erased.<BR> Range: [1 to (flash size / 256)]
*
* @return None
*
* \par<b>Description:</b><BR>
* Erases a set of flash memory pages.<BR><BR>
* Erase starts from the specified \a address.
* It erases a maximum number of \a num_pages flash pages. The maximum erasable pages are limited to
* microcontroller flash size. It sets NVMPROG register to continuous page erase mode before erase and resets
* it action back to normal state on completion. Call XMC_FLASH_GetStatus() after calling this API to verify the erase
* operation.\n
*
* \par<b>Note:</b><BR>
* Flash will be in busy state during erase operation. Hence no operations on flash are allowed until it completes.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EraseSector(), XMC_FLASH_ErasePage() \n\n\n
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages);
/**
*
* @param address Pointer to the starting address of flash block from where the write starts.
* @param data Pointer to the source address where targeted data blocks are located.
* @param num_blocks Maximum number of flash block writes needed.<BR> Range: [1 to (flash size / 16)]
* @param verify If \a true, hardware verification after block write is enabled else disabled.
*
* @return None
*
* \par<b>Description:</b><br>
* Writes a set of data blocks into the flash.\n\n Minimum possible writable area is 16 byte block. It sets the NVMPROG
* register to continuous block write mode before write and resets it action back to normal state on completion.
* Call XMC_FLASH_GetStatus() API after calling this API to verify the erase operation.
*
* \par<b>Note</b><br>
* Flash will be busy state during write is ongoing, hence no operations allowed until it completes.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks, bool verify);
/**
*
* @param address Pointer to the starting address of flash block from where the verification starts.
* @param data Pointer to the source address where targeted data blocks are located.
* @param num_blocks Maximum number of flash blocks writes needed.<BR> Range: [1 to (flash size / 16)]
*
* @return None
*
* \par<b>Description:</b><br>
* Performs verification of written data blocks.\n\n After calling XMC_FLASH_WriteBlocks() API, calling this API will
* verify the correctness of written blocks. It sets the \a NVMPROG register into continuous block write mode before
* write and resets it action back to normal state on completion. It reads back the written data blocks from the flash
* and verify the values against the internal buffer values. Calling XMC_FLASH_GetStatus() API after calling this API
* validates the result of verification.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_VerifyBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks);
/**
*
* @param address Pointer to the starting address of flash block from where the read starts.
* @param data Pointer to the destination address, where the read data blocks to be stored.
* @param num_blocks Number of blocks to be read.<BR> Range: [1 to (flash size / 16)]
*
* @return None
*
* \par<b>Description:</b><br>
* Reads multiple blocks from flash in one shot, starting from the \a address specified.\n\n The read blocks are stored
* into the locations starting from the \a data address. Calling XMC_FLASH_GetStatus() API after calling this API
* verifies the read operation.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks);
/**
*
* @param address Pointer to the flash word address from where the read is expected
*
* @return <BR>
* a 32bit data word stored in the specified \a address.
*
* \par<b>Description:</b><br>
* Reads a single word from the specified flash\a address.\n\n Calling XMC_FLASH_GetStatus() API after calling this
* API returns the read status.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ReadBlocks()
*
*/
__STATIC_INLINE uint32_t XMC_FLASH_ReadWord(const uint32_t *const address)
{
return *address;
}
/**
*
* @param address Pointer to the starting address of the page to be erased
*
* @return None
*
* \par<b>Description:</b><br>
* Erases a single flash page associated to the specified \a address.\n\n XMC1000 Flash can be erased with granularity
* of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls the Flash Firmware routine
* \a XMC1000_NvmErasePage(unsigned long pageAddr) to perform the erase operation. Refer XMC1000 reference manual
* for more details on flash firmware routines (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API,
* to verify the erase operation.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ErasePages() \n\n\n
*/
void XMC_FLASH_ErasePage(uint32_t *address);
/**
*
* @param address Pointer to the starting address of flash page from where the programming starts.
* @param data Pointer to the source address where targeted data blocks are located.
*
* @return None
*
* \par<b>Description:</b><br>
* Erases, programs and verifies a single flash page starting from the \a address specified.\n\n XMC1000 Flash can be
* programmed with granularity of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls the
* Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr) to perform the programming. Refer XMC1000
* reference manual of for more details on flash firmware routines (Section 25.3). Call XMC_FLASH_GetStatus() API after
* calling this API, to verify the erase operation.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data);
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the flash to enter into sleep mode by resetting the NVMCONF register NVM_ON bit.\n\n Flash can wake up from
* sleep mode on any flash operation completion ready event trigger. To disable the sleep mode any time during execution
* call the API XMC_FLASH_ExitSleepMode().\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ExitSleepMode()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_EnterSleepMode(void)
{
NVM->NVMCONF &= (uint16_t)(~(uint32_t)NVM_NVMCONF_NVM_ON_Msk);
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the flash to exit from sleep mode by setting the NVMCONF register NVM_ON bit.\n\n Calling the API
* XMC_FLASH_EnterSleepMode() allows the flash to renter into sleep mode.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnterSleepMode()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_ExitSleepMode(void)
{
NVM->NVMCONF |= (uint16_t)NVM_NVMCONF_NVM_ON_Msk;
}
/**
*
* @param sector Flash sector number for which the address extraction is needed<BR> Range: [0 to 51]
*
* @return uint32_t Starting address of the sector specified<BR> Range: [0x10001000 to 0x10032000]
*
* \par<b>Description:</b><br>
* Finds the starting address of the specified \a sector number.\n\n
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
__STATIC_INLINE uint32_t XMC_FLASH_GetSectorAddress(uint32_t sector)
{
return (XMC_FLASH_BASE + (XMC_FLASH_BYTES_PER_SECTOR * sector));
}
/**
*
* @param num_sectors Number of sectors to be protected<BR> Range: [0 to 51]
*
* @return None
*
* \par<b>Description:</b><br>
* Protect the flash sectors starting from 0th sector to the specified \a num_sectors.\n\n It sets the NVMCONF register
* SECPROT field with the value specified in \a num_sectors. Changing the protection limit can be achieved by calling
* this API at runtime with a different value of \a num_sectors.\n\n
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
__STATIC_INLINE void XMC_FLASH_SetSectorProtection(uint32_t num_sectors)
{
NVM->NVMCONF &= (~(uint16_t)NVM_NVMCONF_SECPROT_Msk);
NVM->NVMCONF |= (uint16_t)((uint16_t)num_sectors << NVM_NVMCONF_SECPROT_Pos);
}
/**
*
* @param level Hard read levels specified in \a XMC_FLASH_HARDREAD_LEVEL_t.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets the hard read level for verification process.\n\n It insists the flash to do a strict margin compare
* with the written/erased data against the internal buffer. Sets the NVMCONF register HRLEV field with \a level
* value. This hardread level is used until the end of the verification sequence and, may not be changed in between.\n\n
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
__STATIC_INLINE void XMC_FLASH_SetHardReadLevel(XMC_FLASH_HARDREAD_LEVEL_t level)
{
NVM->NVMCONF &= (uint16_t)(~(uint16_t)NVM_NVMCONF_HRLEV_Msk);
NVM->NVMCONF |= (uint16_t)(level<< (uint16_t)NVM_NVMCONF_HRLEV_Pos);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif
#endif /* FLASH_H */

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/**
* @file xmc1_gpio.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft<br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#ifndef XMC1_GPIO_H
#define XMC1_GPIO_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC1
#include "xmc1_gpio_map.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup GPIO
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if defined(PORT0)
#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE)
#define XMC_GPIO_CHECK_PORT0(port) (port == XMC_GPIO_PORT0)
#else
#define XMC_GPIO_CHECK_PORT0(port) 0
#endif
#if defined(PORT1)
#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE)
#define XMC_GPIO_CHECK_PORT1(port) (port == XMC_GPIO_PORT1)
#else
#define XMC_GPIO_CHECK_PORT1(port) 0
#endif
#if defined(PORT2)
#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE)
#define XMC_GPIO_CHECK_PORT2(port) (port == XMC_GPIO_PORT2)
#else
#define XMC_GPIO_CHECK_PORT2(port) 0
#endif
#if defined(PORT3)
#define XMC_GPIO_PORT3 ((XMC_GPIO_PORT_t *) PORT3_BASE)
#define XMC_GPIO_CHECK_PORT3(port) (port == XMC_GPIO_PORT3)
#else
#define XMC_GPIO_CHECK_PORT3(port) 0
#endif
#if defined(PORT4)
#define XMC_GPIO_PORT4 ((XMC_GPIO_PORT_t *) PORT4_BASE)
#define XMC_GPIO_CHECK_PORT4(port) (port == XMC_GPIO_PORT4)
#else
#define XMC_GPIO_CHECK_PORT4(port) 0
#endif
#define XMC_GPIO_CHECK_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \
XMC_GPIO_CHECK_PORT1(port) || \
XMC_GPIO_CHECK_PORT2(port) || \
XMC_GPIO_CHECK_PORT3(port) || \
XMC_GPIO_CHECK_PORT4(port))
#define XMC_GPIO_CHECK_OUTPUT_PORT(port) XMC_GPIO_CHECK_PORT(port)
#define XMC_GPIO_CHECK_ANALOG_PORT(port) (port == XMC_GPIO_PORT2)
#define XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis) ((hysteresis == XMC_GPIO_INPUT_HYSTERESIS_STANDARD) || \
(hysteresis == XMC_GPIO_INPUT_HYSTERESIS_LARGE))
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operation
* with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery.
*/
typedef enum XMC_GPIO_MODE
{
XMC_GPIO_MODE_INPUT_TRISTATE = 0x0UL << PORT_IOCR_PC_Pos, /**< No internal pull device active */
XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x1UL << PORT_IOCR_PC_Pos, /**< Internal pull-down device active */
XMC_GPIO_MODE_INPUT_PULL_UP = 0x2UL << PORT_IOCR_PC_Pos, /**< Internal pull-up device active */
XMC_GPIO_MODE_INPUT_SAMPLING = 0x3UL << PORT_IOCR_PC_Pos, /**< No internal pull device active; Pn_OUTx continuously samples the input value */
XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x4UL << PORT_IOCR_PC_Pos, /**< Inverted no internal pull device active */
XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x5UL << PORT_IOCR_PC_Pos, /**< Inverted internal pull-down device active */
XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x6UL << PORT_IOCR_PC_Pos, /**< Inverted internal pull-up device active */
XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x7UL << PORT_IOCR_PC_Pos, /**< Inverted no internal pull device active;Pn_OUTx continuously samples the input value */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */
XMC_GPIO_MODE_OUTPUT_ALT1 = 0x1UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT2 = 0x2UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT3 = 0x3UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT4 = 0x4UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT5 = 0x5UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT6 = 0x6UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT7 = 0x7UL << PORT_IOCR_PC_Pos,
#if (UC_SERIES == XMC14)
XMC_GPIO_MODE_OUTPUT_ALT8 = 0x8UL << PORT_IOCR_PC_Pos,
XMC_GPIO_MODE_OUTPUT_ALT9 = 0x9UL << PORT_IOCR_PC_Pos,
#endif
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Push-pull alternate output function 4 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Push-pull alternate output function 5 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Push-pull alternate output function 6 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Push-pull alternate output function 7 */
#if (UC_SERIES == XMC14)
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Push-pull alternate output function 8 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT9, /**< Push-pull alternate output function 9 */
#endif
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Open drain alternate output function 1 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Open drain alternate output function 2 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Open drain alternate output function 3 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Open drain alternate output function 4 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Open drain alternate output function 5 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Open drain alternate output function 6 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Open drain alternate output function 7 */
#if (UC_SERIES == XMC14)
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Open drain alternate output function 8 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT9 /**< Open drain alternate output function 9 */
#endif
} XMC_GPIO_MODE_t;
/**
* Configures input hysteresis mode of pin. Use type \a XMC_GPIO_INPUT_HYSTERESIS_t for this enum.
* Selecting the appropriate pad hysteresis allows optimized pad oscillation behavior
* for touch-sensing applications.
*/
typedef enum XMC_GPIO_INPUT_HYSTERESIS
{
XMC_GPIO_INPUT_HYSTERESIS_STANDARD = 0x0U, /**< Standard hysteresis */
XMC_GPIO_INPUT_HYSTERESIS_LARGE = 0x4U /**< Large hysteresis */
} XMC_GPIO_INPUT_HYSTERESIS_t;
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure.
*/
typedef struct XMC_GPIO_PORT {
__IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is
selected by Pn_IOCRx as output */
__O uint32_t OMR; /**< The port output modification register contains control bits that make it
possible to individually set, reset, or toggle the logic state of a single port
line*/
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input
driver functionality and characteristics of a GPIO port pin */
__I uint32_t RESERVED1;
__I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register
Pn_IN */
__I uint32_t RESERVED2[6];
__IO uint32_t PHCR[2]; /**< Pad hysteresis control register */
__I uint32_t RESERVED3[6];
__IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital pad
structure in shared analog and digital ports*/
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /**< Pin Power Save Register */
__IO uint32_t HWSEL; /**< Pin Hardware Select Register */
} XMC_GPIO_PORT_t;
/**
* Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure.
*/
typedef struct XMC_GPIO_CONFIG
{
XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */
XMC_GPIO_INPUT_HYSTERESIS_t input_hysteresis; /**< Defines input pad hysteresis of a pin */
XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */
} XMC_GPIO_CONFIG_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
__STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode)
{
return ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) ||
(mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) ||
(mode == XMC_GPIO_MODE_INPUT_PULL_UP) ||
(mode == XMC_GPIO_MODE_INPUT_SAMPLING) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7) ||
#if (UC_SERIES == XMC14)
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9) ||
#endif
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7)
#if (UC_SERIES == XMC14)
|| (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9)
#endif
);
}
/**
* @brief Sets pad hysteresis.
* @param port Constant pointer pointing to GPIO port, to access hardware register Pn_PHCR.
* @param pin Port pin number.
* @param hysteresis input hysteresis selection. Refer data structure @ref XMC_GPIO_INPUT_HYSTERESIS_t
* for details.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets port pin input hysteresis. It configures hardware registers Pn_PHCR.\a hysteresis is initially configured during
* initialization in XMC_GPIO_Init(). Call this API to alter pad hysteresis as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode().
*
*/
void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port,
const uint8_t pin,
const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis);
/**
* @} (end addtogroup GPIO)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* UC_FAMILY == XMC1 */
#endif /* XMC1_GPIO_H */

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/**
* @file xmc1_rtc.h
* @date 2015-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial version
*
* 2015-05-20:
* - Documentation updates <br>
*
* @endcond
*
*/
#ifndef XMC1_RTC_H
#define XMC1_RTC_H
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup RTC
* @{
*/
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Debug mode status values
*/
typedef enum XMC_RTC_DEBUG_MODE
{
XMC_RTC_RUN_IN_DEBUG_MODE = 0U, /**< RTC is not stopped during halting mode debug */
XMC_RTC_STOP_IN_DEBUG_MODE = 1U /**< RTC is stopped during halting mode debug */
} XMC_RTC_DEBUG_MODE_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param debug_mode Debug mode value containing in (::XMC_RTC_DEBUG_MODE_t) to be set
* @return None
*
* \par<b>Description: </b><br>
* Configures the RTC into running or stopping mode during halting mode debug <br>
*
* \par
* The function sets the CTR.SUS bitfield to configure the RTC into running
* or stopping mode during halting mode debug.
*/
void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC1_RTC_H */

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/**
* @file xmc_acmp.h
* @date 2015-09-02
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial version
* 2015-02-20:
* - Removed unused declarations<br>
* 2015-05-08:
* - Fixed sequence problem of low power mode in XMC_ACMP_Init() API<br>
* - Fixed wrong register setting in XMC_ACMP_SetInput() API<br>
* - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
* Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.<br>
* 2015-06-04:
* - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
* - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below<br>
* (a)XMC_ACMP_EnableReferenceDivider <br>
* (b)XMC_ACMP_DisableReferenceDivider <br>
* (c)XMC_ACMP_SetInput <br>
* - Optimized enable and disable API's and moved to header file as static inline APIs.
* - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure.
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* 2015-06-26:
* - API help documentation modified.
* 2015-09-02:
* - API help documentation modified for XMC1400 device support.
* @endcond
*
*/
#ifndef XMC_ACMP_H
#define XMC_ACMP_H
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup ACMP
* @brief Analog Comparator(ACMP) low level driver for XMC1 family of microcontrollers. <br>
*
* The ACMP module consists of minimum of 3 analog comparators. Each analog comparator has two inputs, INP and INN.
* Input INP is compared with input INN in the pad voltage domain.
* It generates a digital comparator output signal. The digital comparator output signal is shifted down from VDDP
* power supply voltage level to VDDC core voltage level. The ACMP module provides the following functionalities.\n
* -# Monitor external voltage level
* -# Operates in low power mode
* -# Provides Inverted ouput option\n
* \par The ACMP low level driver funtionalities
* <OL>
* <LI>Initializes an instance of analog comparator module with the @ref XMC_ACMP_CONFIG_t configuration structure
* using the API XMC_ACMP_Init().</LI>
* <LI>Programs the source of input(INP) specified by @ref XMC_ACMP_INP_SOURCE_t parameter using the API
* XMC_ACMP_SetInput(). </LI>
* <LI>Sets the low power mode of operation using XMC_ACMP_SetLowPowerMode() API.</LI>
* </OL>
* @{
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_common.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/* If ACMP is available*/
#if defined (COMPARATOR)
#define XMC_ACMP0 (XMC_ACMP_t*)COMPARATOR /**< Comparator module base address defined*/
#if UC_SERIES == XMC14
#define XMC_ACMP_MAX_INSTANCES (4U) /* Maximum number of Analog Comparators available*/
#else
#define XMC_ACMP_MAX_INSTANCES (3U) /* Maximum number of Analog Comparators available*/
#endif
/* Checks if the pointer being passed is valid*/
#define XMC_ACMP_CHECK_MODULE_PTR(PTR) (((PTR)== (XMC_ACMP_t*)COMPARATOR))
/* Checks if the instance being addressed is valid*/
#define XMC_ACMP_CHECK_INSTANCE(INST) (((INST)< XMC_ACMP_MAX_INSTANCES))
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines the return value of an API.
*/
typedef enum XMC_ACMP_STATUS
{
XMC_ACMP_STATUS_SUCCESS = 0U, /**< API completes the execution successfully */
XMC_ACMP_STATUS_ERROR , /**< API cannot fulfill the request */
} XMC_ACMP_STATUS_t;
/**
* Defines the hysteresis voltage levels to reduce noise sensitivity.
*/
typedef enum XMC_ACMP_HYSTERESIS
{
XMC_ACMP_HYSTERESIS_OFF = 0U, /**< No hysteresis */
XMC_ACMP_HYSTERESIS_10 , /**< Hysteresis = 10mv */
XMC_ACMP_HYSTERESIS_15 , /**< Hysteresis = 15mv */
XMC_ACMP_HYSTERESIS_20 /**< Hysteresis = 20mv */
} XMC_ACMP_HYSTERESIS_t;
/**
* Defines the comparator output status options.
*/
typedef enum XMC_ACMP_COMP_OUT
{
XMC_ACMP_COMP_OUT_NO_INVERSION = 0U, /**< ACMP output is HIGH when, Input Positive(INP) greater than Input
Negative(INN). Vplus > Vminus */
XMC_ACMP_COMP_OUT_INVERSION /**< ACMP output is HIGH when, Input Negative(INN) greater than Input
Positive(INP). Vminus > Vplus*/
} XMC_ACMP_COMP_OUT_t;
/**
* Defines the analog comparator input connection method.
*/
typedef enum XMC_ACMP_INP_SOURCE
{
XMC_ACMP_INP_SOURCE_STANDARD_PORT = 0U, /**< Input is connected to port */
XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT = (uint16_t)(COMPARATOR_ANACMP0_ACMP0_SEL_Msk) /**< Input is connected to port
and ACMP1 INP */
} XMC_ACMP_INP_SOURCE_t;
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*Anonymous structure/union guard start*/
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* ACMP module
*/
typedef struct {
__IO uint32_t ORCCTRL;
__I uint32_t RESERVED[726];
__IO uint32_t ANACMP[XMC_ACMP_MAX_INSTANCES];
} XMC_ACMP_t;
/**
* Structure for initializing the ACMP module. It configures the ANACMP register of the respective input.
*/
typedef struct XMC_ACMP_CONFIG
{
union
{
struct
{
uint32_t : 1;
uint32_t filter_disable : 1; /**< Comparator filter option for removing glitches. By default this option
is selected in ANACMP register. Setting this option disables the filter */
uint32_t : 1;
uint32_t output_invert : 1; /**< Option to invert the comparator output. Use XMC_@ref XMC_ACMP_COMP_OUT_t type*/
uint32_t hysteresis : 2; /**< Hysteresis voltage to reduce noise sensitivity. Select the voltage levels
from the values defined in @ref XMC_ACMP_HYSTERESIS_t. */
uint32_t : 26;
};
uint32_t anacmp;
};
} XMC_ACMP_CONFIG_t;
/*Anonymous structure/union guard end*/
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*********************************************************************************************************************
* API Prototypes
********************************************************************************************************************/
/**
* @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
* @param instance ACMP instance number. <BR>
* Range:<BR> 0 - ACMP0<BR>
* 1 - ACMP1<BR>
* 2 - ACMP2<BR>
* 3 - ACMP3 - Only applicable for XMC1400 devices <BR>
*
* @param config Pointer to configuration data. Refer data structure @ref XMC_ACMP_CONFIG_t for settings.
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Initializes an instance of analog comparator module.<BR>\n
* Configures the ANACMP resister with hysteresis, comparator filter and inverted comparator output.
*
* \par<b>Related APIs:</b><br>
* None.
*/
void XMC_ACMP_Init(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_CONFIG_t *const config);
/**
* @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
* @param instance ACMP instance number. <BR>
* Range:<BR> 0 - ACMP0<BR>
* 1 - ACMP1<BR>
* 2 - ACMP2<BR>
* 3 - ACMP3 - Only applicable for XMC1400 devices <BR>
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Enables an instance of ACMP module.<BR>\n
* Starts the comparator by setting CMP_EN bit of respective ANACMP \a instance register. The \a instance number
* determines which analog comparator to be switched on. Call this API after the successful completion of the comparator
* initilization and input selection.
*
* \par<b>Related APIs:</b><br>
* XMC_ACMP_DisableComparator().<BR>
*/
__STATIC_INLINE void XMC_ACMP_EnableComparator(XMC_ACMP_t *const peripheral, uint32_t instance)
{
XMC_ASSERT("XMC_ACMP_EnableComparator:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
XMC_ASSERT("XMC_ACMP_EnableComparator:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
peripheral->ANACMP[instance] |= (uint16_t)COMPARATOR_ANACMP0_CMP_EN_Msk;
}
/**
* @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
* @param instance ACMP instance number. <BR>
* Range:<BR> 0 - ACMP0<BR>
* 1 - ACMP1<BR>
* 2 - ACMP2<BR>
* 3 - ACMP3 - Only applicable for XMC1400 devices <BR>
* @return
* None<BR>
* \par<b>Description:</b><br>
* Disables an instance of ACMP module.<BR>\n
* Stops the comparator by resetting CMP_EN bit of respective ANACMP \a instance register. The \a instance number
* determines which analog comparator to be switched off.
*
* \par<b>Related APIs:</b><br>
* XMC_ACMP_EnableComparator().
*/
__STATIC_INLINE void XMC_ACMP_DisableComparator(XMC_ACMP_t *const peripheral, uint32_t instance)
{
XMC_ASSERT("XMC_ACMP_DisableComparator:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
XMC_ASSERT("XMC_ACMP_DisableComparator:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
peripheral->ANACMP[instance] &= (uint16_t)(~((uint32_t)COMPARATOR_ANACMP0_CMP_EN_Msk));
}
/**
* @param None
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Enables the reference divider for analog comparator instance 1.<BR>\n
* ACMP1 input INP is driven by an internal reference voltage by setting DIV_EN bit of ANACMP1 register.
* Other comparator instances can also share this reference divider option by calling the XMC_ACMP_SetInput() API.
*
* \par<b>Related APIs:</b><br>
* XMC_ACMP_SetInput().
*/
__STATIC_INLINE void XMC_ACMP_EnableReferenceDivider(void)
{
/* Enable the divider switch and connect the divided reference to ACMP1.INP */
COMPARATOR->ANACMP1 |= (uint16_t)(COMPARATOR_ANACMP1_REF_DIV_EN_Msk);
}
/**
* @param None
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Disables the reference divider for analog comparator instance 1.<BR>\n
* ACMP1 input INP is disconnected from the reference divider. This is achieved by reseting DIV_EN bit of ANACMP1
* register.
*
* \par<b>Related APIs:</b><br>
* None.
*/
__STATIC_INLINE void XMC_ACMP_DisableReferenceDivider(void)
{
/* Disable the divider switch and use ACMP1.INP as standard port*/
COMPARATOR->ANACMP1 &= (uint16_t)(~(COMPARATOR_ANACMP1_REF_DIV_EN_Msk));
}
/**
* @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
* @param instance ACMP instance number. <BR>
* Range:<BR> 0 - ACMP0<BR>
* 2 - ACMP2<BR>
* 3 - ACMP3 - Only applicable for XMC1400 devices <BR>
* @param source ACMP input source selection options.<BR>
* Range:<BR> XMC_ACMP_INP_SOURCE_STANDARD_PORT - Input is connected to port<BR>
* XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT - Input is connected to port and ACMP1 INP <BR>
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Sets the analog comparartor input selection for ACMP0, ACMP2 instances.<BR>\n
* Apart from ACMP1 instance, each ACMP instances can be connected to its own port and ACMP1 INP.
* Calling @ref XMC_ACMP_EnableReferenceDivider() API, after this API can share the reference divider to one of the
* comparartor input as explained in the following options.<br>
* The hardware options to set input are listed below.<br>
* <OL>
* <LI>The comparator inputs aren't connected to other ACMP1 comparator inputs.</LI>
* <LI>Can program the comparator-0 to connect ACMP0.INP to ACMP1.INP in XMC1200 AA or XMC1300 AA</LI>
* <LI>Can program the comparator-0 to connect ACMP0.INN to ACMP1.INP in XMC1200 AB or XMC1300 AB or XMC1400 AA</LI>
* <LI>Can program the comparator-2 to connect ACMP2.INP to ACMP1.INP</LI>
* </OL><br>
* Directly accessed registers are ANACMP0, ANACMP2 according to the availability of instance in the devices.
*
* \par<b>Related APIs:</b><br>
* @ref XMC_ACMP_EnableReferenceDivider.<BR>
* @ref XMC_ACMP_DisableReferenceDivider.
*/
void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_INP_SOURCE_t source);
/**
* @param None
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Set the comparartors to operate in low power mode, by setting the LPWR bit of ANACMP0 register.<BR>\n
* The low power mode is controlled by ACMP0 instance. Low power mode is applicable for all instances of the
* comparator. In low power mode, blanking time will be introduced to ensure the stability of comparartor output. This
* will slow down the comparator operation.
*
* \par<b>Related APIs:</b><br>
* XMC_ACMP_ClearLowPowerMode().
*/
__STATIC_INLINE void XMC_ACMP_SetLowPowerMode(void)
{
COMPARATOR->ANACMP0 |= (uint16_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk;
}
/**
* @param None
* @return
* None<BR>
*
* \par<b>Description:</b><br>
* Exits the low power mode by reseting LPWR bit of ANACMP0 register.<BR>\n
* The low power mode is controlled by ACMP0 module. Low power mode is applicable for all instances of the
* comparator. To re-enable the low power mode, call the related API @ref XMC_ACMP_SetLowPowerMode().
*
* \par<b>Related APIs:</b><br>
* XMC_ACMP_SetLowPowerMode().
*/
__STATIC_INLINE void XMC_ACMP_ClearLowPowerMode(void)
{
COMPARATOR->ANACMP0 &= (uint16_t)(~(uint16_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk);
}
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* If ACMP is available*/
#endif /* XMC_ACMP_H */

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/**
* @file xmc_can_map.h
* @date 2015-10-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-10-20:
* - Removed "const" in the MOs for avoiding compiler warnings
*
* 2015-09-15:
* - Initial version
*
* @endcond
*
*/
#ifndef XMC_CAN_MAP_H
#define XMC_CAN_MAP_H
/*******************************************************************************
* MACROS
*******************************************************************************/
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LFBGA196)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE3_RXD_P7_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P7_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P8_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#endif
#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC43)|| (UC_SERIES == XMC14)
#define CAN_MO0 ((CAN_MO_TypeDef *)&(CAN_MO->MO[0]))
#define CAN_MO1 ((CAN_MO_TypeDef *)&(CAN_MO->MO[1]))
#define CAN_MO2 ((CAN_MO_TypeDef *)&(CAN_MO->MO[2]))
#define CAN_MO3 ((CAN_MO_TypeDef *)&(CAN_MO->MO[3]))
#define CAN_MO4 ((CAN_MO_TypeDef *)&(CAN_MO->MO[4]))
#define CAN_MO5 ((CAN_MO_TypeDef *)&(CAN_MO->MO[5]))
#define CAN_MO6 ((CAN_MO_TypeDef *)&(CAN_MO->MO[6]))
#define CAN_MO7 ((CAN_MO_TypeDef *)&(CAN_MO->MO[7]))
#define CAN_MO8 ((CAN_MO_TypeDef *)&(CAN_MO->MO[8]))
#define CAN_MO9 ((CAN_MO_TypeDef *)&(CAN_MO->MO[9]))
#define CAN_MO10 ((CAN_MO_TypeDef *)&(CAN_MO->MO[10]))
#define CAN_MO11 ((CAN_MO_TypeDef *)&(CAN_MO->MO[11]))
#define CAN_MO12 ((CAN_MO_TypeDef *)&(CAN_MO->MO[12]))
#define CAN_MO13 ((CAN_MO_TypeDef *)&(CAN_MO->MO[13]))
#define CAN_MO14 ((CAN_MO_TypeDef *)&(CAN_MO->MO[14]))
#define CAN_MO15 ((CAN_MO_TypeDef *)&(CAN_MO->MO[15]))
#define CAN_MO16 ((CAN_MO_TypeDef *)&(CAN_MO->MO[16]))
#define CAN_MO17 ((CAN_MO_TypeDef *)&(CAN_MO->MO[17]))
#define CAN_MO18 ((CAN_MO_TypeDef *)&(CAN_MO->MO[18]))
#define CAN_MO19 ((CAN_MO_TypeDef *)&(CAN_MO->MO[19]))
#define CAN_MO20 ((CAN_MO_TypeDef *)&(CAN_MO->MO[20]))
#define CAN_MO21 ((CAN_MO_TypeDef *)&(CAN_MO->MO[21]))
#define CAN_MO22 ((CAN_MO_TypeDef *)&(CAN_MO->MO[22]))
#define CAN_MO23 ((CAN_MO_TypeDef *)&(CAN_MO->MO[23]))
#define CAN_MO24 ((CAN_MO_TypeDef *)&(CAN_MO->MO[24]))
#define CAN_MO25 ((CAN_MO_TypeDef *)&(CAN_MO->MO[25]))
#define CAN_MO26 ((CAN_MO_TypeDef *)&(CAN_MO->MO[26]))
#define CAN_MO27 ((CAN_MO_TypeDef *)&(CAN_MO->MO[27]))
#define CAN_MO28 ((CAN_MO_TypeDef *)&(CAN_MO->MO[28]))
#define CAN_MO29 ((CAN_MO_TypeDef *)&(CAN_MO->MO[29]))
#define CAN_MO30 ((CAN_MO_TypeDef *)&(CAN_MO->MO[30]))
#define CAN_MO31 ((CAN_MO_TypeDef *)&(CAN_MO->MO[31]))
#endif
#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)|| (UC_SERIES == XMC43)
#define CAN_MO32 ((CAN_MO_TypeDef *)&(CAN_MO->MO[32]))
#define CAN_MO33 ((CAN_MO_TypeDef *)&(CAN_MO->MO[33]))
#define CAN_MO34 ((CAN_MO_TypeDef *)&(CAN_MO->MO[34]))
#define CAN_MO35 ((CAN_MO_TypeDef *)&(CAN_MO->MO[35]))
#define CAN_MO36 ((CAN_MO_TypeDef *)&(CAN_MO->MO[36]))
#define CAN_MO37 ((CAN_MO_TypeDef *)&(CAN_MO->MO[37]))
#define CAN_MO38 ((CAN_MO_TypeDef *)&(CAN_MO->MO[38]))
#define CAN_MO39 ((CAN_MO_TypeDef *)&(CAN_MO->MO[39]))
#define CAN_MO40 ((CAN_MO_TypeDef *)&(CAN_MO->MO[40]))
#define CAN_MO41 ((CAN_MO_TypeDef *)&(CAN_MO->MO[41]))
#define CAN_MO42 ((CAN_MO_TypeDef *)&(CAN_MO->MO[42]))
#define CAN_MO43 ((CAN_MO_TypeDef *)&(CAN_MO->MO[43]))
#define CAN_MO44 ((CAN_MO_TypeDef *)&(CAN_MO->MO[44]))
#define CAN_MO45 ((CAN_MO_TypeDef *)&(CAN_MO->MO[45]))
#define CAN_MO46 ((CAN_MO_TypeDef *)&(CAN_MO->MO[46]))
#define CAN_MO47 ((CAN_MO_TypeDef *)&(CAN_MO->MO[47]))
#define CAN_MO48 ((CAN_MO_TypeDef *)&(CAN_MO->MO[48]))
#define CAN_MO49 ((CAN_MO_TypeDef *)&(CAN_MO->MO[49]))
#define CAN_MO50 ((CAN_MO_TypeDef *)&(CAN_MO->MO[50]))
#define CAN_MO51 ((CAN_MO_TypeDef *)&(CAN_MO->MO[51]))
#define CAN_MO52 ((CAN_MO_TypeDef *)&(CAN_MO->MO[52]))
#define CAN_MO53 ((CAN_MO_TypeDef *)&(CAN_MO->MO[53]))
#define CAN_MO54 ((CAN_MO_TypeDef *)&(CAN_MO->MO[54]))
#define CAN_MO55 ((CAN_MO_TypeDef *)&(CAN_MO->MO[55]))
#define CAN_MO56 ((CAN_MO_TypeDef *)&(CAN_MO->MO[56]))
#define CAN_MO57 ((CAN_MO_TypeDef *)&(CAN_MO->MO[57]))
#define CAN_MO58 ((CAN_MO_TypeDef *)&(CAN_MO->MO[58]))
#define CAN_MO59 ((CAN_MO_TypeDef *)&(CAN_MO->MO[59]))
#define CAN_MO60 ((CAN_MO_TypeDef *)&(CAN_MO->MO[60]))
#define CAN_MO61 ((CAN_MO_TypeDef *)&(CAN_MO->MO[61]))
#define CAN_MO62 ((CAN_MO_TypeDef *)&(CAN_MO->MO[62]))
#define CAN_MO63 ((CAN_MO_TypeDef *)&(CAN_MO->MO[63]))
#if (UC_SERIES != XMC43)
#define CAN_MO64 ((CAN_MO_TypeDef *)&(CAN_MO->MO[64]))
#define CAN_MO65 ((CAN_MO_TypeDef *)&(CAN_MO->MO[65]))
#define CAN_MO66 ((CAN_MO_TypeDef *)&(CAN_MO->MO[66]))
#define CAN_MO67 ((CAN_MO_TypeDef *)&(CAN_MO->MO[67]))
#define CAN_MO68 ((CAN_MO_TypeDef *)&(CAN_MO->MO[68]))
#define CAN_MO69 ((CAN_MO_TypeDef *)&(CAN_MO->MO[69]))
#define CAN_MO70 ((CAN_MO_TypeDef *)&(CAN_MO->MO[70]))
#define CAN_MO71 ((CAN_MO_TypeDef *)&(CAN_MO->MO[71]))
#define CAN_MO72 ((CAN_MO_TypeDef *)&(CAN_MO->MO[72]))
#define CAN_MO73 ((CAN_MO_TypeDef *)&(CAN_MO->MO[73]))
#define CAN_MO74 ((CAN_MO_TypeDef *)&(CAN_MO->MO[74]))
#define CAN_MO75 ((CAN_MO_TypeDef *)&(CAN_MO->MO[75]))
#define CAN_MO76 ((CAN_MO_TypeDef *)&(CAN_MO->MO[76]))
#define CAN_MO77 ((CAN_MO_TypeDef *)&(CAN_MO->MO[77]))
#define CAN_MO78 ((CAN_MO_TypeDef *)&(CAN_MO->MO[78]))
#define CAN_MO79 ((CAN_MO_TypeDef *)&(CAN_MO->MO[79]))
#define CAN_MO80 ((CAN_MO_TypeDef *)&(CAN_MO->MO[80]))
#define CAN_MO81 ((CAN_MO_TypeDef *)&(CAN_MO->MO[81]))
#define CAN_MO82 ((CAN_MO_TypeDef *)&(CAN_MO->MO[82]))
#define CAN_MO83 ((CAN_MO_TypeDef *)&(CAN_MO->MO[83]))
#define CAN_MO84 ((CAN_MO_TypeDef *)&(CAN_MO->MO[84]))
#define CAN_MO85 ((CAN_MO_TypeDef *)&(CAN_MO->MO[85]))
#define CAN_MO86 ((CAN_MO_TypeDef *)&(CAN_MO->MO[86]))
#define CAN_MO87 ((CAN_MO_TypeDef *)&(CAN_MO->MO[87]))
#define CAN_MO88 ((CAN_MO_TypeDef *)&(CAN_MO->MO[88]))
#define CAN_MO89 ((CAN_MO_TypeDef *)&(CAN_MO->MO[89]))
#define CAN_MO90 ((CAN_MO_TypeDef *)&(CAN_MO->MO[90]))
#define CAN_MO91 ((CAN_MO_TypeDef *)&(CAN_MO->MO[91]))
#define CAN_MO92 ((CAN_MO_TypeDef *)&(CAN_MO->MO[92]))
#define CAN_MO93 ((CAN_MO_TypeDef *)&(CAN_MO->MO[93]))
#define CAN_MO94 ((CAN_MO_TypeDef *)&(CAN_MO->MO[94]))
#define CAN_MO95 ((CAN_MO_TypeDef *)&(CAN_MO->MO[95]))
#define CAN_MO96 ((CAN_MO_TypeDef *)&(CAN_MO->MO[96]))
#define CAN_MO97 ((CAN_MO_TypeDef *)&(CAN_MO->MO[97]))
#define CAN_MO98 ((CAN_MO_TypeDef *)&(CAN_MO->MO[98]))
#define CAN_MO99 ((CAN_MO_TypeDef *)&(CAN_MO->MO[99]))
#define CAN_MO100 ((CAN_MO_TypeDef *)&(CAN_MO->MO[100]))
#define CAN_MO101 ((CAN_MO_TypeDef *)&(CAN_MO->MO[101]))
#define CAN_MO102 ((CAN_MO_TypeDef *)&(CAN_MO->MO[102]))
#define CAN_MO103 ((CAN_MO_TypeDef *)&(CAN_MO->MO[103]))
#define CAN_MO104 ((CAN_MO_TypeDef *)&(CAN_MO->MO[104]))
#define CAN_MO105 ((CAN_MO_TypeDef *)&(CAN_MO->MO[105]))
#define CAN_MO106 ((CAN_MO_TypeDef *)&(CAN_MO->MO[106]))
#define CAN_MO107 ((CAN_MO_TypeDef *)&(CAN_MO->MO[107]))
#define CAN_MO108 ((CAN_MO_TypeDef *)&(CAN_MO->MO[108]))
#define CAN_MO109 ((CAN_MO_TypeDef *)&(CAN_MO->MO[109]))
#define CAN_MO110 ((CAN_MO_TypeDef *)&(CAN_MO->MO[110]))
#define CAN_MO111 ((CAN_MO_TypeDef *)&(CAN_MO->MO[111]))
#define CAN_MO112 ((CAN_MO_TypeDef *)&(CAN_MO->MO[112]))
#define CAN_MO113 ((CAN_MO_TypeDef *)&(CAN_MO->MO[113]))
#define CAN_MO114 ((CAN_MO_TypeDef *)&(CAN_MO->MO[114]))
#define CAN_MO115 ((CAN_MO_TypeDef *)&(CAN_MO->MO[115]))
#define CAN_MO116 ((CAN_MO_TypeDef *)&(CAN_MO->MO[116]))
#define CAN_MO117 ((CAN_MO_TypeDef *)&(CAN_MO->MO[117]))
#define CAN_MO118 ((CAN_MO_TypeDef *)&(CAN_MO->MO[118]))
#define CAN_MO119 ((CAN_MO_TypeDef *)&(CAN_MO->MO[119]))
#define CAN_MO120 ((CAN_MO_TypeDef *)&(CAN_MO->MO[120]))
#define CAN_MO121 ((CAN_MO_TypeDef *)&(CAN_MO->MO[121]))
#define CAN_MO122 ((CAN_MO_TypeDef *)&(CAN_MO->MO[122]))
#define CAN_MO123 ((CAN_MO_TypeDef *)&(CAN_MO->MO[123]))
#define CAN_MO124 ((CAN_MO_TypeDef *)&(CAN_MO->MO[124]))
#define CAN_MO125 ((CAN_MO_TypeDef *)&(CAN_MO->MO[125]))
#define CAN_MO126 ((CAN_MO_TypeDef *)&(CAN_MO->MO[126]))
#define CAN_MO127 ((CAN_MO_TypeDef *)&(CAN_MO->MO[127]))
#define CAN_MO128 ((CAN_MO_TypeDef *)&(CAN_MO->MO[128]))
#define CAN_MO129 ((CAN_MO_TypeDef *)&(CAN_MO->MO[129]))
#define CAN_MO130 ((CAN_MO_TypeDef *)&(CAN_MO->MO[130]))
#define CAN_MO131 ((CAN_MO_TypeDef *)&(CAN_MO->MO[131]))
#define CAN_MO132 ((CAN_MO_TypeDef *)&(CAN_MO->MO[132]))
#define CAN_MO133 ((CAN_MO_TypeDef *)&(CAN_MO->MO[133]))
#define CAN_MO134 ((CAN_MO_TypeDef *)&(CAN_MO->MO[134]))
#define CAN_MO135 ((CAN_MO_TypeDef *)&(CAN_MO->MO[135]))
#define CAN_MO136 ((CAN_MO_TypeDef *)&(CAN_MO->MO[136]))
#define CAN_MO137 ((CAN_MO_TypeDef *)&(CAN_MO->MO[137]))
#define CAN_MO138 ((CAN_MO_TypeDef *)&(CAN_MO->MO[138]))
#define CAN_MO139 ((CAN_MO_TypeDef *)&(CAN_MO->MO[139]))
#define CAN_MO140 ((CAN_MO_TypeDef *)&(CAN_MO->MO[140]))
#define CAN_MO141 ((CAN_MO_TypeDef *)&(CAN_MO->MO[141]))
#define CAN_MO142 ((CAN_MO_TypeDef *)&(CAN_MO->MO[142]))
#define CAN_MO143 ((CAN_MO_TypeDef *)&(CAN_MO->MO[143]))
#define CAN_MO144 ((CAN_MO_TypeDef *)&(CAN_MO->MO[144]))
#define CAN_MO145 ((CAN_MO_TypeDef *)&(CAN_MO->MO[145]))
#define CAN_MO146 ((CAN_MO_TypeDef *)&(CAN_MO->MO[146]))
#define CAN_MO147 ((CAN_MO_TypeDef *)&(CAN_MO->MO[147]))
#define CAN_MO148 ((CAN_MO_TypeDef *)&(CAN_MO->MO[148]))
#define CAN_MO149 ((CAN_MO_TypeDef *)&(CAN_MO->MO[149]))
#define CAN_MO150 ((CAN_MO_TypeDef *)&(CAN_MO->MO[150]))
#define CAN_MO151 ((CAN_MO_TypeDef *)&(CAN_MO->MO[151]))
#define CAN_MO152 ((CAN_MO_TypeDef *)&(CAN_MO->MO[152]))
#define CAN_MO153 ((CAN_MO_TypeDef *)&(CAN_MO->MO[153]))
#define CAN_MO154 ((CAN_MO_TypeDef *)&(CAN_MO->MO[154]))
#define CAN_MO155 ((CAN_MO_TypeDef *)&(CAN_MO->MO[155]))
#define CAN_MO156 ((CAN_MO_TypeDef *)&(CAN_MO->MO[156]))
#define CAN_MO157 ((CAN_MO_TypeDef *)&(CAN_MO->MO[157]))
#define CAN_MO158 ((CAN_MO_TypeDef *)&(CAN_MO->MO[158]))
#define CAN_MO159 ((CAN_MO_TypeDef *)&(CAN_MO->MO[159]))
#define CAN_MO160 ((CAN_MO_TypeDef *)&(CAN_MO->MO[160]))
#define CAN_MO161 ((CAN_MO_TypeDef *)&(CAN_MO->MO[161]))
#define CAN_MO162 ((CAN_MO_TypeDef *)&(CAN_MO->MO[162]))
#define CAN_MO163 ((CAN_MO_TypeDef *)&(CAN_MO->MO[163]))
#define CAN_MO164 ((CAN_MO_TypeDef *)&(CAN_MO->MO[164]))
#define CAN_MO165 ((CAN_MO_TypeDef *)&(CAN_MO->MO[165]))
#define CAN_MO166 ((CAN_MO_TypeDef *)&(CAN_MO->MO[166]))
#define CAN_MO167 ((CAN_MO_TypeDef *)&(CAN_MO->MO[167]))
#define CAN_MO168 ((CAN_MO_TypeDef *)&(CAN_MO->MO[168]))
#define CAN_MO169 ((CAN_MO_TypeDef *)&(CAN_MO->MO[169]))
#define CAN_MO170 ((CAN_MO_TypeDef *)&(CAN_MO->MO[170]))
#define CAN_MO171 ((CAN_MO_TypeDef *)&(CAN_MO->MO[171]))
#define CAN_MO172 ((CAN_MO_TypeDef *)&(CAN_MO->MO[172]))
#define CAN_MO173 ((CAN_MO_TypeDef *)&(CAN_MO->MO[173]))
#define CAN_MO174 ((CAN_MO_TypeDef *)&(CAN_MO->MO[174]))
#define CAN_MO175 ((CAN_MO_TypeDef *)&(CAN_MO->MO[175]))
#define CAN_MO176 ((CAN_MO_TypeDef *)&(CAN_MO->MO[176]))
#define CAN_MO177 ((CAN_MO_TypeDef *)&(CAN_MO->MO[177]))
#define CAN_MO178 ((CAN_MO_TypeDef *)&(CAN_MO->MO[178]))
#define CAN_MO179 ((CAN_MO_TypeDef *)&(CAN_MO->MO[179]))
#define CAN_MO180 ((CAN_MO_TypeDef *)&(CAN_MO->MO[180]))
#define CAN_MO181 ((CAN_MO_TypeDef *)&(CAN_MO->MO[181]))
#define CAN_MO182 ((CAN_MO_TypeDef *)&(CAN_MO->MO[182]))
#define CAN_MO183 ((CAN_MO_TypeDef *)&(CAN_MO->MO[183]))
#define CAN_MO184 ((CAN_MO_TypeDef *)&(CAN_MO->MO[184]))
#define CAN_MO185 ((CAN_MO_TypeDef *)&(CAN_MO->MO[185]))
#define CAN_MO186 ((CAN_MO_TypeDef *)&(CAN_MO->MO[186]))
#define CAN_MO187 ((CAN_MO_TypeDef *)&(CAN_MO->MO[187]))
#define CAN_MO188 ((CAN_MO_TypeDef *)&(CAN_MO->MO[188]))
#define CAN_MO189 ((CAN_MO_TypeDef *)&(CAN_MO->MO[189]))
#define CAN_MO190 ((CAN_MO_TypeDef *)&(CAN_MO->MO[190]))
#define CAN_MO191 ((CAN_MO_TypeDef *)&(CAN_MO->MO[191]))
#define CAN_MO192 ((CAN_MO_TypeDef *)&(CAN_MO->MO[192]))
#define CAN_MO193 ((CAN_MO_TypeDef *)&(CAN_MO->MO[193]))
#define CAN_MO194 ((CAN_MO_TypeDef *)&(CAN_MO->MO[194]))
#define CAN_MO195 ((CAN_MO_TypeDef *)&(CAN_MO->MO[195]))
#define CAN_MO196 ((CAN_MO_TypeDef *)&(CAN_MO->MO[196]))
#define CAN_MO197 ((CAN_MO_TypeDef *)&(CAN_MO->MO[197]))
#define CAN_MO198 ((CAN_MO_TypeDef *)&(CAN_MO->MO[198]))
#define CAN_MO199 ((CAN_MO_TypeDef *)&(CAN_MO->MO[199]))
#define CAN_MO200 ((CAN_MO_TypeDef *)&(CAN_MO->MO[200]))
#define CAN_MO201 ((CAN_MO_TypeDef *)&(CAN_MO->MO[201]))
#define CAN_MO202 ((CAN_MO_TypeDef *)&(CAN_MO->MO[202]))
#define CAN_MO203 ((CAN_MO_TypeDef *)&(CAN_MO->MO[203]))
#define CAN_MO204 ((CAN_MO_TypeDef *)&(CAN_MO->MO[204]))
#define CAN_MO205 ((CAN_MO_TypeDef *)&(CAN_MO->MO[205]))
#define CAN_MO206 ((CAN_MO_TypeDef *)&(CAN_MO->MO[206]))
#define CAN_MO207 ((CAN_MO_TypeDef *)&(CAN_MO->MO[207]))
#define CAN_MO208 ((CAN_MO_TypeDef *)&(CAN_MO->MO[208]))
#define CAN_MO209 ((CAN_MO_TypeDef *)&(CAN_MO->MO[209]))
#define CAN_MO210 ((CAN_MO_TypeDef *)&(CAN_MO->MO[210]))
#define CAN_MO211 ((CAN_MO_TypeDef *)&(CAN_MO->MO[211]))
#define CAN_MO212 ((CAN_MO_TypeDef *)&(CAN_MO->MO[212]))
#define CAN_MO213 ((CAN_MO_TypeDef *)&(CAN_MO->MO[213]))
#define CAN_MO214 ((CAN_MO_TypeDef *)&(CAN_MO->MO[214]))
#define CAN_MO215 ((CAN_MO_TypeDef *)&(CAN_MO->MO[215]))
#define CAN_MO216 ((CAN_MO_TypeDef *)&(CAN_MO->MO[216]))
#define CAN_MO217 ((CAN_MO_TypeDef *)&(CAN_MO->MO[217]))
#define CAN_MO218 ((CAN_MO_TypeDef *)&(CAN_MO->MO[218]))
#define CAN_MO219 ((CAN_MO_TypeDef *)&(CAN_MO->MO[219]))
#define CAN_MO220 ((CAN_MO_TypeDef *)&(CAN_MO->MO[220]))
#define CAN_MO221 ((CAN_MO_TypeDef *)&(CAN_MO->MO[221]))
#define CAN_MO222 ((CAN_MO_TypeDef *)&(CAN_MO->MO[222]))
#define CAN_MO223 ((CAN_MO_TypeDef *)&(CAN_MO->MO[223]))
#define CAN_MO224 ((CAN_MO_TypeDef *)&(CAN_MO->MO[224]))
#define CAN_MO225 ((CAN_MO_TypeDef *)&(CAN_MO->MO[225]))
#define CAN_MO226 ((CAN_MO_TypeDef *)&(CAN_MO->MO[226]))
#define CAN_MO227 ((CAN_MO_TypeDef *)&(CAN_MO->MO[227]))
#define CAN_MO228 ((CAN_MO_TypeDef *)&(CAN_MO->MO[228]))
#define CAN_MO229 ((CAN_MO_TypeDef *)&(CAN_MO->MO[229]))
#define CAN_MO230 ((CAN_MO_TypeDef *)&(CAN_MO->MO[230]))
#define CAN_MO231 ((CAN_MO_TypeDef *)&(CAN_MO->MO[231]))
#define CAN_MO232 ((CAN_MO_TypeDef *)&(CAN_MO->MO[232]))
#define CAN_MO233 ((CAN_MO_TypeDef *)&(CAN_MO->MO[233]))
#define CAN_MO234 ((CAN_MO_TypeDef *)&(CAN_MO->MO[234]))
#define CAN_MO235 ((CAN_MO_TypeDef *)&(CAN_MO->MO[235]))
#define CAN_MO236 ((CAN_MO_TypeDef *)&(CAN_MO->MO[236]))
#define CAN_MO237 ((CAN_MO_TypeDef *)&(CAN_MO->MO[237]))
#define CAN_MO238 ((CAN_MO_TypeDef *)&(CAN_MO->MO[238]))
#define CAN_MO239 ((CAN_MO_TypeDef *)&(CAN_MO->MO[239]))
#define CAN_MO240 ((CAN_MO_TypeDef *)&(CAN_MO->MO[240]))
#define CAN_MO241 ((CAN_MO_TypeDef *)&(CAN_MO->MO[241]))
#define CAN_MO242 ((CAN_MO_TypeDef *)&(CAN_MO->MO[242]))
#define CAN_MO243 ((CAN_MO_TypeDef *)&(CAN_MO->MO[243]))
#define CAN_MO244 ((CAN_MO_TypeDef *)&(CAN_MO->MO[244]))
#define CAN_MO245 ((CAN_MO_TypeDef *)&(CAN_MO->MO[245]))
#define CAN_MO246 ((CAN_MO_TypeDef *)&(CAN_MO->MO[246]))
#define CAN_MO247 ((CAN_MO_TypeDef *)&(CAN_MO->MO[247]))
#define CAN_MO248 ((CAN_MO_TypeDef *)&(CAN_MO->MO[248]))
#define CAN_MO249 ((CAN_MO_TypeDef *)&(CAN_MO->MO[249]))
#define CAN_MO250 ((CAN_MO_TypeDef *)&(CAN_MO->MO[250]))
#define CAN_MO251 ((CAN_MO_TypeDef *)&(CAN_MO->MO[251]))
#define CAN_MO252 ((CAN_MO_TypeDef *)&(CAN_MO->MO[252]))
#define CAN_MO253 ((CAN_MO_TypeDef *)&(CAN_MO->MO[253]))
#define CAN_MO254 ((CAN_MO_TypeDef *)&(CAN_MO->MO[254]))
#define CAN_MO255 ((CAN_MO_TypeDef *)&(CAN_MO->MO[255]))
#endif
#endif
#endif /* XMC_CAN_MAP_H*/

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/**
* @file xmc_common.h
* @date 2017-04-04
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
* - Brief section updated
* - Added XMC_LIB_VERSION macro
*
* 2016-02-26:
* - Updated XMC_LIB_VERSION macro to v2.1.6
*
* 2016-05-30:
* - Updated XMC_LIB_VERSION macro to v2.1.8
*
* 2016-11-18:
* - Updated XMC_LIB_VERSION macro to v2.1.10
* - Changed type of size in XMC_PRIOARRAY_t to fix compilation warnings
*
* 2017-04-04:
* - Updated XMC_LIB_VERSION macro to v2.1.12
*
* @endcond
*
*/
#ifndef XMC_COMMON_H
#define XMC_COMMON_H
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "xmc_device.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup COMMON
* @brief Common APIs to all peripherals for XMC microcontroller family
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_LIB_MAJOR_VERSION (2U)
#define XMC_LIB_MINOR_VERSION (1U)
#define XMC_LIB_PATCH_VERSION (12U)
#define XMC_LIB_VERSION ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION)
/* Define WEAK attribute */
#if !defined(__WEAK)
#if defined ( __CC_ARM )
#define __WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ )
#define __WEAK __weak
#elif defined ( __GNUC__ )
#define __WEAK __attribute__ ((weak))
#elif defined ( __TASKING__ )
#define __WEAK __attribute__ ((weak))
#endif
#endif
#ifdef XMC_ASSERT_ENABLE
#define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} }
#else
#define XMC_ASSERT(msg, exp) { ; }
#endif
#ifdef XMC_DEBUG_ENABLE
#include <stdio.h>
#define XMC_DEBUG(...) { printf(__VA_ARGS__); }
#else
#define XMC_DEBUG(...) { ; }
#endif
#define XMC_UNUSED_ARG(x) (void)x
#define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m))
#define XMC_PRIOARRAY_DEF(name, size) \
XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \
XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)};
#define XMC_PRIOARRAY(name) \
&prioarray_def_##name
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/*
*
*/
typedef struct XMC_DRIVER_VERSION
{
uint8_t major;
uint8_t minor;
uint8_t patch;
} XMC_DRIVER_VERSION_t;
/*
*
*/
typedef void *XMC_LIST_t;
/*
*
*/
typedef struct XMC_PRIOARRAY_ITEM
{
int32_t priority;
int32_t previous;
int32_t next;
} XMC_PRIOARRAY_ITEM_t;
/*
*
*/
typedef struct XMC_PRIOARRAY
{
int32_t size;
XMC_PRIOARRAY_ITEM_t *items;
} XMC_PRIOARRAY_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*
*
*/
void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line);
/*
*
*/
void XMC_LIST_Init(XMC_LIST_t *list);
/*
*
*/
void XMC_LIST_Add(XMC_LIST_t *list, void *const item);
/*
*
*/
void XMC_LIST_Remove(XMC_LIST_t *list, void *const item);
/*
*
*/
uint32_t XMC_LIST_GetLength(XMC_LIST_t *list);
/*
*
*/
void *XMC_LIST_GetHead(XMC_LIST_t *list);
/*
*
*/
void *XMC_LIST_GetTail(XMC_LIST_t *list);
/*
*
*/
void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item);
/*
*
*/
void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray);
/*
*
*/
void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority);
/*
*
*/
void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item);
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
return prioarray->items[prioarray->size].next;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
return prioarray->items[prioarray->size + 1].previous;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].priority;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].next;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].previous;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_COMMON_H */

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/**
* @file xmc_eru.h
* @date 2016-03-10
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-10-07:
* - Doc update for XMC_ERU_ETL_CONFIG_t field <br>
*
* 2016-03-10:
* - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
*
* @endcond
*/
#ifndef XMC_ERU_H
#define XMC_ERU_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup ERU
* @brief Event Request Unit (ERU) driver for the XMC microcontroller family.
*
* The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit.
* The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals,
* peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of
* triggers, pattern detection and real-time signal monitoring.
*
* @image html "eru_overview.png"
*
* The driver is divided into two sections:
* \par Event trigger logic (ERU_ETL):
* This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function
* XMC_ERU_ETL_Init().\n
* It can be used to:
* -# Select one out of two inputs (A and B). For each of these two inputs, a vector of 4 possible signals is available.
* (XMC_ERU_ETL_SetSource())
* -# Logically combine the two input signals to a common trigger. (XMC_ERU_ETL_SetSource())
* -# Define the transition (edge selection, or by software) that leads to a trigger event and can also store this status.
* (XMC_ERU_ETL_SetEdgeDetection() and XMC_ERU_ETL_SetStatusFlag())
* -# Distribute the events and status flags to the output channels. (XMC_ERU_ETL_EnableOutputTrigger())
*
* \par Output gating unit (ERU_OGU):
* This section of the LLD provides the provides the configuration structure XMC_ERU_OGU_CONFIG_t and the initialization
* function XMC_ERU_ETL_OGU_Init().
* It can be used to:
* -# Combine the trigger events and status information and gates the output depending on a gating signal.
* (XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_SetServiceRequestMode())
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#if defined(ERU0)
#define XMC_ERU0 ((XMC_ERU_t *) ERU0_BASE) /**< ERU module 0 */
#endif
#if defined(ERU1)
#define XMC_ERU1 ((XMC_ERU_t *) ERU1_BASE) /**< ERU module 1, only available in XMC4 family */
#endif
#if UC_FAMILY == XMC1
#include "xmc1_eru_map.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_eru_map.h"
#endif
#if defined(XMC_ERU0) && defined(XMC_ERU1)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0) | ((PTR)== XMC_ERU1))
#elif defined(XMC_ERU0)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0))
#elif defined(XMC_ERU1)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0))
#endif
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.
* @image html "eru_input_a.png" "ETLx Input A selection"
*/
typedef enum XMC_ERU_ETL_INPUT_A
{
XMC_ERU_ETL_INPUT_A0 = 0x0U, /**< input A0 is selected */
XMC_ERU_ETL_INPUT_A1 = 0x1U, /**< input A1 is selected */
XMC_ERU_ETL_INPUT_A2 = 0x2U, /**< input A2 is selected */
XMC_ERU_ETL_INPUT_A3 = 0x3U /**< input A3 is selected */
} XMC_ERU_ETL_INPUT_A_t;
/**
* Defines input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.
* @image html "eru_input_b.png" "ETLx Input B selection"
*/
typedef enum XMC_ERU_ETL_INPUT_B
{
XMC_ERU_ETL_INPUT_B0 = 0x0U, /**< input B0 is selected */
XMC_ERU_ETL_INPUT_B1 = 0x1U, /**< input B1 is selected */
XMC_ERU_ETL_INPUT_B2 = 0x2U, /**< input B2 is selected */
XMC_ERU_ETL_INPUT_B3 = 0x3U /**< input B3 is selected */
} XMC_ERU_ETL_INPUT_B_t;
/**
* Defines input path combination along with polarity for event generation by ERSx(Event request source) unit to
* ETLx(Event trigger logic),x = [0 to 3] unit.
* @image html "eru_input_trigger.png" "ETLx input trigger signal generation"
*/
typedef enum XMC_ERU_ETL_SOURCE
{
XMC_ERU_ETL_SOURCE_A = 0x0U, /**< select (A) path as a event source */
XMC_ERU_ETL_SOURCE_B = 0x1U, /**< select (B) path as a event source */
XMC_ERU_ETL_SOURCE_A_OR_B = 0x2U, /**< select (A <b>OR</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_A_AND_B = 0x3U, /**< select (A <b>AND</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A = 0x4U, /**< select (inverted A) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_OR_B = 0x6U, /**< select (inverted A <b>OR</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_AND_B = 0x7U, /**< select (inverted A <b>AND</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_B = 0x9U, /**< select (inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_A_OR_NOT_B = 0xaU, /**< select (A <b>OR</b> inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_A_AND_NOT_B = 0xbU, /**< select (A <b>AND</b> inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B = 0xeU, /**< select (inverted A <b>OR</b> inverted B) path as a event
source */
XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B = 0xfU /**< select (inverted A <b>AND</b> inverted B) path as a event
source */
} XMC_ERU_ETL_SOURCE_t;
/**
* Defines trigger edge for the event generation by ETLx (Event Trigger Logic, x = [0 to 3]) unit, by getting the signal
* from ERSx(Event request source, x = [0 to 3]) unit.
*/
typedef enum XMC_ERU_ETL_EDGE_DETECTION
{
XMC_ERU_ETL_EDGE_DETECTION_DISABLED = 0U, /**< no event enabled */
XMC_ERU_ETL_EDGE_DETECTION_RISING = 1U, /**< detection of rising edge generates the event */
XMC_ERU_ETL_EDGE_DETECTION_FALLING = 2U, /**< detection of falling edge generates the event */
XMC_ERU_ETL_EDGE_DETECTION_BOTH = 3U /**< detection of either edges generates the event */
} XMC_ERU_ETL_EDGE_DETECTION_t;
/**
* Defines Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* @note Generation of output trigger pulse need to be enabled @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t
* @image html "eru_connection_matrix.png" "ERU_ETL ERU_OGU Connection matrix"
*/
typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL
{
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0 = 0U, /**< Event from input ETLx triggers output OGU0 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1 = 1U, /**< Event from input ETLx triggers output OGU1 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2 = 2U, /**< Event from input ETLx triggers output OGU2 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3 = 3U, /**< Event from input ETLx triggers output OGU3 */
} XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t;
/**
* Defines generation of the trigger pulse by ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* Use type XMC_ERU_ETL_OUTPUT_TRIGGER_t for this enum.
*/
typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER
{
XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED = 0U, /**< trigger pulse generation disabled */
XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED = 1U /**< trigger pulse generation enabled */
} XMC_ERU_ETL_OUTPUT_TRIGGER_t;
/**
* Defines status flag reset mode generated by ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* Use type XMC_ERU_ETL_STATUS_FLAG_MODE_t for this enum.
*/
typedef enum XMC_ERU_ETL_STATUS_FLAG_MODE
{
XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL = 0U, /**< Status flag is in sticky mode. Retain the same state until
cleared by software. In case of pattern match this mode
is used. */
XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL = 1U /**< Status flag is in non-sticky mode. Automatically cleared by
the opposite edge detection.\n
eg. if positive edge is selected as trigger event, for the
negative edge event the status flag is cleared. */
} XMC_ERU_ETL_STATUS_FLAG_MODE_t;
/**
* Defines pattern detection feature to be enabled or not in OGUy(Output gating unit, y = [0 to 3]).
*
*/
typedef enum XMC_ERU_OGU_PATTERN_DETECTION
{
XMC_ERU_OGU_PATTERN_DETECTION_DISABLED = 0U, /**< Pattern match is disabled */
XMC_ERU_OGU_PATTERN_DETECTION_ENABLED = 1U /**< Pattern match is enabled, the selected status flags of
ETLx(Event Trigger Logic, x = [0 to 3]) unit, are
used in pattern detection. */
} XMC_ERU_OGU_PATTERN_DETECTION_t;
/**
* Defines the inputs for Pattern detection. The configured status flag signal from the ETLx(Event Trigger Logic,
* x = [0 to 3]) unit indicates the pattern to be detected.
*/
typedef enum XMC_ERU_OGU_PATTERN_DETECTION_INPUT
{
XMC_ERU_OGU_PATTERN_DETECTION_INPUT0 = 1U, /**< Status flag ETL0, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT1 = 2U, /**< Status flag ETL1, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT2 = 4U, /**< Status flag ETL0, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT3 = 8U /**< Status flag ETL0, participating in pattern match */
} XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t;
/**
* Defines peripheral trigger signal for event generation. Based on the selected peripheral for event generation,
* the trigger signal is mapped.
*/
typedef enum XMC_ERU_OGU_PERIPHERAL_TRIGGER
{
XMC_ERU_OGU_PERIPHERAL_TRIGGER1 = 1U, /**< OGUy1 signal is mapped for event generation */
XMC_ERU_OGU_PERIPHERAL_TRIGGER2 = 2U, /**< OGUy2 signal is mapped for event generation */
XMC_ERU_OGU_PERIPHERAL_TRIGGER3 = 3U /**< OGUy3 signal is mapped for event generation */
} XMC_ERU_OGU_PERIPHERAL_TRIGGER_t;
/**
* Defines the gating scheme for service request generation. In later stage of the OGUy(Output gating unit,
* y = [0 to 3]) based on the gating scheme selected ERU_GOUTy(gated output signal) output is defined.
* @image html "interrupt_gating_signal.png" "Interrupt gating signal"
*/
typedef enum XMC_ERU_OGU_SERVICE_REQUEST
{
XMC_ERU_OGU_SERVICE_REQUEST_DISABLED = 0U, /**< Service request blocked, ERUx_GOUTy = 0 */
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER = 1U, /**< Service request generated enabled, ERUx_GOUTy = 1 */
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH = 2U, /**< Service request generated on trigger
event and input pattern match,
ERUx_GOUTy = ~pattern matching result*/
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH = 3U/**< Service request generated on trigger
event and input pattern mismatch,
ERUx_GOUTy = pattern matching result*/
} XMC_ERU_OGU_SERVICE_REQUEST_t;
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*Anonymous structure/union guard start*/
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* ERU module
*/
typedef struct {
union {
__IO uint32_t EXISEL;
struct {
__IO uint32_t EXS0A : 2;
__IO uint32_t EXS0B : 2;
__IO uint32_t EXS1A : 2;
__IO uint32_t EXS1B : 2;
__IO uint32_t EXS2A : 2;
__IO uint32_t EXS2B : 2;
__IO uint32_t EXS3A : 2;
__IO uint32_t EXS3B : 2;
} EXISEL_b;
};
__I uint32_t RESERVED0[3];
union {
__IO uint32_t EXICON[4];
struct {
__IO uint32_t PE : 1;
__IO uint32_t LD : 1;
__IO uint32_t ED : 2;
__IO uint32_t OCS : 3;
__IO uint32_t FL : 1;
__IO uint32_t SS : 4;
__I uint32_t RESERVED1 : 20;
} EXICON_b[4];
};
union {
__IO uint32_t EXOCON[4];
struct {
__IO uint32_t ISS : 2;
__IO uint32_t GEEN : 1;
__I uint32_t PDR : 1;
__IO uint32_t GP : 2;
uint32_t : 6;
__IO uint32_t IPEN : 4;
__I uint32_t RESERVED2 : 16;
} EXOCON_b[4];
};
} XMC_ERU_t;
/**
* \if XMC4
* Structure for initializing ERUx_ETLy (x = [0..1], y = [0..4]) module.
* \endif
* \if XMC1
* Structure for initializing ERUx_ETLy (x = [0], y = [0..4]) module.
* \endif
*/
typedef struct XMC_ERU_ETL_CONFIG
{
union
{
uint32_t input; /**< While configuring the bit fields, the values have to be shifted according to the position */
struct
{
uint32_t input_a: 2; /**< Configures input A. Refer @ref XMC_ERU_ETL_INPUT_A_t for valid values */
uint32_t input_b: 2; /**< Configures input B. Refer @ref XMC_ERU_ETL_INPUT_B_t for valid values */
uint32_t : 28;
};
};
union
{
uint32_t raw;
struct
{
uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge
detection. This accepts boolean values as input. */
uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the
configured event edge. This accepts boolean values as input. */
uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE).
Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t for valid values. */
uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse.
Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid values. */
uint32_t : 1;
uint32_t source: 4; /**< Input path combination along with polarity for event generation.
Refer @ref XMC_ERU_ETL_SOURCE_t for valid values. */
uint32_t : 20;
};
};
} XMC_ERU_ETL_CONFIG_t;
/**
* \if XMC4
* Structure for initializing ERUx_OGUy (x = [0..1], y = [0..4]) module.
* \endif
* \if XMC1
* Structure for initializing ERUx_OGUy (x = [0], y = [0..4]) module.
* \endif
*/
typedef union XMC_ERU_OGU_CONFIG
{
uint32_t raw;
struct
{
uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection.
Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for valid values. */
uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change.
This accepts boolean values as input. */
uint32_t : 1;
uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result.
Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. */
uint32_t : 6;
uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]).
Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values.
<b>OR</b> combination of the enum items given as input */
uint32_t : 16;
};
} XMC_ERU_OGU_CONFIG_t;
/*Anonymous structure/union guard end */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/*********************************************************************************************************************
* API PROTOTYPES
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* If ERU1 module is selected, it enables clock and releases reset.<br>
* \endif
* \if XMC1
* Abstract API, not mandatory to call. <br>
* \endif
* \par
* This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during
* initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling
* XMC_ERU_Disable(). For ERU0 module clock gating and reset features are not available.
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are
* reset with default values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_Init(), XMC_ERU_OGU_Init(), XMC_ERU_Disable().
*/
void XMC_ERU_Enable(XMC_ERU_t *const eru);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Disables clock and releases reset for ERU1 module.<br>
* \endif
* \if XMC1
* Abstract API, not mandatory to call. <br>
* \endif
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Required to configure ERU1 module again after calling XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init(). Since the all the
* registers are reset with default values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_ERU_Enable()
*/
void XMC_ERU_Disable(XMC_ERU_t *const eru);
/* ERU_ETL APIs */
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_ETLx(Event trigger logic unit) channel
* Range : [0 to 3]
* @param config pointer to a constant ERU_ETLx configuration data structure.
* Refer data structure XMC_ERU_ETL_CONFIG_t for detail.
*
* @return None
*
* <b>Description:</b><br>
* Initializes the selected ERU_ETLx \a channel with the \a config structure.<br>
*
* Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures
* <ul>
* <li>Input signal for path A and Path B,</li>
* <li>Trigger pulse generation,</li>
* <li>status flag clear mode,</li>
* <li>Event Trigger edge,</li>
* <li>Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse,</li>
* <li>input path combination along with polarity for event generation</li>
* </ul>.
*/
void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *const config);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param input_a input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.\n
* Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of
* the input is done based on selected signal.\n
* e.g: ERU0_ETL3_INPUTA_P2_7.
* @param input_b input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.\n
* Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of
* the input is done based on selected signal.\n
* e.g: ERU0_ETL0_INPUTB_P2_0.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the event source for path A and path B in with selected \a input_a and \a input_b respectively.<br>
* \par
* These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in
* the program. According to the ports/peripheral selected, the event source has to be changed.
*/
void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_INPUT_A_t input_a,
const XMC_ERU_ETL_INPUT_B_t input_b);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param source input path combination along with polarity for event generation by ERSx(Event request source) unit.
* Refer @ref XMC_ERU_ETL_SOURCE_t enum for valid input values.
*
* @return None
*
* \par<b>Description:</b><br>
* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in
* ERSx(Event request source) unit <br>
* \par
* The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic,
* x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to
* change the source, as needed later in the program.
*/
void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_SOURCE_t source);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param edge_detection event trigger edge.
* Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t enum for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.<br>
* \par
* Rising edge, falling edge or either edges can be selected to generate the event.These values are set during
* initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*/
void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return XMC_ERU_ETL_EDGE_DETECTION_t indicate which egde/s is configured for event generation
*
* \par<b>Description:</b><br>
* Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.<br>
* \par
* Rising edge, falling edge or either edges can be selected to generate the event.
* Call this to get the configured trigger edge. */
XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Set the status flag bit(FL) in EXICONx(x = [0 to 3]).<br>
* \par
* The status flag indicates that the configured event has occurred. This status flag is used in Pattern match detection
* by OGUy(Output gating unit, y = [0 to 3]).
* \par
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
__STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].FL = true;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Set the status flag bit(FL) in EXICONx(x = [0 to 3]).<br>
* \par
* If auto clear of the status flag is not enabled by detection of the opposite edge of the event edge, this API clears
* the Flag. SO that next event is considered as new event.
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
__STATIC_INLINE void XMC_ERU_ETL_ClearStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].FL = false;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
*
* @return uint32_t Current state of the status flag bit(FL). Result is in 32-bit format.
*
* \par<b>Description:</b><br>
* Returns status flag state of \a channel.
* \par
* The function can typically be used to clear the status flag using software, when auto clear is not enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_ClearStatusFlag()
*/
__STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Channel Number", (channel < 4U));
return (uint32_t)eru->EXICON_b[channel].FL;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
* @param mode Set whether status flag has to be cleared by software or hardware.
* Refer @ref XMC_ERU_ETL_STATUS_FLAG_MODE_t for valid value.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the mode for status flag mode by setting (LD) bit in EXICONx(x = \a channel) register.<br>
* \par
* If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection.
* If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative
* edge status flag is cleared and vice versa.This is typically used for continuous event detection.These values are set
* during initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
* @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse
* Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid value.
*
* @return None
*
* \par<b>Description:</b><br>
* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = \a channel) by setting (OCS and PE) bit fields.
* \par
* The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to
* trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event
* based on the trigger pulse.If output trigger pulse generation is disabled by XMC_ERU_ETL_DisableOutputTrigger(),
* XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in
* XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_DisableOutputTrigger()
*/
void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = \a channel).
* \par
* Typically this can used when only pattern match is being used for event generation.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_EnableOutputTrigger()
*/
void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel);
/* ERU_OGU APIs */
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param config pointer to constant ERU_OGUy configuration data structure.
* Refer data structure XMC_ERU_OGU_CONFIG_t for detail.
*
* @return None
*
* <b>Description:</b><br>
* Initializes the selected ERU_OGUy \a channel with the \a config structure.<br>
*
* Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures
* <ul>
* <li>Pattern detection,</li>
* <li>Peripheral trigger input,</li>
* <li>Gating for service request generation</li>
* </ul>.
*/
void XMC_ERU_OGU_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_CONFIG_t *const config);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param input ERU_ETLx(x = [0 to 3]), for pattern match detection.
* Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical <b>OR</b> combination of the
* enum items can be passed as the input.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3]) and GEEN bits.
* \par
* These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in
* XMC_ERU_OGU_Init(). Call this to change the pattern, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_DisablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus()
*/
void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Disable the pattern detection by clearing (GEEN) bit.
* \par
* Typically XMC_ERU_OGU_DisablePatternDetection is used when events has to be generated peripheral triggers.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus()
*/
void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return uint32_t returns the pattern match result. Result is in 32-bit format.
*
* \par<b>Description:</b><br>
* This API returns the pattern match result by reading (PDR) bit.
* \par
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePatternDetection()
*/
__STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const eru,
const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Channel Number", (channel < 4U));
return (uint32_t)eru->EXOCON_b[channel].PDR;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param peripheral_trigger which peripheral trigger signal is used for event generation.
* Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or
xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based
on input. e.g: ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures peripheral trigger input, by setting (ISS) bit.
* \par
* Based on the peripheral the input signal has to be selected. These values are set during initialization in
* XMC_ERU_OGU_Init(). Call this to change the input, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_DisablePeripheralTrigger()
*/
void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Disables event generation based on peripheral trigger by clearing (ISS) bit.
* \par
* This is typically used when peripheral trigger is no longer need. After calling
* XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the
* signals again.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePeripheralTrigger()
*/
void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param mode gating scheme for service request generation.
* Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the gating scheme for service request generation by setting (GP) bit.<br>
* \par
* Typically this function is used to change the service request generation scheme. These values are set during
* initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program.
*
*/
void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_SERVICE_REQUEST_t mode);
#ifdef __cplusplus
}
#endif
/**
* @} (end addtogroup ERU)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* XMC_ERU_H */

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/**
* @file xmc_flash.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial <br>
* 2015-02-20:
* - Updated for Documentation related changes<br>
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* @endcond
*
*/
#ifndef XMC_FLASH_H
#define XMC_FLASH_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC1
#include "xmc1_flash.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_flash.h"
#endif
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup FLASH
* @brief Flash driver for XMC microcontroller family.
*
* Flash is a non volatile memory module used to store instruction code or constant data.
* The flash low level driver provides support to the following functionalities of flash memory.<BR>
* <OL>
* \if XMC4
* <LI>Provides function to program a page. ( XMC_FLASH_ProgramPage() )</LI><BR>
* <LI>Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(),
* XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() ) </LI><BR>
* <LI>Provides function to erase sector. ( XMC_FLASH_EraseSector() ) </LI><BR>
* \endif
* \if XMC1
* <LI>Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages()
* XMC_FLASH_ProgramVerifyPage() )</LI><BR>
* <LI>Provides functions to write and verify blocks. ( XMC_FLASH_WriteBlocks(), XMC_FLASH_VerifyBlocks() )</LI><BR>
* <LI>Provides functions to read data in terms of word and blocks. ( XMC_FLASH_ReadBlocks(), XMC_FLASH_ReadWord() )
* </LI><BR>
* <LI>Provides function to erase page. ( XMC_FLASH_ErasePage() ) </LI><BR>
* \endif
* </OL>
* @{
*/
/*******************************************************************************
* API PROTOTYPE
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Clears the previous error status by reseting the ECC and VERR error status bits of NVMSTATUS register.\n\n
* Call this API before starting any flash programming / erase related APIs to ensure all previous errors are cleared.
* \endif
* \if XMC4
* Clears the previous error status by reseting the FSR status register.\n\n Call this API before starting any flash
* programming / erase related APIs to ensure all previous errors are cleared.
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ClearStatus(void);
/**
*
* @param None
*
* @return uint32_t Status of the previous flash operation.
*
* \par<b>Description:</b><br>
* \if XMC1
* Informs the status of flash by reading the NVMSTATUS register.\n\n It indicates the ECC, VERR(verification error),
* WRPERR (Write protocol error) errors as well as the current flash state. After calling the flash read/write/erase
* operation related APIs, call this API to get the verification status. The return value of this API shall be checked
* against the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status.
* \endif
* \if XMC4
* Informs the status of flash by reading the FSR register.\n\n It indicates the error status such as PFOPER, SQER,
* PROER, PFDBER, ORIER, VER errors as well as the current flash state. After calling the flash read/write/erase
* operation related APIs, call this API to verify flash status. The return value of this API shall be checked against
* the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status.
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
uint32_t XMC_FLASH_GetStatus(void);
/**
*
* @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the particular flash events as specified in the input parameter.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_DisableEvent()\n\n\n
*
*/
void XMC_FLASH_EnableEvent(const uint32_t event_msk);
/**
*
* @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the particular flash events as specified in the input parameter.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnableEvent()\n\n\n
*
*/
void XMC_FLASH_DisableEvent(const uint32_t event_msk);
/**
*
* @param address Pointer to the starting address of flash page from where the programming starts.
* @param data Pointer to the source address where targeted data is located.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one
* page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr)
* to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines
* (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation.
* \endif
* \if XMC4
* Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a
* granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status
* bits inside status register. It starts the write process by issuing the page mode command followed by the load page
* command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page
* command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the
* programming operation.\n
* \endif
*
* \par<b>Note:</b><br>
* Flash will be busy state during write is ongoing, hence no operations allowed until it completes.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data);
/**
*
* @param address Pointer to the starting address of the page to be erased.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity
* of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16
* times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API,
* to verify the erase operation.\n
* \endif
*
* \if XMC4
* Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside
* FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash
* erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n
* \endif
* \if XMC1
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ErasePages() \n\n\n
* \endif
* \if XMC4
* \par<b>Related APIs:</b><BR>
* None
* \endif
*/
void XMC_FLASH_EraseSector(uint32_t *address);
/**
*
* @param None
*
* @return true if flash is in busy state else returns \a false.
*
* \par<b>Description:</b><br>
* Checks whether flash is in busy state or not.\n\n It is checked by calling the XMC_FLASH_GetStatus() API internally.
* Refer XMC_FLASH_GetStatus() for more details.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_GetStatus()\n\n\n
*
*/
__STATIC_INLINE bool XMC_FLASH_IsBusy(void)
{
return (bool)(XMC_FLASH_GetStatus() & XMC_FLASH_STATUS_BUSY);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_gpio.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft<br>
* - Documentation improved <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#ifndef XMC_GPIO_H
#define XMC_GPIO_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup GPIO
* @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family.
*
* GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins.
* Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the
* connectivity to the on-chip periphery and the control for the pad characteristics.
*
* The driver is divided into Input and Output mode.
*
* Input mode features:
* -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init()
* -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode()
* \if XMC1
* -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis()
* \endif
*
*
* Output mode features:
* -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode()
* \if XMC4
* -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength()
* \endif
*
* -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel()
*
*@{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define PORT_IOCR_PC_Pos PORT0_IOCR0_PC0_Pos
#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk
#define PORT_IOCR_PC_Size (8U)
#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \
(level == XMC_GPIO_OUTPUT_LEVEL_HIGH))
#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \
(hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \
(hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2))
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum.
*/
typedef enum XMC_GPIO_OUTPUT_LEVEL
{
XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */
XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */
} XMC_GPIO_OUTPUT_LEVEL_t;
/**
* Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum.
*/
typedef enum XMC_GPIO_HWCTRL
{
XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */
XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */
XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */
} XMC_GPIO_HWCTRL_t;
/**********************************************************************************************************************
* DEVICE FAMILY EXTENSIONS
*********************************************************************************************************************/
#if UC_FAMILY == XMC1
#include "xmc1_gpio.h"
#elif UC_FAMILY == XMC4
#include "xmc4_gpio.h"
#else
#error "xmc_gpio.h: family device not supported"
#endif
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc.
* @param pin Port pin number.
* @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain.
* Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin.
* \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR.
* \endif
* \if XMC4
* Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode.
* Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin .
* It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* This API is called in definition of DAVE_init by code generation and therefore should not be explicitly called
* for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS).
*
*
*/
void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config);
/**
*
* @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR.
* @param pin Port pin number.
* @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardware
* registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alter
* the port direction functionality as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode);
/**
*
* @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin Port pin number.
* @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially
* configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow().
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level)
{
XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level));
port->OMR = (uint32_t)level << pin;
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin Port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets port pin output to high. It configures hardware registers Pn_OMR.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputLow()
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\n
* Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = (uint32_t)0x1U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin port pin number.
*
* @return None
*
*\par<b>Description:</b><br>
* Sets port pin output to low. It configures hardware registers Pn_OMR.\n
*
* \par<b>Related APIs:</b><BR>>
* XMC_GPIO_SetOutputHigh()
*
*\par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().
* Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = 0x10000U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures port pin output to Toggle. It configures hardware registers Pn_OMR.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow().
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtual
* and does not contain any flip-flop. A read action delivers the value of 0.
*
*/
__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = 0x10001U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN.
* @param pin Port pin number.
*
* @return uint32_t pin logic level status.
*
*\par<b>Description:</b><br>
* Reads the Pn_IN register and returns the current logical value at the GPIO pin.
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode().
*
*/
__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port));
return (((port->IN) >> pin) & 0x1U);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters
* Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Trigger
* as well as the output driver stage are switched off. By default port pin does not react to power save mode request.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_DisablePowerSaveMode()
*
* <b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so
* may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
port->PPS |= (uint32_t)0x1U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters
* Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power
* save mode previously). By default port \a pin does not react to power save mode request.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_EnablePowerSaveMode()
*
*\par<b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so
* may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL.
* @param pin port pin number.
* @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins
* overlaid with peripheral functions for which the connected peripheral needs hardware control.
*
* \par<b>Related APIs:</b><BR>
* None
*
*\par<b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B).
* Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl);
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC.
* @param pin port pin number.
*
* @return None
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Description:</b><br>
* Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for
* analog port pins.
*
*/
__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port));
port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC.
* @param pin port pin number.
*
* @return None
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Description:</b><br>
* Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only
* for analog port pins.
*
*/
__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port));
port->PDISC |= (uint32_t)0x1U << pin;
}
#ifdef __cplusplus
}
#endif
/**
* @} (end addtogroup GPIO)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* XMC_GPIO_H */

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/**
* @file xmc_i2c.h
* @date 2016-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Description updated <br>
* - Added XMC_I2C_CH_TriggerServiceRequest() and XMC_I2C_CH_SelectInterruptNodePointer() <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-27:
* - Added APIs for external input for BRG configuration:XMC_I2C_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-09-01:
* - Added APIs for enabling or disabling the ACK response to a 0x00 slave address: XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and
* XMC_I2C_CH_DisableSlaveAcknowledgeTo00(). <br>
* - Modified XMC_I2C_CH_SetInputSource() API for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_I2C_CH_EVENT_t enum for supporting XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent()
* for supporting multiple events configuration <br>
*
* 2015-10-02:
* - Fix 10bit addressing
*
* 2015-10-07:
* - Fix register access in XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and XMC_I2C_CH_DisableSlaveAcknowledgeTo00() APIs.
* - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to XMC_I2C_CH_EnableAcknowledgeAddress0()
* and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0().
*
* 2016-05-20:
* - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission()
*
* 2016-08-17:
* - Improved documentation of slave address passing
*
* @endcond
*
*/
#ifndef XMC_I2C_H
#define XMC_I2C_H
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup I2C
* @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family.
*
* USIC IIC Features: <br>
* * Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA) <br>
* * Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s) <br>
* * Support of 7-bit addressing, as well as 10-bit addressing <br>
* * Master mode operation, where the IIC controls the bus transactions and provides the clock signal. <br>
* * Slave mode operation, where an external master controls the bus transactions and provides the clock signal.<br>
* * Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave. <br>
The master/slave operation of an IIC bus participant can change from frame to frame. <br>
* * Efficient frame handling (low software effort), also allowing DMA transfers <br>
* * Powerful interrupt handling due to multitude of indication flags <br>
* @{
*/
/*******************************************************************************
* MACROS
*******************************************************************************/
#if defined(USIC0)
#define XMC_I2C0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_I2C0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_I2C1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_I2C1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_I2C2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_I2C2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
#define XMC_I2C_10BIT_ADDR_GROUP (0x7800U) /**< Value to verify the address is 10-bit or not */
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* @brief I2C Status
*/
typedef enum XMC_I2C_CH_STATUS
{
XMC_I2C_CH_STATUS_OK, /**< Status OK */
XMC_I2C_CH_STATUS_ERROR, /**< Status ERROR */
XMC_I2C_CH_STATUS_BUSY /**< Status BUSY */
} XMC_I2C_CH_STATUS_t;
/**
* @brief I2C status
*/
typedef enum XMC_I2C_CH_STATUS_FLAG
{
XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT = USIC_CH_PSR_IICMode_SLSEL_Msk, /**< Slave select status */
XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND = USIC_CH_PSR_IICMode_WTDF_Msk, /**< Wrong TDF status */
XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_SCR_Msk, /**< Start condition received status */
XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_RSCR_Msk, /**< Repeated start condition received status */
XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_PCR_Msk, /**< Stop condition received status */
XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED = USIC_CH_PSR_IICMode_NACK_Msk, /**< NACK received status */
XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST = USIC_CH_PSR_IICMode_ARL_Msk, /**< Arbitration lost status */
XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED = USIC_CH_PSR_IICMode_SRR_Msk, /**< Slave read requested status */
XMC_I2C_CH_STATUS_FLAG_ERROR = USIC_CH_PSR_IICMode_ERR_Msk, /**< Error status */
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED = USIC_CH_PSR_IICMode_ACK_Msk, /**< ACK received status */
XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IICMode_RSIF_Msk, /**< Receive start indication status */
XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IICMode_DLIF_Msk, /**< Data lost indication status */
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IICMode_TSIF_Msk, /**< Transmit shift indication status */
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IICMode_TBIF_Msk, /**< Transmit buffer indication status */
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_RIF_Msk, /**< Receive indication status */
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_AIF_Msk, /**< Alternate receive indication status */
XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IICMode_BRGIF_Msk /**< Baud rate generator indication status */
} XMC_I2C_CH_STATUS_FLAG_t;
/**
* @brief I2C receiver status. The received data byte is available at the bit
* positions RBUF[7:0], whereas the additional information is monitored at the bit positions
* RBUF[12:8].
*/
typedef enum XMC_I2C_CH_RECEIVER_STATUS_FLAG
{
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK = 0x1U, /**< Bit 8: Value of Received Acknowledgement bit */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition
followed by the address reception the first data byte of a new frame has
been received. A 0 at this bit position indicates further data bytes */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received
when the device has been in slave mode, whereas a 1 indicates a reception in master mode */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous
data byte in the receive buffer */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address
has been received. A 1 indicates a general call address. */
} XMC_I2C_CH_RECEIVER_STATUS_FLAG_t;
/**
* @brief I2C commands
*/
typedef enum XMC_I2C_CH_CMD
{
XMC_I2C_CH_CMD_WRITE, /**< I2C Command Write */
XMC_I2C_CH_CMD_READ /**< I2C Command Read */
} XMC_I2C_CH_CMD_t;
/**
* @brief I2C events
*/
typedef enum XMC_I2C_CH_EVENT
{
XMC_I2C_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_I2C_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_I2C_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_I2C_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_I2C_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_SCRIEN_Msk, /**< Start condition received event */
XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_RSCRIEN_Msk, /**< Repeated start condition received event */
XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_PCRIEN_Msk, /**< Stop condition received event */
XMC_I2C_CH_EVENT_NACK = USIC_CH_PCR_IICMode_NACKIEN_Msk, /**< NACK received event */
XMC_I2C_CH_EVENT_ARBITRATION_LOST = USIC_CH_PCR_IICMode_ARLIEN_Msk, /**< Arbitration lost event */
XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST = USIC_CH_PCR_IICMode_SRRIEN_Msk, /**< Slave read request event */
XMC_I2C_CH_EVENT_ERROR = USIC_CH_PCR_IICMode_ERRIEN_Msk, /**< Error condition event */
XMC_I2C_CH_EVENT_ACK = USIC_CH_PCR_IICMode_ACKIEN_Msk /**< ACK received event */
} XMC_I2C_CH_EVENT_t;
/**
* @brief I2C input stage selection
*/
typedef enum XMC_I2C_CH_INPUT
{
XMC_I2C_CH_INPUT_SDA = 0U, /**< selection of sda input stage */
#if UC_FAMILY == XMC1
XMC_I2C_CH_INPUT_SDA1 = 3U,
XMC_I2C_CH_INPUT_SDA2 = 5U,
#endif
XMC_I2C_CH_INPUT_SCL = 1U, /**< selection of scl input stage */
#if UC_FAMILY == XMC1
XMC_I2C_CH_INPUT_SCL1 = 4U
#endif
} XMC_I2C_CH_INPUT_t;
/**
* I2C channel interrupt node pointers
*/
typedef enum XMC_I2C_CH_INTERRUPT_NODE_POINTER
{
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_I2C_CH_INTERRUPT_NODE_POINTER_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* @brief I2C_CH configuration structure
*/
typedef struct XMC_I2C_CH_CONFIG
{
uint32_t baudrate; /**< baud rate configuration upto max of 400KHz */
uint16_t address; /**< slave address
A 7-bit address needs to be left shifted it by 1.
A 10-bit address needs to be ORed with XMC_I2C_10BIT_ADDR_GROUP. */
} XMC_I2C_CH_CONFIG_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Initializes the I2C \a channel.<br>
*
* \par
* Configures the data format in SCTR register. Sets the slave address, baud rate. Enables transmit data valid, clears status flags
* and disables parity generation.<br>
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_Enable()\n\n
*/
void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param rate baud rate of I2C channel
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the rate of I2C \a channel.
*
* \par<b>Note:</b><br>
* Standard over sampling is considered if rate <= 100KHz and fast over sampling is considered if rate > 100KHz.<br>
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetBaudrate()\n\n
*/
XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Starts the I2C \a channel.
*
* \par
* Sets the USIC input operation mode to I2C mode using CCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetMode()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_Start(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2C);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
*
* @return @ref XMC_I2C_CH_STATUS_t<br>
*
* \par<b>Description:</b><br>
* Stops the I2C \a channel.<br>
*
* \par
* Sets the USIC input operation to IDLE mode using CCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetMode()\n\n
*/
XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param service_request Service request number in the range of 0-5
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the interrupt node for protocol interrupt.<br>
*
* \par
* To generate interrupt for an event, node pointer should be configured with service request number(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
*
* \par<b>Note:</b><br>
* NVIC node should be separately enabled to generate the interrupt. After setting the node pointer, desired event must be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableEvent(), NVIC_SetPriority(), NVIC_EnableIRQ(), XMC_I2C_CH_SetInputSource()<br>
*/
__STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a I2C interrupt service request.\n\n
* When the I2C service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param input I2C channel input stage of type @ref XMC_I2C_CH_INPUT_t
* @param source Input source select for the input stage(0->DX0A, 1->DX1A, .. 7->DX7G)
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the input source for I2C \a channel.<br>
* Defines the input stage for the corresponding input line.
*
* @note After configuring the input source for corresponding channel, interrupt node pointer is set.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetInptSource(), XMC_USIC_CH_SetInterruptNodePointer()
*
*/
__STATIC_INLINE void XMC_I2C_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_INPUT_t input, const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_INSW_Msk)) | USIC_CH_DX0CR_DSEN_Msk;
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param address I2C slave address
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the I2C \a channel slave address.<br>
*
* \par
* Address is set in PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.
* (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)\n
* @note A 7-bit address should include an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. A 10-bit address should be provided with the identifier 0b11110xx at the most significant bits. For example,
* address 0x305 should be provided as 0x7b05(bitwise OR with 0x7800).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_GetSlaveAddress()\n\n
*/
void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address);
/**
* @param channel Constant pointer to USIC channel handler of type @ref XMC_USIC_CH_t
* @return uint16_t Slave address<br>
*
* \par<b>Description:</b><br>
* Gets the I2C \a channel slave address.<br>
*
* \par
* Returns the address using PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.<br>
* (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)\n
* @note A 7-bit address will include an additional bit at the LSB. For example, address 0x05 will be returned as 0x0a.
* 10-bit address will not include the 10-bit address identifier 0b11110xx at the most signifcant bits.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_SetSlaveAddress()\n\n
*/
uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param addr I2C master address
* @param command read/write command
* @return None<br>
*
* \par<b>Description:</b><br>
* Starts the I2C master \a channel.<br>
*
* \par
* Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
* @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
* For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
* followed by 1-bit field for read/write).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param addr I2C master address
* @param command read/write command
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the repeated start condition from I2C master \a channel.<br>
*
* \par
* Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
* @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
* For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
* followed by 1-bit field for read/write).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Stops the I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Stop command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param data data to transmit from I2C \a channel
* @return None<br>
*
* \par<b>Description:</b><br>
* Transmit the data from the I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Send command.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param data data to transmit from I2C \a channel
* @return None<br>
*
* \par<b>Description:</b><br>
* Transmit the data from the I2C slave \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Slave Send command.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_GetTransmitBufferStatus(),XMC_I2C_CH_ClearStatusFlag()\n\n
*/
void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the Ack request from I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Ack command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the Nack request from I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Nack command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint8_t OUTR/RBUF register data<br>
*
* \par<b>Description:</b><br>
* Reads the data from I2C \a channel.<br>
*
* \par
* Data is read by using OUTR/RBUF register based on FIFO/non-FIFO modes.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint8_t Receiver status flag<br>
*
* \par<b>Description:</b><br>
* Gets the receiver status of I2C \a channel using RBUF register of bits 8-12 which gives information about receiver status.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
__STATIC_INLINE uint8_t XMC_I2C_CH_GetReceiverStatusFlag(XMC_USIC_CH_t *const channel)
{
return((uint8_t)((channel->RBUF) >> 8U));
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum
* @return None<br>
*
* \par<b>Description:</b><br>
* Enables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_DisableEvent()\n\n
*/
void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, uint32_t event);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum
* @return None<br>
*
* \par<b>Description:</b><br>
* Disables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableEvent()\n\n
*/
void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, uint32_t event);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint32_t Status byte<br>
*
* \par<b>Description:</b><br>
* Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_ClearStatusFlag()\n\n
*/
__STATIC_INLINE uint32_t XMC_I2C_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return (channel->PSR_IICMode);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param flag Status flag
* @return None<br>
*
* \par<b>Description:</b><br>
* Clears the status flag of I2C \a channel by setting the input parameter \a flag in PSCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_GetStatusFlag()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, uint32_t flag)
{
channel->PSCR |= flag;
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n
* @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n
* This can be related to the number of samples for each logic state of the data signal. \n
* \b Range: 1 to 32. Value should be chosen based on the protocol used.
* @param combination_mode USIC channel input combination mode \n
*
* @return None
*
* \par<b>Description</b><br>
* Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and
* the combination mode of the USIC channel. \n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
const uint16_t pdiv,
const uint32_t oversampling,
const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
{
XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,oversampling,combination_mode);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None
*
* \par<b>Description:</b><br>
* Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_DisableAcknowledgeAddress0()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_EnableAcknowledgeAddress0(XMC_USIC_CH_t *const channel)
{
channel->PCR_IICMode |= USIC_CH_PCR_IICMode_ACK00_Msk;
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None
*
* \par<b>Description:</b><br>
* This bit defines that slave device should not be sensitive to the slave address 00H.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableAcknowledgeAddress0()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_DisableAcknowledgeAddress0(XMC_USIC_CH_t *const channel)
{
channel->PCR_IICMode &= ~USIC_CH_PCR_IICMode_ACK00_Msk;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_I2C_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_I2C_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_i2s.h
* @date 2016-06-30
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-08-21:
* - Initial <br>
*
* 2015-08-24:
* - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and
* XMC_I2S_CH_EnableDelayCompensation() <br>
*
* 2015-09-01:
* - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() <br>
* for supporting multiple events configuration <br>
*
* 2015-09-14:
* - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length<br>
*
* 2016-05-20:
* - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission()
*
* 2016-06-30:
* - Documentation updates.
*
* @endcond
*
*/
#ifndef XMC_I2S_H_
#define XMC_I2S_H_
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup I2S
* @brief (IIS) driver for the XMC microcontroller family.
*
* USIC IIS Features: <br>
* @{
*/
/*******************************************************************************
* MACROS
*******************************************************************************/
#if defined(USIC0)
#define XMC_I2S0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_I2S0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_I2S1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_I2S1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_I2S2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_I2S2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* @brief I2S Status
*/
typedef enum XMC_I2S_CH_STATUS
{
XMC_I2S_CH_STATUS_OK, /**< Status OK */
XMC_I2S_CH_STATUS_ERROR, /**< Status ERROR */
XMC_I2S_CH_STATUS_BUSY /**< Status BUSY */
} XMC_I2S_CH_STATUS_t;
/**
* @brief I2S status flag
*/
typedef enum XMC_I2S_CH_STATUS_FLAG
{
XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS = USIC_CH_PSR_IISMode_WA_Msk, /**< Word Address status */
XMC_I2S_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_IISMode_DX2S_Msk, /**< Status of WA input(DX2) signal*/
XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_IISMode_DX2TEV_Msk, /**< Status for WA input signal transition */
XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT = USIC_CH_PSR_IISMode_WAFE_Msk, /**< Falling edge of the WA output
signal has been generated */
XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT = USIC_CH_PSR_IISMode_WARE_Msk, /**< Rising edge of the WA output
signal has been generated */
XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END = USIC_CH_PSR_IISMode_END_Msk, /**< The WA generation has ended */
XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IISMode_RSIF_Msk, /**< Receive start indication status */
XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IISMode_DLIF_Msk, /**< Data lost indication status */
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IISMode_TSIF_Msk, /**< Transmit shift indication status */
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IISMode_TBIF_Msk, /**< Transmit buffer indication status */
XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_RIF_Msk, /**< Receive indication status */
XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_AIF_Msk, /**< Alternate receive indication status */
XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IISMode_BRGIF_Msk /**< Baud rate generator indication status */
} XMC_I2S_CH_STATUS_FLAG_t;
/**
* @brief I2S Baudrate Generator shift clock output
*/
typedef enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT
{
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/
} XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
/**
* @brief I2S channel interrupt node pointers
*/
typedef enum XMC_I2S_CH_INTERRUPT_NODE_POINTER
{
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_I2S_CH_INTERRUPT_NODE_POINTER_t;
/**
* @brief I2S events
*/
typedef enum XMC_I2S_CH_EVENT
{
XMC_I2S_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_I2S_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_I2S_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_I2S_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_I2S_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_I2S_CH_EVENT_WA_FALLING_EDGE = USIC_CH_PCR_IISMode_WAFEIEN_Msk << 2U, /**< WA falling edge event */
XMC_I2S_CH_EVENT_WA_RISING_EDGE = USIC_CH_PCR_IISMode_WAREIEN_Msk << 2U, /**< WA rising edge event */
XMC_I2S_CH_EVENT_WA_GENERATION_END = USIC_CH_PCR_IISMode_ENDIEN_Msk << 2U, /**< END event */
XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_IISMode_DX2TIEN_Msk << 2U /**< WA input signal transition event*/
} XMC_I2S_CH_EVENT_t;
/**
* @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
*/
typedef enum XMC_I2S_CH_WA_POLARITY
{
XMC_I2S_CH_WA_POLARITY_DIRECT = 0x0UL, /**< The SELO outputs have the same polarity
as the WA signal (active high) */
XMC_I2S_CH_WA_POLARITY_INVERTED = 0x1UL << USIC_CH_PCR_IISMode_SELINV_Pos /**< The SELO outputs have the inverted
polarity to the WA signal (active low)*/
} XMC_I2S_CH_WA_POLARITY_t;
/**
* @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
*/
typedef enum XMC_I2S_CH_CHANNEL
{
XMC_I2S_CH_CHANNEL_1_LEFT = 0U, /**< Channel 1 (left) */
XMC_I2S_CH_CHANNEL_2_RIGHT = 1U /**< Channel 2 (right) */
} XMC_I2S_CH_CHANNEL_t;
/**
* @brief I2S input stage selection
*/
typedef enum XMC_I2S_CH_INPUT
{
XMC_I2S_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */
XMC_I2S_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */
XMC_I2S_CH_INPUT_SLAVE_WA = 2UL, /**< WA input stage */
#if UC_FAMILY == XMC1
XMC_I2S_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */
XMC_I2S_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */
XMC_I2S_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */
#endif
} XMC_I2S_CH_INPUT_t;
/**
* @brief Defines the I2S bus mode
*/
typedef enum XMC_I2S_CH_BUS_MODE
{
XMC_I2S_CH_BUS_MODE_MASTER, /**< I2S Master */
XMC_I2S_CH_BUS_MODE_SLAVE /**< I2S Slave */
} XMC_I2S_CH_BUS_MODE_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* @brief I2S_CH configuration structure
*/
typedef struct XMC_I2S_CH_CONFIG
{
uint32_t baudrate; /**< Module baud rate for communication */
uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n
Value configured as USIC channel word length. \n
\b Range: minimum= 1, maximum= 16*/
uint8_t frame_length; /**< Number of data bits transferred after a change of signal WA (data frame). \n
Configured as USIC channel frame length. \n
\b Range: minimum= 1, maximum= 63*/
uint8_t data_delayed_sclk_periods; /**< Data delay defined in sclk periods */
XMC_I2S_CH_WA_POLARITY_t wa_inversion; /**< Enable inversion of Slave select signal relative to the internal WA */
XMC_I2S_CH_BUS_MODE_t bus_mode; /**< Bus mode MASTER/SLAVE */
} XMC_I2S_CH_CONFIG_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t.
* @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n
* \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n
* @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed.
*
* \par<b>Description</b><br>
* Initializes the USIC channel for I2S protocol.\n\n
* During the initialization, USIC channel is enabled and baudrate is configured.
* After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length).
* The number of data bits transferred after a change of signal WA is defined by config->frame_length.
* A data frame can consist of several data words with a data word length defined by config->data_bits.
* The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA.
* The system word length is set by default to the frame length defined by config->frame_length.
*
* XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n
*/
void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.\n\n
* It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set
* to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
*/
__STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel)
{
/* USIC channel in I2S mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed. \n
* XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n
* XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.
*
* \par<b>Description:</b><br>
* Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.\n\n
* After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be
* invoked to start the communication again.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Start()
*/
XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param rate Bus speed in bits per second
*
* @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n
* XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n
* XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range.
*
* \par<b>Description:</b><br>
* Sets the bus speed in bits per second
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
*/
XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the system word length by setting BRG.DCTQ bit field.\n\n
* This value has to be always higher than 1U and lower than the data with (SCTR.FLE)
*
*/
void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param data Data to be transmitted
* @param channel_number Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated.\n
* Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n
* TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto
* update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes.
*
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Receive()
*/
void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param channel_number Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated.\n
* Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n
* XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data
* XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_GetReceivedData()
*/
__STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number)
{
/* Transmit dummy data */
XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return uint16_t Data read from the receive buffer.
*
* \par<b>Description:</b><br>
* Reads data from the receive buffer based on the FIFO selection.\n\n
* Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data
* XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Receive()
*/
uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n
* This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in
* the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetBitOrderMsbFirst()
*/
__STATIC_INLINE void XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel)
{
channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n
* This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init().
* Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetBitOrderLsbFirst()
*/
__STATIC_INLINE void XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel)
{
channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param event Protocol events which have to be enabled.
* Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum items can be used
* as input.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the I2S protocol specific events, by configuring PCR register.\n\n
* Events can be enabled as needed using XMC_I2S_CH_EnableEvent().
* XMC_I2S_CH_DisableEvent() can be used to disable the events.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableEvent()
*/
void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param event Protocol events which have to be disabled.
* Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum item can be used
* as input.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the I2S protocol specific events, by configuring PCR register.\n\n
* After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableEvent()
*/
void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return uint32_t Status of I2S protocol events.
*
* \par<b>Description:</b><br>
* Returns the status of the events, by reading PSR register.\n\n
* This indicates the status of the all the events, for I2S communication.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_ClearStatusFlag()
*/
__STATIC_INLINE uint32_t XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return channel->PSR_IISMode;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param flag Protocol event status to be cleared for detection of next occurence.
* Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. <b>OR</b> combinations of these enum item can be used
* as input.
* @return None
*
* \par<b>Description:</b><br>
* Clears the events specified, by setting PSCR register.\n\n
* During communication the events occurred have to be cleared to detect their next occurence.\n
* e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This
* event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_GetStatusFlag()
*/
__STATIC_INLINE void XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
{
channel->PSCR |= flag;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the generation of Master clock by setting PCR.MCLK bit.\n\n
* This clock can be used as a clock reference for external devices. This is not enabled during initialization in
* XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by
* XMC_I2S_CH_DisableMasterClock().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableMasterClock()
*/
__STATIC_INLINE void XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
{
channel->PCR_IISMode |= (uint32_t)USIC_CH_PCR_IISMode_MCLK_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n
* This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableMasterClock()
*/
__STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
{
channel->PCR_IISMode &= (uint32_t)~USIC_CH_PCR_IISMode_MCLK_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param clock_output shift clock source.\n
* Refer @ref XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the shift clock source by setting BRG.SCLKOSEL.\n\n
* In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available
* for external slave devices by SCLKOUT signal.\n
* In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n
*/
__STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)
{
XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U,
(XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param word_length Number of bits to be configured for a data word. \n
* \b Range: 1 to 16.
*
* @return None
*
* \par<b>Description</b><br>
* Defines the data word length.\n\n
* Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetFrameLength()
*/
__STATIC_INLINE void XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
{
XMC_USIC_CH_SetWordLength(channel, word_length);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param frame_length Number of bits in a frame. \n
* \b Range: 1 to 64.
*
* @return None
*
* \par<b>Description</b><br>
* Define the data frame length.\n\n
* Set the number of bits to be serially transmitted in a frame.
* The frame length should be multiples of word length.
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_SetWordLength()
*/
__STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
{
XMC_USIC_CH_SetFrameLength(channel, frame_length);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid values
* @param source Input source select for the input stage.
* Range : [0 to 7]
*
* @return None
*
* \par<b>Description</b><br>
* Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.\n\n
* Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the
* input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting
* the I2S communication.
*/
__STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input,
const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk;
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param wa_inversion Polarity of the word address signal.\n
* Refer @ref XMC_I2S_CH_WA_POLARITY_t for valid values
*
* @return None
*
* \par<b>Description</b><br>
* Set the polarity of the word address signal, by configuring PCR.SELINV bit.\n\n
* Normally WA signal is active low level signal. This is configured
* in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as
* needed later in the program.
*/
__STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_WA_POLARITY_t wa_inversion)
{
/* Configuration of Protocol Control Register */
channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n
* This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To
* disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableInputInversion()
*/
__STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description</b><br>
* Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n
* Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableInputInversion()
*/
__STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param service_request Service request number.
Range: [0 to 5]
*
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for I2S channel events.\n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during
* initialization.
*
* \par<b>Note::</b><BR>
* 1. NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_EnableEvent()
*/
__STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a I2S interrupt service request.\n\n
* When the I2S service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enables delay compensation. \n\n
*
* Delay compensation can be applied to the receive path.
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableDelayCompensation()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_EnableDelayCompensation(channel);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disables delay compensation.. \n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableDelayCompensation()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_DisableDelayCompensation(channel);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_I2S_H_ */

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/**
* @file xmc_pau.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial version
*
* 2015-05-20:
* - Documentation updated
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* @endcond
*
*/
#ifndef XMC_PAU_H
#define XMC_PAU_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if defined(PAU)
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup PAU
* @brief Peripheral Access Unit (PAU) driver for the XMC1000 microcontroller family
*
* The Peripheral Access Unit (PAU) supports access control of memories and peripherals.
* It allows user application to enable/disable the access to the registers of a peripheral.
* It generates a HardFault exception when there is an access to a disabled or unassigned
* address location. It also provides information on the availability of peripherals and
* sizes of memories.
*
* The PAU low level driver provides functions to check the availability of peripherals
* and to enable/disable peripheral access.
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/**
* A convenient symbol for the PAU peripheral base address
*/
#define XMC_PAU ((XMC_PAU_t *) PAU_BASE)
/*
* This macro is used in the LLD for assertion checks (XMC_ASSERT)
*/
#define XMC_PAU_CHECK_MODULE_PTR(p) ((p) == XMC_PAU)
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Status return values for PAU low level driver
*/
typedef enum XMC_PAU_STATUS
{
XMC_PAU_STATUS_OK = 0U, /**< Operation successful */
XMC_PAU_STATUS_BUSY = 1U, /**< Busy with a previous request */
XMC_PAU_STATUS_ERROR = 2U /**< Operation unsuccessful */
} XMC_PAU_STATUS_t;
/**
* PAU peripheral select
*/
typedef enum XMC_PAU_PERIPHERAL
{
XMC_PAU_PERIPHERAL_FLASH = PAU_PRIVDIS0_PDIS2_Msk, /**< Flash SFRs Privilege Disable Flag */
XMC_PAU_PERIPHERAL_RAM_BLOCK1 = PAU_PRIVDIS0_PDIS5_Msk, /**< RAM Block 1 Privilege Disable Flag */
XMC_PAU_PERIPHERAL_RAM_BLOCK2 = PAU_PRIVDIS0_PDIS6_Msk, /**< RAM Block 2 Privilege Disable Flag */
XMC_PAU_PERIPHERAL_RAM_BLOCK3 = PAU_PRIVDIS0_PDIS7_Msk, /**< RAM Block 3 Privilege Disable Flag */
#if defined(WDT)
XMC_PAU_PERIPHERAL_WDT = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */
#endif
#if defined(MATH)
XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */
#endif
#if defined(MATH)
XMC_PAU_PERIPHERAL_MATH_CORDIC = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag */
#endif
#if defined(PORT0)
XMC_PAU_PERIPHERAL_PORT0 = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */
#endif
#if defined(PORT1)
XMC_PAU_PERIPHERAL_PORT1 = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */
#endif
#if defined(PORT2)
XMC_PAU_PERIPHERAL_PORT2 = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */
#endif
#if defined(PORT3)
XMC_PAU_PERIPHERAL_PORT3 = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */
#endif
#if defined(PORT4)
XMC_PAU_PERIPHERAL_PORT4 = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */
#endif
#if defined(USIC0)
XMC_PAU_PERIPHERAL_USIC0_CH0 = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */
XMC_PAU_PERIPHERAL_USIC0_CH1 = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */
#endif
#if defined(USIC1)
XMC_PAU_PERIPHERAL_USIC1_CH0 = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */
XMC_PAU_PERIPHERAL_USIC1_CH1 = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */
#endif
#if defined(PRNG)
XMC_PAU_PERIPHERAL_PRNG = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/
#endif
#if defined(VADC)
XMC_PAU_PERIPHERAL_VADC_GLOBAL = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */
#if defined(VADC_G0)
XMC_PAU_PERIPHERAL_VADC_GROUP0 = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */
#endif
#if defined(VADC_G1)
XMC_PAU_PERIPHERAL_VADC_GROUP1 = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */
#endif
#endif
#if defined(SHS0)
XMC_PAU_PERIPHERAL_VADC_SHS0 = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */
#endif
#if defined(CCU40)
XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */
#if defined(CCU40_CC41)
XMC_PAU_PERIPHERAL_CCU40_CC41 = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */
#endif
#if defined(CCU40_CC42)
XMC_PAU_PERIPHERAL_CCU40_CC42 = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */
#endif
#if defined(CCU40_CC43)
XMC_PAU_PERIPHERAL_CCU40_CC43 = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */
#endif
#endif
#if defined(CCU41)
XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */
#if defined(CCU41_CC41)
XMC_PAU_PERIPHERAL_CCU41_CC41 = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */
#endif
#if defined(CCU41_CC42)
XMC_PAU_PERIPHERAL_CCU41_CC42 = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */
#endif
#if defined(CCU41_CC43)
XMC_PAU_PERIPHERAL_CCU41_CC43 = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */
#endif
#endif
#if defined(CCU80)
XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */
#if defined(CCU80_CC81)
XMC_PAU_PERIPHERAL_CCU80_CC81 = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */
#endif
#if defined(CCU80_CC82)
XMC_PAU_PERIPHERAL_CCU80_CC82 = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */
#endif
#if defined(CCU80_CC83)
XMC_PAU_PERIPHERAL_CCU80_CC83 = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */
#endif
#endif
#if defined(CCU81)
XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */
#if defined(CCU81_CC81)
XMC_PAU_PERIPHERAL_CCU81_CC81 = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */
#endif
#if defined(CCU81_CC82)
XMC_PAU_PERIPHERAL_CCU81_CC82 = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */
#endif
#if defined(CCU81_CC83)
XMC_PAU_PERIPHERAL_CCU81_CC83 = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */
#endif
#endif
#if defined(POSIF0)
XMC_PAU_PERIPHERAL_POSIF0 = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */
#endif
#if defined(POSIF1)
XMC_PAU_PERIPHERAL_POSIF1 = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */
#endif
#if defined(LEDTS0)
XMC_PAU_PERIPHERAL_LEDTS0 = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */
#endif
#if defined(LEDTS1)
XMC_PAU_PERIPHERAL_LEDTS1 = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */
#endif
#if defined(LEDTS2)
XMC_PAU_PERIPHERAL_LEDTS2 = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */
#endif
#if defined(BCCU0)
XMC_PAU_PERIPHERAL_BCCU0 = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */
#endif
#if defined(CAN)
#if defined(CAN_NODE0)
XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */
#endif
#if defined(CAN_NODE1)
XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */
#endif
XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */
#endif
} XMC_PAU_PERIPHERAL_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* External Peripheral Access Unit (PAU) device structure <br>
*
* The structure represents a collection of all hardware registers
* used to configure the PAU peripheral on the XMC microcontroller.
* The registers can be accessed with ::XMC_PAU.
*/
typedef struct
{
__I uint32_t RESERVED0[16];
__I uint32_t AVAIL[3];
__I uint32_t RESERVED1[13];
__IO uint32_t PRIVDIS[3];
__I uint32_t RESERVED2[221];
__I uint32_t ROMSIZE;
__I uint32_t FLSIZE;
__I uint32_t RESERVED3[2];
__I uint32_t RAM0SIZE;
} XMC_PAU_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be enabled
* @return None
*
* \par<b>Description: </b><br>
* Enable the peripheral access <br>
*
* \par
* The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral
* during run time.
*
* \par<b>Related APIs:</b><br>
* XMC_PAU_DisablePeripheralAccess()
*/
void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
/**
* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
* @return None
*
* \par<b>Description: </b><br>
* Disable the peripheral access <br>
*
* \par
* The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral
* during run time. An access to a disabled or unassigned address location generates a hardfault
* exception.
*
* \par<b>Related APIs:</b><br>
* XMC_PAU_EnablePeripheralAccess()
*/
void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
/**
* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access enabled status to be checked
* @return bool "false" if peripheral access is enabled, "true" otherwise
*
* \par<b>Description: </b><br>
* Checks if the peripheral access is enabled or not <br>
*
* \par
* The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral
* during run time is enabled or not.
*
* \par<b>Related APIs:</b><br>
* XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess()
*/
bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral);
/**
* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
* @return bool Returns "true" if peripheral is available, "false" otherwise
*
* \par<b>Description: </b><br>
* Checks if a peripheral is available or not <br>
*
* \par
* The function checks the AVAILx.AVAILy bit to know whether the peripheral
* is available or not for the particular device variant.
*/
bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral);
/**
* @return uint32_t Returns ROM size
*
* \par<b>Description: </b><br>
* Gets the ROM size <br>
*
* \par
* The function checks the ROMSIZE.ADDR bitfield to indicate the available size of ROM in the device in bytes.
*/
__STATIC_INLINE uint32_t XMC_PAU_GetROMSize(void)
{
return (uint32_t)(((XMC_PAU->ROMSIZE & PAU_ROMSIZE_ADDR_Msk) >> PAU_ROMSIZE_ADDR_Pos) * 256U);
}
/**
* @return uint32_t Returns flash size
*
* \par<b>Description: </b><br>
* Gets the flash size <br>
*
* \par
* The function checks the FLSIZE.ADDR bitfield to indicate the available size of FLASH in the device in Kbytes.
*/
__STATIC_INLINE uint32_t XMC_PAU_GetFlashSize(void)
{
return (uint32_t)((((XMC_PAU->FLSIZE & PAU_FLSIZE_ADDR_Msk) >> PAU_FLSIZE_ADDR_Pos) - 1U) * 4U);
}
/**
* @return uint32_t Returns RAM size
*
* \par<b>Description: </b><br>
* Gets RAM size <br>
*
* \par
* The function checks the RAM0SIZE.ADDR bitfield to indicate the available size of RAM in the device in bytes.
*/
__STATIC_INLINE uint32_t XMC_PAU_GetRAMSize(void)
{
return (uint32_t)(((XMC_PAU->RAM0SIZE & PAU_RAM0SIZE_ADDR_Msk) >> PAU_RAM0SIZE_ADDR_Pos) * 256U);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PAU) */
#endif /* XMC_PAU_H */

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/**
* @file xmc_prng.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* @endcond
*/
#ifndef XMC_PRNG_H
#define XMC_PRNG_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if defined (PRNG)
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup PRNG
* @brief Pseudo Random Number Generator (PRNG) driver for XMC1000 microcontroller family
*
* The pseudo random bit generator (PRNG) provides random data with fast generation times.
* PRNG has to be initialized by the user software before use. The initialization consists
* of two basic phases: key-loading and warm-up.
*
* The PRNG low level driver provides functions to configure and initialize the PRNG hardware
* peripheral.
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/**
* Byte mask value for random data block size
*/
#define XMC_PRNG_RDBS_BYTE_READ_MASK (0x00FFU)
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* PRNG key load operation modes
*/
typedef enum XMC_PRNG_KEY_LOAD_OP_MODE {
XMC_PRNG_STRM_MODE = 0U, /**< Streaming mode (default) */
XMC_PRNG_KLD_MODE = 1U /**< Loading mode */
} XMC_PRNG_KEY_LOAD_OP_MODE_t;
/**
* PRNG data block size
*/
typedef enum XMC_PRNG_DATA_BLOCK_SIZE {
XMC_PRNG_RDBS_RESET = 0U, /**< Reset state (no random data block size defined) */
XMC_PRNG_RDBS_BYTE = 1U, /**< BYTE (8-bit) */
XMC_PRNG_RDBS_WORD = 2U /**< WORD (16-bit) */
} XMC_PRNG_DATA_BLOCK_SIZE_t;
/**
* PRNG driver initialization status
*/
typedef enum XMC_PRNG_INIT_STATUS {
XMC_PRNG_NOT_INITIALIZED = 0U, /**< Reset state or Non-initialized state (Same as XMC_PRNG_RDBS_RESET) */
XMC_PRNG_INITIALIZED = 1U /**< Initialized state */
} XMC_PRNG_INIT_STATUS_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* Key words and data block size configuration values of PRNG <br>
*
* The structure presents a convenient way to set/obtain the key word and data block configuration
* values of PRNG.
* The XMC_PRNG_Init() can be used to populate the structure with the key word and data block
* configuration values of the PRNG module.
*/
typedef struct XMC_PRNG_INIT
{
uint16_t key_words[5]; /**< Keywords */
XMC_PRNG_DATA_BLOCK_SIZE_t block_size; /**< Block size */
} XMC_PRNG_INIT_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param prng Pointer to a constant instance of ::XMC_PRNG_INIT_t, pointing to
* the initialization configuration.
* @return XMC_PRNG_INIT_STATUS_t XMC_PRNG_INITIALIZED if initialized,
* XMC_PRNG_NOT_INITIALIZED otherwise.
*
* \par<b>Description: </b><br>
* Initialize the PRNG peripheral with the configured key words and block size <br>
*
* \par
* The function configures block size for key loading mode, enables key loading mode,
* loads key words (80 bits) and wait till RDV is set, enables the streaming mode and
* waits for warmup phase. This function programmes the CTRL and WORD registers.
*/
XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng);
/**
* @param block_size Block size of type ::XMC_PRNG_DATA_BLOCK_SIZE_t for read access
* @return None
*
* \par<b>Description: </b><br>
* Programming Random Block Size <br>
*
* \par
* The function sets the random data block size as byte or word by programming CTRL.RDBS bitfield.
* block_size = 0 for Reset state, block_size = 1 for 'byte' and block_size = 2 for 'word'.
*/
__STATIC_INLINE void XMC_PRNG_SetRandomDataBlockSize(XMC_PRNG_DATA_BLOCK_SIZE_t block_size)
{
PRNG->CTRL = (uint16_t)((PRNG->CTRL & (uint32_t)~PRNG_CTRL_RDBS_Msk) |
((uint32_t)block_size << (uint32_t)PRNG_CTRL_RDBS_Pos));
}
/**
* @return None
*
* \par<b>Description: </b><br>
* Checks the validity (CHK.RDV bit) of the generated random data <br>
*
* \par
* The function checks the validity (CHK.RDV bit) of the generated random data.
* In key loading mode, this value indicates if the next partial key word can be written
* to PRNG_WORD or not.
*/
__STATIC_INLINE uint16_t XMC_PRNG_CheckValidStatus(void)
{
return (PRNG->CHK & PRNG_CHK_RDV_Msk);
}
/**
* @return None
*
* \par<b>Description: </b><br>
* Enables the PRNG key loading mode <br>
*
* \par
* The function initializes the key loading by setting the bit CTRL.KLD. In this mode, Register WORD
* acts as always as a 16 bit destination register. After the complete key has been loaded, the CTRL.KLD
* must be set to '0' to prepare the following warmup phase.
*
* \par<b>Related APIs:</b><br>
* XMC_PRNG_EnableStreamingMode()
*/
__STATIC_INLINE void XMC_PRNG_EnableKeyLoadingMode(void)
{
PRNG->CTRL |= (uint16_t)PRNG_CTRL_KLD_Msk;
}
/**
* @return None
*
* \par<b>Description: </b><br>
* Enables the Streaming mode <br>
*
* \par
* The function enables the streaming mode and disables the PRNG key loading mode by resetting the
* CTRL.KLD bit.
*
* \par<b>Related APIs:</b><br>
* XMC_PRNG_EnableKeyLoadingMode()
*/
__STATIC_INLINE void XMC_PRNG_EnableStreamingMode(void)
{
PRNG->CTRL &= (uint16_t)~PRNG_CTRL_KLD_Msk;
}
/**
* @param key Key word to load into PRNG WORD register
* @return None
*
* \par<b>Description: </b><br>
* Loads a partial key word to the PRNG WORD register <br>
*
* \par
* The function loads partial key word to WORD registr. These partial
* words are sequentially written and loading a key word will take 16 clock
* cycles. The CHK.RDV bit is set to '0' while loading is in progress. '1' indicates
* that the next partial key word can be written to WORD register.
*/
__STATIC_INLINE void XMC_PRNG_LoadKeyWords(uint16_t key)
{
PRNG->WORD = key;
}
/**
* @param None
* @return uint16_t Generated random number
*
* \par<b>Description: </b><br>
* Gets the generated random number <br>
*
* \par
* The function gives the generated random number by returning the content of WORD
* register. Before reading the WORD register to get the generated random number it is
* required to check the bit CHK.RDV is set which indicates that the next random data block
* can be read from WORD register. After a word has been read the bit CHK.RDV is reset
* by the hardware and generation of new random bits starts.
*
* \par<b>Related APIs:</b><br>
* XMC_PRNG_CheckValidStatus()
*/
__STATIC_INLINE uint16_t XMC_PRNG_GetPseudoRandomNumber(void)
{
return PRNG->WORD;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* #if defined (PRNG) */
#endif /* XMC_PRNG_H */

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/**
* @file xmc_rtc.h
* @date 2016-05-19
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Documentation updates <br>
* - In xmc1_rtc file XMC_RTC_Init function
* is modified by adding the RTC running condition check
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2016-05-19:
* - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
*
* @endcond
*
*/
#ifndef XMC_RTC_H
#define XMC_RTC_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_common.h>
#include <time.h>
/**
*
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup RTC
* @brief RTC driver for XMC microcontroller family.
*
* Real-time clock (RTC) is a clock that keeps track of the current time. Precise
* real time keeping is with a 32.768 KHz external crystal clock or a 32.768 KHz
* high precision internal clock. It provides a periodic time based interrupt and
* a programmable alarm interrupt on time match. It also supports wakeup from
* hibernate.
*
* The RTC low level driver provides functions to configure and initialize the RTC
* hardware peripheral.
*
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Status return values for RTC low level driver
*/
typedef enum XMC_RTC_STATUS
{
XMC_RTC_STATUS_OK = 0U, /**< Operation successful */
XMC_RTC_STATUS_ERROR = 1U, /**< Operation unsuccessful */
XMC_RTC_STATUS_BUSY = 2U /**< Busy with a previous request */
} XMC_RTC_STATUS_t;
/**
* Events which enables interrupt request generation
*/
typedef enum XMC_RTC_EVENT
{
XMC_RTC_EVENT_PERIODIC_SECONDS = RTC_MSKSR_MPSE_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an event on periodic seconds */
} XMC_RTC_EVENT_t;
/**
* Months used to program the date
*/
typedef enum XMC_RTC_MONTH
{
XMC_RTC_MONTH_JANUARY = 0U,
XMC_RTC_MONTH_FEBRUARY = 1U,
XMC_RTC_MONTH_MARCH = 2U,
XMC_RTC_MONTH_APRIL = 3U,
XMC_RTC_MONTH_MAY = 4U,
XMC_RTC_MONTH_JUNE = 5U,
XMC_RTC_MONTH_JULY = 6U,
XMC_RTC_MONTH_AUGUST = 7U,
XMC_RTC_MONTH_SEPTEMBER = 8U,
XMC_RTC_MONTH_OCTOBER = 9U,
XMC_RTC_MONTH_NOVEMBER = 10U,
XMC_RTC_MONTH_DECEMBER = 11U
} XMC_RTC_MONTH_t;
/**
* Week days used program the date
*/
typedef enum XMC_RTC_WEEKDAY
{
XMC_RTC_WEEKDAY_SUNDAY = 0U,
XMC_RTC_WEEKDAY_MONDAY = 1U,
XMC_RTC_WEEKDAY_TUESDAY = 2U,
XMC_RTC_WEEKDAY_WEDNESDAY = 3U,
XMC_RTC_WEEKDAY_THURSDAY = 4U,
XMC_RTC_WEEKDAY_FRIDAY = 5U,
XMC_RTC_WEEKDAY_SATURDAY = 6U
} XMC_RTC_WEEKDAY_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/*Anonymous structure/union guard start*/
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* Alarm time values of RTC <br>
*
* The structure presents a convenient way to set/obtain the
* alarm time values for seconds, minutes, hours, days, month and year of RTC.
* The XMC_RTC_SetAlarm() and XMC_RTC_GetAlarm() can be
* used to populate the structure with the alarm time value of
* RTC
*/
typedef struct XMC_RTC_ALARM
{
union
{
uint32_t raw0;
struct
{
uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/
uint32_t : 2;
uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/
uint32_t : 2;
uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
};
};
union
{
uint32_t raw1;
struct
{
uint32_t : 8;
uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */
uint32_t : 4;
uint32_t year : 16; /**< Alarm year compare value */
};
};
} XMC_RTC_ALARM_t;
/**
* Time values of RTC <br>
*
* The structure presents a convenient way to set/obtain the
* time values for seconds, minutes, hours, days, month and year of RTC.
* The XMC_RTC_SetTime() and XMC_RTC_GetTime() can be
* used to populate the structure with the time value of
* RTC
*/
typedef struct XMC_RTC_TIME
{
union
{
uint32_t raw0;
struct
{
uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */
uint32_t : 2;
uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */
uint32_t : 2;
uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */
uint32_t : 3;
uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
};
};
union
{
uint32_t raw1;
struct
{
uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */
uint32_t : 5;
uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */
uint32_t : 4;
uint32_t year : 16; /**< Year time value */
};
};
} XMC_RTC_TIME_t;
/*Anonymous structure/union guard end*/
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/**
* RTC initialization with time, alarm and clock divider(prescaler) configurations <br>
*
* The structure presents a convenient way to set/obtain the time and alarm configurations
* for RTC. The XMC_RTC_Init() can be used to populate the structure with the time and alarm
* values of RTC.
*/
typedef struct XMC_RTC_CONFIG
{
XMC_RTC_TIME_t time;
XMC_RTC_ALARM_t alarm;
uint16_t prescaler;
} XMC_RTC_CONFIG_t;
/*******************************************************************************
* EXTENSIONS
*******************************************************************************/
#if UC_FAMILY == XMC1
#include "xmc1_rtc.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_rtc.h"
#endif
/*******************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param config Constant pointer to a constant ::XMC_RTC_CONFIG_t structure containing the
* time, alarm time and clock divider(prescaler) configuration.
* @return XMC_RTC_STATUS_t Always returns XMC_RTC_STATUS_OK (It contains only register assignment statements)
*
* \par<b>Description: </b><br>
* Initialize the RTC peripheral <br>
*
* \par \if XMC4
* The function enables the hibernate domain for accessing RTC peripheral registers, configures
* internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and
* ATIM1 registers.
* \endif
*
* \if XMC1
* The function ungates the peripheral clock for RTC, configures
* internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and
* ATIM1 registers.
* \endif
*/
XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config);
/**
* @return None
*
* \par<b>Description</b><br>
* Enables RTC peripheral for programming its registers <br>
*
* \par \if XMC4
* Enables the hibernate domain for accessing RTC peripheral registers.
* \endif
*
* \if XMC1
* Ungates the peripheral clock.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset()
*/
void XMC_RTC_Enable(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Disables RTC peripheral for programming its registers <br>
*
* \par \if XMC4
* Empty function (Hibernate domain is not disabled).
* \endif
*
* \if XMC1
* Gates the peripheral clock.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_SCU_RESET_AssertPeripheralReset()
*/
void XMC_RTC_Disable(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Checks RTC peripheral is enabled for programming its registers <br>
*
* \par \if XMC4
* Checks the hibernate domain is enabled or not.
* \endif
*
* \if XMC1
* Checks peripheral clock is ungated or not.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset(),
* XMC_SCU_RESET_AssertPeripheralReset()
*/
bool XMC_RTC_IsEnabled(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Enables RTC peripheral to start counting time <br>
*
* \par
* The function starts the RTC for counting time by setting
* CTR.ENB bit. Before starting the RTC, it should not be in
* running mode and also hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Stop(), XMC_SCU_RESET_DeassertPeripheralReset()
*/
void XMC_RTC_Start(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Disables RTC peripheral to start counting time <br>
*
* \par
* The function stops the RTC for counting time by resetting
* CTR.ENB. Before stopping the RTC, hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Start(), XMC_SCU_RESET_AssertPeripheralReset()
*/
void XMC_RTC_Stop(void);
/**
* @param prescaler Prescaler value to be set
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module prescaler value <br>
*
* \par
* The function sets the CTR.DIV bitfield to configure the prescalar value.
* The default value for the prescalar with the 32.768kHz crystal (or the internal clock)
* is 7FFFH for a time interval of 1 sec. Before setting the prescaler value RTC should be
* in stop mode and hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Stop(), XMC_RTC_Enable(), XMC_RTC_GetPrescaler()
*/
void XMC_RTC_SetPrescaler(uint16_t prescaler);
/**
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module prescaler value <br>
*
* \par
* The function reads the CTR.DIV bitfield to get the prescalar value. The default value
* for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a
* time interval of 1 sec.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetPrescaler()
*/
__STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void)
{
return (uint32_t)(((uint32_t)RTC->CTR & (uint32_t)RTC_CTR_DIV_Msk) >> (uint32_t)RTC_CTR_DIV_Pos);
}
/**
* @param timeval Contstant pointer to a constant ::XMC_RTC_TIME_t structure containing the
* time parameters seconds, minutes, hours, days, daysofweek, month and year.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module time values <br>
*
* \par
* The function sets the TIM0, TIM1 registers with time values.
* The values can only be written when RTC is disabled.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetTime(), XMC_RTC_Stop()
*/
void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval);
/**
* @param time Pointer to a constant ::XMC_RTC_TIME_t structure containing the time parameters
* seconds, minutes, hours, days, daysofweek, month and year.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module time value <br>
*
* \par
* The function gets the time values from TIM0, TIM1 registers.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime()
*/
void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time);
/**
* @param stdtime Pointer to a ::tm structure containing the time parameters seconds,
* minutes, hours, days, daysofweek, month, year(since 1900) and days in a
* year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module time value in standard format <br>
*
* \par
* The function sets the time values from TIM0, TIM1 registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime(), XMC_RTC_GetTime()
*/
void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime);
/**
* @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds,
* minutes, hours, days, daysofweek, month, year(since 1900) and days in a
* year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module time value in standard format <br>
*
* \par
* The function gets the time values from TIM0, TIM1 registers.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
* For days the valid range is (1 - Actual days of month), year (since 1900) and
* daysinyear (0 -365).
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime(), XMC_RTC_GetTime()
*/
void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime);
/**
* @param alarm Constant pointer to a constant ::XMC_RTC_ALARM_t structure containing the
* alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days,
* alarm daysofweek, alarm month and alarm year.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module alarm time value <br>
*
* \par
* The function sets the ATIM0, ATIM1 registers with alarm time values.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetAlarm()
*/
void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm);
/**
* @param alarm Pointer to a constant ::XMC_RTC_ALARM_t structure containing the
* time parameters alarm seconds, alarm minutes, alarm hours, alarm days,
* alarm daysofweek, alarm month and alarm year.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module alarm time value <br>
*
* \par
* The function gets the alarm time values from ATIM0, ATIM1 registers.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm()
*/
void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm);
/**
* @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds,
* alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,
* alarm year(since 1900) and alarm days in a year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module alarm time value in standard format <br>
*
* \par
* The function sets the alarm time values from ATIM0, ATIM1 registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm()
*/
void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime);
/**
* @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds,
* alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,
* alarm year(since 1900) and alarm days in a year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module alarm time value in standard format <br>
*
* \par
* The function gets the alarm time values from ATIM0, ATIM1 registers.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
* For days the valid range is (1 - Actual days of month), year (since 1900) and
* daysinyear (0 -365).
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm()
*/
void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Enable RTC periodic and alarm event(s) <br>
*
* \par
* The function sets the bitfields of MSKSR register to enable interrupt generation
* for requested RTC event(s).
* Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads
* to a generation of the interrupt.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_DisableEvent()
*/
void XMC_RTC_EnableEvent(const uint32_t event);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Disable RTC periodic and alarm event(s) <br>
*
* \par
* The function resets the bitfields of MSKSR register to disable interrupt generation
* for requested RTC event(s).
* Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks
* the generation of the interrupt.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_EnableEvent()
*/
void XMC_RTC_DisableEvent(const uint32_t event);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Clears periodic and alarm event(s) status <br>
*
* \par
* The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers.
* Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the
* corresponding status bits in RAWSTAT and STSSR registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetEventStatus()
*/
void XMC_RTC_ClearEvent(const uint32_t event);
/**
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC periodic and alarm event(s) status <br>
*
* \par
* The function reads the bitfields of STSSR register
* to get the status of RTC events.
* Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_ClearEvent()
*/
uint32_t XMC_RTC_GetEventStatus(void);
/**
* @return bool true if RTC is running
* false if RTC is not running
*
* \par<b>Description: </b><br>
* Checks the running status of the RTC <br>
*
* \par
* The function reads the bitfield ENB of CTR register
* to get the running status of RTC.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Start(), XMC_RTC_Stop()
*/
__STATIC_INLINE bool XMC_RTC_IsRunning(void)
{
return (bool)(RTC->CTR & RTC_CTR_ENB_Msk);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_RTC_H */

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/**
* @file xmc_scu.h
* @date 2016-03-09
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Documentation improved <br>
* - XMC_ASSERT() hanging issues have fixed for XMC4 devices. <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* - Removed STATIC_INLINE property for the below APIs and declared as void
* XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,
* XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,
* XMC_SCU_INTERUPT_ClearEventStatus
*
* 2015-11-30:
* - Documentation improved <br>
*
* 2016-03-09:
* - Optimization of write only registers
*
* @endcond
*
*/
#ifndef XMC_SCU_H
#define XMC_SCU_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_common.h>
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup SCU
* @brief System Control Unit(SCU) driver for XMC microcontroller family.
*
* System control unit is the SoC power, reset and a clock manager with additional responsibility of
* providing system stability protection and other auxiliary functions.<br>
* SCU provides the following features,
* -# Power control
\if XMC4
* -# Hibernate control
\endif
* -# Reset control
* -# Clock control
* -# Miscellaneous control(boot mode, system interrupts etc.)<br><br>
*
* The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic
\if XMC4
* , hibernate control logic, trap control logic, parity control logic
\endif
* and miscellaneous control logic.<br>
*
* Clock driver features:
* -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init()
\if XMC4
* -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL
* -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource()
* -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()
* -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()
* -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()
* -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(),
XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()<br>
\endif
\if XMC1
* -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()
* -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()
\endif
*
* Reset driver features:
\if XMC4
* -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()
* -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest()
\endif
\if XMC1
* -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()
* -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest()
\endif <br>
*
* Interrupt driver features:
* -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(),
XMC_SCU_INTERRUPT_DisableEvent()
* -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()<br>
*
\if XMC4
* Hibernate driver features:
* -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()
* -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()
* -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()
* -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()<br>
*
* Trap driver features:
* -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()<br>
*
* Parity driver features:
* -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()
* -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration()
*
* Power driver features:
* -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb()
\endif
*
* Miscellaneous features:
* -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh()
\if XMC4
* -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()
* -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()
* -# Enables configuration of device boot mode XMC_SCU_SetBootMode()<br>
\endif
\if XMC1
* -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()
* -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()
* -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()<br>
\endif
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines the status of SCU API execution, used to verify the SCU related API calls.
*/
typedef enum XMC_SCU_STATUS
{
XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/
XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */
XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request because
another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy
processing another request. */
} XMC_SCU_STATUS_t;
/*********************************************************************************************************************
* DATA TYPES
********************************************************************************************************************/
/**
* Function pointer type used for registering callback functions on SCU event occurrence.
*/
typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);
/*********************************************************************************************************************
* DEVICE EXTENSIONS
********************************************************************************************************************/
#if (UC_FAMILY == XMC1)
#include <xmc1_scu.h>
#elif (UC_FAMILY == XMC4)
#include <xmc4_scu.h>
#else
#error "Unspecified chipset"
#endif
/*********************************************************************************************************************
* API Prototypes
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
* in the register CCUCON. <br>
* \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
* combined using \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\n
* Before executing this API, all the required CCU timers should configure external start.
* The edge of the start signal should be selected as active edge.
* The input signal for the CCU slice should be selected as SCU input.
* The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
* CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
* the timer using this API.<BR>
* \par<b>Related APIs:</b><BR>
* XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n
*/
__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger)
{
SCU_GENERAL->CCUCON |= (uint32_t)trigger;
}
/**
*
* @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
* in the register CCUCON. <br>
* \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
* combined using \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\n
* Before executing this API, all the required CCU timers should configure external start.
* The edge of the start signal should be selected as passive edge.
* The input signal for the CCU slice should be selected as SCU input.
* The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
* CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
* the timer using this API.<BR>
* \par<b>Related APIs:</b><BR>
* XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n
*/
__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger)
{
SCU_GENERAL->CCUCON &= (uint32_t)~trigger;
}
/**
*
* @param config Pointer to structure holding the clock prescaler values and divider values for
* configuring clock generators and clock tree.\n
* \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various
* parameters of clock setup.
*
* @return None
*
* \par<b>Description</b><br>
* Initializes clock generators and clock tree.\n\n
* \if XMC1
* Peripheral clock and system clock are configured based on the input configuration \a config.
* The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register.
* The values of FDIV and IDIV can be provided as part of input configuration.
* The PCLK divider determines the ratio of peripheral clock to the system clock.
* The source of RTC clock is set based on the input configuration.
* \a SystemCoreClock variable will be updated with the value of
* system clock frequency. Access to protected bit fields are handled internally.
* \endif
* \if XMC4
* Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies.
* Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock.
* Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency.
* The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration.
* The \a SystemCoreClock variable is set with the value of system clock frequency.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n
*/
void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);
/**
*
* @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the generation of interrupt for the input events.\n\n
* The events are enabled by setting the respective bit fields in the SRMSK register. \n
* Note: User should separately enable the NVIC node responsible for handling the SCU interrupt.
* The interrupt will be generated when the respective event occurs.
* \par<b>Related APIs:</b><BR>
* NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n
*/
void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Disables generation of interrupt on occurrence of the input event.\n\n
* The events are disabled by resetting the respective bit fields in the SRMSK register. \n
* \par<b>Related APIs:</b><BR>
* NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n
*/
void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Triggers the event as if the hardware raised it.\n\n
* Event will be triggered by setting the respective bitfield in the SRSET register.\n
* Note: User should enable the NVIC node that handles the respective event for interrupt generation.
* \par<b>Related APIs:</b><BR>
* NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n
*/
void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
* @return uint32_t Status of the SCU events.
*
* \par<b>Description</b><br>
* Provides the status of all SCU events.\n\n
* The status is read from the SRRAW register. To check the status of a particular
* event, the returned value should be masked with the bit mask of the event. The bitmask
* of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events'
* status can be checked by combining the bit masks using \a OR operation.
* After detecting the event, the event status should be cleared using software to detect the event again.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
*/
XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void);
/**
*
* @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Clears the event status bit in SRRAW register.\n\n
* The events are cleared by writing value 1 to their bit positions in the SRCLR register.
* The API can be used when polling method is used. After detecting the event, the event status
* should be cleared using software to detect the event again.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n
*/
void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @return uint32_t Status representing the reason for device reset.
*
* \par<b>Description</b><br>
* Provides the value representing the reason for device reset.\n\n
* The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the
* returned word is representative of a last reset cause. The returned value should be appropriately masked to check
* the cause of reset.
* The cause of the last reset gets automatically stored in
* the \a SCU_RSTSTAT register. The reset status shall be reset after each
* startup in order to ensure consistent source indication after the next reset.
* \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n
*/
__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void)
{
return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);
}
/**
* @return None
*
* \par<b>Description</b><br>
* Clears the reset reason bits in the reset status register. \n\n
* Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is strongly
* recommended to ensure a clear indication of the cause of next reset.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_RESET_GetDeviceResetReason() \n\n\n
*/
__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void)
{
/* Clear RSTSTAT.RSTSTAT bitfield */
SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
}
/**
* @return uint32_t Value of CPU clock frequency.
*
* \par<b>Description</b><br>
* Provides the vlaue of CPU clock frequency.\n\n
* The value is stored in a global variable \a \b SystemCoreClock.
* It is updated when the clock configuration is done using the SCU LLD APIs.
* The value represents the frequency of clock used for CPU operation.
* \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void)
{
return SystemCoreClock;
}
/**
* @return uint32_t Value of peripheral clock frequency in Hertz.
*
* \par<b>Description</b><br>
* Provides the vlaue of clock frequency at which the peripherals are working.\n\n
* The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void);
#if(UC_SERIES != XMC45)
/**
*
* @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
* to identify the peripheral clock to be gated.
*
* @return None
*
* \par<b>Description</b><br>
* Blocks the supply of clock to the selected peripheral.\n\n
* Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals.
* \if XMC1
* fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
* the clock supply for the selected peripheral.
* Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0
* register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected
* bit fields are handled internally.
* \endif
* \if XMC4
* fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
* the clock supply for the selected peripheral.
* Software can request for individual gating of such peripheral clocks by enabling one of the \a
* SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields.
*
* \endif
* Note: Clock gating shall not be activated unless the module is in reset state. So use \a
* XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n
*/
void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
/**
*
* @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
* to identify the peripheral.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the supply of clock to the selected peripheral.\n\n
* By default when the device powers on, the peripheral clock will be gated for the
* peripherals that support clock gating.
* The peripheral clock should be enabled before using it for any functionality.
* \if XMC1
* fPCLK is the source of clock to various peripherals. Some peripherals support clock gate.
* Software can request for individual ungating of such peripheral clocks by setting respective bits
* in the \a SCU_CGATCLR0 register.
* \endif
* \if XMC4
* fPERI is the source of clock to various peripherals. Some peripherals support clock gate.
* Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a
* SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers.
* \endif
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
/**
*
* @param peripheral The peripheral for which the check for clock gating has to be done.
* \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.
*
* @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated.
* false if the peripheral clock ungated(gate de-asserted).
*
* \par<b>Description</b><br>
* Gives the status of peripheral clock gating.\n\n
* \if XMC1
* Checks the status of peripheral clock gating using the register CGATSTAT0.
* \endif
* \if XMC4
* Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers.
* \endif
* It is recommended to use this API before
* enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
#endif
/**
* @return uint32_t Status of the register mirror update.\n
* \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of
* interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined
* using \a OR operation.
*
* \par<b>Description</b><br>
* Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n
* The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register
* representing the communication of changed value of a mirror register to its corresponding register in the
* hibernate domain. The bit fields of the register indicate
* that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface
* is busy with executing the previous operation.\n
* Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose.
*/
__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void)
{
return(SCU_GENERAL->MIRRSTS);
}
/**
* @param event The event for which the interrupt handler is to be configured. \n
* \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
* @param handler Name of the function to be executed when the event if detected. \n
* \b Range: The function accepts no arguments and returns no value.
* @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n
* \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n
* \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n
* \par<b>Description</b><br>
* Assigns the event handler function to be executed on occurrence of the selected event.\n\n
* If the input event is valid, the handler function will be assigned to a table to be executed
* when the interrupt is generated and the event status is set in the event status register. By using this API,
* polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events
* can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed.
* It checks for status flags of events which can generate the interrupt. The handler function will be executed if the
* event flag is set.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n
*/
XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);
/**
* @param sr_num Service request number identifying the SCU interrupt generated.\n
* \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\n
* But XMC1x devices support 3 interrupt nodes.
* @return None
* \par<b>Description</b><br>
* A common function to execute callback functions for multiple events.\n\n
* It checks for the status of events which can generate the interrupt with the selected service request.
* If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\n
* \b Note: This is an internal function. It should not be called by the user application.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
*/
void XMC_SCU_IRQHandler(uint32_t sr_num);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* SCU_H */

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/**
* @file xmc_uart.h
* @date 2016-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Description updated <br>
* - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent()
* for supporting multiple events configuration <br>
*
* 2016-05-20:
* - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission()
*
* @endcond
*
*/
#ifndef XMC_UART_H
#define XMC_UART_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup UART
* @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC microcontroller family.
*
* The UART driver uses Universal Serial Interface Channel(USIC) module to implement UART protocol.
* It provides APIs to configure USIC channel for UART communication. The driver enables the user
* in getting the status of UART protocol events, configuring interrupt service requests, protocol
* related parameter configuration etc.
*
* UART driver features:
* -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init()
* -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t
* -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource()
* -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using
XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength()
* -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag()
* -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData()
*
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if defined(USIC0)
#define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* UART driver status
*/
typedef enum XMC_UART_CH_STATUS
{
XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/
XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */
XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */
} XMC_UART_CH_STATUS_t;
/**
* UART portocol status. The enum values can be used for getting the status of UART channel.
*
*/
typedef enum XMC_UART_CH_STATUS_FLAG
{
XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk, /**< UART Protocol Status transmit IDLE*/
XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk, /**< UART Protocol Status receive IDLE*/
XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk, /**< UART Protocol Status synchronization break detected*/
XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk, /**< UART Protocol Status collision detected*/
XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk, /**< UART Protocol Status receiver noise detected */
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk, /**< UART Protocol Status format error in stop bit 0 */
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk, /**< UART Protocol Status format error in stop bit 1 */
XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk, /**< UART Protocol Status receive frame finished */
XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk, /**< UART Protocol Status transmit frame finished */
XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk, /**< UART Protocol Status transfer status busy */
XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk, /**< UART Protocol Status receive start indication flag*/
XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk, /**< UART Protocol Status data lost indication flag*/
XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk, /**< UART Protocol Status transmit shift indication flag*/
XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk, /**< UART Protocol Status transmit buffer indication flag*/
XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk, /**< UART Protocol Status receive indication flag*/
XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk, /**< UART Protocol Status alternative receive indication flag*/
XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator indication flag*/
} XMC_UART_CH_STATUS_FLAG_t;
/**
* UART configuration events. The enums can be used for configuring events using the CCR register.
*/
typedef enum XMC_CH_UART_EVENT
{
XMC_UART_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_UART_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_UART_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_UART_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */
XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */
XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */
XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event format error */
XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event frame finished */
} XMC_UART_CH_EVENT_t;
/**
* UART Input sampling frequency options
*/
typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ
{
XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input fperiph*/
XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input fractional divider*/
} XMC_UART_CH_INPUT_SAMPLING_FREQ_t;
/**
* UART input stages
*/
typedef enum XMC_UART_CH_INPUT
{
XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/
#if UC_FAMILY == XMC1
,
XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/
XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/
#endif
} XMC_UART_CH_INPUT_t;
/**
* UART channel interrupt node pointers
*/
typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER
{
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_UART_CH_INTERRUPT_NODE_POINTER_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* UART initialization structure
*/
typedef struct XMC_UART_CH_CONFIG
{
uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */
uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n
\b Range: minimum= 1, maximum= 16*/
uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n
\b Range: minimum= 1, maximum= 63*/
uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */
uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/
XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n
@ref XMC_USIC_CH_PARITY_MODE_ODD*/
} XMC_UART_CH_CONFIG_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t.
* @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n
* \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n
* @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed.
*
* \par<b>Description</b><br>
* Initializes the USIC channel for UART protocol.\n\n
* During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value
* in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16
* is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the
* majority decision among 3 samples.
* Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length
* is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length.
* Parity mode is set to the value configured for \a parity_mode.
* The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
*/
void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Sets the USIC channel operation mode to UART mode.\n\n
* CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring
* the USIC channel. Transmission and reception can happen only when the UART mode is set.
* This is an inline function.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel)
{
channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERATING_MODE_UART);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is stopped successfully.\n
* @ref XMC_UART_CH_STATUS_OK if the communication channel is stopped.
* @ref XMC_UART_CH_STATUS_BUSY if the communication channel is busy.
*
* \par<b>Description</b><br>
* Stops the UART communication.\n\n
* CCR register bitfield \a Mode is reset. This disables the communication.
* Before starting the communication again, the channel has to be reconfigured.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Init() \n\n\n
*/
XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param rate Desired baudrate. \n
* \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n
* and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
* @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n
* This can be related to the number of samples for each logic state of the data signal.\n
* \b Range: 4 to 32. Value should be chosen based on the protocol used.
* @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n
* \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
* @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
*
* \par<b>Description:</b><br>
* Sets the bus speed in bits per second.\n\n
* Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible.
* \a oversampling is the number of samples to be taken for each symbol of UART protocol.
* Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep
* a minimum oversampling of 4 for UART.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Init(), XMC_UART_CH_Stop()
*/
XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param data Data to be transmitted. \n
* \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of
* data transmitted depends on the configured number of bits for the UART protocol in the register SCTR.
* @return None
*
* \par<b>Description</b><br>
* Transmits data over serial communication channel using UART protocol.\n\n
* Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register.
* Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register.
* So user can continuously execute the API without checking for TBUF busy status. Based on the number of
* data bits configured, the lower significant bits will be extracted for transmission.
*
* Note: When FIFO is not configured, the API waits for the TBUF to be available.
* This makes the execution a blocking call.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_GetReceivedData() \n\n\n
*/
void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return uint16_t Received data over UART communication channel.
* \par<b>Description</b><br>
* Provides one word of data received over UART communication channel.\n\n
* Based on the channel configuration, data is either read from the receive FIFO or RBUF register.
* Before returning the value, there is no check for data validity. User should check the appropriate
* data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO alternative receive)
* before executing the API. Reading from an empty receive FIFO can generate a receive error event.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n
*/
uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param word_length Data word length. \n
* \b Range: minimum= 1, maximum= 16.
* @return None
*
* \par<b>Description</b><br>
* Sets the data word length in number of bits.\n\n
* Word length can range from 1 to 16. It indicates the number of data bits in a data word.
* The value of \a word_length will be decremented by 1 before setting the value to \a SCTR register.
* If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and
* word length should be configured with the number of bits expected in each transaction. For example, if number of data bits
* for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the
* transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case,
* a full message of UART data should be transmitted/ received as 3 data words.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SetFrameLength() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
{
XMC_USIC_CH_SetWordLength(channel, word_length);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param frame_length Number of data bits in each UART frame. \n
* \b Range: minimum= 1, maximum= 64.
* @return None
*
* \par<b>Description</b><br>
* Sets the number of data bits for UART communication.\n\n
* The frame length is configured by setting the input value to \a SCTR register.
* The value of \a frame_length will be decremented by 1, before setting it to the register.
* Frame length should not be set to 64 for UART communication.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SetWordLength() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
{
XMC_USIC_CH_SetFrameLength(channel, frame_length);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for naming events. \n
* \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
* @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
* etc.
* @return None
*
* \par<b>Description</b><br>
* Enables interrupt events for UART communication.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
* Events are configured by setting bits in the CCR register.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(), XMC_UART_CH_GetStatusFlag() \n\n\n
*/
void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t for naming events.\n
* \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
* @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
* etc.
* @return None
*
* \par<b>Description</b><br>
* Disables the interrupt events by clearing the bits in CCR register.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n
*/
void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param service_request Service request number for generating protocol interrupts.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for UART channel protocol events.\n\n
* For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common
* interrupt gets generated. The service request connects the interrupt node to the UART
* protocol events.
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a UART interrupt service request.\n\n
* When the UART service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return Status of UART channel events. \n
* \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
* event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
* @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
*
* \par<b>Description</b><br>
* Provides the status of UART channel events.\n\n
* Status provided by the API represents the status of multiple events at their bit positions. The bitmasks can be
* obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained by reading
* the register PSR_ASCMode.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n
*/
__STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return channel->PSR_ASCMode;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param flag UART events to be cleared. \n
* \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
* event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
* @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
* @return None
*
* \par<b>Description</b><br>
* Clears the status of UART channel events.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
* Events are cleared by setting the bitmask to the PSCR register.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
{
channel->PSCR = flag;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @param source Input source select for the input stage. The table provided below maps the decimal value with the input source.
* <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
* <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
* </tr></table>
* @return None
*
* \par<b>Description</b><br>
* Sets input soource for the UART communication.\n\n
* It is used for configuring the input stage for data reception.
* Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
* The API can be used for the input stages DX0, DX3 and DX5.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk)));
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param pulse_length Length of the zero pulse in number of time quanta. \n
* \b Range: 0 to 7.
* @return None
*
* \par<b>Description</b><br>
* Sets the length of zero pulse in number of time quanta. Value 0 indicates one time quanta.\n\n
* Maximum possible is 8 time quanta with the value configured as 7.\n
* The value is set to PCR_ASCMode register.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
*
*/
__STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const uint8_t pulse_length)
{
channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~USIC_CH_PCR_ASCMode_PL_Msk)) |
((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param sample_point Sample point among the number of samples. \n
* \b Range: minimum= 0, maximum= \a oversampling (DCTQ).
* @return None
*
* \par<b>Description</b><br>
* Sets the sample point among the multiple samples for each UART symbol.\n\n
* The sample point is the one sample among number of samples set as oversampling. The value should be less than
* the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For
* example if the oversampling is 16, then the sample point is set to 9.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point)
{
channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) |
(sample_point << USIC_CH_PCR_ASCMode_SP_Pos));
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Enables input inversion for UART input data signal.\n\n
* Polarity of the input source can be changed to provide inverted data input.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputInversion()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables input inversion for UART input data signal.\n\n
* Resets the input data polarity for the UART input data signal.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Enables the digital filter for UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables the digital filter for UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
* \par<b>Description</b><br>
* Enables synchronous input for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables synchronous input for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @param sampling_freq Input sampling frequency. \n
* \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER.
* @return None
*
* \par<b>Description</b><br>
* Sets the sampling frequency for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INPUT_t input,
const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq)
{
XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_vadc_map.h
* @date 2016-11-17
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-15:
* - Initial version
*
* 2015-12-01:
* - Added:
* - XMC4300 device supported
*
* - Fixed:
* - Wrong MACRO name corrected for XMC4200/4100 devices.
* XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE
*
* 2016-11-17:
* - Fixed: Add missing support for XMC47000
* - Fixed: Renamed XMC_CCU_41_ST2 to XMC_CCU_41_ST3
* - Added: New macros equivalent to th existing ones but with better naming.
* Old macros are kept for backward compatibility but they deprecated.
* - Added: ECAT support for XMC48/43
*
* @endcond
*
*/
#ifndef XMC_ADC_MAP_H
#define XMC_ADC_MAP_H
#ifdef __cplusplus
extern "C" {
#endif
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if ( UC_FAMILY == XMC1 )
/* Group request source Gating input connection mappings */
#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
#define XMC_CCU_40_ST2 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST2 */
#define XMC_CCU_40_ST1 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST1 */
#define XMC_CCU_40_ST0 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST0 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */
#define XMC_CCU_81_ST3 XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3 */
#endif
#if (UC_SERIES != XMC13 && UC_SERIES != XMC11)
#define XMC_LEDTS0_FN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS0_FN */
#define XMC_LEDTS1_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS1_FN */
#endif
#define XMC_ERU_0_PDOUT2 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT2 */
#define XMC_ERU_0_PDOUT3 XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT3 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_ST0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST0 */
#define XMC_CCU_80_ST1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST1 */
#endif
#define XMC_ERU_0_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT0 */
#define XMC_ERU_0_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT1 */
/* Group request source Trigger input connection mappings */
#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */
#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */
#if (UC_SERIES != XMC11)
#define XMC_BCCU0_TRIGOUT XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_BCCU0_TRIGOUT0, XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 or XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 */
#endif
#define XMC_ERU_0_IOUT2 XMC_VADC_REQ_TR_G /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT2 */
#define XMC_ERU_0_IOUT3 XMC_VADC_REQ_TR_H /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT3 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */
#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */
#endif
#define XMC_ERU_0_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT0 */
#define XMC_ERU_0_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT1 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1 */
#endif
#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_TR_REQ_GT_SEL */
/* Group request source Gating input connection mappings */
#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */
#define XMC_VADC_REQ_GT_CCU40_ST2 XMC_VADC_REQ_GT_B /**< VADC Gating input B */
#define XMC_VADC_REQ_GT_CCU40_ST1 XMC_VADC_REQ_GT_C /**< VADC Gating input C */
#define XMC_VADC_REQ_GT_CCU40_ST0 XMC_VADC_REQ_GT_D /**< VADC Gating input D */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */
#define XMC_VADC_REQ_GT_CCU80_ST3 XMC_VADC_REQ_GT_F /**< VADC Gating input F */
#endif
#if (UC_SERIES != XMC13 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_LEDTS0_FN XMC_VADC_REQ_GT_I /**< VADC Gating input I */
#define XMC_VADC_REQ_GT_LEDTS1_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */
#endif
#define XMC_VADC_REQ_GT_ERU0_PDOUT2 XMC_VADC_REQ_GT_K /**< VADC Gating input K */
#define XMC_VADC_REQ_GT_ERU0_PDOUT3 XMC_VADC_REQ_GT_L /**< VADC Gating input L */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_CCU80_ST0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */
#define XMC_VADC_REQ_GT_CCU80_ST1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */
#endif
#define XMC_VADC_REQ_GT_ERU0_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */
#define XMC_VADC_REQ_GT_ERU0_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */
/* Group request source Trigger input connection mappings */
#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */
#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */
#if (UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Global Background Source Trigger input F */
#define XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Group 0 Trigger input F */
#define XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 XMC_VADC_REQ_TR_F /**< VADC Group1 Trigger input F */
#endif
#define XMC_VADC_REQ_TR_ERU0_IOUT2 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */
#define XMC_VADC_REQ_TR_ERU0_IOUT3 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */
#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */
#endif
#define XMC_VADC_REQ_TR_ERU0_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */
#define XMC_VADC_REQ_TR_ERU0_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Trigger input N */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Trigger input O */
#endif
#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */
#endif
#if ( UC_FAMILY == XMC4 )
/* Group request source Gating input connection mappings */
#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
#define XMC_CCU_41_ST3 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_ST3 */
#define XMC_CCU_40_SR0 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_SR0 */
#define XMC_CCU_41_SR1 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_SR1 */
#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */
#define XMC_CCU_80_ST3_B XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3B */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_CCU_81_ST3_A XMC_VADC_REQ_GT_G /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3A */
#define XMC_CCU_81_ST3_B XMC_VADC_REQ_GT_H /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3B */
#endif
#define XMC_DAC_0_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G0_DAC0_SGN or XMC_VADC_REQ_GT_G2_DAC0_SGN */
#define XMC_DAC_1_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G1_DAC1_SGN or XMC_VADC_REQ_GT_G3_DAC1_SGN */
#define XMC_LEDTS_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS_FN */
#define XMC_VADC_G0_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 */
#define XMC_VADC_G1_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_G2_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 */
#define XMC_VADC_G3_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 */
#endif
#define XMC_VADC_G0_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_G1_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE */
#define XMC_VADC_G2_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE */
#define XMC_VADC_G3_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE */
#endif
#define XMC_CCU_80_SR0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR0 */
#define XMC_CCU_80_SR1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR1 */
#define XMC_ERU_1_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT0 */
#define XMC_ERU_1_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT1 */
/* Group request source Trigger input connection mappings */
#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */
#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */
#define XMC_CCU_41_SR2 XMC_VADC_REQ_TR_C /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR2 */
#define XMC_CCU_41_SR3 XMC_VADC_REQ_TR_D /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR3 */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_CCU_42_SR3 XMC_VADC_REQ_TR_E /**< @deprecated use instead XMC_VADC_REQ_TR_CCU42_SR3 */
#define XMC_CCU_43_SR3 XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_CCU43_SR3 */
#endif
#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */
#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */
#define XMC_CCU_81_SR2 XMC_VADC_REQ_TR_K /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR2 */
#define XMC_CCU_81_SR3 XMC_VADC_REQ_TR_L /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR3 */
#define XMC_ERU_1_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT0 */
#define XMC_ERU_1_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G0_ERU1_IOUT1 or XMC_VADC_REQ_TR_G1_ERU1_IOUT1 */
#define XMC_ERU_1_IOUT2 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G2_ERU1_IOUT2 or XMC_VADC_REQ_TR_G3_ERU1_IOUT1 */
#if ( (UC_SERIES != XMC43) )
#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G0_POSIF0_SR1 or XMC_VADC_REQ_TR_G2_POSIF0_SR1 */
#endif
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_POSIF_1_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G1_POSIF0_SR1 or XMC_VADC_REQ_TR_G3_POSIF0_SR1 */
#endif
#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
/* Group request source Gating input connection mappings */
#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */
#define XMC_VADC_REQ_GT_CCU41_ST3 XMC_VADC_REQ_GT_B /**< VADC Gating input B */
#define XMC_VADC_REQ_GT_CCU40_SR0 XMC_VADC_REQ_GT_C /**< VADC Gating input C */
#define XMC_VADC_REQ_GT_CCU41_SR1 XMC_VADC_REQ_GT_D /**< VADC Gating input D */
#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */
#define XMC_VADC_REQ_GT_CCU80_ST3B XMC_VADC_REQ_GT_F /**< VADC Gating input F */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_CCU81_ST3A XMC_VADC_REQ_GT_G /**< VADC Gating input G */
#define XMC_VADC_REQ_GT_CCU81_ST3B XMC_VADC_REQ_GT_H /**< VADC Gating input H */
#endif
#define XMC_VADC_REQ_GT_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Global Background Source Gating input I */
#define XMC_VADC_REQ_GT_G0_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 0 Gating input I */
#define XMC_VADC_REQ_GT_G1_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 1 Gating input I */
#define XMC_VADC_REQ_GT_G2_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 2 Gating input I */
#define XMC_VADC_REQ_GT_G3_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 3 Gating input I */
#define XMC_VADC_REQ_GT_LEDTS_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */
#define XMC_VADC_REQ_GT_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Global Background Source Gating input K */
#define XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 0 Gating input K */
#define XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 1 Gating input K */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 2 Gating input K */
#define XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 3 Gating input K */
#endif
#define XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 0 Gating input L */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 1 Gating input L */
#define XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 2 Gating input L */
#define XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 3 Gating input L */
#endif
#define XMC_VADC_REQ_GT_CCU80_SR0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */
#define XMC_VADC_REQ_GT_CCU80_SR1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */
#define XMC_VADC_REQ_GT_ERU1_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */
#define XMC_VADC_REQ_GT_ERU1_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */
/* Group request source Trigger input connection mappings */
#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */
#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */
#define XMC_VADC_REQ_TR_CCU41_SR2 XMC_VADC_REQ_TR_C /**< VADC Trigger input C */
#define XMC_VADC_REQ_TR_CCU41_SR3 XMC_VADC_REQ_TR_D /**< VADC Trigger input D */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_TR_CCU42_SR3 XMC_VADC_REQ_TR_E /**< VADC Trigger input E */
#define XMC_VADC_REQ_TR_CCU43_SR3 XMC_VADC_REQ_TR_F /**< VADC Trigger input F */
#endif
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC43))
#define XMC_VADC_REQ_TR_ECAT_SYNC0 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */
#define XMC_VADC_REQ_TR_ECAT_SYNC1 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */
#endif
#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */
#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */
#define XMC_VADC_REQ_TR_CCU81_SR2 XMC_VADC_REQ_TR_K /**< VADC Trigger input K */
#define XMC_VADC_REQ_TR_CCU81_SR3 XMC_VADC_REQ_TR_L /**< VADC Trigger input L */
#define XMC_VADC_REQ_TR_ERU1_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */
#define XMC_VADC_REQ_TR_ERU1_IOUT1 XMC_VADC_REQ_TR_M /**< VADC Global Background Source Trigger input N */
#define XMC_VADC_REQ_TR_G0_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 0 Trigger input N */
#define XMC_VADC_REQ_TR_G1_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 1 Trigger input N */
#define XMC_VADC_REQ_TR_G2_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 2 Trigger input N */
#define XMC_VADC_REQ_TR_G3_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 3 Trigger input N */
#if ( (UC_SERIES != XMC43) )
#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Global Background Source Trigger input O */
#define XMC_VADC_REQ_TR_G0_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 0 Trigger input O */
#define XMC_VADC_REQ_TR_G1_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 1 Trigger input O */
#endif
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_TR_G2_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 2 Trigger input O */
#define XMC_VADC_REQ_TR_G3_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 3 Trigger input O */
#endif
#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */
#endif
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file xmc_wdt.h
* @date 2015-08-06
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-06:
* - Bug fix in XMC_WDT_SetDebugMode() API, Wrong register is being configured.<br>
* @endcond
*/
#ifndef XMC_WDT_H
#define XMC_WDT_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#include "xmc_scu.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup WDT
* @brief Watchdog driver for the XMC microcontroller family.
*
* The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system
* back from the unresponsive state to normal operation.
*
* This LLD provides the Configuration structure XMC_WDT_CONFIG_t and initialization function XMC_WDT_Init().\n
* It can be used to:
* -# Start or Stop the watchdog timer. (XMC_WDT_Start() and XMC_WDT_Stop())
* -# Service the watchdog timer. (XMC_WDT_Service())
* -# Configure the service window upper bound and lower bound timing values. (XMC_WDT_SetWindowBounds())
* -# Enable the generation of the pre-warning event for the first overflow of the timer. (XMC_WDT_SetMode())
* -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop
generating reset request for the second overflow of the timer. (XMC_WDT_ClearAlarm())
* -# Suspend the watchdog timer during Debug HALT mode. (XMC_WDT_SetDebugMode())
* -# Configure service indication pulse width.(XMC_WDT_SetServicePulseWidth())
*
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV),
to service or feed the watchdog. */
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines working modes for watchdog. Use type XMC_WDT_MODE_t for this enum.
*/
typedef enum XMC_WDT_MODE
{
XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow
occurs. */
XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And
reset request after subsequent overflow, if not
serviced after first overflow. */
} XMC_WDT_MODE_t;
/**
* Defines debug behaviour of watchdog when the CPU enters HALT mode. Use type XMC_WDT_DEBUG_MODE_t for this enum.
*/
typedef enum XMC_WDT_DEBUG_MODE
{
XMC_WDT_DEBUG_MODE_STOP = (uint32_t)0x0 << WDT_CTR_DSP_Pos, /**< Watchdog counter is paused during debug halt. */
XMC_WDT_DEBUG_MODE_RUN = (uint32_t)0x1 << WDT_CTR_DSP_Pos /**< Watchdog counter is not paused during debug halt. */
} XMC_WDT_DEBUG_MODE_t;
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/* Anonymous structure/union guard start */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* Structure for initializing watchdog timer. Use type XMC_WDT_CONFIG_t for this structure.
*/
typedef struct XMC_WDT_CONFIG
{
uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of
timer. ALways upper bound value has to be more than lower bound value. If it is set
lower than WLB, triggers a system reset after timer crossed upper bound value.\n
Range: [0H to FFFFFFFFH] */
uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the
window mechanism.\n
Range: [0H to FFFFFFFFH] */
union
{
struct
{
uint32_t : 1;
uint32_t prewarn_mode : 1; /**< Pre-warning mode (PRE). This accepts boolean values as input. */
uint32_t : 2;
uint32_t run_in_debug_mode : 1; /**< Watchdog timer behaviour during debug (DSP). This accepts boolean values as input. */
uint32_t : 3;
uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1),
in fwdt cycles.\n
Range: [0H to FFH] */
uint32_t : 16;
};
uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above
union members. */
};
} XMC_WDT_CONFIG_t;
/* Anonymous structure/union guard end */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/*********************************************************************************************************************
* API PROTOTYPES
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Enables watchdog clock and releases watchdog reset.\n
* \endif
* \if XMC1
* Enables watchdog clock.\n
* \endif
* \par
* This API is invoked by XMC_WDT_Init() and therefore no need to call it explicitly during watchdog initialization
* sequence. Invoke this API to enable watchdog once again if the watchdog is disabled by invoking XMC_WDT_Disable().
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. It is required to configure the watchdog, again after invoking XMC_WDT_Disable(). Since all the registers are
* reset with default values.
* \endif
* \if XMC1
* 1. Not required to configure the watchdog again after invoking XMC_WDT_Disable(). Since the registers retains with
* the configured values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Disable()
*/
void XMC_WDT_Enable(void);
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Disables the clock and resets watchdog timer.\n
* \endif
* \if XMC1
* Disables the clock to the watchdog timer.\n
* \endif
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Resets the registers with default values. So XMC_WDT_Init() has to be invoked again to configure the watchdog.
* \endif
* \if XMC1
* 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by
calling XMC_WDT_Enable(), previous configured register values are displayed. No need to invoke XMC_WDT_Init()
again.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Enable()
*/
void XMC_WDT_Disable(void);
/**
* @param config pointer to a constant watchdog configuration data structure. Refer data structure XMC_WDT_CONFIG_t
* for detail.
*
* @return None
*
* \par<b>Description:</b><br>
* Initializes and configures watchdog with configuration data pointed by \a config.\n
* \par
* It invokes XMC_WDT_Enable() to enable clock and release reset. Then configures the lower and upper window bounds,
* working mode (timeout/pre-warning), debug behaviour and service request indication pulse width.
*
* \par<b>Note:</b><br>
* 1. With out invoking this XMC_WDT_Init() or XMC_WDT_Enable(), invocation of other APIs like XMC_WDT_SetWindowBounds(),
* XMC_WDT_SetMode(), XMC_WDT_SetServicePulseWidth(), XMC_WDT_SetDebugMode(), XMC_WDT_Start(), XMC_WDT_GetCounter(),
* XMC_WDT_Service(), XMC_WDT_ClearAlarm() has no affect.
*/
void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config);
/**
* @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles.
* Range: [0H to FFFFFFFFH].
* @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles.
* Range: [0H to FFFFFFFFH].
*
* @return None
*
* \par<b>Description:</b><br>
* Sets watchdog window lower and upper bounds by updating WLB and WUB registers.\n
* \par
* Window lower and upper bounds are set during initialization in XMC_WDT_Init(). Invoke this API to alter the values as
* needed later in the program. This upper bound and lower bound can be calculated by using the below formula\n
* upper_bound or lower_bound = desired_boundary_time(sec) * fwdt(hz)
*
* \par<b>Note:</b>
* 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the
* upper_bound value it triggers the reset(wdt_rst_req) of the controller.
*/
__STATIC_INLINE void XMC_WDT_SetWindowBounds(uint32_t lower_bound, uint32_t upper_bound)
{
WDT->WLB = lower_bound;
WDT->WUB = upper_bound;
}
/**
* @param mode is one of the working modes of the watchdog timer, i.e timeout or pre-warning. Refer @ref XMC_WDT_MODE_t
* for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets watchdog working mode (timeout or pre-warning) by updating PRE bit of CTR register.\n
* \par
* The working mode is set during initialization in XMC_WDT_Init(). Invoke this API to alter the mode as needed later in
* the program.
*/
__STATIC_INLINE void XMC_WDT_SetMode(XMC_WDT_MODE_t mode)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_PRE_Msk) | (uint32_t)mode;
}
/**
* @param service_pulse_width specifies Service indication pulse width in terms of fwdt.
* Range: [0H – FFH].
* @return None
*
* \par<b>Description:</b><br>
* Sets service indication pulse width by updating SPW bit field of CTR register.\n
* \par
* The service indication pulse (with width service_pulse_width + 1 in fwdt cycles) is generated on successful servicing
* or feeding of watchdog. The pulse width is initially set during initialization in XMC_WDT_Init(). Invoke this API to
* alter the width as needed later in the program.
*/
__STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_SPW_Msk) | ((uint32_t)service_pulse_width << WDT_CTR_SPW_Pos);
}
/**
* @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for
* valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets debug behaviour of watchdog by modifying DSP bit of CTR register.\n
* \par
* Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as
* XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as
* needed later in the program.
*/
__STATIC_INLINE void XMC_WDT_SetDebugMode(const XMC_WDT_DEBUG_MODE_t debug_mode)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_DSP_Msk) | (uint32_t)debug_mode;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Start the watchdog timer by setting ENB bit of CTR register.\n
* \par
* Invoke this API to start the watchdog after initialization, or to resume the watchdog when
* paused by invoking XMC_WDT_Stop().
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Stop()
*/
__STATIC_INLINE void XMC_WDT_Start(void)
{
WDT->CTR |= (uint32_t)WDT_CTR_ENB_Msk;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Pauses watchdog timer by resetting ENB bit of CTR register.\n
* \par
* Invoke this API to pause the watchdog as needed in the program e.g. debugging through software control.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Stop()
*/
__STATIC_INLINE void XMC_WDT_Stop(void)
{
WDT->CTR &= (uint32_t)~WDT_CTR_ENB_Msk;
}
/**
* @param None
*
* @return uint32_t Current count value of watchdog timer register (TIM).
* Range: [0H to FFFFFFFFH]
*
* \par<b>Description:</b><br>
* Reads current count of timer register (TIM).\n
* \par
* Invoke this API before servicing or feeding the watchdog to check whether count is between lower and upper
* window bounds.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Service()
*/
__STATIC_INLINE uint32_t XMC_WDT_GetCounter(void)
{
return WDT->TIM;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Services or feeds the watchdog by writing the Magic word in SRV register.\n
* \par
* Service watchdog when count value of watchdog timer is between lower and upper window bounds. Successful servicing
* will reset watchdog timer (TIM register) to 0H and generate service indication pulse.
*
* \par<b>Note:</b><br>
* 1. invoking this API when count value of watchdog timer is less than window lower bound results
* wrong servicing and immediately triggers reset request.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_GetCounter(), XMC_WDT_SetWindowBounds(), XMC_WDT_SetServicePulseWidth()
*/
__STATIC_INLINE void XMC_WDT_Service(void)
{
WDT->SRV = XMC_WDT_MAGIC_WORD;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Clears pre-warning alarm by setting ALMC bit in WDTCLR register.\n
* \par
* In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm()
* must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid
* time window. Otherwise watchdog timer triggers the reset request up on crossing the upper bound value in a subsequent
* cycle.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Service(), XMC_WDT_SetMode()
*/
__STATIC_INLINE void XMC_WDT_ClearAlarm(void)
{
WDT->WDTCLR = WDT_WDTCLR_ALMC_Msk;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_WDT_H */

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/**
* @file xmc1_eru.c
* @date 2015-02-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* @endcond
*/
#include "xmc_eru.h"
#if UC_FAMILY == XMC1
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
void XMC_ERU_Enable(XMC_ERU_t *const eru)
{
XMC_UNUSED_ARG(eru);
}
void XMC_ERU_Disable(XMC_ERU_t *const eru)
{
XMC_UNUSED_ARG(eru);
}
#endif /* if( UC_FAMILY == XMC1 ) */

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/**
* @file xmc1_flash.c
* @date 2015-10-14
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-10:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API
*
* 2015-10-14:
* - Fixed defect in API XMC_FLASH_ErasePages, related to the errata NVM_CM.001
* - NVM ROM user routine XMC1000_NvmErasePage(address) used for erase page.
*
* @endcond
*
*/
#include "xmc_flash.h"
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#if UC_FAMILY == XMC1
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/* FLASH programming / erase options */
typedef enum FLASH_ACTION
{
FLASH_ACTION_IDLE = (uint32_t)0x00,
FLASH_ACTION_ONESHOT_WRITE_VERIFY = ((uint32_t)0x51 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_ONESHOT_WRITE = ((uint32_t)0x91 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_CONTINUOUS_WRITE_VERIFY = ((uint32_t)0x61 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_CONTINUOUS_WRITE = ((uint32_t)0xa1 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_ONESHOT_PAGE_ERASE = ((uint32_t)0x92 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_CONTINUOUS_PAGE_ERASE = ((uint32_t)0xa2 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_ONESHOT_VERIFY_ONLY = ((uint32_t)0xd0 << NVM_NVMPROG_ACTION_Pos),
FLASH_ACTION_CONTINUOUS_VERIFY_ONLY = ((uint32_t)0xe0 << NVM_NVMPROG_ACTION_Pos)
} FLASH_ACTION_t;
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/*
* This API shall clear the ECC and VERIFICATION error status.
*/
void XMC_FLASH_ClearStatus(void)
{
NVM->NVMPROG |= (uint16_t)((uint16_t)NVM_NVMPROG_RSTVERR_Msk | (uint16_t)NVM_NVMPROG_RSTECC_Msk);
}
/*
* This API shall return the status of NVM.
*/
uint32_t XMC_FLASH_GetStatus(void)
{
return NVM->NVMSTATUS;
}
/*
* This API shall enable the the flash interrupt event.
*/
void XMC_FLASH_EnableEvent(const uint32_t event_msk)
{
NVM->NVMCONF |= (uint16_t)event_msk;
}
/*
* This API shall disable the the flash interrupt event.
*/
void XMC_FLASH_DisableEvent(const uint32_t event_msk)
{
NVM->NVMCONF &= (uint16_t)(~(uint16_t)event_msk);
}
void XMC_FLASH_ErasePage(uint32_t *address)
{
(void)XMC1000_NvmErasePage(address);
}
void XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data)
{
(void)XMC1000_NvmProgVerify(data, address);
}
/* Write blocks of data into flash*/
void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks, bool verify)
{
uint32_t word;
uint32_t block;
XMC_ASSERT("XMC_FLASH_WriteBlocks: Starting address not aligned to Block",
((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U)
/* Configure the continuous Write option command and reset the NVM error / verification status*/
NVM->NVMPROG &= (uint16_t)(~(uint16_t)NVM_NVMPROG_ACTION_Msk);
NVM->NVMPROG |= (uint16_t)(NVM_NVMPROG_RSTVERR_Msk | NVM_NVMPROG_RSTECC_Msk);
if (verify == true)
{
NVM->NVMPROG |= (uint16_t)FLASH_ACTION_CONTINUOUS_WRITE_VERIFY;
}
else
{
NVM->NVMPROG |= (uint16_t)FLASH_ACTION_CONTINUOUS_WRITE;
}
for (block = 0U; block < num_blocks; ++block)
{
for (word = 0U; word < XMC_FLASH_WORDS_PER_BLOCK; ++word)
{
*address = *data;
data++;
address++;
}
while (XMC_FLASH_IsBusy() == true)
{
}
}
/* Stop continuous write operation */
NVM->NVMPROG &= (uint16_t)(~(uint16_t)NVM_NVMPROG_ACTION_Msk);
}
/* Erase flash pages */
void XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages)
{
uint32_t page;
XMC_ASSERT("XMC_FLASH_ErasePages: Starting address not aligned to Page",
((uint32_t)address & FLASH_PAGE_ADDR_MASK) == 0U)
for (page = 0U; page < num_pages; ++page)
{
(void)XMC1000_NvmErasePage(address);
while (XMC_FLASH_IsBusy() == true)
{
}
/* Increment the page address for the next erase */
address += XMC_FLASH_WORDS_PER_PAGE;
}
}
/* Write multiple data blocks and verify the written data */
void XMC_FLASH_VerifyBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks)
{
uint32_t word;
uint32_t block;
XMC_ASSERT("XMC_FLASH_VerifyBlocks: Starting address not aligned to Block",
((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U)
/* Configure the Continuous write with verify option command and reset the NVM error / verification status*/
NVM->NVMPROG &= (uint16_t)~NVM_NVMPROG_ACTION_Msk;
NVM->NVMPROG |= (uint16_t)((uint16_t)NVM_NVMPROG_RSTVERR_Msk |
(uint16_t)NVM_NVMPROG_RSTECC_Msk |
(uint16_t)FLASH_ACTION_CONTINUOUS_VERIFY_ONLY);
for (block = 0U; block < num_blocks; ++block)
{
for (word = 0U; word < XMC_FLASH_WORDS_PER_BLOCK; ++word)
{
*address = *data;
data++;
address++;
}
while (XMC_FLASH_IsBusy() == true)
{
}
}
/* Stop continuous verify operation */
NVM->NVMPROG &= (uint16_t)(~(uint16_t)NVM_NVMPROG_ACTION_Msk);
}
/* Read data blocks from flash */
void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks)
{
uint32_t word;
uint32_t block;
XMC_ASSERT("XMC_FLASH_ReadBlocks: Starting address not aligned to Block",
((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U)
for (block = 0U; block < num_blocks; ++block)
{
for (word = 0U; word < XMC_FLASH_WORDS_PER_BLOCK; ++word)
{
*data = *address;
data++;
address++;
}
}
}
/* Erase single sector */
void XMC_FLASH_EraseSector(uint32_t *address)
{
XMC_ASSERT("XMC_FLASH_EraseSector: Starting address not aligned to Sector",
((uint32_t)address & FLASH_SECTOR_ADDR_MASK) == 0U)
XMC_FLASH_ErasePages(address, XMC_FLASH_PAGES_PER_SECTOR);
}
/* Program single page */
void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data)
{
XMC_FLASH_ProgramVerifyPage(address, data);
}
#endif

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/**
* @file xmc1_gpio.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#include "xmc_gpio.h"
#if UC_FAMILY == XMC1
/*******************************************************************************
* MACROS
*******************************************************************************/
#define PORT_PHCR_Msk PORT0_PHCR0_PH0_Msk
#define PORT_PHCR_Size PORT0_PHCR0_PH0_Msk
#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config)
{
XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode));
XMC_ASSERT("XMC_GPIO_Init: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(config->input_hysteresis));
/* Switch to input */
port->IOCR[pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U)));
/* HW port control is disabled */
port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U));
/* Set input hysteresis */
port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)));
port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)config->input_hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U));
/* Enable digital input */
if (XMC_GPIO_CHECK_ANALOG_PORT(port))
{
port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);
}
/* Set output level */
port->OMR = (uint32_t)config->output_level << pin;
/* Set mode */
port->IOCR[pin >> 2U] |= (uint32_t)config->mode << (PORT_IOCR_PC_Size * (pin & 0x3U));
}
void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port,
const uint8_t pin,
const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis)
{
XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis));
port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)));
port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U));
}
#endif /* UC_FAMILY == XMC1 */

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/**
* @file xmc1_rtc.c
* @date 2016-03-09
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - XMC_RTC_Init() function is modified
* by adding RTC running condition check
*
* 2016-03-09:
* - Optimize write only registers
*
* @endcond
*
*/
/**
*
* @brief RTC driver for XMC microcontroller family.
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_rtc.h>
#if UC_FAMILY == XMC1
#include <xmc_scu.h>
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Initialize the RTC peripheral
*/
XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config)
{
if (XMC_RTC_IsRunning() == false)
{
if (XMC_RTC_IsEnabled() == false)
{
XMC_RTC_Enable();
}
XMC_RTC_SetPrescaler(config->prescaler);
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = config->time.raw0;
RTC->TIM1 = config->time.raw1;
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = config->alarm.raw0;
RTC->ATIM1 = config->alarm.raw1;
}
return XMC_RTC_STATUS_OK;
}
/*
* Ungates a clock node for RTC
*/
void XMC_RTC_Enable(void)
{
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_RTC);
}
/*
* Gates a clock node for RTC
*/
void XMC_RTC_Disable(void)
{
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_RTC);
}
/*
* Suspends RTC function during CPU HALT mode
*/
void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode)
{
uint32_t regval;
regval = (RTC->CTR & (uint32_t)~RTC_CTR_SUS_Msk);
RTC->CTR = (regval | (uint32_t)debug_mode);
}
/*
* Enable RTC periodic and alarm event(s)
*/
void XMC_RTC_EnableEvent(const uint32_t event)
{
RTC->MSKSR |= event;
}
/*
* Disable RTC periodic and alarm event(s)
*/
void XMC_RTC_DisableEvent(const uint32_t event)
{
RTC->MSKSR &= ~event;
}
/*
* Clear RTC periodic and alarm event(s)
*/
void XMC_RTC_ClearEvent(const uint32_t event)
{
RTC->CLRSR = event;
}
/*
* Checks RTC peripheral is enabled for programming to its registers
*/
bool XMC_RTC_IsEnabled(void)
{
return !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_RTC);
}
#endif /* UC_FAMILY == XMC1 */

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/**
* @file xmc1_scu.c
* @date 2017-04-11
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - XMC_SCU_StartTempMeasurement API is modified
* - XMC_ASSERT statements are added in XMC_SCU_INTERRUPT_SetEventHandler
*
* 2015-06-20:
* - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent,
* - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus,
* - XMC_SCU_INTERRUPT_ClearEventStatus APIs are added
*
* 2015-09-23:
* - XMC1400 support added
*
* 2015-11-30:
* - Documentation improved
*
* 2016-02-29:
* - Fixed XMC_SCU_CLOCK_ScaleMCLKFrequency
* It solves issues with down clock frequency scaling
*
* 2016-04-15:
* - Fixed XMC_SCU_CLOCK_Init for XMC1400
* It solves issues when trying to disable the OSCHP and use the XTAL pins as GPIO
*
* 2017-02-09
* - At XMC_SCU_CLOCK_Init() fixed issue while reading oscillator watchdog status
*
* 2017-04-11:
* - Added XMC_SCU_SetBMI()
*
* @endcond
*
*/
/**
*
* @brief SCU low level driver API prototype definition for XMC1 family of microcontrollers <br>
*
* <b>Detailed description of file</b> <br>
* APIs provided in this file cover the following functional blocks of SCU: <br>
* -- GCU (APIs prefixed with XMC_SCU_GEN_) <br>
* ----Temperature Monitoring, Voltage Monitoring, CCU Start etc
*
* -- CCU (APIs prefixed with XMC_SCU_CLOCK_)<br>
* ---- Clock initialization, Clock Gating, Sleep Management etc
*
* -- RCU (APIs prefixed with XMC_SCU_RESET_) <br>
* ---- Reset Init, Cause, Manual Reset Assert/Deassert etc
*
* -- INTERRUPT (APIs prefixed with XMC_SCU_INTERRUPT_)<br>
* ---- Initialization, Manual Assert/Deassert, Acknowledge etc
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_scu.h>
#if UC_FAMILY == XMC1
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define SCU_IRQ_NUM (3U) /**< array index value for list of events that can generate SCU interrupt */
#define SCU_GCU_PASSWD_PROT_ENABLE (195UL) /**< Password for enabling protection */
#define SCU_GCU_PASSWD_PROT_DISABLE (192UL) /**< Password for disabling protection */
#define XMC_SCU_CHECK_RTCCLKSRC(source) ( (source == XMC_SCU_CLOCK_RTCCLKSRC_DCO2) || \
(source == XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0) || \
(source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT) || \
(source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT) || \
(source == XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT) ) /**< Used to verify
whether provided RTC
clock source is valid
or not */
#define SCU_GENERAL_INTCR_INTSEL_Msk SCU_GENERAL_INTCR0_INTSEL0_Msk /**< Mask value of Interrupt Source Select
for Node 0 */
#define SCU_GENERAL_INTCR_INTSEL_Size SCU_GENERAL_INTCR0_INTSEL1_Pos /**< Bit position value of Interrupt Source Select
for Node 1 */
#define ANA_TSE_T1 (0x10000F30U) /**< d is a constant data can be retrieved from Flash sector 0 to calculate OFFSET
value for DCO calibration */
#define ANA_TSE_T2 (0x10000F31U) /**< e is a constant data can be retrieved from Flash sector 0 to calculate OFFSET
value for DCO calibration */
#define DCO_ADJLO_T1 (0x10000F32U) /**< b is a constant data can be retrieved from Flash sector 0 to calculate OFFSET
value for DCO calibration */
#define DCO_ADJLO_T2 (0x10000F33U) /**< a is a constant data can be retrieved from Flash sector 0 to calculate OFFSET
value for DCO calibration */
#if UC_SERIES == XMC14
#define XMC_SCU_INTERRUPT_EVENT_MAX (64U) /**< Maximum supported SCU events for XMC14 device. */
#else
#define XMC_SCU_INTERRUPT_EVENT_MAX (32U) /**< Maximum supported SCU events for XMC11/12/13 device. */
#endif
#if UC_SERIES == XMC14
#define DCO1_DIV2_FREQUENCY_KHZ_Q22_10 (48000U << 10) /**< used to configures main clock (MCLK) frequency to requested
frequency value during runtime for XMC14 device. */
#else
#define DCO1_DIV2_FREQUENCY_KHZ_Q24_8 (32000U << 8) /**< used to configures main clock (MCLK) frequency to requested
frequency value during runtime for XMC11/12/13 device. */
#endif
#define ROM_BmiInstallationReq \
(*((uint32_t (**)(uint32_t requestedBmiValue))0x00000108U)) /**< Pointer to Request BMI installation routine is
available inside ROM. */
#define ROM_CalcTemperature \
(*((uint32_t (**)(void))0x0000010cU)) /**< Pointer to Calculate chip temperature routine is
available inside ROM. */
#define ROM_CalcTSEVAR \
(*((uint32_t (**)(uint32_t temperature))0x00000120U)) /**< Pointer to Calculate target level for temperature
comparison routine is available inside ROM. */
/*********************************************************************************************************************
* LOCAL DATA
********************************************************************************************************************/
static XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callback
functions on SCU event
occurrence. */
static XMC_SCU_INTERRUPT_EVENT_t event_masks[SCU_IRQ_NUM] =
{
(XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR |
XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED |
XMC_SCU_INTERRUPT_EVENT_PESRAM |
XMC_SCU_INTERRUPT_EVENT_PEUSIC0 |
#if defined(USIC1)
XMC_SCU_INTERRUPT_EVENT_PEUSIC1 |
#endif
#if defined(CAN)
XMC_SCU_INTERRUPT_EVENT_PEMCAN |
#endif
#if UC_SERIES == XMC14
XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK |
#endif
XMC_SCU_INTERRUPT_EVENT_LOCI),
(XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL |
#if UC_SERIES == XMC14
XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC |
#endif
XMC_SCU_INTERRUPT_EVENT_VDDPI |
XMC_SCU_INTERRUPT_EVENT_VDROP |
XMC_SCU_INTERRUPT_EVENT_VCLIP |
XMC_SCU_INTERRUPT_EVENT_TSE_DONE |
XMC_SCU_INTERRUPT_EVENT_TSE_HIGH |
XMC_SCU_INTERRUPT_EVENT_TSE_LOW |
XMC_SCU_INTERRUPT_EVENT_WDT_WARN |
XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC |
XMC_SCU_INTERRUPT_EVENT_RTC_ALARM |
XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED |
XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED |
XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED |
XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED |
XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED),
(
#if UC_SERIES != XMC11
XMC_SCU_INTERRUPT_EVENT_ORC0 |
XMC_SCU_INTERRUPT_EVENT_ORC1 |
XMC_SCU_INTERRUPT_EVENT_ORC2 |
XMC_SCU_INTERRUPT_EVENT_ORC3 |
XMC_SCU_INTERRUPT_EVENT_ORC4 |
XMC_SCU_INTERRUPT_EVENT_ORC5 |
XMC_SCU_INTERRUPT_EVENT_ORC6 |
XMC_SCU_INTERRUPT_EVENT_ORC7 |
#endif
#if defined(COMPARATOR)
XMC_SCU_INTERRUPT_EVENT_ACMP0 |
XMC_SCU_INTERRUPT_EVENT_ACMP1 |
XMC_SCU_INTERRUPT_EVENT_ACMP2 |
#if UC_SERIES == XMC14
XMC_SCU_INTERRUPT_EVENT_ACMP3 |
#endif
#endif
0)
}; /**< Defines list of events that can generate SCU interrupt and also indicates SCU events mapping to corresponding
service request number. These event mask values can be used to verify which event is triggered that corresponds
to service request number during runtime. All the event items are tabulated as per service request sources list
table of SCU. */
/*********************************************************************************************************************
* LOCAL ROUTINES
********************************************************************************************************************/
/* Utility routine to perform frequency up scaling */
static void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t idiv);
/* Utility routine to perform frequency down scaling */
static void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t idiv);
/* Calculates the value which must be installed in ANATSEIx register to get indication in
SCU_INTERRUPT->SRRAW bit when the chip temperature is above/below some target/threshold. */
static uint32_t XMC_SCU_CalcTSEVAR(uint32_t temperature)
{
uint32_t limit;
XMC_ASSERT("XMC_SCU_CalcTSEVAR: temperature out of range", (temperature >= 233U) && (temperature <= 388U));
limit = ROM_CalcTSEVAR(temperature);
if (limit == 0U)
{
limit = ROM_CalcTSEVAR(temperature + 1U);
if (limit == 0U)
{
limit = ROM_CalcTSEVAR(temperature - 1U);
}
}
return (limit);
}
#if UC_SERIES == XMC14
/* This is a local function used to generate the delay until register get updated with new configured value. */
static void delay(uint32_t cycles)
{
while(cycles > 0U)
{
__NOP();
cycles--;
}
}
#endif
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
#ifdef XMC_ASSERT_ENABLE
/* API to verify SCU event weather it is valid event or not */
__STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t event)
{
return ((event == XMC_SCU_INTERRUPT_EVENT_WDT_WARN) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTC_ALARM) ||
(event == XMC_SCU_INTERRUPT_EVENT_VDDPI) ||
#if defined(USIC1)
(event == XMC_SCU_INTERRUPT_EVENT_PEUSIC1) ||
#endif
#if defined(CAN)
(event == XMC_SCU_INTERRUPT_EVENT_PEMCAN) ||
#endif
#if UC_SERIES == XMC14
(event == XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK) ||
(event == XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC) ||
#endif
#if defined(COMPARATOR)
(event == XMC_SCU_INTERRUPT_EVENT_ACMP0) ||
(event == XMC_SCU_INTERRUPT_EVENT_ACMP1) ||
(event == XMC_SCU_INTERRUPT_EVENT_ACMP2) ||
#if UC_SERIES == XMC14
(event == XMC_SCU_INTERRUPT_EVENT_ACMP3) ||
#endif
#endif
(event == XMC_SCU_INTERRUPT_EVENT_VDROP) ||
#if UC_SERIES != XMC11
(event == XMC_SCU_INTERRUPT_EVENT_ORC0) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC1) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC2) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC3) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC4) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC5) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC6) ||
(event == XMC_SCU_INTERRUPT_EVENT_ORC7) ||
#endif
(event == XMC_SCU_INTERRUPT_EVENT_LOCI) ||
(event == XMC_SCU_INTERRUPT_EVENT_PESRAM) ||
(event == XMC_SCU_INTERRUPT_EVENT_PEUSIC0) ||
(event == XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR) ||
(event == XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED) ||
(event == XMC_SCU_INTERRUPT_EVENT_VCLIP) ||
(event == XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED) ||
(event == XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED) ||
(event == XMC_SCU_INTERRUPT_EVENT_TSE_DONE) ||
(event == XMC_SCU_INTERRUPT_EVENT_TSE_HIGH) ||
(event == XMC_SCU_INTERRUPT_EVENT_TSE_LOW));
}
#endif
/* API to enable the SCU event */
void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event)
{
SCU_INTERRUPT->SRMSK |= (uint32_t)event;
#if UC_SERIES == XMC14
SCU_INTERRUPT->SRMSK1 |= (uint32_t)(event >> 32U);
#endif
}
/* API to disable the SCU event */
void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event)
{
SCU_INTERRUPT->SRMSK &= ~(uint32_t)event;
#if UC_SERIES == XMC14
SCU_INTERRUPT->SRMSK1 &= (uint32_t)~(event >> 32U);
#endif
}
/* API to trigger the SCU event */
void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event)
{
SCU_INTERRUPT->SRSET |= (uint32_t)event;
#if UC_SERIES == XMC14
SCU_INTERRUPT->SRSET1 |= (uint32_t)(event >> 32U);
#endif
}
/* API to get the SCU event status */
XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void)
{
XMC_SCU_INTERRUPT_EVENT_t tmp;
tmp = SCU_INTERRUPT->SRRAW;
#if UC_SERIES == XMC14
tmp |= ((int64_t)SCU_INTERRUPT->SRRAW1 << 32U);
#endif
return (tmp);
}
/* API to clear the SCU event status */
void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event)
{
SCU_INTERRUPT->SRCLR |= (uint32_t)event;
#if UC_SERIES == XMC14
SCU_INTERRUPT->SRCLR1 |= (uint32_t)(event >> 32U);
#endif
}
/* API to lock protected bitfields from being modified */
void XMC_SCU_LockProtectedBits(void)
{
SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_ENABLE;
}
/* API to make protected bitfields available for modification */
void XMC_SCU_UnlockProtectedBits(void)
{
SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_DISABLE;
while(((SCU_GENERAL->PASSWD) & SCU_GENERAL_PASSWD_PROTS_Msk))
{
/* Loop until the lock is removed */
}
}
/* API to initialize power supply monitoring unit */
void XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj)
{
uint32_t anavdel;
uint32_t irqmask;
anavdel = 0UL;
anavdel |= (uint32_t)((obj-> ext_supply_threshold) << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos);
anavdel |= (uint32_t)((obj->ext_supply_monitor_speed) << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos);
if(true == (obj->enable_at_init))
{
anavdel |= (uint32_t)SCU_ANALOG_ANAVDEL_VDEL_EN_Msk;
}
SCU_ANALOG->ANAVDEL = (uint16_t) anavdel;
irqmask = 0UL;
if(true == (obj->enable_prewarning_int))
{
irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDDPI_Msk;
}
if(true == (obj->enable_vdrop_int))
{
irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDROPI_Msk;
}
if(true == (obj->enable_vclip_int))
{
irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VCLIPI_Msk;
}
SCU_INTERRUPT->SRMSK |= (uint32_t)irqmask;
}
/* API to program lower temperature limit */
XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit)
{
XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK;
limit = XMC_SCU_CalcTSEVAR(limit);
if (limit != 0)
{
SCU_ANALOG->ANATSEIL = (uint16_t)limit;
}
else
{
status = XMC_SCU_STATUS_ERROR;
}
return (status);
}
/* API to program higher temperature limit */
XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit)
{
XMC_SCU_STATUS_t status = XMC_SCU_STATUS_OK;
limit = XMC_SCU_CalcTSEVAR(limit);
if (limit != 0)
{
SCU_ANALOG->ANATSEIH = (uint16_t)limit;
}
else
{
status = XMC_SCU_STATUS_ERROR;
}
return (status);
}
/* API to program temperature limits as raw digital values into temperature sensor */
void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp)
{
SCU_ANALOG->ANATSEIH = (uint16_t)(upper_temp & SCU_ANALOG_ANATSEIH_TSE_IH_Msk);
SCU_ANALOG->ANATSEIL = (uint16_t)(lower_temp & SCU_ANALOG_ANATSEIL_TSE_IL_Msk);
}
/* API to start temperature measurement */
void XMC_SCU_StartTempMeasurement(void)
{
SCU_ANALOG->ANATSECTRL |= (uint16_t)SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;
}
/* API to stop temperature measurement */
void XMC_SCU_StopTempMeasurement(void)
{
SCU_ANALOG->ANATSECTRL &= (uint16_t)~SCU_ANALOG_ANATSECTRL_TSE_EN_Msk;
}
/* API to check if the temperature has gone past the ceiling */
bool XMC_SCU_HighTemperature(void)
{
return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk) == SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk);
}
/* API to check if the temperature is lower than normal */
bool XMC_SCU_LowTemperature(void)
{
return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_LOW_Msk) == SCU_INTERRUPT_SRRAW_TSE_LOW_Msk);
}
/* API to retrieve the device temperature */
uint32_t XMC_SCU_GetTemperature(void)
{
uint32_t temperature;
temperature = (uint32_t)(SCU_ANALOG->ANATSEMON);
return (temperature);
}
/* Calculates the die temperature value using ROM function */
uint32_t XMC_SCU_CalcTemperature(void)
{
return (ROM_CalcTemperature());
}
/* API which initializes the clock tree ofthe device */
void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config)
{
/* Remove protection */
XMC_SCU_UnlockProtectedBits();
#if (UC_SERIES == XMC14)
/* OSCHP source selection - OSC mode */
if (config->oschp_mode != XMC_SCU_CLOCK_OSCHP_MODE_DISABLED)
{
if (OSCHP_GetFrequency() > 20000000U)
{
SCU_ANALOG->ANAOSCHPCTRL |= (uint16_t)SCU_ANALOG_ANAOSCHPCTRL_HYSCTRL_Msk;
}
SCU_ANALOG->ANAOSCHPCTRL = (uint16_t)(SCU_ANALOG->ANAOSCHPCTRL & ~(SCU_ANALOG_ANAOSCHPCTRL_SHBY_Msk | SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk)) |
config->oschp_mode;
do
{
/* Restart OSC_HP oscillator watchdog */
SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk;
/* Enable OSC_HP oscillator watchdog*/
SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_XOWDEN_Msk;
SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk;
/* Wait a few DCO2 cycles for the update of the clock detection result */
delay(2500);
/* check clock is ok */
}
while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk);
}
else /* (config->oschp_mode == XMC_SCU_CLOCK_OSCHP_MODE_DISABLED) */
{
SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk;
}
SCU_ANALOG->ANAOSCLPCTRL = (uint16_t)config->osclp_mode;
SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & ~SCU_CLK_CLKCR1_DCLKSEL_Msk) |
config->dclk_src;
#endif
/* Update PCLK selection mux. */
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_PCLKSEL_Msk | SCU_CLK_CLKCR_RTCCLKSEL_Msk)) |
config->rtc_src |
config->pclk_src;
/* Close the lock opened above. */
XMC_SCU_LockProtectedBits();
/* Update the dividers now */
XMC_SCU_CLOCK_ScaleMCLKFrequency(config->idiv, config->fdiv);
}
/* API which selects one of the available parent clock nodes for a given child clock node */
void XMC_SCU_CLOCK_SetRtcClockSource(const XMC_SCU_CLOCK_RTCCLKSRC_t source)
{
XMC_ASSERT("XMC_SCU_CLOCK_SetRtcSourceClock:Wrong Parent Clock", XMC_SCU_CHECK_RTCCLKSRC(source));
XMC_SCU_UnlockProtectedBits();
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_RTCCLKSEL_Msk) |
source;
XMC_SCU_LockProtectedBits();
}
/* API to program the divider placed between fperiph and its parent */
void XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source)
{
XMC_SCU_UnlockProtectedBits();
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~SCU_CLK_CLKCR_PCLKSEL_Msk) |
source;
XMC_SCU_LockProtectedBits();
}
/* API which gates a clock node at its source */
void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
{
XMC_SCU_UnlockProtectedBits();
SCU_CLK->CGATSET0 |= (uint32_t)peripheral;
XMC_SCU_LockProtectedBits();
}
/* API which ungates a clock note at its source */
void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
{
XMC_SCU_UnlockProtectedBits();
SCU_CLK->CGATCLR0 |= (uint32_t)peripheral;
while ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
/* Wait voltage suply stabilization */
}
XMC_SCU_LockProtectedBits();
}
/* Checks the status of peripheral clock gating */
bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
{
return (bool)((SCU_CLK->CGATSTAT0 & peripheral) != 0);
}
/* This API configures main clock (MCLK) frequency to requested frequency value. */
void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz)
{
uint32_t ratio;
uint32_t ratio_int;
uint32_t ratio_frac;
#if UC_SERIES == XMC14
if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U)
{
ratio = DCO1_DIV2_FREQUENCY_KHZ_Q22_10 / freq_khz;
}
else
{
ratio = ((OSCHP_GetFrequency() / 1000U) << 10U) / freq_khz;
}
/* Manage overflow */
if (ratio > 0xffffffU)
{
ratio = 0xffffffU;
}
ratio_int = ratio >> 10U;
ratio_frac = ratio & 0x3ffU;
#else
ratio = DCO1_DIV2_FREQUENCY_KHZ_Q24_8 / freq_khz;
/* Manage overflow */
if (ratio > 0xffffU)
{
ratio = 0xffffU;
}
ratio_int = ratio >> 8U;
ratio_frac = ratio & 0xffU;
#endif
XMC_SCU_CLOCK_ScaleMCLKFrequency(ratio_int, ratio_frac);
}
/* A utility routine which updates the fractional dividers in steps */
void XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv)
{
/* Find out current and target value of idiv */
uint32_t curr_idiv;
XMC_SCU_UnlockProtectedBits();
/* Take a snapshot of value already programmed into IDIV */
curr_idiv = (SCU_CLK->CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
#if (UC_SERIES == XMC14)
SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & (uint32_t)~(SCU_CLK_CLKCR1_FDIV_Msk)) |
(uint32_t)((fdiv >> 8U) << SCU_CLK_CLKCR1_FDIV_Pos);
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |
(uint32_t)((fdiv & 0xffU) << SCU_CLK_CLKCR_FDIV_Pos) |
(uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);
#else
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |
(uint32_t)(fdiv << SCU_CLK_CLKCR_FDIV_Pos) |
(uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);
#endif
while ((SCU_CLK->CLKCR)& SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
/* Spin until the core supply stabilizes */
}
if(curr_idiv <= idiv)
{
/* Requested IDIV is greater than currently programmed IDIV. So downscale the frequency */
XMC_SCU_CLOCK_lFrequencyDownScaling(curr_idiv, idiv);
}
else
{
/* Requested IDIV is lower than currently programmed IDIV. So upscale the frequency */
XMC_SCU_CLOCK_lFrequencyUpScaling(curr_idiv, idiv);
}
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |
(uint32_t)(idiv << SCU_CLK_CLKCR_IDIV_Pos) | (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);
while ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
/* Wait voltage suply stabilization */
}
XMC_SCU_LockProtectedBits();
SystemCoreClockUpdate();
}
/* Utility routine to perform frequency up scaling */
static void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t target_idiv)
{
while (curr_idiv > (target_idiv * 4UL))
{
curr_idiv = (uint32_t)(curr_idiv >> 2UL); /* Divide by 4. */
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |
(uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) |
(uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);
while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
/* Wait voltage suply stabilization */
}
}
}
/* Utility routine to perform frequency down scaling */
static void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t target_idiv)
{
while ((curr_idiv * 4UL) < target_idiv)
{
if(0U == curr_idiv)
{
curr_idiv = 1U;
}
curr_idiv = (uint32_t)(curr_idiv << 2UL); /* Multiply by 4. */
SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) |
(uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) |
(uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos);
while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk)
{
/* Wait voltage suply stabilization */
}
}
}
/*
* API to retrieve clock frequency of peripherals on the peripheral bus using a shared functional clock
*/
uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void)
{
return (SystemCoreClock);
}
/* Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock */
uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void)
{
return (SystemCoreClock << ((SCU_CLK->CLKCR & SCU_CLK_CLKCR_PCLKSEL_Msk) >> SCU_CLK_CLKCR_PCLKSEL_Pos));
}
/* DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy */
void XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature)
{
int32_t a;
int32_t b;
int32_t d;
int32_t e;
int32_t offset;
a = *((uint8_t*)DCO_ADJLO_T2);
b = *((uint8_t*)DCO_ADJLO_T1);
d = *((uint8_t*)ANA_TSE_T1);
e = *((uint8_t*)ANA_TSE_T2);
offset = b + (((a - b) * (temperature - d)) / (e - d));
offset &= SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk;
XMC_SCU_UnlockProtectedBits();
SCU_ANALOG->ANAOFFSET = (uint16_t)offset;
XMC_SCU_LockProtectedBits();
}
/*
* API to assign the event handler function to be executed on occurrence of the selected event
*/
XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(XMC_SCU_INTERRUPT_EVENT_t event, XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler)
{
uint32_t index;
XMC_SCU_STATUS_t status;
XMC_ASSERT("XMC_SCU_INTERRUPT_SetEventHandler: Invalid event", XMC_SCU_INTERRUPT_IsValidEvent(event));
XMC_ASSERT("XMC_SCU_INTERRUPT_SetEventHandler: Invalid handler", handler != NULL);
index = 0U;
while (((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) == 0U) && (index < XMC_SCU_INTERRUPT_EVENT_MAX))
{
index++;
}
if (index == XMC_SCU_INTERRUPT_EVENT_MAX)
{
status = XMC_SCU_STATUS_ERROR;
}
else
{
event_handler_list[index] = handler;
status = XMC_SCU_STATUS_OK;
}
return (status);
}
/*
* A common function to execute callback functions for multiple events
*/
void XMC_SCU_IRQHandler(uint32_t sr_num)
{
XMC_ASSERT("XMC_SCU_IRQHandler: Invalid sr_num", sr_num < SCU_IRQ_NUM);
uint32_t index;
XMC_SCU_INTERRUPT_EVENT_t event;
XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler;
index = 0U;
event = XMC_SCU_INTERUPT_GetEventStatus() & event_masks[sr_num];
XMC_SCU_INTERRUPT_ClearEventStatus(event);
while ((event != 0) && (index < XMC_SCU_INTERRUPT_EVENT_MAX))
{
if ((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) != 0U)
{
event &= ~((XMC_SCU_INTERRUPT_EVENT_t)1 << index);
event_handler = event_handler_list[index];
if (event_handler != NULL)
{
event_handler();
}
/* break; XMC1: Only PULSE interrupts */
}
index++;
}
}
/* Install BMI */
uint32_t XMC_SCU_SetBMI(uint32_t flags, uint8_t timeout)
{
return ROM_BmiInstallationReq((flags & 0x0fffU) | ((timeout << 12) & 0xf000U));
}
#if (UC_SERIES == XMC14)
/* DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy */
void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_clk, uint32_t prescaler, uint32_t syn_preload)
{
XMC_SCU_UnlockProtectedBits();
SCU_ANALOG->ANASYNC2 = (uint16_t)(prescaler << SCU_ANALOG_ANASYNC2_PRESCALER_Pos);
SCU_ANALOG->ANASYNC1 = (uint16_t)(syn_preload |
sync_clk |
SCU_ANALOG_ANASYNC1_SYNC_DCO_EN_Msk);
XMC_SCU_LockProtectedBits();
}
/* This function stops the automatic DCO1 calibration based on the selected clock source */
void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void)
{
XMC_SCU_UnlockProtectedBits();
SCU_ANALOG->ANASYNC2 = 0U;
SCU_ANALOG->ANASYNC1 = 0U;
XMC_SCU_LockProtectedBits();
}
/* This functions checks the status of the synchronisation */
bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void)
{
return (bool)((SCU_ANALOG->ANASYNC2 & SCU_ANALOG_ANASYNC2_SYNC_READY_Msk) != 0U);
}
/**
* This function enables the watchdog on the DCO1 frequency
*/
void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void)
{
SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDEN_Msk;
}
/**
* This function disables the watchdog on the DCO1 frequency
*/
void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void)
{
SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_OWDEN_Msk;
}
/**
* This function clears the status of the watchdog on the DCO1 frequency
*/
void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void)
{
SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDRES_Msk;
}
/**
* This function checks if the DCO1 frequency is in the limits of the watchdog.
*/
bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void)
{
return ((SCU_CLK->OSCCSR & (SCU_CLK_OSCCSR_OSC2L_Msk | SCU_CLK_OSCCSR_OSC2H_Msk)) == 0U);
}
/* This function selects service request source for a NVIC interrupt node */
void XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source)
{
XMC_ASSERT("XMC_SCU_SetInterruptControl: Invalid irq_number", irq_number < 32);
XMC_ASSERT("XMC_SCU_SetInterruptControl: Invalid source", (source >> 8) == irq_number);
source &= 0x3U;
if (irq_number < 16U)
{
SCU_GENERAL->INTCR0 = (SCU_GENERAL->INTCR0 & ~(SCU_GENERAL_INTCR_INTSEL_Msk << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size))) |
(source << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size));
}
else
{
irq_number &= 0x0fU;
SCU_GENERAL->INTCR1 = (SCU_GENERAL->INTCR1 & ~(SCU_GENERAL_INTCR_INTSEL_Msk << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size))) |
(source << (irq_number * SCU_GENERAL_INTCR_INTSEL_Size));
}
}
#endif
#endif /* UC_FAMILY == XMC1 */

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/**
* @file xmc_acmp.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial <br>
* 2015-02-20:
* - Removed unused declarations<br>
* 2015-05-08:
* - Fixed sequence problem of low power mode in XMC_ACMP_Init() API<br>
* - Fixed wrong register setting in XMC_ACMP_SetInput() API<br>
* - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
* Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.<br>
* 2015-06-04:
* - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
* - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below<br>
* (a)XMC_ACMP_EnableReferenceDivider <br>
* (b)XMC_ACMP_DisableReferenceDivider <br>
* (c)XMC_ACMP_SetInput <br>
* - Optimized enable and disable API's and moved to header file as static inline APIs.
* - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure.
* 2015-06-20:
* - Removed definition of GetDriverVersion API
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_acmp.h>
/* If ACMP is available*/
#if defined (COMPARATOR)
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_ACMP_INSTANCE_1 (1U) /* Instance number for Slice-1 */
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* API to initialize an instance of ACMP module */
void XMC_ACMP_Init(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_CONFIG_t *const config)
{
XMC_ASSERT("XMC_ACMP_Init:NULL Configuration", (config != (XMC_ACMP_CONFIG_t *)NULL))
XMC_ASSERT("XMC_ACMP_Init:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
XMC_ASSERT("XMC_ACMP_Init:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
/*
* Initializes the comparator with configuration supplied. Low power node setting is retained during initialization.
* All the instances passed are handled with low power setting, to avoid conditional check for ACMP0 instance.
* This reduces the code size. No side effects, because this register bit field is empty for other instances.
*/
peripheral->ANACMP[instance] = ((peripheral->ANACMP[instance] & (uint32_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk)) |
(uint32_t)config->anacmp;
}
/* API to select INP source */
void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, XMC_ACMP_INP_SOURCE_t source)
{
XMC_ASSERT("XMC_ACMP_SetInput:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
XMC_ASSERT("XMC_ACMP_SetInput:Wrong instance number", ((instance != XMC_ACMP_INSTANCE_1) &&
XMC_ACMP_CHECK_INSTANCE(instance)) )
XMC_ASSERT("XMC_ACMP_SetInput:Wrong input source", ((source == XMC_ACMP_INP_SOURCE_STANDARD_PORT) ||
(source == XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT)) )
/*
* Three options of Input Setting are listed below
* 1. The comparator inputs aren't connected to other comparator inputs
* 2. Can program the comparators to connect ACMP0.INP to ACMP1.INP in XMC1200 AA or XMC1300 AA
* Can program the comparators to connect ACMP0.INN to ACMP1.INP in XMC1200 AB or XMC1300 AB or XMC1400 AA
* 3. Can program the comparators to connect ACMP2.INP to ACMP1.INP
* 4. Can program the comparators to connect ACMP3.INP to ACMP1.INP in XMC1400
*/
peripheral->ANACMP[instance] = ((peripheral->ANACMP[instance] & (uint32_t)(~COMPARATOR_ANACMP0_ACMP0_SEL_Msk))) |
(uint32_t)source;
}
#endif /* #ifdef ACMP_AVAILABLE */

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/**
* @file xmc_bccu.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-19:
* - Initial draft <br>
*
* 2015-05-08:
* - Minor bug fixes in following APIs: XMC_BCCU_ConcurrentStartDimming(), XMC_BCCU_ConcurrentAbortDimming(),
* XMC_BCCU_SetGlobalDimmingLevel() <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* <b>Detailed description of file:</b><br>
* APIs for the functional blocks of BCCU have been defined:<br>
* -- GLOBAL configuration <br>
* -- Clock configuration, Function/Event configuration, Interrupt configuration <br>
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_bccu.h>
#if defined(BCCU0)
#include <xmc_scu.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_BCCU_NO_OF_CHANNELS (9U)
#define XMC_BCCU_CHANNEL_MASK ((0x1 << XMC_BCCU_NO_OF_CHANNELS)-1)
#define XMC_BCCU_NO_OF_DIM_ENGINE (3U)
#define XMC_BCCU_DIM_ENGINE_MASK (((0x1 << XMC_BCCU_NO_OF_DIM_ENGINE)-1))
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*********************************************************************************************************************
* GLOBAL DATA
********************************************************************************************************************/
/*********************************************************************************************************************
* LOCAL/UTILITY ROUTINES
********************************************************************************************************************/
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/*
* API to initialise the global resources of a BCCU module
*/
void XMC_BCCU_GlobalInit(XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t *const config)
{
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_BCCU0);
bccu->GLOBCON = config->globcon;
bccu->GLOBCLK = config->globclk;
bccu->GLOBDIM = config->global_dimlevel;
}
/*
* API to configure the global trigger mode & delay of a BCCU module
*/
void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay)
{
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);
bccu->GLOBCON |= ((uint32_t)mode | ((uint32_t)delay << BCCU_GLOBCON_TRDEL_Pos));
}
/*
* API to configure the trap input selection of a BCCU module
*/
void XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t input)
{
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPIS_Msk);
bccu->GLOBCON |= ((uint32_t)input << BCCU_GLOBCON_TRAPIS_Pos);
}
/*
* API to configure the trap edge selection of a BCCU module
*/
void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge)
{
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPED_Msk);
bccu->GLOBCON |= ((uint32_t)edge << BCCU_GLOBCON_TRAPED_Pos);
}
/*
* API to configure the suspend mode of a BCCU module
*/
void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t mode)
{
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_SUSCFG_Msk);
bccu->GLOBCON |= ((uint32_t)mode << BCCU_GLOBCON_SUSCFG_Pos);
}
/*
* API to configure number of consecutive zeroes allowed at modulator output (flicker watch-dog number)
*/
void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no)
{
XMC_ASSERT("XMC_BCCU_SetFlickerWDThreshold: Invalid threshold no", (threshold_no <= BCCU_GLOBCON_WDMBN_Msk));
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_WDMBN_Msk);
bccu->GLOBCON |= (uint32_t)(threshold_no << BCCU_GLOBCON_WDMBN_Pos);
}
/*
* API to configure the fast clock prescaler factor of a BCCU module
*/
void XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div)
{
XMC_ASSERT("XMC_BCCU_SetFastClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_FCLK_PS_Msk));
bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_FCLK_PS_Msk);
bccu->GLOBCLK |= div;
}
/*
* API to configure the dimmer clock prescaler factor of a BCCU module
*/
void XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div)
{
XMC_ASSERT("XMC_BCCU_SetDimClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_DCLK_PS_Msk));
bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_DCLK_PS_Msk);
bccu->GLOBCLK |= (uint32_t)(div << BCCU_GLOBCLK_DCLK_PS_Pos);
}
/*
* API to configure the modulator output (bit-time) clock prescaler factor of a BCCU module
*/
void XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div)
{
bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_BCS_Msk);
bccu->GLOBCLK |= ((uint32_t)div << BCCU_GLOBCLK_BCS_Pos);
}
/*
* API to enable the channels at the same time
*/
void XMC_BCCU_ConcurrentEnableChannels (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentEnableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHEN |= mask;
}
/*
* API to disable the channels at the same time
*/
void XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentDisableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHEN &= ~(uint32_t)(mask);
}
/*
* API to set the channel's output passive levels at the same time
*/
void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level)
{
XMC_ASSERT("XMC_BCCU_ConcurrentSetOutputPassiveLevel: Invalid channel mask", (chan_mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHOCON &= ~(uint32_t)(chan_mask);
bccu->CHOCON |= (chan_mask * (uint32_t)level);
}
/*
* API to enable the various types of traps at the same time
*/
void XMC_BCCU_ConcurrentEnableTrap (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentEnableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHOCON |= (uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);
}
/*
* API to disable the various types of traps at the same time
*/
void XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentDisableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHOCON &= ~(uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);
}
/*
* API to configure trigger mode and trigger delay at the same time, and also configure the channel enable
*/
void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig)
{
uint32_t reg;
XMC_ASSERT("XMC_BCCU_ConcurrentConfigTrigger: Invalid channel mask", (trig->mask_chans <= XMC_BCCU_CHANNEL_MASK));
bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);
bccu->GLOBCON |= ((uint32_t)trig->mode | ((uint32_t)trig->delay << BCCU_GLOBCON_TRDEL_Pos));
reg = 0U;
reg |= trig->mask_chans;
reg |= ((uint32_t)trig->mask_trig_lines << BCCU_CHTRIG_TOS0_Pos);
bccu->CHTRIG = reg;
}
/*
* API to start the linear walk of the channels to change towards target intensity at the same time
*/
void XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentStartLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHSTRCON |= (uint32_t)(mask);
}
/*
* API to abort the linear walk of the channels at the same time
*/
void XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentAbortLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
bccu->CHSTRCON |= (uint32_t)(mask << BCCU_CHSTRCON_CH0A_Pos);
}
/*
* API to enable the dimming engines at the same time
*/
void XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentEnableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
bccu->DEEN = (uint32_t)(mask);
}
/*
* API to enable the dimming engines at the same time
*/
void XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentDisableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
bccu->DEEN &= ~(uint32_t)(mask);
}
/*
* API to start the dimming engines at the same time to change towards target dim level
*/
void XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentStartDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
bccu->DESTRCON = (uint32_t)(mask);
}
/*
* API to abort the dimming engines at the same time
*/
void XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask)
{
XMC_ASSERT("XMC_BCCU_ConcurrentAbortDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
bccu->DESTRCON = (uint32_t)(mask << BCCU_DESTRCON_DE0A_Pos);
}
/*
* API to configure the dim level of a dimming engine
*/
void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level)
{
XMC_ASSERT("XMC_BCCU_SetGlobalDimmingLevel: Invalid global dimming level", (level <= BCCU_GLOBDIM_GLOBDIM_Msk));
bccu->GLOBDIM = level;
}
/*
* API to enable a specific channel
*/
void XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no)
{
XMC_ASSERT("XMC_BCCU_EnableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHEN |= (uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);
}
/*
* API to disable a specific channel
*/
void XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no)
{
XMC_ASSERT("XMC_BCCU_DisableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHEN &= ~(uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);
}
/*
* API to set the specific channel's passive level
*/
void XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level)
{
XMC_ASSERT("XMC_BCCU_SetOutputPassiveLevel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHOCON |= ((uint32_t)level << chan_no);
}
/*
* API to enable the specific channel trap
*/
void XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no)
{
XMC_ASSERT("XMC_BCCU_EnableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHOCON |= (uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);
}
/*
* API to disable the specific channel trap
*/
void XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no)
{
XMC_ASSERT("XMC_BCCU_DisableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHOCON &= ~(uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);
}
/*
* API to configure specific channel trigger enable and trigger line.
*/
void XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line)
{
uint32_t reg;
XMC_ASSERT("XMC_BCCU_EnableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_TOS0_Msk << chan_no);
reg = (uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);
reg |= ((uint32_t)trig_line << (BCCU_CHTRIG_TOS0_Pos + chan_no));
bccu->CHTRIG |= reg;
}
/*
* API to disable specific channel
*/
void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no)
{
XMC_ASSERT("XMC_BCCU_DisableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);
}
/*
* API to initialise the channel of a BCCU module
*/
void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config)
{
channel->CHCONFIG = config->chconfig;
channel->PKCMP = config->pkcmp;
channel->PKCNTR = config->pkcntr;
}
/*
* API to configure channel trigger edge and force trigger edge
*/
void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en)
{
uint32_t reg;
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_TRED_Msk | BCCU_CH_CHCONFIG_ENFT_Msk);
reg = ((uint32_t)edge << BCCU_CH_CHCONFIG_TRED_Pos);
reg |= (uint32_t)(force_trig_en << BCCU_CH_CHCONFIG_ENFT_Pos);
channel->CHCONFIG |= reg;
}
/*
* API to configure the linear walker clock prescaler factor of a BCCU channel
*/
void XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_LINPRES_Msk);
channel->CHCONFIG |= (uint32_t)(clk_div << BCCU_CH_CHCONFIG_LINPRES_Pos);
}
/*
* API to set channel target intensity
*/
void XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int)
{
channel->INTS = ch_int;
}
/*
* API to retrieve the channel actual intensity
*/
uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel)
{
return (uint32_t)(channel->INT & BCCU_CH_INT_CHINT_Msk);
}
/*
* API to enable packer. Also configures packer threshold, off-time and on-time compare levels
*/
void XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, uint32_t on_comp)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk | BCCU_CH_CHCONFIG_PKTH_Msk);
channel->CHCONFIG |= thresh;
channel->PKCMP = (off_comp | (uint32_t)(on_comp << BCCU_CH_PKCMP_ONCMP_Pos));
channel->CHCONFIG |= (uint32_t)BCCU_CH_CHCONFIG_PEN_Msk;
}
/*
* API to configure packer threshold
*/
void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PKTH_Msk);
channel->CHCONFIG |= val;
}
/*
* API to configure packer off-time compare level
*/
void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level)
{
channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_OFFCMP_Msk);
channel->PKCMP |= level;
}
/*
* API to configure packer on-time compare level.
*/
void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level)
{
channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_ONCMP_Msk);
channel->PKCMP |= (level << BCCU_CH_PKCMP_ONCMP_Pos);
}
/*
* API to disable a packer.
*/
void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk);
}
/*
* API to set packer off-time counter value
*/
void XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val)
{
channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_OFFCNTVAL_Msk);
channel->PKCNTR |= cnt_val;
}
/*
* API to set packer on-time counter value
*/
void XMC_BCCU_CH_SetPackerOnCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val)
{
channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_ONCNTVAL_Msk);
channel->PKCNTR |= (uint32_t)(cnt_val << BCCU_CH_PKCNTR_ONCNTVAL_Pos);
}
/*
* API to select the dimming engine of a channel
*/
void XMC_BCCU_CH_SelectDimEngine (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_DIMMING_SOURCE_t sel)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DSEL_Msk);
channel->CHCONFIG |= ((uint32_t)sel << BCCU_CH_CHCONFIG_DSEL_Pos);
}
/*
* API to bypass the dimming engine. And the brightness of channel is depending only on
* intensity of the channel.
*/
void XMC_BCCU_CH_EnableDimmingBypass (XMC_BCCU_CH_t *const channel)
{
channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);
}
/*
* API to disable the bypass of dimming engine. And the brightness of channel is depending
* on intensity of channel and dimming level of dimming engine.
*/
void XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel)
{
channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);
}
/*
* API to initialise a specific dimming engine of a BCCU module
*/
void XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CONFIG_t *const config)
{
dim_engine->DTT = config->dtt;
}
/*
* API to set dimming engine target dim level
*/
void XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level)
{
dim_engine->DLS = level;
}
/*
* API to configure the dimming clock prescaler factor of a dimming engine
*/
void XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div)
{
dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DIMDIV_Msk);
dim_engine->DTT |= div;
}
/*
* API to configure the dimming curve
*/
void XMC_BCCU_DIM_ConfigDimCurve (XMC_BCCU_DIM_t *const dim_engine, uint32_t dither_en, XMC_BCCU_DIM_CURVE_t sel)
{
uint32_t reg;
dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DTEN_Msk | BCCU_DE_DTT_CSEL_Msk);
reg = (uint32_t)(dither_en << BCCU_DE_DTT_DTEN_Pos);
reg |= ((uint32_t)sel << BCCU_DE_DTT_CSEL_Pos);
dim_engine->DTT |= reg;
}
#endif /* BCCU0 */

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@ -0,0 +1,744 @@
/**
* @file xmc_can.c
* @date 2016-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-05-20:
* - New API added: XMC_CAN_MO_ReceiveData() <br>
* - XMC_CAN_MO_Config() signature has changed <br>
* - Minor fix in XMC_CAN_TXFIFO_ConfigMOSlaveObject(). <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2015-09-01:
* - Removed fCANB clock support <br>
*
* 2015-09-08:
* - Fixed bug in XMC_CAN_Init() <br>
*
* 2016-06-07:
* - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller
*
* 2015-06-20:
* - Fixed bug in XMC_CAN_MO_Config() <br>
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_can.h"
#if defined(CAN)
#include "xmc_scu.h"
__STATIC_INLINE uint32_t max(uint32_t a, uint32_t b)
{
return (a > b) ? a : b;
}
__STATIC_INLINE uint32_t min(uint32_t a, uint32_t b)
{
return (a < b) ? a : b;
}
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Baudrate Configuration */
void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node,
const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time)
{
uint32_t temp_brp = 12U ;
uint32_t temp_tseg1 = 12U;
uint32_t best_brp = 0U;
uint32_t best_tseg1 = 1U;
uint32_t best_tseg2 = 0U;
uint32_t best_tbaud = 0U;
uint32_t best_error = 10000U;
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: rate not supported", (can_bit_time->baudrate < 1000000U) ||
(can_bit_time->baudrate >= 100000U));
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported",
can_bit_time->can_frequency <= 120000000U);
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported",
can_bit_time->can_frequency > 5000000U);
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: sample point not supported",
(can_bit_time->sample_point < 10000U) && ((can_bit_time->sample_point > 0U)));
/*
* Bit timing & sampling
* Tq = (BRP+1)/Fcan if DIV8 = 0
* Tq = 8*(BRP+1)/Fcan if DIV8 = 1
* TSync = 1.Tq
* TSeg1 = (TSEG1+1)*Tq >= 3Tq
* TSeg2 = (TSEG2+1)*Tq >= 2Tq
* Bit Time = TSync + TSeg1 + TSeg2 >= 8Tq
*
* Resynchronization:
*
* Tsjw = (SJW + 1)*Tq
* TSeg1 >= Tsjw + Tprop
* TSeg2 >= Tsjw
*/
/* search for best baudrate */
for (temp_brp = 1U; temp_brp <= 64U; temp_brp++)
{
uint32_t f_quanta = (uint32_t)((can_bit_time->can_frequency * 10U) / temp_brp);
uint32_t temp_tbaud = (uint32_t)(f_quanta / (can_bit_time->baudrate));
uint32_t temp_baudrate;
uint32_t error;
if((temp_tbaud % 10U) > 5U)
{
temp_tbaud = (uint32_t)(temp_tbaud / 10U);
temp_tbaud++;
}
else
{
temp_tbaud = (uint32_t)(temp_tbaud / 10U);
}
if(temp_tbaud > 0U)
{
temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U));
}
else
{
temp_baudrate = f_quanta / 10U;
temp_tbaud = 1;
}
if(temp_baudrate >= can_bit_time->baudrate)
{
error = temp_baudrate - can_bit_time->baudrate;
}
else
{
error = can_bit_time->baudrate - temp_baudrate;
}
if ((temp_tbaud <= 20U) && (best_error > error))
{
best_brp = temp_brp;
best_tbaud = temp_tbaud;
best_error = (error);
if (error < 1000U)
{
break;
}
}
}
/* search for best sample point */
best_error = 10000U;
for (temp_tseg1 = 64U; temp_tseg1 >= 3U; temp_tseg1--)
{
uint32_t tempSamplePoint = ((temp_tseg1 + 1U) * 10000U) / best_tbaud;
uint32_t error;
if (tempSamplePoint >= can_bit_time->sample_point)
{
error = tempSamplePoint - can_bit_time->sample_point;
}
else
{
error = can_bit_time->sample_point - tempSamplePoint;
}
if (best_error > error)
{
best_tseg1 = temp_tseg1;
best_error = error;
}
if (tempSamplePoint < (can_bit_time->sample_point))
{
break;
}
}
best_tseg2 = best_tbaud - best_tseg1 - 1U;
XMC_CAN_NODE_EnableConfigurationChange(can_node);
/* Configure bit timing register */
can_node->NBTR = (((uint32_t)(best_tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) |
((((uint32_t)((uint32_t)(can_bit_time->sjw)-1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk)|
(((uint32_t)(best_tseg1-1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk)|
(((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk)|
(((uint32_t)0U << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk);
XMC_CAN_NODE_DisableConfigurationChange(can_node);
}
/* Function to allocate message object from free list to node list */
void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num)
{
/* wait while panel operation is in progress. */
while (XMC_CAN_IsPanelControlReady(obj) == false)
{
/*Do nothing*/
};
/* Panel Command for allocation of MO to node list */
XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U));
}
/* Disable XMC_CAN Peripheral */
void XMC_CAN_Disable(XMC_CAN_t *const obj)
{
/* Disable CAN Module */
obj->CLC = CAN_CLC_DISR_Msk;
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN);
#endif
}
/* Enable XMC_CAN Peripheral */
void XMC_CAN_Enable(XMC_CAN_t *const obj)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN);
#endif
/* Enable CAN Module */
obj->CLC &= ~(uint32_t)CAN_CLC_DISR_Msk;
while (obj->CLC & CAN_CLC_DISS_Msk)
{
/*Do nothing*/
};
}
#if defined(MULTICAN_PLUS)
uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj)
{
uint32_t frequency;
switch(XMC_CAN_GetBaudrateClockSource(obj))
{
#if UC_FAMILY == XMC4
case XMC_CAN_CANCLKSRC_FPERI:
frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
break;
#else
case XMC_CAN_CANCLKSRC_MCLK:
frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
break;
#endif
case XMC_CAN_CANCLKSRC_FOHP:
frequency = OSCHP_GetFrequency();
break;
default:
frequency = 0;
break;
}
return frequency;
}
void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency)
{
uint32_t step_n, step_f;
bool normal_divider;
uint32_t freq_n, freq_f;
uint32_t step;
uint32_t can_frequency_khz;
uint32_t peripheral_frequency_khz;
XMC_CAN_DM_t can_divider_mode;
uint32_t peripheral_frequency;
/*Enabling the module*/
XMC_CAN_Enable(obj);
XMC_CAN_SetBaudrateClockSource(obj, clksrc);
peripheral_frequency = XMC_CAN_GetBaudrateClockFrequency(obj);
XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency);
/* Normal divider mode */
step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U);
freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n));
/* Fractional divider mode */
can_frequency_khz = (uint32_t) (can_frequency >> 6);
peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6);
step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U ));
freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U);
freq_f = freq_f << 6;
normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f);
step = (normal_divider != 0U) ? step_n : step_f;
can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL;
obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk);
obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos);
}
void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source)
{
obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ;
}
XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj)
{
return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos));
}
#else
/* Initialization of XMC_CAN GLOBAL Object */
void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency)
{
uint32_t step_n, step_f;
bool normal_divider;
uint32_t freq_n, freq_f;
uint32_t step;
uint32_t can_frequency_khz;
uint32_t peripheral_frequency_khz;
XMC_CAN_DM_t can_divider_mode;
uint32_t peripheral_frequency = (XMC_SCU_CLOCK_GetPeripheralClockFrequency());
XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency);
/*Enabling the module*/
XMC_CAN_Enable(obj);
/* Normal divider mode */
step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U);
freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n));
/* Fractional divider mode */
can_frequency_khz = (uint32_t) (can_frequency >> 6);
peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6);
step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U ));
freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U);
freq_f = freq_f << 6;
normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f);
step = (normal_divider != 0U) ? step_n : step_f;
can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL;
obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk);
obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos);
}
#endif
/* Sets the Identifier of the MO */
void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier)
{
if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)
{
can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) |
((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk);
}
else
{
can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) |
(can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk);
}
can_mo->can_identifier = can_identifier;
}
/* Gets the Identifier of the MO */
uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo)
{
uint32_t identifier;
if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)
{
identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk));
}
return identifier;
}
/* Gets the acceptance mask for the CAN MO. */
uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo)
{
uint32_t identifier_mask;
if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk)
&& ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk))
{
identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk));
}
return identifier_mask;
}
/* Gets the acceptance mask of the MO */
void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask)
{
if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk)
&& ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk))
{
can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) |
(can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos);
}
else
{
can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) |
(can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk);
}
can_mo->can_id_mask = can_id_mask;
}
/* Initialization of XMC_CAN MO Object */
void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo)
{
uint32_t reg;
/* Configure MPN */
uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U;
uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos));
can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk);
can_mo->can_mo_ptr->MOIPR |= set;
if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) &&
(can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) ||
((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) &&
(can_mo->can_mo_type != XMC_CAN_MO_TYPE_TRANSMSGOBJ)))
{
; /*Do nothing*/
}
else
{
/* Disable Message object */
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk;
if (can_mo->can_id_mode == (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS)
{
reg = can_mo->mo_ar;
reg &= (uint32_t) ~(CAN_MO_MOAR_ID_Msk);
reg |= (can_mo->can_identifier << XMC_CAN_MO_MOAR_STDID_Pos);
can_mo->can_mo_ptr->MOAR = reg;
reg = can_mo->mo_amr;
reg &= (uint32_t) ~(CAN_MO_MOAMR_AM_Msk);
reg |= (can_mo->can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos);
can_mo->can_mo_ptr->MOAMR = reg;
}
else
{
can_mo->can_mo_ptr->MOAR = can_mo->mo_ar;
can_mo->can_mo_ptr->MOAMR = can_mo->mo_amr;
}
/* Check whether message object is transmit message object */
if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ)
{
/* Set MO as Transmit message object */
XMC_CAN_MO_UpdateData(can_mo);
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETDIR_Msk;
}
else
{
/* Set MO as Receive message object and set RXEN bit */
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESDIR_Msk;
}
/* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */
can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk |
CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk);
}
}
/* Update of XMC_CAN Object */
XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
/* Check whether message object is transmit message object */
if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ)
{
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk;
/* Configure data length */
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) |
(((uint32_t) can_mo->can_data_length << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk);
/* Configure Data registers*/
can_mo->can_mo_ptr->MODATAL = can_mo->can_data[0];
can_mo->can_mo_ptr->MODATAH = can_mo->can_data[1];
/* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */
can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk| CAN_MO_MOCTR_SETMSGVAL_Msk |CAN_MO_MOCTR_RESRTSEL_Msk);
error = XMC_CAN_STATUS_SUCCESS;
}
else
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
return error;
}
/* This function is will put a transmit request to transmit message object */
XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint32_t mo_type = (uint32_t)(((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos);
uint32_t mo_transmission_ongoing = (uint32_t) ((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos;
/* check if message is disabled */
if (mo_type == 0U)
{
error = XMC_CAN_STATUS_MO_DISABLED;
}
/* check if transmission is ongoing on message object */
else if (mo_transmission_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* set TXRQ bit */
can_mo->can_mo_ptr-> MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* This function is will read the message object data bytes */
XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint8_t rx_pnd = 0U;
uint8_t new_data = 0U;
uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos;
uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos;
/* check if message object is a receive message object */
if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ)
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
/* check if reception is ongoing on message object */
else if (mo_recepcion_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* read message parameters */
do
{
can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL;
can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH;
rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos);
new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos);
} while ((rx_pnd != 0U) && (new_data != 0U));
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* This function is will read the message object data bytes */
XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint8_t rx_pnd = 0U;
uint8_t new_data = 0U;
uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos;
uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos;
/* check if message object is a receive message object */
if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ)
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
/* check if reception is ongoing on message object */
else if (mo_recepcion_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* read message parameters */
do
{
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk;
if ((((can_mo->can_mo_ptr->MOAR) & CAN_MO_MOAR_IDE_Msk) >> CAN_MO_MOAR_IDE_Pos) == 0U)
{
can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS;
can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos;
can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos;
if(can_mo->can_ide_mask == 1U)
{
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk);
}
}
else
{
can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS;
can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_ID_Msk);
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk);
can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos;
}
can_mo->can_data_length = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOFCR) & CAN_MO_MOFCR_DLC_Msk) >> CAN_MO_MOFCR_DLC_Pos);
can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL;
can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH;
rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos);
new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos);
} while ((rx_pnd != 0U) && (new_data != 0U));
can_mo->can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* Function to enable node event */
void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event)
{
if(event != XMC_CAN_NODE_EVENT_CFCIE)
{
can_node->NCR |= (uint32_t)event;
}
else
{
can_node->NFCR |= (uint32_t)event;
}
}
/* Function to disable node event */
void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event)
{
if(event != XMC_CAN_NODE_EVENT_CFCIE)
{
can_node->NCR &= ~(uint32_t)event;
}
else
{
can_node->NFCR &= ~(uint32_t)event;
}
}
/* Function to transmit MO from the FIFO */
XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint32_t mo_type = ((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos);
uint32_t mo_transmission_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos;
uint32_t mo_cur = (uint32_t)(can_mo->can_mo_ptr-> MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos;
CAN_MO_TypeDef* mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL));
/* check if message is disabled */
if (mo_type == 0U)
{
error = XMC_CAN_STATUS_MO_DISABLED;
}
/* check if transmission is ongoing on message object */
else if (mo_transmission_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
mo->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* Function to initialize the transmit FIFO MO base object */
void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x2U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_BOT_Msk |
CAN_MO_MOFGPR_TOP_Msk |
CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t) CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t) CAN_MO_MOFGPR_TOP_Msk);
}
/* Function to Initialize the receive FIFO MO base object */
void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x1U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~( uint32_t)(CAN_MO_MOFGPR_BOT_Msk |
CAN_MO_MOFGPR_TOP_Msk |
CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk);
}
/* Function to Initialize the FIFO MO slave object */
void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x3U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk);
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk|
CAN_MO_MOCTR_RESTXEN1_Msk;
}
/* Function to Initialize the Gateway Source Object */
void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway)
{
can_mo->can_mo_ptr->MOFCR = (((uint32_t)0x4U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk) |
((((uint32_t)can_gateway.gateway_data_frame_send) << CAN_MO_MOFCR_GDFS_Pos) & (uint32_t)CAN_MO_MOFCR_GDFS_Msk) |
((((uint32_t)can_gateway.gateway_data_length_code_copy) << CAN_MO_MOFCR_DLCC_Pos) & (uint32_t)CAN_MO_MOFCR_DLCC_Msk) |
((((uint32_t)can_gateway.gateway_identifier_copy) << CAN_MO_MOFCR_IDC_Pos) & (uint32_t)CAN_MO_MOFCR_IDC_Msk) |
((((uint32_t)can_gateway.gateway_data_copy) << CAN_MO_MOFCR_DATC_Pos) & (uint32_t)CAN_MO_MOFCR_DATC_Msk) ;
can_mo->can_mo_ptr->MOFGPR = (uint32_t)((((uint32_t)can_gateway.gateway_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk));
}
#endif /* XMC_CAN_H */

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/**
* @file xmc_common.c
* @date 2017-02-25
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2017-02-25:
* - Remove the need to define XMC_USER_ASSERT_FUNCTION
* - XMC_AssertHandler fixed compilation warnings
*
* @endcond
*
*/
#include "xmc_common.h"
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
struct list
{
struct list *next;
};
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
#if defined(XMC_ASSERT_ENABLE)
__WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line)
{
XMC_UNUSED_ARG(msg);
XMC_UNUSED_ARG(file);
XMC_UNUSED_ARG(line);
while(1)
{
/* Endless loop */
}
}
#endif
void XMC_LIST_Init(XMC_LIST_t *list)
{
*list = NULL;
}
void *XMC_LIST_GetHead(XMC_LIST_t *list)
{
return *list;
}
void *XMC_LIST_GetTail(XMC_LIST_t *list)
{
struct list *tail;
if (*list == NULL)
{
tail = NULL;
}
else
{
for (tail = (struct list *)*list; tail->next != NULL; tail = tail->next)
{
/* Loop through the list */
}
}
return tail;
}
void XMC_LIST_Add(XMC_LIST_t *list, void *item)
{
struct list *tail;
((struct list *)item)->next = NULL;
tail = (struct list *)XMC_LIST_GetTail(list);
if (tail == NULL)
{
*list = item;
}
else
{
tail->next = (struct list *)item;
}
}
void XMC_LIST_Remove(XMC_LIST_t *list, void *item)
{
struct list *right, *left;
if (*list != NULL)
{
left = NULL;
for(right = (struct list *)*list; right != NULL; right = right->next)
{
if(right == item)
{
if(left == NULL)
{
/* First on list */
*list = right->next;
}
else
{
/* Not first on list */
left->next = right->next;
}
right->next = NULL;
break;
}
left = right;
}
}
}
void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item)
{
if (prev_item == NULL)
{
((struct list *)new_item)->next = (struct list *)*list;
*list = new_item;
}
else
{
((struct list *)new_item)->next = ((struct list *)prev_item)->next;
((struct list *)prev_item)->next = (struct list *)new_item;
}
}
void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
/* Initialize head, next points to tail, previous to NULL and the priority is MININT */
prioarray->items[prioarray->size].next = prioarray->size + 1;
prioarray->items[prioarray->size].previous = -1;
prioarray->items[prioarray->size].priority = INT32_MAX;
/* Initialize tail, next points to NULL, previous is the head and the priority is MAXINT */
prioarray->items[prioarray->size + 1].next = -1;
prioarray->items[prioarray->size + 1].previous = prioarray->size;
prioarray->items[prioarray->size + 1].priority = INT32_MIN;
}
void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority)
{
int32_t next;
int32_t previous;
XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size));
next = XMC_PRIOARRAY_GetHead(prioarray);
while (XMC_PRIOARRAY_GetItemPriority(prioarray, next) > priority)
{
next = XMC_PRIOARRAY_GetItemNext(prioarray, next);
}
previous = prioarray->items[next].previous;
prioarray->items[item].next = next;
prioarray->items[item].previous = previous;
prioarray->items[item].priority = priority;
prioarray->items[previous].next = item;
prioarray->items[next].previous = item;
}
void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
int32_t next;
int32_t previous;
XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size));
next = prioarray->items[item].next;
previous = prioarray->items[item].previous;
prioarray->items[previous].next = next;
prioarray->items[next].previous = previous;
}

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/**
* @file xmc_eru.c
* @date 2016-03-10
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API <br>
*
* 2016-03-10:
* - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
*
* @endcond
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_eru.h"
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define ERU_EXISEL_BITSIZE (4UL) /* Used to set the input for path A and path B based on the channel */
#define ERU_EXISEL_INPUT_BITSIZE (2UL)
#define XMC_ERU_ETL_CHECK_INPUT_A(input) \
((input == XMC_ERU_ETL_INPUT_A0) || \
(input == XMC_ERU_ETL_INPUT_A1) || \
(input == XMC_ERU_ETL_INPUT_A2) || \
(input == XMC_ERU_ETL_INPUT_A3))
#define XMC_ERU_ETL_CHECK_INPUT_B(input) \
((input == XMC_ERU_ETL_INPUT_B0) || \
(input == XMC_ERU_ETL_INPUT_B1) || \
(input == XMC_ERU_ETL_INPUT_B2) || \
(input == XMC_ERU_ETL_INPUT_B3))
#define XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode) \
((mode == XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL) || \
(mode == XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL))
#define XMC_ERU_ETL_CHECK_EVENT_SOURCE(source) \
((source == XMC_ERU_ETL_SOURCE_A) || \
(source == XMC_ERU_ETL_SOURCE_B) || \
(source == XMC_ERU_ETL_SOURCE_A_OR_B) || \
(source == XMC_ERU_ETL_SOURCE_A_AND_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_OR_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_AND_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_A_OR_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_A_AND_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B))
#define XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge) \
((edge == XMC_ERU_ETL_EDGE_DETECTION_DISABLED) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_RISING) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_FALLING) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_BOTH))
#define XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(channel) \
((channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3))
#define XMC_ERU_OGU_CHECK_PATTERN_INPUT(input) \
((input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT0) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT1) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT2) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT3))
#define XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(trigger) \
((trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER1) || \
(trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER2) || \
(trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER3))
#define XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(service) \
((service == XMC_ERU_OGU_SERVICE_REQUEST_DISABLED) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH))
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected ERU_ETLx channel with the config structure. */
void XMC_ERU_ETL_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_CONFIG_t *const config)
{
XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U));
XMC_ERU_Enable(eru);
eru->EXISEL = (eru->EXISEL &
~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) |
(config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE));
eru->EXICON[channel] = config->raw;
}
/* Initializes the selected ERU_OGUy channel with the config structure. */
void XMC_ERU_OGU_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_CONFIG_t *const config)
{
XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Channel Number", (channel < 4U));
XMC_ERU_Enable(eru);
eru->EXOCON[channel] = config->raw;
}
/* Configures the event source for path A and path B, with selected input_a and input_b respectively.*/
void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_INPUT_A_t input_a,
const XMC_ERU_ETL_INPUT_B_t input_b)
{
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid A", XMC_ERU_ETL_CHECK_INPUT_A(input_a));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid B", XMC_ERU_ETL_CHECK_INPUT_B(input_b));
eru->EXISEL = (eru->EXISEL & ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) |
(((uint32_t)input_a | (uint32_t)(input_b << ERU_EXISEL_INPUT_BITSIZE)) << (channel * ERU_EXISEL_BITSIZE));
}
/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of
EXICONx(x = [0 to 3]) register */
void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_SOURCE_t source)
{
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Source", XMC_ERU_ETL_CHECK_EVENT_SOURCE(source));
eru->EXICON_b[channel].SS = (uint8_t)source;
}
/* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.*/
void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection)
{
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Trigger Edge", XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge_detection));
eru->EXICON_b[channel].ED = (uint8_t)edge_detection;
}
/* Returns the configured event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register. */
XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Channel Number", (channel < 4U));
return ((XMC_ERU_ETL_EDGE_DETECTION_t)(eru->EXICON_b[channel].ED));
}
/* Set the status flag bit(FL) in EXICONx(x = [0 to 3]). */
void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode)
{
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Status Flag Mode", XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode));
eru->EXICON_b[channel].LD = (uint8_t)mode;
}
/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = [0 to 3]) by setting (OCS and PE) bit fields. */
void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger)
{
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Output Channel", XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(trigger));
eru->EXICON_b[channel].OCS = (uint8_t)trigger;
eru->EXICON_b[channel].PE = (uint8_t)true;
}
/* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = [0 to 3]). */
void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].PE = false;
}
/* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3) and GEEN bits. */
void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input)
{
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Pattern input", XMC_ERU_OGU_CHECK_PATTERN_INPUT(input));
eru->EXOCON_b[channel].IPEN = (uint8_t)input;
eru->EXOCON_b[channel].GEEN = true;
}
/* Disable the pattern detection by clearing (GEEN) bit. */
void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Channel Number", (channel < 4U));
eru->EXOCON_b[channel].GEEN = false;
}
/* Configures peripheral trigger input, by setting (ISS) bit. */
void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger)
{
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input",
XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger));
eru->EXOCON_b[channel].ISS = (uint8_t)peripheral_trigger;
}
/* Disables event generation based on peripheral trigger by clearing (ISS) bit. */
void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Channel Number", (channel < 4U));
eru->EXOCON_b[channel].ISS = (uint8_t)0;
}
/* Configures the gating scheme for service request generation by setting (GP) bit. */
void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_SERVICE_REQUEST_t mode)
{
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Service Request Mode", XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(mode));
eru->EXOCON_b[channel].GP = (uint8_t)mode;
}

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/**
* @file xmc_gpio.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <xmc_gpio.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode)
{
XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_IsModeValid(mode));
port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)));
port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U));
}
void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl)
{
XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl));
port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U));
port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U);
}

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/**
* @file xmc_i2c.c
* @date 2015-10-02
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
- Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-08-14:
* - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies <br>
*
* 2015-09-01:
* - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2015-10-02:
* - Fixed 10bit addressing
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_i2c.h>
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_I2C_7BIT_ADDR_Pos (8U) /**< 7-bit address position */
#define TRANSMISSION_MODE (3U) /**< The shift control signal is considered active
without referring to the actual signal level. Data
frame transfer is possible after each edge of the signal.*/
#define WORDLENGTH (7U) /**< Word length */
#define SET_TDV (1U) /**< Transmission data valid */
#define XMC_I2C_10BIT_ADDR_MASK (0x7C00U) /**< Address mask for 10-bit mode */
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
typedef enum XMC_I2C_CH_TDF
{
XMC_I2C_CH_TDF_MASTER_SEND = 0U,
XMC_I2C_CH_TDF_SLAVE_SEND = (uint32_t)1U << 8U,
XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK = (uint32_t)2U << 8U,
XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK = (uint32_t)3U << 8U,
XMC_I2C_CH_TDF_MASTER_START = (uint32_t)4U << 8U,
XMC_I2C_CH_TDF_MASTER_RESTART = (uint32_t)5U << 8U,
XMC_I2C_CH_TDF_MASTER_STOP = (uint32_t)6U << 8U
} XMC_I2C_CH_TDF_t;
typedef enum XMC_I2C_CH_MAX_SPEED
{
XMC_I2C_CH_MAX_SPEED_STANDARD = 100000U,
XMC_I2C_CH_MAX_SPEED_FAST = 400000U
} XMC_I2C_CH_MAX_SPEED_t;
typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING
{
XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD = 10U,
XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST = 25U
} XMC_I2C_CH_CLOCK_OVERSAMPLINGS_t;
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */
void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config)
{
XMC_USIC_CH_Enable(channel);
/* Data format configuration */
channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */
((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */
USIC_CH_SCTR_FLE_Msk | /* unlimited data flow */
USIC_CH_SCTR_SDIR_Msk | /* MSB shifted first */
USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */
XMC_I2C_CH_SetSlaveAddress(channel, config->address);
(void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate);
/* Enable transfer buffer */
channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk;
/* Clear status flags */
channel->PSCR = 0xFFFFFFFFU;
/* Disable parity generation */
channel->CCR = 0x0U;
}
/* Sets the slave address */
void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address)
{
if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP)
{
channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U);
}
else
{
channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos;
}
}
/* Read the slave address */
uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel)
{
uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk;
if ((address & 0xffU) == 0U)
{
address = address >> XMC_I2C_7BIT_ADDR_Pos;
}
else
{
address = (address & 0xffU) | ((address >> 1) & 0x0300U);
}
return (uint16_t)address;
}
/* Sets the baudrate and oversampling based on standard speed or fast speed */
XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate)
{
XMC_I2C_CH_STATUS_t status;
status = XMC_I2C_CH_STATUS_ERROR;
if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD)
{
channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk;
if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_I2C_CH_STATUS_OK;
}
}
else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST)
{
channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk;
if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_I2C_CH_STATUS_OK;
}
}
else
{
status = XMC_I2C_CH_STATUS_ERROR;
}
return status;
}
/* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
{
uint32_t temp;
temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START;
if (command == XMC_I2C_CH_CMD_READ)
{
temp |= 0x1U;
}
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = temp;
}
else
{
channel->IN[0U] = temp;
}
}
/* Sends master repeated start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
{
uint32_t tmp;
tmp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_RESTART;
if (command == XMC_I2C_CH_CMD_READ)
{
tmp |= 0x1U;
}
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = tmp;
}
else
{
channel->IN[0U] = tmp;
}
}
/* Sends master stop command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
}
else
{
channel->IN[0U] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
}
}
/* Sends master send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
}
}
/* Sends slave send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
}
}
/* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
}
}
/* Sends master receive nack command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
}
}
/* Reads the data from RBUF if FIFO size is 0 otherwise from OUTR. */
uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel)
{
uint8_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint8_t)channel->RBUF;
}
else
{
retval = (uint8_t)channel->OUTR;
}
return retval;
}
/* Sets the operating mode of USIC to IDLE */
XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_I2C_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_IICMode |= ((event) & 0x41fc0000U);
}
void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U);
}

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/**
* @file xmc_i2s.c
* @date 2015-06-30
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-08-21:
* - Initial <br>
*
* 2015-09-01:
* - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration<br>
*
* 2015-09-14:
* - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length.
* - Removed parity configuration<br>
*
* 2015-09-28:
* - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs <br>
*
* 2015-11-04:
* - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API <br>
*
* 2016-06-30:
* - Modified XMC_I2S_CH_Init:
* + change default passive level to 0
* + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length.
* - Modified XMC_I2S_CH_SetBaudrate:
* + Optional Master clock output signal generated with a fixed phase relation to SCLK.
*
* @endcond
*
*/
/**
*
* @brief I2S driver for XMC microcontroller family
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_i2s.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */
#define XMC_I2S_CH_OVERSAMPLING (4UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected I2S channel with the config structure. */
void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config)
{
XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) &&
(config->data_delayed_sclk_periods < config->frame_length));
XMC_USIC_CH_Enable(channel);
if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
{
/* Configure baud rate */
(void)XMC_I2S_CH_SetBaudrate(channel, config->baudrate);
}
/* Configuration of USIC Shift Control */
/* Transmission Mode (TRM) = 1 */
channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) |
(uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) |
(uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) |
USIC_CH_SCTR_SDIR_Msk;
/* Configuration of USIC Transmit Control/Status Register */
/* TBUF Data Enable (TDEN) = 1 */
/* TBUF Data Single Shot Mode (TDSSM) = 1 */
/* WA mode enabled(WAMD) = 1 */
channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk |
USIC_CH_TCSR_SELMD_Msk |
USIC_CH_TCSR_FLEMD_Msk |
USIC_CH_TCSR_HPCMD_Msk))) |
USIC_CH_TCSR_WAMD_Msk |
(0x01UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk);
if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
{
/* Configuration of Protocol Control Register */
channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk;
}
/* Configuration of Protocol Control Register */
channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk |
(uint32_t)config->wa_inversion) |
((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos);
XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length);
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
}
XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
{
XMC_I2S_CH_STATUS_t status;
status = XMC_I2S_CH_STATUS_ERROR;
if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
{
channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) |
(0x2UL << USIC_CH_BRG_CTQSEL_Pos)) |
USIC_CH_BRG_PPPEN_Msk;
status = XMC_I2S_CH_STATUS_OK;
}
}
return status;
}
void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length)
{
uint32_t sclk_cycles_system_word_length_temp;
uint8_t dctq_temp;
uint8_t pctq_temp;
uint8_t dctq = 1U;
uint8_t pctq = 1U;
uint8_t best_error = 64U;
uint8_t error;
XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U));
for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++)
{
for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++)
{
sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp);
if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length)
{
dctq = dctq_temp;
pctq = pctq_temp;
break;
}
if (sclk_cycles_system_word_length_temp > sclk_cycles_system_word_length)
{
error = (uint8_t)(sclk_cycles_system_word_length_temp - sclk_cycles_system_word_length);
}
else
{
error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp);
}
if(error < best_error)
{
best_error = error;
dctq = dctq_temp;
pctq = pctq_temp;
}
}
}
channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PCTQ_Msk))) |
(uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) |
(uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos)));
}
/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
XMC_I2S_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[(uint32_t)channel_number << 4] = data;
}
else
{
channel->IN[(uint32_t)channel_number << 4] = data;
}
}
/* Reads the data from the buffers based on the FIFO mode selection. */
uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_I2S_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_IISMode |= ((event >> 2U) & 0x8070U);
}
void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U);
}

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/**
* @file xmc_ledts.c
* @date 2017-02-25
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
* - New API added: XMC_LEDTS_SetActivePADNo() <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2017-02-25:
* - XMC_LEDTS_InitGlobal() fixed compilation warnings
*
* <b>Detailed description of file:</b><br>
* APIs for the functional blocks of LEDTS have been defined:<br>
* -- GLOBAL (APIs prefixed with LEDTS_GLOBAL_) <br>
* -- Clock configuration, Function/Event configuration, Interrupt configuration
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_ledts.h>
#if defined(LEDTS0)
#include "xmc_scu.h"
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_LEDTS_CLOCK_NOT_RUNNING 0U
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*********************************************************************************************************************
* GLOBAL DATA
********************************************************************************************************************/
/*********************************************************************************************************************
* LOCAL/UTILITY ROUTINES
********************************************************************************************************************/
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/**
* Initialization of global register
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config)
{
XMC_ASSERT("XMC_LEDTS_InitGlobal:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_InitGlobal:Null Pointer", (config != (XMC_LEDTS_GLOBAL_CONFIG_t *)NULL));
if (ledts == XMC_LEDTS0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0);
#endif
}
#if defined(LEDTS1)
else if (ledts == XMC_LEDTS1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1);
#endif
}
#endif
#if defined(LEDTS2)
else if (ledts == XMC_LEDTS2)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_LEDTS_InitGlobal:Invalid Module Pointer", 0);
}
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
ledts->GLOBCTL = config->globctl;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for LED-driving function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config)
{
XMC_ASSERT("XMC_LEDTS_LED_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_LED_Init:Null Pointer", (config != (XMC_LEDTS_LED_CONFIG_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
ledts->FNCTL &= ~(LEDTS_FNCTL_COLLEV_Msk | LEDTS_FNCTL_NR_LEDCOL_Msk);
ledts->FNCTL |= (config->fnctl);
/* Enable LED function */
ledts->GLOBCTL |= LEDTS_GLOBCTL_LD_EN_Msk;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for basic Touch-Sense control function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_BASIC_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
reg = ~(LEDTS_FNCTL_ACCCNT_Msk | LEDTS_FNCTL_TSCCMP_Msk | LEDTS_FNCTL_TSCTRR_Msk | LEDTS_FNCTL_TSCTRSAT_Msk |
LEDTS_FNCTL_NR_TSIN_Msk);
ledts->FNCTL &= (reg);
ledts->FNCTL |= (config->fnctl);
/* Enable TS function */
ledts->GLOBCTL |= LEDTS_GLOBCTL_TS_EN_Msk;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for advanced Touch-Sense control function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_ADVANCED_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
reg = ~(LEDTS_GLOBCTL_MASKVAL_Msk | LEDTS_GLOBCTL_FENVAL_Msk);
ledts->GLOBCTL &= (reg);
ledts->GLOBCTL |= (config->globctl);
reg = ~(LEDTS_FNCTL_PADT_Msk | LEDTS_FNCTL_PADTSW_Msk | LEDTS_FNCTL_EPULL_Msk | LEDTS_FNCTL_TSOEXT_Msk);
ledts->FNCTL &= (reg);
ledts->FNCTL |= (config->fnctl);
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Starts LEDTS-counter
*/
void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler)
{
XMC_ASSERT("XMC_LEDTS_Start_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->GLOBCTL |= prescaler<<16U;
}
/**
* Stops LEDTS-counter
*/
void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts)
{
XMC_ASSERT("XMC_LEDTS_Stop_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->GLOBCTL &= 0x0000FFFF;
}
/**
* Reads time interrupt flags
*/
uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts)
{
XMC_ASSERT("XMC_LEDTS_ReadInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
return (ledts->EVFR & 0xF);
}
/**
* Set the active pad number
*/
void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_SetActivePADNo:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->FNCTL;
reg &= ~(LEDTS_FNCTL_PADT_Msk);
reg |= (uint32_t)pad_num;
ledts->FNCTL = reg;
}
/**
* Clears interrupt indication flags
*/
void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask)
{
XMC_ASSERT("XMC_LEDTS_ClearInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->EVFR = (interrupt_mask << LEDTS_EVFR_CTSF_Pos);
}
/**
* Programming of registers to output pattern on an LED column in LED matrix
*/
void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)column) >> 2;
uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_LED_Line_Pattern:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LINE[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= pattern << bit_shift_count;
ledts->LINE[reg_index] = reg;
}
/**
* Programming of registers to adjust brightness of an LED column in LED matrix
*/
void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)column) >> 2;
uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_Column_Brightness:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LDCMP[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= brightness << bit_shift_count;
ledts->LDCMP[reg_index] = reg;
}
/**
* Programming of registers to set common oscillation window size for touch-sense inputs
*/
void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_Set_Common_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LDCMP[1];
reg &= ~LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk;
reg |= (common_size << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos);
ledts->LDCMP[1] = reg;
}
/**
* Checking the previous active function or LED column status
*/
uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts)
{
uint32_t fncol_read;
XMC_ASSERT("XMC_LEDTS_Read_FNCOL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
fncol_read = ledts->FNCTL & LEDTS_FNCTL_FNCOL_Msk;
fncol_read >>= LEDTS_FNCTL_FNCOL_Pos;
return fncol_read;
}
/**
* Set the number of LED column Enabled
*/
void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count)
{
XMC_ASSERT("XMC_LEDTS_SetNumOfLEDColumns:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->FNCTL &= ~(LEDTS_FNCTL_NR_LEDCOL_Msk);
ledts->FNCTL |= (count << LEDTS_FNCTL_NR_LEDCOL_Pos);
}
/**
* Reading recorded number of oscillation counts
*/
uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts)
{
uint16_t no_of_oscillations;
XMC_ASSERT("XMC_LEDTS_Read_TSVAL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
no_of_oscillations = (ledts->TSVAL & 0xFFFF);
return no_of_oscillations;
}
/**
* Programming of registers to adjust the size of oscillation window
*/
void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)touchpad) >> 2;
uint8_t bit_shift_count = ((uint8_t)touchpad & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->TSCMP[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= size << bit_shift_count;
ledts->TSCMP[reg_index] = reg;
}
#endif /* LEDTS0 */

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@ -0,0 +1,473 @@
/**
* @file xmc_math.c
* @date 2017-04-20
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
* - Updated copyright and change history section.
*
* 2015-09-23:
* - Added SQRT functions
*
* 2015-10-08:
* - Return values for sin(), cos(), sinh(), cosh(), arctan() are corrected.
*
* 2017-04-20:
* - Foward declaration of __aeabi_* to fix link time optimization (-flto) compilation errors
*
* @endcond
*
*/
/**
*
* @brief MATH driver - API implementation for XMC13 family MATH libraries. <br>
*
* <b>Detailed description of file</b> <br>
* APIs provided in this file cover the following functional blocks of MATH: <br>
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_math.h>
#if defined (MATH)
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/* Reciprocal of Circular gain in XMC_MATH_Q0_23_t format ((2^23)/1.646760258121) */
#define XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 (0x4DBA76U)
/* Reciprocal of Hyperbolic gain in XMC_MATH_Q1_22_t format ((2^22)/0.828159360960) */
#define XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 (0x4D47A1U)
/* Signed division is selected */
#define XMC_MATH_SIGNED_DIVISION ((uint32_t) 0 << MATH_DIVCON_USIGN_Pos)
/* Unsigned division is selected */
#define XMC_MATH_UNSIGNED_DIVISION ((uint32_t) 1 << MATH_DIVCON_USIGN_Pos)
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/*********************************************************************************************************************
* GLOBAL DATA
********************************************************************************************************************/
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*********************************************************************************************************************
* LOCAL ROUTINES
********************************************************************************************************************/
/*********************************************************************************************************************
* API IMPLEMENTATION - Utility functions
********************************************************************************************************************/
/* Utility function to check if the DIV unit is busy */
bool XMC_MATH_DIV_IsBusy(void)
{
bool status;
if (MATH->DIVST & MATH_DIVST_BSY_Msk)
{
status = true; /* DIV unit is busy running a division operation */
}
else
{
status = false; /* DIV unit is idle */
}
return (status);
}
/* Utility function to check if the CORDIC unit is busy */
bool XMC_MATH_CORDIC_IsBusy(void)
{
bool status;
if (MATH->STATC & MATH_STATC_BSY_Msk)
{
status = true; /* CORDIC unit is busy running an operation */
}
else
{
status = false; /* CORDIC unit is idle */
}
return (status);
}
/* This functions returns the status of a requested event */
bool XMC_MATH_GetEventStatus(const XMC_MATH_EVENT_t event)
{
bool status;
if (MATH->EVFR & (uint32_t) event)
{
status = true; /* Requested event has been detected */
}
else
{
status = false; /* Requested event has not been detected */
}
return (status);
}
#ifndef XMC_MATH_DISABLE_DIV_ABI
/* Forward prototypes. */
uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor) __attribute__((externally_visible));
int32_t __aeabi_idiv(int32_t dividend, int32_t divisor) __attribute__((externally_visible));
uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor) __attribute__((externally_visible));
int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor) __attribute__((externally_visible));
/***********************************************************************************************************************
* API IMPLEMENTATION - aeabi routines
**********************************************************************************************************************/
/* This function performs unsigned integer division */
uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor)
{
MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
return ((uint32_t) MATH->QUOT);
}
/* This function performs signed integer division */
int32_t __aeabi_idiv(int32_t dividend, int32_t divisor)
{
MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
return ((int32_t) MATH->QUOT);
}
/* This function performs unsigned integer division modulo */
uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor)
{
uint64_t remainder;
MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
remainder = ((uint64_t) MATH->RMD) << 32U;
return (remainder | MATH->QUOT);
}
/* This function performs signed integer division modulo */
int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor)
{
uint64_t remainder;
uint64_t result;
MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
remainder = ((uint64_t) MATH->RMD) << 32U;
result = (remainder | MATH->QUOT);
return ((int64_t) result);
}
#endif
/***********************************************************************************************************************
* API IMPLEMENTATION - Blocking functions
**********************************************************************************************************************/
/* This function computes the cosine of a given angle in radians */
XMC_MATH_Q0_23_t XMC_MATH_CORDIC_Cos(XMC_MATH_Q0_23_t angle_in_radians)
{
int32_t result;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
result = ((int32_t)MATH->CORRX) >> MATH_CORRX_RESULT_Pos;
return ((XMC_MATH_Q0_23_t) result);
}
/* This function computes the sine of a given angle in radians */
XMC_MATH_Q0_23_t XMC_MATH_CORDIC_Sin(XMC_MATH_Q0_23_t angle_in_radians)
{
int32_t result;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
result = ((int32_t)MATH->CORRY) >> MATH_CORRY_RESULT_Pos;
return ((XMC_MATH_Q0_23_t) result);
}
/* This function computes the tangent of a given angle in radians */
XMC_MATH_Q0_11_t XMC_MATH_CORDIC_Tan(XMC_MATH_Q0_23_t angle_in_radians)
{
uint32_t result;
MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
(uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE; /* Chain the results of CORDIC operation to DIV unit */
MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos; /* Right Shifts Divisor by 11 places prior to division */
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
result = MATH->QUOT;
return ((XMC_MATH_Q0_11_t) result);
}
/* This function computes the arc tangent of a given angle in radians */
XMC_MATH_Q0_23_t XMC_MATH_CORDIC_ArcTan(XMC_MATH_Q8_15_t x, XMC_MATH_Q8_15_t y)
{
uint32_t result;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR;
MATH->CORDZ = 0U; /* Clear register */
MATH->CORDY = ((uint32_t) y) << MATH_CORDY_DATA_Pos;
MATH->CORDX = ((uint32_t) x) << MATH_CORDX_DATA_Pos;
result = ((int32_t)MATH->CORRZ) >> MATH_CORRZ_RESULT_Pos;
return ((XMC_MATH_Q0_23_t) result);
}
/* This function computes the hyperbolic cosine of a given angle in radians */
XMC_MATH_Q1_22_t XMC_MATH_CORDIC_Cosh(XMC_MATH_Q0_23_t angle_in_radians)
{
int32_t result;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
result = ((int32_t)MATH->CORRX) >> MATH_CORRX_RESULT_Pos;
return ((XMC_MATH_Q1_22_t) result);
}
/* This function computes the hyperbolic sine of a given angle in radians */
XMC_MATH_Q1_22_t XMC_MATH_CORDIC_Sinh(XMC_MATH_Q0_23_t angle_in_radians)
{
int32_t result;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
result = ((int32_t)MATH->CORRY) >> MATH_CORRY_RESULT_Pos;
return ((XMC_MATH_Q1_22_t) result);
}
/* This function computes the hyperbolic tangent of a given angle in radians */
XMC_MATH_Q0_11_t XMC_MATH_CORDIC_Tanh(XMC_MATH_Q0_23_t angle_in_radians)
{
uint32_t result;
MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
(uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE; /* Chain the results of CORDIC operation to DIV unit */
MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos; /* Right Shifts Divisor by 11 places prior to division */
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
result = MATH->QUOT;
return ((XMC_MATH_Q0_11_t) result);
}
/***********************************************************************************************************************
* API IMPLEMENTATION - Non blocking functions
**********************************************************************************************************************/
/* This function computes the cosine of a given angle in radians */
void XMC_MATH_CORDIC_CosNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
}
/* This function computes the sine of a given angle in radians */
void XMC_MATH_CORDIC_SinNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
}
/* This function computes the tangent of a given angle in radians */
void XMC_MATH_CORDIC_TanNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
(uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE; /* Chain the results of CORDIC operation to DIV unit */
MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos; /* Right Shifts Divisor by 11 places prior to division */
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
}
/* This function computes the arc tangent of a given value */
void XMC_MATH_CORDIC_ArcTanNB(XMC_MATH_Q8_15_t x, XMC_MATH_Q8_15_t y)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR;
MATH->CORDZ = 0U; /* Clear register */
MATH->CORDY = ((uint32_t) y) << MATH_CORDY_DATA_Pos;
MATH->CORDX = ((uint32_t) x) << MATH_CORDX_DATA_Pos;
}
/* This function computes the hyperbolic cosine of a given angle in radians */
void XMC_MATH_CORDIC_CoshNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
}
/* This function computes the hyperbolic sine of a given angle in radians */
void XMC_MATH_CORDIC_SinhNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
}
/* This function computes the hyperbolic tangent of a given angle in radians */
void XMC_MATH_CORDIC_TanhNB(XMC_MATH_Q0_23_t angle_in_radians)
{
MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
(uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE; /* Chain the results of CORDIC operation to DIV unit */
MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos; /* Right Shifts Divisor by 11 places prior to division */
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
(uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
MATH->CORDY = 0U; /* Clear register */
MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
}
/* This function performs division for given two unsigned arguments */
void XMC_MATH_DIV_UnsignedDivNB(uint32_t dividend, uint32_t divisor)
{
MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
}
/* This function performs division for given two signed arguments */
void XMC_MATH_DIV_SignedDivNB(int32_t dividend, int32_t divisor)
{
MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
}
/* This function performs modulo operation for given two unsigned arguments */
void XMC_MATH_DIV_UnsignedModNB(uint32_t dividend, uint32_t divisor)
{
MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
}
/* This function performs modulo operation for given two signed arguments */
void XMC_MATH_DIV_SignedModNB(int32_t dividend, int32_t divisor)
{
MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
MATH->DVD = dividend;
MATH->DVS = divisor;
}
int16_t XMC_MATH_CORDIC_Q15_Sqrt(int16_t x)
{
int32_t temp;
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t)XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC |
(uint32_t)XMC_MATH_CORDIC_ROTVEC_MODE_VECTORING;
temp = (int32_t)x << 15; /* Q30 to handle numbers > 1.0 */
MATH->CORDY = (temp - 0x10000000U); /* x - 0.25 */
MATH->CORDX = (temp + 0x10000000U); /* x + 0.25 */
return (int16_t)(((MATH->CORRX >> 14) * 39568) >> 16); /* Q16 * Q15 */
}
int32_t XMC_MATH_CORDIC_Q31_Sqrt(int32_t x)
{
MATH->STATC = 0U; /* Clear register */
MATH->CON = (uint32_t)XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC |
(uint32_t)XMC_MATH_CORDIC_ROTVEC_MODE_VECTORING;
x >>= 1; /* Q30 to handle numbers > 1.0 */
MATH->CORDY = (x - 0x10000000U); /* x - 0.25 */
MATH->CORDX = (x + 0x10000000U); /* x + 0.25 */
return ((MATH->CORRX >> 14) * 39568); /* Q16 * Q15 */
}
#endif /* end of #if defined (MATH) */

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/**
* @file xmc_pau.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API
* @endcond
*
*/
/**
*
* @brief PAU driver for XMC1 microcontroller family.
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_pau.h"
#if defined(PAU)
/**********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Enable peripheral access
*/
void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral)
{
uint32_t reg_num;
reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
XMC_PAU->PRIVDIS[reg_num] &= (uint32_t)~((uint32_t)peripheral & 0x0fffffffUL);
}
/*
* Disable peripheral access
*/
void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral)
{
uint32_t reg_num;
reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
XMC_PAU->PRIVDIS[reg_num] |= (uint32_t)((uint32_t)peripheral & 0x0fffffffUL);
}
/*
* Check if peripheral access is enabled
*/
bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral)
{
uint32_t reg_num;
reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
return (bool)(XMC_PAU->PRIVDIS[reg_num] & ((uint32_t)peripheral & 0x0fffffffUL));
}
/*
* Check if peripheral is available
*/
bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral)
{
uint32_t reg_num;
reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
return (bool)(XMC_PAU->AVAIL[reg_num] & ((uint32_t)peripheral & 0x0fffffffUL));
}
#endif /* defined(PAU) */

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/**
* @file xmc_posif.c
* @date 2017-02-25
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-02-18:
* - Initial version
*
* 2015-02-20:
* - Driver description added <BR>
*
* 2015-04-30:
* - XMC_POSIF_Enable and XMC_POSIF_Disable APIs updated for POSIF1 peripheral check <BR>
*
* 2015-06-19:
* - Removed GetDriverVersion API <BR>
*
* 2017-02-25:
* - XMC_POSIF_Enable() and XMC_POSIF_Disable() fixed compilation warnings
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_posif.h>
/* POSIF is not available on XMC1100 and XMC1200 */
#if defined(POSIF0)
#include <xmc_scu.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */
#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */
/*********************************************************************************************************************
* LOCAL ROUTINES
********************************************************************************************************************/
#ifdef XMC_ASSERT_ENABLE
__STATIC_INLINE bool XMC_POSIF_IsPeripheralValid(const XMC_POSIF_t *const peripheral)
{
bool tmp;
tmp = (peripheral == POSIF0);
#if defined(POSIF1)
tmp |= (peripheral == POSIF1);
#endif
return tmp;
}
#endif
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* API to enable the POSIF module */
void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral)
{
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU);
#endif
if (peripheral == POSIF0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
}
#if defined(POSIF1)
else if (peripheral == POSIF1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
}
}
/* API to disable the POSIF module */
void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral)
{
if (peripheral == POSIF0)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
}
#if defined(POSIF1)
else if (peripheral == POSIF1)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
}
}
/* API to initialize POSIF global resources */
void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *const config)
{
XMC_ASSERT("XMC_POSIF_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_Init:NULL Pointer", (config != (XMC_POSIF_CONFIG_t *)NULL) );
/* Enable the POSIF module */
XMC_POSIF_Enable(peripheral);
/* Stop POSIF */
XMC_POSIF_Stop(peripheral);
/* Program the operational mode, input selectors and debounce filter */
peripheral->PCONF = config->pconf;
}
/* API to initialize hall sensor interface */
XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config)
{
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_HSC_Init:Invalid module pointer\n", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_HSC_Init:NULL Pointer\n", (config != (XMC_POSIF_HSC_CONFIG_t *)NULL) );
if (XMC_POSIF_MODE_HALL_SENSOR == (XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) )
{
peripheral->PCONF |= config->hall_config;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to initialize quadrature decoder interface */
XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config)
{
uint8_t reg;
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_QD_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_QD_Init:NULL Pointer", (config != (XMC_POSIF_QD_CONFIG_t *)NULL) );
reg = (uint8_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk);
if (((uint32_t)XMC_POSIF_MODE_QD == reg) || ((uint32_t)XMC_POSIF_MODE_MCM_QD == reg))
{
/* Program the quadrature mode */
peripheral->PCONF |= (uint32_t)(config->mode) << POSIF_PCONF_QDCM_Pos;
peripheral->QDC = config->qdc;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to initialize multi-channel mode.
* This is used in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode
*/
XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config)
{
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_MCM_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_MCM_Init:NULL Pointer", (config != (XMC_POSIF_MCM_CONFIG_t *)NULL) );
if ((XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) != XMC_POSIF_MODE_QD)
{
peripheral->PCONF |= config->mcm_config;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to configure input source */
void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0,
const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2)
{
uint32_t reg;
XMC_ASSERT("XMC_POSIF_SelectInputSource:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input0", (input0 < XMC_POSIF_INSEL_MAX));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input1", (input1 < XMC_POSIF_INSEL_MAX));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input2", (input2 < XMC_POSIF_INSEL_MAX));
reg = (uint32_t)((((uint32_t)input0 << POSIF_PCONF_INSEL0_Pos) & (uint32_t)POSIF_PCONF_INSEL0_Msk) |
(((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) |
(((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk));
peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)XMC_POSIF_PCONF_INSEL_Msk) | reg);
}
/* API to select an interrupt node */
void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr)
{
uint32_t reg;
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) );
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong SR ID", (sr <= XMC_POSIF_SR_ID_1) );
reg = peripheral->PFLGE;
reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos));
reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos);
peripheral->PFLGE = reg;
}
#endif /* #if defined(POSIF0) */

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/**
* @file xmc_prng.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Removed GetDriverVersion API <br>
*
* 2015-06-20
* - Removed definition of GetDriverVersion API <br>
*
* @endcond
*/
#include "xmc_prng.h"
#if defined (PRNG)
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Initializes the PRNG peripheral with the settings in the
* initialization structure XMC_PRNG_INIT_t
*/
XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng)
{
volatile uint16_t read_warm_up;
uint16_t reg_val, iter;
XMC_PRNG_INIT_STATUS_t status = XMC_PRNG_INITIALIZED;
XMC_ASSERT("XMC_PRNG_Init:Null Pointer", (prng != (XMC_PRNG_INIT_t *)NULL));
/* Configure block size for key loading mode */
XMC_PRNG_SetRandomDataBlockSize(XMC_PRNG_RDBS_WORD);
/* Enable key loading mode */
XMC_PRNG_EnableKeyLoadingMode();
/* Load key words (80 bits) and wait till RDV is set */
for (iter = (uint16_t)0UL; iter < (uint16_t)5UL; iter++)
{
XMC_PRNG_LoadKeyWords(prng->key_words[iter]);
while (PRNG_CHK_RDV_Msk != XMC_PRNG_CheckValidStatus());
}
XMC_PRNG_EnableStreamingMode();
/* Warm up phase: Read and discard 64 bits */
read_warm_up = PRNG->WORD;
read_warm_up = PRNG->WORD;
read_warm_up = PRNG->WORD;
reg_val = PRNG->WORD;
read_warm_up &= reg_val;
/* Configure block size either byte (8 bit) or word (16 bit) */
XMC_PRNG_SetRandomDataBlockSize(prng->block_size);
/*
* Checks for reset value for "random data block size". If reset,
* PRNG is not initialized
*/
if ((uint16_t)XMC_PRNG_RDBS_RESET == (PRNG->CTRL & (uint16_t)PRNG_CTRL_RDBS_Msk))
{
status = XMC_PRNG_NOT_INITIALIZED;
}
return status;
}
#endif /* #if defined (PRNG) */

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/**
* @file xmc_rtc.c
* @date 2015-05-19
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API
*
* 2016-05-19:
* - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
*
* @endcond
*
*/
/**
*
* @brief RTC driver for XMC microcontroller family.
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_scu.h"
#include "xmc_rtc.h"
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_RTC_MAXSECONDS (59U) /**< RTC time : Maximum seconds */
#define XMC_RTC_MAXMINUTES (59U) /**< RTC time : Maximum minutes */
#define XMC_RTC_MAXHOURS (23U) /**< RTC time : Maximum hours */
#define XMC_RTC_MAXDAYS (31U) /**< RTC time : Maximum days */
#define XMC_RTC_MAXDAYSOFWEEK (7U) /**< RTC time : Maximum days of week */
#define XMC_RTC_MAXMONTH (12U) /**< RTC time : Maximum month */
#define XMC_RTC_MAXYEAR (0xFFFFU) /**< RTC time : Maximum year */
#define XMC_RTC_MAXPRESCALER (0xFFFFU) /**< RTC time : Maximum prescaler */
#define XMC_RTC_YEAR_OFFSET (1900U) /**< RTC year offset : Year offset */
#if (UC_FAMILY == XMC4)
#define XMC_RTC_INIT_SEQUENCE (1U)
#endif
#if (UC_FAMILY == XMC1)
#define XMC_RTC_INIT_SEQUENCE (0U)
#endif
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Enables RTC peripheral to start counting time
*/
void XMC_RTC_Start(void)
{
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR |= (uint32_t)RTC_CTR_ENB_Msk;
}
/*
* Disables RTC peripheral to start counting time
*/
void XMC_RTC_Stop(void)
{
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR &= ~(uint32_t)RTC_CTR_ENB_Msk;
}
/*
* Sets the RTC module prescaler value
*/
void XMC_RTC_SetPrescaler(uint16_t prescaler)
{
XMC_ASSERT("XMC_RTC_SetPrescaler:Wrong prescaler value", (prescaler < XMC_RTC_MAXPRESCALER));
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR = (RTC->CTR & ~(uint32_t)RTC_CTR_DIV_Msk) |
((uint32_t)prescaler << (uint32_t)RTC_CTR_DIV_Pos);
}
/*
* Sets the RTC_TIM0, RTC_TIM1 registers with time values
*/
void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const time)
{
XMC_ASSERT("XMC_RTC_SetTime:Wrong seconds value", ((uint32_t)time->seconds < XMC_RTC_MAXSECONDS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong minutes value", ((uint32_t)time->minutes < XMC_RTC_MAXMINUTES));
XMC_ASSERT("XMC_RTC_SetTime:Wrong hours value", ((uint32_t)time->hours < XMC_RTC_MAXHOURS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong month day value", ((uint32_t)time->days < XMC_RTC_MAXDAYS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong week day value", ((uint32_t)time->daysofweek < XMC_RTC_MAXDAYSOFWEEK));
XMC_ASSERT("XMC_RTC_SetTime:Wrong month value", ((uint32_t)time->month < XMC_RTC_MAXMONTH));
XMC_ASSERT("XMC_RTC_SetTime:Wrong year value", ((uint32_t)time->year < XMC_RTC_MAXYEAR));
#if (XMC_RTC_INIT_SEQUENCE == 1U)
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = time->raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM1 = time->raw1;
#endif
#if (XMC_RTC_INIT_SEQUENCE == 0U)
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = time->raw0;
RTC->TIM1 = time->raw1; ;
#endif
}
/*
* Gets the RTC module time value
*/
void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time)
{
time->raw0 = RTC->TIM0;
time->raw1 = RTC->TIM1;
}
/*
* Sets the RTC module time values in standard format
*/
void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime)
{
XMC_RTC_TIME_t time;
time.seconds = stdtime->tm_sec;
time.minutes = stdtime->tm_min;
time.hours = stdtime->tm_hour;
time.days = stdtime->tm_mday - 1;
time.month = stdtime->tm_mon;
time.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
time.daysofweek = stdtime->tm_wday;
XMC_RTC_SetTime(&time);
}
/*
* Gets the RTC module time values in standard format
*/
void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime)
{
XMC_RTC_TIME_t time;
time.raw0 = RTC->TIM0;
time.raw1 = RTC->TIM1;
stdtime->tm_sec = (int8_t)time.seconds;
stdtime->tm_min = (int8_t)time.minutes;
stdtime->tm_hour = (int8_t)time.hours;
stdtime->tm_mday = ((int8_t)time.days + (int8_t)1);
stdtime->tm_mon = (int8_t)time.month;
stdtime->tm_year = (int32_t)time.year - (int32_t)XMC_RTC_YEAR_OFFSET;
stdtime->tm_wday = (int8_t)time.daysofweek;
}
/*
* Sets the RTC module alarm time value
*/
void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm)
{
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong seconds value", ((uint32_t)alarm->seconds < XMC_RTC_MAXSECONDS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong minutes value", ((uint32_t)alarm->minutes < XMC_RTC_MAXMINUTES));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong hours value", ((uint32_t)alarm->hours < XMC_RTC_MAXHOURS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong days value", ((uint32_t)alarm->days < XMC_RTC_MAXDAYS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong month value", ((uint32_t)alarm->month < XMC_RTC_MAXMONTH));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong year value", ((uint32_t)alarm->year < XMC_RTC_MAXYEAR));
#if (XMC_RTC_INIT_SEQUENCE == 1U)
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = alarm->raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM1 = alarm->raw1;
#endif
#if (XMC_RTC_INIT_SEQUENCE == 0U)
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = alarm->raw0;
RTC->ATIM1 = alarm->raw1;
#endif
}
/*
* Gets the RTC module alarm time value
*/
void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm)
{
alarm->raw0 = RTC->ATIM0;
alarm->raw1 = RTC->ATIM1;
}
/*
* Sets the RTC module alarm time value in standard format
*/
void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime)
{
XMC_RTC_ALARM_t alarm;
alarm.seconds = stdtime->tm_sec;
alarm.minutes = stdtime->tm_min;
alarm.hours = stdtime->tm_hour;
alarm.days = stdtime->tm_mday - 1;
alarm.month = stdtime->tm_mon;
alarm.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
XMC_RTC_SetAlarm(&alarm);
}
/*
* Gets the RTC module alarm time value in standard format
*/
void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime)
{
XMC_RTC_ALARM_t alarm;
alarm.raw0 = RTC->ATIM0;
alarm.raw1 = RTC->ATIM1;
stdtime->tm_sec = (int8_t)alarm.seconds;
stdtime->tm_min = (int8_t)alarm.minutes;
stdtime->tm_hour = (int8_t)alarm.hours;
stdtime->tm_mday = ((int8_t)alarm.days + (int8_t)1);
stdtime->tm_mon = (int8_t)alarm.month;
stdtime->tm_year = (int32_t)alarm.year - (int32_t)XMC_RTC_YEAR_OFFSET;
}
/*
* Gets the RTC periodic and alarm event(s) status
*/
uint32_t XMC_RTC_GetEventStatus(void)
{
return RTC->STSSR;
}

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/**
* @file xmc_spi.c
* @date 2015-11-04
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy
* - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2015-11-04:
* - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag <br>
* @endcond
*
*/
/**
*
* @brief SPI driver for XMC microcontroller family
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_spi.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_SPI_CH_OVERSAMPLING (2UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected SPI channel with the config structure. */
void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config)
{
XMC_USIC_CH_Enable(channel);
if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
{
/* Configure baud rate */
(void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING);
}
/* Configuration of USIC Shift Control */
/* Transmission Mode (TRM) = 1 */
/* Passive Data Level (PDL) = 1 */
channel->SCTR = USIC_CH_SCTR_PDL_Msk |
(0x1UL << USIC_CH_SCTR_TRM_Pos) |
(0x3fUL << USIC_CH_SCTR_FLE_Pos)|
(0x7UL << USIC_CH_SCTR_WLE_Pos);
/* Configuration of USIC Transmit Control/Status Register */
/* TBUF Data Enable (TDEN) = 1 */
/* TBUF Data Single Shot Mode (TDSSM) = 1 */
channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk |
(0x01UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk);
if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
{
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk |
USIC_CH_PCR_SSCMode_SELCTR_Msk |
(uint32_t)config->selo_inversion |
USIC_CH_PCR_SSCMode_FEM_Msk);
}
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
/* Set parity settings */
channel->CCR = (uint32_t)config->parity_mode;
}
XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
{
XMC_SPI_CH_STATUS_t status;
status = XMC_SPI_CH_STATUS_ERROR;
if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_SPI_CH_STATUS_OK;
}
}
return status;
}
/* Enable the selected slave signal by setting (SELO) bits in PCR register. */
void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave)
{
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
channel->PCR_SSCMode |= (uint32_t)slave;
}
/* Disable the slave signals by clearing (SELO) bits in PCR register. */
void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel)
{
XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS);
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
}
/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode)
{
channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) |
(((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk);
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[mode] = data;
}
else
{
channel->IN[mode] = data;
}
}
/* Reads the data from the buffers based on the FIFO mode selection. */
uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
/* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */
void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us)
{
uint32_t peripheral_clock;
uint32_t pdiv;
uint32_t step;
uint32_t fFD;
uint32_t fpdiv;
uint32_t divider_factor1 = 0U;
uint32_t divider_factor2 = 32U;
uint32_t divider_factor1_int = 0U;
uint32_t divider_factor1_int_min = 4U;
uint32_t divider_factor1_frac_min =100U;
uint32_t divider_factor1_frac = 0U;
uint32_t divider_factor2_temp = 0U;
peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos;
step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos;
fFD = (uint32_t)((peripheral_clock >> 10U) * step);
fpdiv= fFD/(1U+pdiv);
if(tinterword_delay_us < (128000000/fpdiv))
{
for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp)
{
divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000);
divider_factor1_frac = divider_factor1%100U;
if(divider_factor1_frac > 50)
{
divider_factor1_int = (divider_factor1/100U)+1;
divider_factor1_frac = (divider_factor1_int*100)-divider_factor1;
}
else
{
divider_factor1_int = (divider_factor1/100U);
}
if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min))
{
divider_factor1_frac_min = divider_factor1_frac;
divider_factor1_int_min = divider_factor1_int;
divider_factor2= divider_factor2_temp;
}
}
}
channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk |
USIC_CH_PCR_SSCMode_PCTQ1_Msk |
USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) |
(((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) |
(((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk);
}
XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_SPI_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_SSCMode |= ((event << 13U) & 0xe000U);
}
void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U);
}

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/**
* @file xmc_uart.c
* @date 2016-07-22
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - xmc_uart_ch_stop API implementation corrected.
* - Modified XMC_UART_CH_Stop() API for not setting to IDLE the channel if it is busy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2016-07-22:
* - Modified XMC_UART_CH_Init() to enable transfer status BUSY
* - Modified XMC_UART_CH_Stop() to check for transfer status
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_uart.h>
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_UART_CH_OVERSAMPLING (16UL)
#define XMC_UART_CH_OVERSAMPLING_MIN_VAL (4UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config)
{
uint32_t oversampling = XMC_UART_CH_OVERSAMPLING;
/* USIC channel switched on*/
XMC_USIC_CH_Enable(channel);
if(config->oversampling != 0U)
{
oversampling = (uint32_t)config->oversampling;
}
/* Configure baud rate */
(void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling);
/* Configure frame format
* Configure the number of stop bits
* Pulse length is set to 0 to have standard UART signaling,
* i.e. the 0 level is signaled during the complete bit time
* Sampling point set equal to the half of the oversampling period
* Enable Sample Majority Decision
* Enable Transfer Status BUSY
*/
channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) |
(((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) |
USIC_CH_PCR_ASCMode_SMD_Msk |
USIC_CH_PCR_ASCMode_RSTEN_Msk | USIC_CH_PCR_ASCMode_TSTEN_Msk);
/* Set passive data level, high
Set word length. Data bits - 1
If frame length is > 0, frame_lemgth-1; else, FLE = WLE (Data bits - 1)
Transmission Mode: The shift control signal is considered active if it
is at 1-level. This is the setting to be programmed to allow data transfers */
channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) |
((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk));
if (config->frame_length != 0U)
{
channel->SCTR |= (uint32_t)(((uint32_t)config->frame_length - 1UL) << USIC_CH_SCTR_FLE_Pos);
}
else
{
channel->SCTR |= (uint32_t)(((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_FLE_Pos);
}
/* Enable transfer buffer */
channel->TCSR = (0x1UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk;
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
/* Set parity settings */
channel->CCR = (uint32_t)config->parity_mode;
}
XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling)
{
XMC_UART_CH_STATUS_t status;
status = XMC_UART_CH_STATUS_ERROR;
if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, oversampling) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_UART_CH_STATUS_OK;
}
}
return status;
}
void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0UL)
{
/* Wait till the Transmit Buffer is free for transmission */
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
/* Clear the Transmit Buffer indication flag */
XMC_UART_CH_ClearStatusFlag(channel, (uint32_t)XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
/*Transmit data */
channel->TBUF[0U] = data;
}
else
{
channel->IN[0U] = data;
}
}
uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK;
if (((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) ||
((XMC_UART_CH_GetStatusFlag(channel) & XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY) != 0))
{
status = XMC_UART_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_ASCMode |= (event&0xf8U);
}
void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U);
}

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/**
* @file xmc_usic.c
* @date 2015-09-01
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
* - Documentation improved <br>
*
* 2015-05-08:
* - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-27:
* - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-08-28:
* - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-09-01:
* - Fixed warning in the asserts <br>
*
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_usic.h"
#include "xmc_scu.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define USIC_CH_INPR_Msk (0x7UL)
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel)
{
XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel));
if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1))
{
XMC_USIC_Enable(XMC_USIC0);
}
#if defined(USIC1)
else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1))
{
XMC_USIC_Enable(XMC_USIC1);
}
#endif
#if defined(USIC2)
else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1))
{
XMC_USIC_Enable(XMC_USIC2);
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0U/*Always*/);
}
/* USIC channel switched on*/
channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk);
while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U)
{
/* Wait till the channel is enabled */
}
/* Set USIC channel in IDLE mode */
channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk;
}
void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel)
{
channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_Msk);
}
XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling)
{
XMC_USIC_CH_STATUS_t status;
uint32_t peripheral_clock;
uint32_t clock_divider;
uint32_t clock_divider_min;
uint32_t pdiv;
uint32_t pdiv_int;
uint32_t pdiv_int_min;
uint32_t pdiv_frac;
uint32_t pdiv_frac_min;
/* The rate and peripheral clock are divided by 100 to be able to use only 32bit arithmetic */
if ((rate >= 100U) && (oversampling != 0U))
{
peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U;
rate = rate / 100U;
clock_divider_min = 1U;
pdiv_int_min = 1U;
pdiv_frac_min = 0x3ffU;
for(clock_divider = 1023U; clock_divider > 0U; --clock_divider)
{
pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling));
pdiv_int = pdiv >> 10U;
pdiv_frac = pdiv & 0x3ffU;
if ((pdiv_int < 1024U) && (pdiv_frac < pdiv_frac_min))
{
pdiv_frac_min = pdiv_frac;
pdiv_int_min = pdiv_int;
clock_divider_min = clock_divider;
}
}
channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL |
(clock_divider_min << USIC_CH_FDR_STEP_Pos);
channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PDIV_Msk |
USIC_CH_BRG_PCTQ_Msk |
USIC_CH_BRG_PPPEN_Msk)) |
((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) |
((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos);
status = XMC_USIC_CH_STATUS_OK;
}
else
{
status = XMC_USIC_CH_STATUS_ERROR;
}
return status;
}
void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
const uint16_t pdiv,
const uint32_t oversampling,
const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
{
XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U < pdiv) || (pdiv < 1024U)));
XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range", ((1U < oversampling) || (oversampling < 32U)));
/* Setting the external input frequency source through DX1 */
XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T);
/* Setting the trigger combination mode */
XMC_USIC_CH_SetInputTriggerCombinationMode(channel,XMC_USIC_CH_INPUT_DX1,combination_mode);
/* Configuring the dividers and oversampling */
channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PDIV_Msk |
USIC_CH_BRG_PCTQ_Msk |
USIC_CH_BRG_PPPEN_Msk)) |
(((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) |
(((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos);
}
void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel,
const uint32_t data_pointer,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk;
/* LOF = 0, A standard transmit buffer event occurs when the filling level equals the limit value and gets
* lower due to transmission of a data word
* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level
* from equal to below the limit, not the fact being below
*/
channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk |
USIC_CH_TBCTR_DPTR_Msk |
USIC_CH_TBCTR_SIZE_Msk)) |
(uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) |
(data_pointer << USIC_CH_TBCTR_DPTR_Pos) |
((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos));
}
void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel,
const uint32_t data_pointer,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk;
/* LOF = 1, A standard receive buffer event occurs when the filling level equals the limit value and gets bigger
* due to the reception of a new data word
*/
channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk |
USIC_CH_RBCTR_DPTR_Msk |
USIC_CH_RBCTR_LOF_Msk)) |
((limit << USIC_CH_RBCTR_LIMIT_Pos) |
(data_pointer << USIC_CH_RBCTR_DPTR_Pos) |
((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) |
(uint32_t)USIC_CH_RBCTR_LOF_Msk));
}
void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk;
/* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level
* from equal to below the limit, not the fact being below
*/
channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) |
(limit << USIC_CH_TBCTR_LIMIT_Pos) |
((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos));
}
void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk;
channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) |
(limit << USIC_CH_RBCTR_LIMIT_Pos) |
((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos));
}
void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_Enable(XMC_USIC_t *const usic)
{
if (usic == USIC0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
#endif
}
#if defined(USIC1)
else if (usic == USIC1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
#endif
}
#endif
#if defined(USIC2)
else if (usic == USIC2)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
#endif
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0/*Always*/);
}
}
void XMC_USIC_Disable(XMC_USIC_t *const usic)
{
if (usic == (XMC_USIC_t *)USIC0)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
#endif
}
#if defined(USIC1)
else if (usic == (XMC_USIC_t *)USIC1)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
#endif
}
#endif
#if defined(USIC2)
else if (usic == (XMC_USIC_t *)USIC2)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
#endif
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0/*Always*/);
}
}

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/**
* @file xmc_wdt.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API <br>
*
* @endcond
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_wdt.h"
#include "xmc_scu.h"
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Enables watchdog clock and releases watchdog reset. */
void XMC_WDT_Enable(void)
{
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_WDT);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT);
#endif
}
/* Disables watchdog clock and resets watchdog. */
void XMC_WDT_Disable(void)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT);
#endif
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_WDT);
#endif
}
/* Initializes and configures watchdog with configuration data pointed by \a config. */
void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config)
{
XMC_WDT_Enable();
WDT->CTR = config->wdt_ctr;
WDT->WLB = config->window_lower_bound;
WDT->WUB = config->window_upper_bound;
}

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/*********************************************************************************************************************
* @file startup_XMC1400.S
* @brief CMSIS Core Device Startup File for Infineon XMC1400 Device Series
* @version V1.1
* @date 05 Jan 2016
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history ********************************
* V1.0, Sep, 03, 2015 JFT:Initial version
* MCLK=8MHz, PCLK=16MHz
* V1.1, Jan, 05, 2016 JFT:Fix .reset section attributes
*
* @endcond
*/
/*****************************************************************************
* <h> Clock system handling by SSW
* <h> CLK_VAL1 Configuration
* <o0.0..9> FDIV Fractional Divider Selection <0-1023>
* <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024))
* <o0.10..17> IDIV Divider Selection <1-16>
* <i> Deafult: 6. Interger part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024) = 8MHz)
* <o0.18> PCLKSEL PCLK Clock Select
* <0=> PCLK = MCLK
* <1=> PCLK = 2 x MCLK
* <i> Deafult: 2 x MCLK
* <o0.19..21> RTCCLKSEL RTC Clock Select
* <0=> 32.768kHz standby clock
* <1=> 32.768kHz external clock from ERU0.IOUT0
* <2=> 32.768kHz external clock from ACMP0.OUT
* <3=> 32.768kHz external clock from ACMP1.OUT
* <4=> 32.768kHz external clock from ACMP2.OUT
* <5=> 32.768kHz XTAL clock via OSC_LP
* <6=> Reserved
* <7=> Reserved
* <i> Deafult: 32.768kHz standby clock
* <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
* </h>
*****************************************************************************/
#define CLKVAL1_SSW 0x00041800
/*****************************************************************************
* <h> CLK_VAL2 Configuration
* <o0.0> disable VADC and SHS Gating
* <o0.1> disable CCU80 Gating
* <o0.2> disable CCU40 Gating
* <o0.3> disable USIC0 Gating
* <o0.4> disable BCCU0 Gating
* <o0.5> disable LEDTS0 Gating
* <o0.6> disable LEDTS1 Gating
* <o0.7> disable POSIF0 Gating
* <o0.8> disable MATH Gating
* <o0.9> disable WDT Gating
* <o0.10> disable RTC Gating
* <o0.16> disable CCU81 Gating
* <o0.17> disable CCU41 Gating
* <o0.18> disable USIC1 Gating
* <o0.19> disable LEDTS2 Gating
* <o0.20> disable POSIF1 Gating
* <o0.21> disable MCAN0 Gating
* <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
* </h>
*****************************************************************************/
#define CLKVAL2_SSW 0x00000100
/* A couple of macros to ease definition of the various handlers */
.macro Insert_InterruptHandler Interrupt
.weak \Interrupt\()_Handler
.thumb_set \Interrupt\()_Handler, Default_Handler
.endm
.macro Insert_InterruptVeener Interrupt
.globl \Interrupt\()_Veener
\Interrupt\()_Veener:
LDR R0, =\Interrupt\()_Handler
BX R0
.endm
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This is indirectly branched to through the veneers */
.syntax unified
.cpu cortex-m0
.section .reset, "a", %progbits
.align 2
.globl __Vectors
.type __Vectors, %object
__Vectors:
.long __initial_sp /* Top of Stack */
.long Reset_Handler /* Reset Handler */
/*
* All entries below are redundant for M0, but are retained because they can
* in the future be directly ported to M0 Plus devices.
*/
.long 0 /* Reserved */
.long HardFault_Handler /* Hard Fault Handler */
.long CLKVAL1_SSW /* Reserved */
.long CLKVAL2_SSW /* Reserved */
#ifdef RETAIN_VECTOR_TABLE
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC1400 Peripherals */
.long IRQ0_Handler /* SCU.SR0, CAN0.SR0, CCU40.SR0, SCU.SR0 | CAN0.SR0 */
.long IRQ1_Handler /* SCU.SR1, CAN0.SR1, CCU80.SR0, SCU.SR1 | CAN0.SR1 */
.long IRQ2_Handler /* SCU.SR2, CAN0.SR2, CCU80.SR1, SCU.SR2 | CAN0.SR2 */
.long IRQ3_Handler /* ERU0.SR0, ERU1.SR0, CAN0.SR0, ERU0.SR0 | ERU1.SR0 */
.long IRQ4_Handler /* ERU0.SR1, ERU1.SR1, CAN0.SR1, ERU0.SR1 | ERU1.SR1 */
.long IRQ5_Handler /* ERU0.SR2, ERU1.SR2, CAN0.SR2, ERU0.SR2 | ERU1.SR2 */
.long IRQ6_Handler /* ERU0.SR3, ERU1.SR3, CAN0.SR3, ERU0.SR3 | ERU1.SR3 */
.long IRQ7_Handler /* MATH.SR0, CAN0.SR3, CCU40.SR1, MATH.SR0 | CAN0.SR3 */
.long IRQ8_Handler /* LEDTS2.SR0, CCU40.SR0, CCU80.SR0, LEDTS2.SR0 | CCU40.SR0 */
.long IRQ9_Handler /* USIC0.SR0, USIC1.SR0, ERU0.SR0, USIC0.SR0 | USIC1.SR0 */
.long IRQ10_Handler /* USIC0.SR1, USIC1.SR1, ERU0.SR1, USIC0.SR1 | USIC1.SR1 */
.long IRQ11_Handler /* USIC0.SR2, USIC1.SR2, ERU0.SR2, USIC0.SR2 | USIC1.SR2 */
.long IRQ12_Handler /* USIC0.SR3, USIC1.SR3, ERU0.SR3, USIC0.SR3 | USIC1.SR3 */
.long IRQ13_Handler /* USIC0.SR4, USIC1.SR4, CCU80.SR1, USIC0.SR4 | USIC1.SR4 */
.long IRQ14_Handler /* USIC0.SR5, USIC1.SR5, POSIF0.SR0, USIC0.SR5 | USIC1.SR5 */
.long IRQ15_Handler /* VADC0.C0SR0, USIC0.SR0, POSIF0.SR1, VADC0.C0SR0 | USIC0.SR0 */
.long IRQ16_Handler /* VADC0.C0SR1, USIC0.SR1, CCU40.SR2, VADC0.C0SR1 | USIC0.SR1 */
.long IRQ17_Handler /* VADC0.G0SR0, USIC0.SR2, CAN0.SR0, VADC0.G0SR0 | USIC0.SR2 */
.long IRQ18_Handler /* VADC0.G0SR1, USIC0.SR3, CAN0.SR1, VADC0.G0SR1 | USIC0.SR3 */
.long IRQ19_Handler /* VADC0.G1SR0, USIC0.SR4, CAN0.SR2, VADC0.G1SR0 | USIC0.SR4 */
.long IRQ20_Handler /* VADC0.G1SR1, USIC0.SR5, CAN0.SR3, VADC0.G1SR1 | USIC0.SR5 */
.long IRQ21_Handler /* CCU40.SR0, CCU41.SR0, USIC0.SR0, CCU40.SR0 | CCU41.SR0 */
.long IRQ22_Handler /* CCU40.SR1, CCU41.SR1, USIC0.SR1, CCU40.SR1 | CCU41.SR1 */
.long IRQ23_Handler /* CCU40.SR2, CCU41.SR2, USIC0.SR2, CCU40.SR2 | CCU41.SR2 */
.long IRQ24_Handler /* CCU40.SR3, CCU41.SR3, USIC0.SR3, CCU40.SR3 | CCU41.SR3 */
.long IRQ25_Handler /* CCU80.SR0, CCU81.SR0, USIC0.SR4, CCU80.SR0 | CCU81.SR0 */
.long IRQ26_Handler /* CCU80.SR1, CCU81.SR1, USIC0.SR5, CCU80.SR1 | CCU81.SR1 */
.long IRQ27_Handler /* POSIF0.SR0, POSIF1.SR0, CCU40.SR3, POSIF0.SR0 | POSIF1.SR0 */
.long IRQ28_Handler /* POSIF0.SR1, POSIF1.SR1, ERU0.SR0, POSIF0.SR1 | POSIF1.SR1 */
.long IRQ29_Handler /* LEDTS0.SR0, CCU40.SR1, ERU0.SR1, LEDTS0.SR0 | CCU40.SR1 */
.long IRQ30_Handler /* LEDTS1.SR0, CCU40.SR2, ERU0.SR2, LEDTS1.SR0 | CCU40.SR2 */
.long IRQ31_Handler /* BCCU0.SR0, CCU40.SR3, ERU0.SR3, BCCU0.SR0 | CCU40.SR3 */
#endif
.size __Vectors, . - __Vectors
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.thumb
.align 1
/* Reset Handler */
.thumb_func
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Initialize interrupt veneer */
ldr r1, =eROData
ldr r2, =VeneerStart
ldr r3, =VeneerEnd
bl __copy_data
ldr r0, =SystemInit
blx r0
/* Initialize data */
ldr r1, =DataLoadAddr
ldr r2, =__data_start
ldr r3, =__data_end
bl __copy_data
/* RAM code */
ldr r1, =__ram_code_load
ldr r2, =__ram_code_start
ldr r3, =__ram_code_end
bl __copy_data
/* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
#ifndef __SKIP_BSS_CLEAR
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __SKIP_BSS_CLEAR */
#ifndef __SKIP_LIBC_INIT_ARRAY
ldr r0, =__libc_init_array
blx r0
#endif
ldr r0, =main
blx r0
.thumb_func
.type __copy_data, %function
__copy_data:
/* The ranges of copy from/to are specified by following symbols
* r1: start of the section to copy from.
* r2: start of the section to copy to
* r3: end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
* Uses r0
*/
subs r3, r2
ble .L_loop_done
.L_loop:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop
.L_loop_done:
bx lr
.pool
.size Reset_Handler,.-Reset_Handler
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
.align 1
.thumb_func
.weak Default_handler
.type Default_handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
Insert_InterruptHandler HardFault
Insert_InterruptHandler SVC
Insert_InterruptHandler PendSV
Insert_InterruptHandler SysTick
Insert_InterruptHandler IRQ0
Insert_InterruptHandler IRQ1
Insert_InterruptHandler IRQ2
Insert_InterruptHandler IRQ3
Insert_InterruptHandler IRQ4
Insert_InterruptHandler IRQ5
Insert_InterruptHandler IRQ6
Insert_InterruptHandler IRQ7
Insert_InterruptHandler IRQ8
Insert_InterruptHandler IRQ9
Insert_InterruptHandler IRQ10
Insert_InterruptHandler IRQ11
Insert_InterruptHandler IRQ12
Insert_InterruptHandler IRQ13
Insert_InterruptHandler IRQ14
Insert_InterruptHandler IRQ15
Insert_InterruptHandler IRQ16
Insert_InterruptHandler IRQ17
Insert_InterruptHandler IRQ18
Insert_InterruptHandler IRQ19
Insert_InterruptHandler IRQ20
Insert_InterruptHandler IRQ21
Insert_InterruptHandler IRQ22
Insert_InterruptHandler IRQ23
Insert_InterruptHandler IRQ24
Insert_InterruptHandler IRQ25
Insert_InterruptHandler IRQ26
Insert_InterruptHandler IRQ27
Insert_InterruptHandler IRQ28
Insert_InterruptHandler IRQ29
Insert_InterruptHandler IRQ30
Insert_InterruptHandler IRQ31
/* ======================================================================== */
/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
.section ".XmcVeneerCode","ax",%progbits
.align 1
Insert_InterruptVeener HardFault
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
Insert_InterruptVeener SVC
.long 0
.long 0
Insert_InterruptVeener PendSV
Insert_InterruptVeener SysTick
Insert_InterruptVeener IRQ0
Insert_InterruptVeener IRQ1
Insert_InterruptVeener IRQ2
Insert_InterruptVeener IRQ3
Insert_InterruptVeener IRQ4
Insert_InterruptVeener IRQ5
Insert_InterruptVeener IRQ6
Insert_InterruptVeener IRQ7
Insert_InterruptVeener IRQ8
Insert_InterruptVeener IRQ9
Insert_InterruptVeener IRQ10
Insert_InterruptVeener IRQ11
Insert_InterruptVeener IRQ12
Insert_InterruptVeener IRQ13
Insert_InterruptVeener IRQ14
Insert_InterruptVeener IRQ15
Insert_InterruptVeener IRQ16
Insert_InterruptVeener IRQ17
Insert_InterruptVeener IRQ18
Insert_InterruptVeener IRQ19
Insert_InterruptVeener IRQ20
Insert_InterruptVeener IRQ21
Insert_InterruptVeener IRQ22
Insert_InterruptVeener IRQ23
Insert_InterruptVeener IRQ24
Insert_InterruptVeener IRQ25
Insert_InterruptVeener IRQ26
Insert_InterruptVeener IRQ27
Insert_InterruptVeener IRQ28
Insert_InterruptVeener IRQ29
Insert_InterruptVeener IRQ30
Insert_InterruptVeener IRQ31
/* ======================================================================== */
/* ======================================================================== */
/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
.end

276
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Boot/Startup/system_XMC1400.c Normal file
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/*********************************************************************************************************************
* @file system_XMC1400.c
* @brief Device specific initialization for the XMC1400-Series according to CMSIS
* @version V1.1
* @date 09 Dec 2015
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* *************************** Change history ********************************
* V1.0, 03 Sep 2015, JFT : Initial version
* MCLK = 48MHz, PCLK = 96MHz
* V1.1, 09 Dec 2015, JFT : Enable prefetch unit
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <XMC1400.h>
#include "system_XMC1400.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
/* Define WEAK attribute */
#if !defined(__WEAK)
#if defined ( __CC_ARM )
#define __WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ )
#define __WEAK __weak
#elif defined ( __GNUC__ )
#define __WEAK __attribute__ ((weak))
#elif defined ( __TASKING__ )
#define __WEAK __attribute__ ((weak))
#endif
#endif
#define DCO1_FREQUENCY (48000000U)
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*
// <h> Clock configuration
*/
/*
// <o> External crystal frequency [Hz]
// <8000000=> 8MHz
// <12000000=> 12MHz
// <16000000=> 16MHz
// <20000000=> 20MHz
// <i> Defines external crystal frequency
// <i> Default: 20MHz
*/
#define OSCHP_FREQUENCY (20000000U)
/*
// <o> DCLK clock source selection
// <0=> Internal oscillator DCO1 (48MHz)
// <1=> External crystal oscillator
// <i> Default: Internal oscillator DCO1 (48MHz)
*/
#define DCLK_CLOCK_SRC 0
#define DCLK_CLOCK_SRC_DCO1 0
#define DCLK_CLOCK_SRC_EXT_XTAL 1
/*
// <o> OSCHP external oscillator mode
// <0=> Crystal mode
// <1=> External clock direct input mode
// <i> Default: Crystal mode
*/
#define OSCHP_MODE 0
#define OSCHP_MODE_XTAL 0
#define OSCHP_MODE_DIRECT 1
/*
// <o> RTC clock source selection
// <0=> Internal oscillator DCO2 (32768Hz)
// <5=> External crystal oscillator
// <i> Default: Internal oscillator DCO2 (32768Hz)
*/
#define RTC_CLOCK_SRC 0
#define RTC_CLOCK_SRC_DCO2 0
#define RTC_CLOCK_SRC_EXT_XTAL 5
/*
// <o> PCLK clock source selection
// <0=> MCLK
// <1=> 2xMCLK
// <i> Default: 2xMCLK
*/
#define PCLK_CLOCK_SRC 1
#define PCLK_CLOCK_SRC_MCLK 0
#define PCLK_CLOCK_SRC_2XMCLK 1
/*
//-------- <<< end of configuration section >>> ------------------
*/
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((at(0x20003FFC)));
#elif defined ( __ICCARM__ )
__no_init uint32_t SystemCoreClock;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((section(".no_init")));
#elif defined ( __TASKING__ )
uint32_t SystemCoreClock __at( 0x20003FFC );
#endif
/*******************************************************************************
* LOCAL FUNCTIONS
*******************************************************************************/
#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1
static inline void delay(uint32_t cycles)
{
while(cycles > 0)
{
__NOP();
cycles--;
}
}
#endif
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
__WEAK void SystemInit(void)
{
SystemCoreSetup();
SystemCoreClockSetup();
}
__WEAK void SystemCoreSetup(void)
{
/* Enable Prefetch unit */
SCU_GENERAL->PFUCR &= ~SCU_GENERAL_PFUCR_PFUBYP_Msk;
}
__WEAK void SystemCoreClockSetup(void)
{
/* Clock setup done during SSW using the CLOCK_VAL1 and CLOCK_VAL2 defined in vector table */
/* disable bit protection */
SCU_GENERAL->PASSWD = 0x000000C0UL;
#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1
if (OSCHP_GetFrequency() > 20000000U)
{
SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_HYSCTRL_Msk;
}
/* OSCHP source selection - OSC mode */
SCU_ANALOG->ANAOSCHPCTRL = (SCU_ANALOG->ANAOSCHPCTRL & ~SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk) |
(OSCHP_MODE << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos);
/* Enable OSC_HP oscillator watchdog*/
SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk;
do
{
/* Restart OSC_HP oscillator watchdog */
SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk;
SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDRES_Msk;
/* Wait a few DCO2 cycles for the update of the clock detection result */
delay(2500);
/* check clock is ok */
}
while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk);
/* DCLK source using OSC_HP */
SCU_CLK->CLKCR1 |= SCU_CLK_CLKCR1_DCLKSEL_Msk;
#else
/* DCLK source using DCO1 */
SCU_CLK->CLKCR1 &= ~SCU_CLK_CLKCR1_DCLKSEL_Msk;
#endif
#if RTC_CLOCK_SRC == RTC_CLOCK_SRC_EXT_XTAL
/* Enable OSC_LP */
SCU_ANALOG->ANAOSCLPCTRL &= ~SCU_ANALOG_ANAOSCLPCTRL_MODE_Msk;
#endif
/* Update PCLK selection mux. */
/* Fractional divider enabled, MCLK frequency equal DCO1 frequency or external crystal frequency */
SCU_CLK->CLKCR = (1023UL <<SCU_CLK_CLKCR_CNTADJ_Pos) |
(RTC_CLOCK_SRC << SCU_CLK_CLKCR_RTCCLKSEL_Pos) |
(PCLK_CLOCK_SRC << SCU_CLK_CLKCR_PCLKSEL_Pos) |
0x100U; /* IDIV = 1 */
/* enable bit protection */
SCU_GENERAL->PASSWD = 0x000000C3UL;
SystemCoreClockUpdate();
}
__WEAK void SystemCoreClockUpdate(void)
{
static uint32_t IDIV, FDIV;
IDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
if (IDIV != 0)
{
FDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
FDIV |= ((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_FDIV_Msk) << 8;
/* Fractional divider is enabled and used */
if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U)
{
SystemCoreClock = ((uint32_t)((DCO1_FREQUENCY << 6U) / ((IDIV << 10) + FDIV))) << 4U;
}
else
{
SystemCoreClock = ((uint32_t)((OSCHP_GetFrequency() << 6U) / ((IDIV << 10) + FDIV))) << 4U;
}
}
else
{
/* Fractional divider bypassed. */
if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U)
{
SystemCoreClock = DCO1_FREQUENCY;
}
else
{
SystemCoreClock = OSCHP_GetFrequency();
}
}
}
__WEAK uint32_t OSCHP_GetFrequency(void)
{
return OSCHP_FREQUENCY;
}

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/************************************************************************************//**
* \file Demo\ARMCM0_XMC1_XMC1400_Boot_Kit_GCC\Boot\blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (48000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (1)
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_UART_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_UART_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_UART_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_UART_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_UART_CHANNEL_INDEX (1)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (200)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

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/**
\defgroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC Bootloader
\brief Bootloader.
\ingroup ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
*/

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/************************************************************************************//**
* \file Demo\ARMCM0_XMC1_XMC1400_Boot_Kit_GCC\Boot\hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* LED driver header */
#include "xmc_gpio.h" /* GPIO module */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* default implementation always activates the bootloader after a reset */
return BLT_TRUE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* clean up the LED driver */
LedBlinkExit();
/* okay to start the user program.*/
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
/* this function is called upon initialization. might as well use it to initialize
* the LED driver. It is kind of a visual watchdog anyways.
*/
LedBlinkInit(100);
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
/* run the LED blink task. this is a better place to do it than in the main() program
* loop. certain operations such as flash erase can take a long time, which would cause
* a blink interval to be skipped. this function is also called during such operations,
* so no blink intervals will be skipped when calling the LED blink task here.
*/
LedBlinkTask();
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
return BLT_TRUE;
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "FeaserKey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

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/************************************************************************************//**
* \file Demo\ARMCM0_XMC1_XMC1400_Boot_Kit_GCC\Boot\led.c
* \brief LED driver source file.
* \ingroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* module header */
#include "xmc_gpio.h" /* GPIO module */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Holds the desired LED blink interval time. */
static blt_int16u ledBlinkIntervalMs;
/************************************************************************************//**
** \brief Initializes the LED blink driver.
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
** \return none.
**
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms)
{
/* initialize and turn of the LED */
XMC_GPIO_SetMode(P4_0, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);
XMC_GPIO_SetOutputLevel(P4_0, XMC_GPIO_OUTPUT_LEVEL_HIGH);
/* store the interval time between LED toggles */
ledBlinkIntervalMs = interval_ms;
} /*** end of LedBlinkInit ***/
/************************************************************************************//**
** \brief Task function for blinking the LED as a fixed timer interval.
** \return none.
**
****************************************************************************************/
void LedBlinkTask(void)
{
static blt_bool ledOn = BLT_FALSE;
static blt_int32u nextBlinkEvent = 0;
/* check for blink event */
if (TimerGet() >= nextBlinkEvent)
{
/* toggle the LED state */
if (ledOn == BLT_FALSE)
{
/* turn the LED on */
ledOn = BLT_TRUE;
XMC_GPIO_SetOutputLevel(P4_0, XMC_GPIO_OUTPUT_LEVEL_LOW);
}
else
{
/* turn the LED off */
ledOn = BLT_FALSE;
XMC_GPIO_SetOutputLevel(P4_0, XMC_GPIO_OUTPUT_LEVEL_HIGH);
}
/* schedule the next blink event */
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
}
} /*** end of LedBlinkTask ***/
/************************************************************************************//**
** \brief Cleans up the LED blink driver. This is intended to be used upon program
** exit.
** \return none.
**
****************************************************************************************/
void LedBlinkExit(void)
{
/* turn the LED off */
XMC_GPIO_SetOutputLevel(P4_0, XMC_GPIO_OUTPUT_LEVEL_HIGH);
} /*** end of LedBlinkExit ***/
/*********************************** end of led.c **************************************/

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/************************************************************************************//**
* \file Demo\ARMCM0_XMC1_XMC1400_Boot_Kit_GCC\Boot\led.h
* \brief LED driver header file.
* \ingroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms);
void LedBlinkTask(void);
void LedBlinkExit(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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/************************************************************************************//**
* \file Demo\ARMCM0_XMC1_XMC1400_Boot_Kit_GCC\Boot\main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARMCM0_XMC1_XMC1400_Boot_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "xmc_gpio.h" /* GPIO module */
#include "xmc_uart.h" /* UART driver header */
#include "xmc_can.h" /* CAN driver header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void PostInit(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program exit code.
**
****************************************************************************************/
int main(void)
{
/* initialize the bootloader */
BootInit();
/* post initialization of the microcontroller */
PostInit();
/* start the infinite program loop */
while (1)
{
/* run the bootloader task */
BootTask();
}
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Post initialization of the microcontroller. Contains all initialization
** code that should run after the bootloader's core was initialized.
** \return none.
**
****************************************************************************************/
static void PostInit(void)
{
#if (BOOT_COM_UART_ENABLE > 0)
XMC_GPIO_CONFIG_t rx_uart_config;
XMC_GPIO_CONFIG_t tx_uart_config;
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
XMC_GPIO_CONFIG_t rx_can_config;
XMC_GPIO_CONFIG_t tx_can_config;
#endif
#if (BOOT_COM_UART_ENABLE > 0)
/* initialize UART Rx pin */
rx_uart_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
XMC_GPIO_Init(P1_3, &rx_uart_config);
/* initialize UART Tx pin */
tx_uart_config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7;
XMC_GPIO_Init(P1_2, &tx_uart_config);
/* set input source path to DXnA to connect P1_3 to ASC Receive. note that this
* function must be called after XMC_UART_CH_Init(), which is called when initializing
* the bootloader core with BootInit().
*/
XMC_UART_CH_SetInputSource(XMC_UART0_CH1, XMC_UART_CH_INPUT_RXD, USIC0_C1_DX0_P1_3);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* configure CAN receive pin */
rx_can_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
XMC_GPIO_Init(P4_8, &rx_can_config);
/* configure CAN transmit pin */
tx_can_config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9;
XMC_GPIO_Init(P4_9, &tx_can_config);
/* select CAN Receive Input C (N1_RXDC) to map P4_8 to CAN_NODE1 */
XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE1);
XMC_CAN_NODE_SetReceiveInput(CAN_NODE1, XMC_CAN_NODE_RECEIVE_INPUT_RXDCC);
XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE1);
#endif
} /*** end of PostInit ***/
/*********************************** end of main.c *************************************/

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.ifx.xmc4000.appDebug.401952777">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ifx.xmc4000.appDebug.401952777" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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28
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/.project Normal file
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14
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/.settings/com.dave.mbs.xc800.prefs Normal file
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13
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/.settings/language.settings.xml Normal file
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163
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/.settings/org.eclipse.cdt.core.prefs Normal file
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org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression=do not insert
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org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types=do not insert
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org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters=do not insert
org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_throws=do not insert
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org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert
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org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert
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org.eclipse.cdt.core.formatter.insert_space_before_unary_operator=do not insert
org.eclipse.cdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert
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3
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eclipse.preferences.version=1
formatter_profile=_Feaser
formatter_settings_version=1

5
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/.settings/properties.index Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<com.ifx.xmc4000.appDebug_memory>
<details IMemento.internal.id="0" enable="Yes" endAddress="0x10032FFF" memModelType="ROM" modelName="FLASH" startAddress="0x10003000"/>
<details IMemento.internal.id="1" enable="Yes" endAddress="0x20003FFF" memModelType="RAM" modelName="SRAM " startAddress="0x20000000"/>
</com.ifx.xmc4000.appDebug_memory>

BIN
Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/Debug/demoprog_xmc1400.elf Normal file
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Target/Demo/ARMCM0_XMC1_XMC1400_Boot_Kit_GCC/Prog/Libraries/CMSIS/Include/cmsis_compiler.h Normal file
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.1
* @date 30. January 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.1
* @date 25. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifndef CMSIS_NVIC_VIRTUAL
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#endif /* CMSIS_NVIC_VIRTUAL */
#ifndef CMSIS_VECTAB_VIRTUAL
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*********************************************************************************************************************
* @file XMC1000_RomFunctionTable.h
* @brief ROM functions prototypes for the XMC1400-Series
* @version V1.0
* @date 03 Sep 2015
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history *********************************
* V1.0, 03 Sep 2015, JFT : Initial version
*****************************************************************************
* @endcond
*/
#ifndef ROM_FUNCTION_TABLE_H
#define ROM_FUNCTION_TABLE_H
#ifdef __cplusplus
extern "C" {
#endif
/* ***************************************************************************
******************************* Constants *******************************
*************************************************************************** */
/* Start address of the ROM function table */
#define ROM_FUNCTION_TABLE_START (0x00000100U)
/* Pointer to Erase Flash Page routine */
#define _NvmErase (ROM_FUNCTION_TABLE_START + 0x00U)
/* Pointer to Erase, Program & Verify Flash Page routine */
#define _NvmProgVerify (ROM_FUNCTION_TABLE_START + 0x04U)
/* Pointer to Request BMI installation routine */
#define _BmiInstallationReq (ROM_FUNCTION_TABLE_START + 0x08U)
/* ***************************************************************************
******************************** Enumerations ********************************
*************************************************************************** */
typedef enum TagNVMStatus
{
/* The function succeeded */
NVM_PASS = (int32_t)0x00010000U,
/* Generic error code */
NVM_E_FAIL = (int32_t)0x80010001U,
/* Source data not in RAM */
NVM_E_SRC_AREA_EXCCEED = (int32_t)0x80010003U,
/* Source data is not 4 byte aligned */
NVM_E_SRC_ALIGNMENT = (int32_t)0x80010004U,
/* NVM module cannot be physically accessed */
NVM_E_NVM_FAIL = (int32_t)0x80010005U,
/* Verification of written page not successful */
NVM_E_VERIFY = (int32_t)0x80010006U,
/* Destination data is not (completely) located in NVM */
NVM_E_DST_AREA_EXCEED = (int32_t)0x80010009U,
/* Destination data is not properly aligned */
NVM_E_DST_ALIGNMENT = (int32_t)0x80010010U,
} NVM_STATUS;
/* ***************************************************************************
*********************************** Macros ***********************************
*************************************************************************** */
/* ***************************************************************************
Description: Erase granularity = 1 Page of 16 blocks of 16 Bytes
= Equivalent to 256 Bytes using this routine.
Input parameters:
– Logical address of the Flash Page to be erased which must be page aligned
and in NVM address range
Return status:
– OK (NVM_PASS)
– Invalid address (NVM_E_DST_ALIGNMENT or NVM_E_DST_AREA_EXCEED)
– Operation failed (Error during low level NVM programming driver):
NVM_E_FAIL
NVM_E_VERIFY
NVM_E_NVM_FAIL
Prototype:
NVM_STATUS XMC1000_NvmErasePage(uint32_t *pageAddr)
*************************************************************************** */
#define XMC1000_NvmErasePage (*((NVM_STATUS (**) (uint32_t * )) \
_NvmErase))
/* ***************************************************************************
Description: This procedure performs erase (skipped if not necessary), program
and verify of selected Flash page.
Input parameter:
– Logical address of the target Flash Page, must be page aligned and in NVM
address range
– Address in SRAM where the data starts, must be 4-byte aligned
Return status:
– OK (NVM_PASS)
– Invalid addresses
NVM_E_DST_ALIGNMENT
NVM_E_SRC_ALIGNMENT
NVM_E_DST_AREA_EXCEED
NVM_E_SRC_AREA_EXCCEED
– Operation failed (Error during low level NVM programming driver):
NVM_E_FAIL
NVM_E_VERIFY
NVM_E_NVM_FAIL
Prototype:
NVM_STATUS XMC1000_NvmProgVerify(const uint32_t *srcAddr, uint32_t *dstAddr)
*************************************************************************** */
#define XMC1000_NvmProgVerify (*((NVM_STATUS (**) (const uint32_t * ,\
uint32_t * ))\
_NvmProgVerify))
/* ***************************************************************************
Description: This procedure initiates installation of a new BMI value. In
particular, it can be used as well as to restore the state upon delivery for a
device already in User Productive mode.
Input parameter:
– BMI value to be installed
Return status:
– wrong input BMI value (0x01) - only upon error, if OK the procedure triggers
a reset respectively does not return to calling routine !
Prototype:
unsigned long XMC1000_BmiInstallationReq(unsigned short requestedBmiValue)
**************************************************************************** */
#define XMC1000_BmiInstallationReq (*((uint32_t (**) (uint16_t)) \
_BmiInstallationReq))
#ifdef __cplusplus
}
#endif
#endif /* ROM_FUNCTION_TABLE_H */

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