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Remove m68k support 

The m68k support is compile broken for a long time now and nobody
cared so far. We cannot keep the architecture uptodate with current
development wihtout being able to compile it. It's still in the
archives and can be re-added anytime once somebody cares for.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2010-11-17 09:14:33 +01:00
parent 33e3dc3cdb
commit 8ef2947fff
125 changed files with 0 additions and 18837 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/boards.dox
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@ -43,11 +43,6 @@ x86 type:
@li @subpage generic_pc
coldfire/m68k type:
@li @subpage phycore_mcf54xx
@li @subpage kp_ukd_r1
*/
/* TODO

1
arch/architecture.dox
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@ -87,7 +87,6 @@ TODO
@li @subpage dev_arm_mach
@li @subpage dev_bf_mach
@li @subpage dev_ppc_mach
@li @subpage dev_m68k_mach
@li @subpage dev_x86_mach
*/

182
arch/m68k/Kconfig
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@ -1,182 +0,0 @@
#
# Default location of link barebox Image on M68k/Coldfire
#
config ARCH_TEXT_BASE
hex
default 0x07f00000 if MACH_MCF54xx
default 0x07f00000 if MACH_MCF5445x
help
Vector table for M68k and barebox Link Address
On M68k/Coldfire cores all exceptions and interrupts are routed through
a vector array. This vector is by default at address 0x0000_0000, but
can be moved to any other 1MB aligned address.
We take advantage of this to move barebox out of low memory. Some BDM
debuggers won't like a moved vector base and might need tweaking to
work.
Note: Respect alignment restrictions for TEXT_BASE, which must be
1MB aligned (VBR register constrain).
#
# Internal configurations
#
config BOARDINFO
default "konzeptpark UKD Prototype with Phycore MCF5485" if MACH_KPUKDR1
default "konzeptpark UKD Prototype with Phycore MCF5475 NUM" if MACH_KPUKDR1_NUM
default "konzeptpark UKD Revision 2 with Phycore MCF5485" if MACH_KPUKDR2
default "konzeptpark UKD Revision 2 with Phycore MCF5475 NUM" if MACH_KPUKDR2_NUM
default "Phytec Baseboard with Phycore MCF5485" if MACH_PCM982_5485
default "Phytec Baseboard with Phycore MCF5475" if MACH_PCM982_5475
default "Phytec Baseboard with Phycore MCF5475 NUM" if MACH_PCM982_5475_NUM
default "Phytec Baseboard with Phycore MCF54455" if MACH_PCM982_54455
default "!No boardinfo string set!"
config HAS_EARLY_INIT
bool
default n
config BOARD_LINKER_SCRIPT
bool
default n
config GENERIC_LINKER_SCRIPT
bool
default y
depends on !BOARD_LINKER_SCRIPT
config M68K
bool
select HAS_KALLSYMS
select HAS_MODULES
default y
config MCFV4E
bool
config MCFV4M
bool
config ARCH_MCF54xx
bool
select MCFV4E
config ARCH_MCF5445x
bool
select MCFV4M
#
# Board selection
#
choice
prompt "Select your board"
config MACH_KPUKDR1
bool "konzeptpark UKD R1 + phyCore MCF5485"
select HAS_CFI
select ARCH_MCF54xx
help
Say Y here if you are using the konzeptpark UKD R1 with a
Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor
config MACH_KPUKDR1_NUM
bool "konzeptpark UKD R1 + phyCore MCF5475 NUM"
select HAS_CFI
select ARCH_MCF54xx
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using the konzeptpark UKD R1 with a
Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor
config MACH_KPUKDR2
bool "konzeptpark UKD R2 + phyCore MCF5485"
select HAS_CFI
select ARCH_MCF54xx
help
Say Y here if you are using the konzeptpark UKD R2 with a
Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor
config MACH_KPUKDR2_NUM
bool "konzeptpark UKD R2 + phyCore MCF5475 NUM"
select HAS_CFI
select ARCH_MCF54xx
help
Say Y here if you are using the konzeptpark UKD R2 with a
Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor
config MACH_PCM982_5485
bool "Phytec pcm982 + phyCore MCF5485"
select HAS_CFI
select ARCH_MCF54xx
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using the Phytec Phycore PCM-024 equipped
with a Freescale MC5485 Processor
config MACH_PCM982_5475
bool "Phytec pcm982 + phyCore MCF5475"
select HAS_CFI
select ARCH_MCF54xx
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using the Phytec Phycore PCM-024 equipped
with a Freescale MC5475 Processor
config MACH_PCM982_5475_NUM
bool "Phytec pcm982 + phyCore MCF5475 NUM"
select HAS_CFI
select ARCH_MCF54xx
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using the Phytec Phycore PCM-024 equipped
with a Freescale MC5475 Processor (NUM Variant)
config MACH_PCM982_54455
bool "Phytec pcm982 + phyCore MCF54455 (experimental)"
select HAS_CFI
select ARCH_MCF5445x
help
Say Y here if you are using the Phytec Phycore PCM-mcf54455 equipped
with a Freescale MC54455 Processor (experimental)
endchoice
#
# M68k/Coldfire Subarch Configuration
#
source arch/m68k/mach-mcfv4e/Kconfig
menu "M68k/Coldfire specific Linux boot settings"
config CMDLINE_TAG
bool "Send commandline to kernel"
default y
help
If you want to start a 2.6 kernel say y here.
config SETUP_MEMORY_TAGS
bool "send memory definition to kernel"
default y
help
If you want to start a 2.6 kernel say y here.
config INITRD_TAG
bool "send initrd params to kernel"
default n
help
If you want to start a 2.6 kernel and use an
initrd image say y here.
endmenu
#
# Common barebox options
#
source common/Kconfig
source commands/Kconfig
source net/Kconfig
source drivers/Kconfig
source fs/Kconfig
source lib/Kconfig

82
arch/m68k/Makefile
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@ -1,82 +0,0 @@
#
# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
# See file CREDITS for list of people who contributed to this project.
#
# This file is part of barebox.
#
# barebox is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# barebox is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with barebox. If not, see <http://www.gnu.org/licenses/>.
#
CPPFLAGS += -isystem $(gccincdir) -fno-strict-aliasing
machine-$(CONFIG_ARCH_MCF54xx) := mcfv4e
board-$(CONFIG_MACH_KPUKDR1) := kp_ukd_r1
board-$(CONFIG_MACH_KPUKDR1_NUM) := kp_ukd_r1_num
board-$(CONFIG_MACH_KPUKDR2) := kp_ukd_r2
board-$(CONFIG_MACH_KPUKDR2_NUM) := kp_ukd_r2_num
board-$(CONFIG_MACH_PCM982_5485) := phycore_mcf54xx
board-$(CONFIG_MACH_PCM982_5475) := phycore_mcf54xx
board-$(CONFIG_MACH_PCM982_5475_NUM) := phycore_mcf54xx_num
board-$(CONFIG_MACH_PCM982_54455) := phycore_mcf5445x
cpu-$(CONFIG_MCFV4E) := mcfv4e
cpu-$(CONFIG_MCFV4M) := mcfv4m
TEXT_BASE = $(CONFIG_TEXT_BASE)
CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -P
AFLAGS += -gdwarf-2 -save-temps
# FIXME - remove overide
CFLAGS += -msoft-float -mcfv4e -gdwarf-2 -feliminate-unused-debug-types \
-fmerge-all-constants
# Incompatible code in barebox for -std=c99
LDFLAGS_barebox :=-L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
# --verbose --stats
machdirs := $(patsubst %,arch/m68k/mach-%/,$(machine-y))
ifeq ($(KBUILD_SRC),)
CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
else
CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
endif
all: $(KBUILD_IMAGE)
archprepare: maketools
PHONY += maketools
ifneq ($(board-y),)
BOARD := arch/m68k/boards/$(board-y)/
else
BOARD :=
endif
ifneq ($(machine-y),)
MACH := arch/m68k/mach-$(machine-y)/
else
MACH :=
endif
common-y += $(BOARD) $(MACH)
common-y += arch/m68k/lib/ arch/m68k/cpu/
lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/m68k/lib/barebox.lds
lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/barebox.lds
CLEAN_FILES += arch/m68k/lib/barebox.lds

31
arch/m68k/boards/kp_ukd_r1_num/Makefile
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@ -1,31 +0,0 @@
#
# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
# See file CREDITS for list of people who contributed to this project.
#
# This file is part of barebox.
#
# barebox is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# barebox is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with barebox. If not, see <http://www.gnu.org/licenses/>.
#
# The build system allows to split everything into distinct files covering an
# separate issue. Use that!
# Board specific callbacks and initialisations
obj-y += lowlevel_init.o
obj-y += highlevel_init.o
obj-y += kp_ukd_r1_num.o
obj-y += pci-stubs.o

36
arch/m68k/boards/kp_ukd_r1_num/env/bin/_update vendored
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@ -1,36 +0,0 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

38
arch/m68k/boards/kp_ukd_r1_num/env/bin/boot vendored
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@ -1,38 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xflash ]; then
root=flash
kernel=flash
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xflash ]; then
bootargs="$bootargs root=$rootpart rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot"
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
else
bootm /dev/nor0.kernel
fi

20
arch/m68k/boards/kp_ukd_r1_num/env/bin/init vendored
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@ -1,20 +0,0 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
addpart /dev/nor0 $mtdparts
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel [<imagename>] to update kernel into flash"
echo "type udate_root [<imagename>] to update rootfs into flash"
echo
exit
fi
boot

14
arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop vendored
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@ -1,14 +0,0 @@
pci stat
pci stat -c
while true; do
pci readm 32 0xA1000000 32 -s
pci readm 32 0xA2000000 256 -s
pci dmatx 2000 a2000100 128 -s
pci writem 32 0xa2000100 0x12345678 4 -s
pci readm 32 0xA3000000 256 -s
pci dmatx 2000 a3000040 128 -s
pci writem 32 0xa3000100 0x12345678 4 -s
pci readm 32 0xA4000000 16 -s
pci dmatx 2000 a4000080 4 -s
pci writem 32 0xa4000080 0x12345678 4 -s
done

13
arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop vendored
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@ -1,13 +0,0 @@
pci stat
pci stat -c
while true; do
pci readm 32 0xA1000000 32 -s
pci readm 32 0xA2000000 256 -s
pci writem 32 0xa2000100 0x12345678 4 -s
pci readm 32 0xA3000000 256 -s
pci writem 32 0xa3000100 0x12345678 4 -s
pci readm 32 0xA4000000 16 -s
pci writem 32 0xa4000080 0x12345678 4 -s
# pci dmatx 2000 a3000040 128 -s
done

8
arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel vendored
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@ -1,8 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
part=/dev/nor0.kernel
. /env/bin/_update $1

8
arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root vendored
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@ -1,8 +0,0 @@
#!/bin/sh
. /env/config
image=$jffs2
part=/dev/nor0.root
. /env/bin/_update $1

32
arch/m68k/boards/kp_ukd_r1_num/env/config vendored
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@ -1,32 +0,0 @@
#!/bin/sh
# can be either 'net' or 'flash'
kernel=net
root=net
# use 'dhcp' todo dhcp in barebox and in kernel
ip=dhcp
#
# setup default ethernet address
#
eth0.ipaddr=192.168.0.99
eth0.netmask=255.255.255.0
eth0.gateway=192.168.0.110
eth0.serverip=192.168.0.110
uimage=uImage-mcf5475
jffs2=root-mcf5475-ptx.jffs2
autoboot_timeout=3
#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs"
nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3"
bootargs="console=ttyS0 rw initcall_debug debug"
#
# setup the partitions in the main flash
#
mtdparts=512k(self),256k(env),3M(kernel),-(root)
rootpart="/dev/mtdblock3"

124
arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c
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@ -1,124 +0,0 @@
/*
* (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains high-level init functions.
*
*/
#include <common.h>
#include <reloc.h>
#include <config.h>
#include <mach/mcf54xx-regs.h>
static void board_gpio_init(void)
{
/*
* Enable Ethernet signals so that, if a cable is plugged into
* the ports, the lines won't be floating and potentially cause
* erroneous transmissions
*/
MCF_GPIO_PAR_FECI2CIRQ = 0
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E17
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E07;
}
static void board_psc_init(void)
{
#if (CFG_EARLY_UART_PORT == 0)
MCF_GPIO_PAR_PSC0 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS
| MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS
#endif
| MCF_GPIO_PAR_PSC0_PAR_TXD0
| MCF_GPIO_PAR_PSC0_PAR_RXD0);
#elif (CFG_EARLY_UART_PORT == 1)
MCF_GPIO_PAR_PSC1 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS
| MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS
#endif
| MCF_GPIO_PAR_PSC1_PAR_TXD1
| MCF_GPIO_PAR_PSC1_PAR_RXD1);
#elif (CFG_EARLY_UART_PORT == 2)
MCF_GPIO_PAR_PSC2 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS
| MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS
#endif
| MCF_GPIO_PAR_PSC2_PAR_TXD2
| MCF_GPIO_PAR_PSC2_PAR_RXD2);
#elif (CFG_EARLY_UART_PORT == 3)
MCF_GPIO_PAR_PSC3 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS
| MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS
#endif
| MCF_GPIO_PAR_PSC3_PAR_TXD3
| MCF_GPIO_PAR_PSC3_PAR_RXD3);
#else
#error "Invalid CFG_EARLY_UART_PORT setting"
#endif
/* Put PSC in UART mode */
MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART;
/* Call generic UART initialization */
// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud());
}
/** Do board specific early init
*
* @note We run at link address now, you can now call other code
*/
void board_init_highlevel(void)
{
/* Initialize platform specific GPIOs */
board_gpio_init();
/* Init UART GPIOs and Modes */
board_psc_init();
/* Setup the early init data */
#ifdef CONFIG_HAS_EARLY_INIT
early_init();
#endif
/* Configure the early debug output facility */
#ifdef CONFIG_DEBUG_LL
early_debug_init();
#endif
}
/** Provide address of early debug low-level output
*
* @todo Should return real address for UART register map.
*/
void *get_early_console_base(const char *name)
{
return (void*)1 + CFG_EARLY_UART_PORT;
}

160
arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c
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@ -1,160 +0,0 @@
/*
* (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <init.h>
#include <driver.h>
#include <fec.h>
#include <environment.h>
#include <mach/mcf54xx-regs.h>
//#include <mach/gpio.h>
#include <mach/clocks.h>
#include <asm/io.h>
#include <partition.h>
/*
* Return board clock in MHz FIXME move to clocks file
*/
ulong mcfv4e_get_bus_clk(void)
{
return CFG_SYSTEM_CORE_CLOCK;
}
/*
* Up to 64MiB NOR type flash, connected to
* CS line 0, data width is 32 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = CFG_FLASH_ADDRESS,
.size = CFG_FLASH_SIZE,
};
/*
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
//static struct device_d sram_dev = {
// .id = -1,
// .name = "sram",
//FIXME .map_base = IMX_CS4_BASE,
//FIXME .size = IMX_CS4_RANGE, /* area size */
//};
/*
* ?MiB NAND type flash, data width 8 bit
*/
//static struct device_d nand_dev = {
// .id = -1,
// .name = "cfi_flash_nand",
// .map_base = 0xfc000000, /* FIXME */
// .size = 32 * 1024 * 1024, /* FIXME */
//};
/*
* Build in FastEthernetControllers (FECs)
*/
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
};
static struct device_d network_dev0 = {
.id = -1,
.name = "fec_mcf54xx",
.map_base = MCF_FEC_ADDR(0),
.size = MCF_FEC_SIZE(0), /* area size */
.platform_data = &fec_info,
};
static struct device_d network_dev1 = {
.id = -1,
.name = "fec_mcf54xx",
.map_base = MCF_FEC_ADDR(1),
.size = MCF_FEC_SIZE(1), /* area size */
.platform_data = &fec_info,
};
/*
* 128MiB of SDRAM, data width is 32 bit
*/
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = CFG_SDRAM_ADDRESS,
.size = CFG_SDRAM_SIZE,
.platform_data = &ram_pdata,
};
static int mcfv4e_devices_init(void)
{
printf("Setting up board devices...\n");
/* setup pins for I2C2 (for EEPROM, RTC) */
//FIXME imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL);
//FIXME imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL);
register_device(&cfi_dev);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
//register_device(&sram_dev);
//register_device(&nand_dev);
register_device(&network_dev0);
//register_device(&network_dev1);
register_device(&sdram_dev);
return 0;
}
device_initcall(mcfv4e_devices_init);
static struct device_d mcfv4e_serial_device = {
.id = -1,
.name = "mcfv4e_serial",
.map_base = 1+CFG_EARLY_UART_PORT,
.size = 16 * 1024,
};
static int mcfv4e_console_init(void)
{
/* init gpios for serial port */
/* Already set in lowlevel_init.c */
register_device(&mcfv4e_serial_device);
return 0;
}
console_initcall(mcfv4e_console_init);

13
arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox
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@ -1,13 +0,0 @@
/** @page kp_ukd_r1 konzeptpark MCB2 Prototype Board
This target is based on a PhyTec PhyCore MCF54x5 NUM CPU. The card is shipped with:
- up to 64MiB NOR type Flash Memory
- 128MiB synchronous dynamic RAM
- PCI USB 2.0 Host
- PCCard Controller
- MiniPCI Parallel
- MiniPCIe (USB lane only)
- ...
*/

183
arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c
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/*
* (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains ...
*
*/
#include <common.h>
#include <config.h>
#include <mach/mcf54xx-regs.h>
/** Initialize board specific very early inits
*
* @note This code is not allowed to call other code - just init
* your Chipselects and SDRAM stuff here!
*/
void board_init_lowlevel(void)
{
/*
* The phyCORE-MCF548x has a 32MB or 64MB boot flash.
* The is a CF Card and ControlRegs on CS1 and CS2
*/
/* Setup SysGlue Chip-Select */
MCF_FBCS_CSAR5 = MCF_FBCS_CSAR_BA(CFG_SYSGLUE_ADDRESS);
MCF_FBCS_CSCR5 = (MCF_FBCS_CSCR_PS_32
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_SYSGLUE_WAIT_STATES));
MCF_FBCS_CSMR5 = (MCF_FBCS_CSMR_BAM_16M
| MCF_FBCS_CSMR_V);
/* Setup boot flash chip-select */
MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);
MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));
MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
| MCF_FBCS_CSMR_V);
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
{
/*
* Basic configuration and initialization
*/
// 0x000002AA
MCF_SDRAMC_SDRAMDS = (0
| MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
);
// 0x0000001A
MCF_SDRAMC_CS0CFG = (0
| MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
| MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
);
MCF_SDRAMC_CS1CFG = 0;
MCF_SDRAMC_CS2CFG = 0;
MCF_SDRAMC_CS3CFG = 0;
// 0x73611730
MCF_SDRAMC_SDCFG1 = (0
| MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
| MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
| MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
| MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_WTLAT(3)
);
// 0x46770000
MCF_SDRAMC_SDCFG2 = (0
| MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
| MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
| MCF_SDRAMC_SDCFG2_BRD2WT(7)
| MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
);
/*
* Precharge and enable write to SDMR
*/
// 0xE10B0002
MCF_SDRAMC_SDCR = (0
| MCF_SDRAMC_SDCR_MODE_EN
| MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_DDR
| MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1
| MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
| MCF_SDRAMC_SDCR_IPALL
);
/*
* Write extended mode register
*/
// 0x40010000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Write mode register and reset DLL
*/
// 0x048d0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Execute a PALL command
*/
// 0xE10B0002
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
/*
* Perform two REF cycles
*/
// 0xE10B0004
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
/*
* Write mode register and clear reset DLL
*/
// 0x008D0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Enable auto refresh and lock SDMR
*/
// 0x610B0000
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
// 0x710B0F00
MCF_SDRAMC_SDCR |= (0
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_DQS_OE(0xF)
);
}
}
/** @file
*
* Target specific early chipselect and SDRAM init.
*/

41
arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c
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/*
* (C) 2007,2008 Carsten Schlote <schlote@vahanus.net>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains callbacks for the PCI subsystem
*
*/
#include <common.h>
#include <config.h>
/** Returns mapping from PCI slot to CPU irq for the target board
* @return Coldfire IRQ vector number, or -1 for no irq
*/
int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin)
{
int rc = -1;
switch (slot)
{
case 16 : break;
case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7
}
return rc;
}

31
arch/m68k/boards/phycore_mcf54xx/Makefile
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@ -1,31 +0,0 @@
#
# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
# See file CREDITS for list of people who contributed to this project.
#
# This file is part of barebox.
#
# barebox is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# barebox is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with barebox. If not, see <http://www.gnu.org/licenses/>.
#
# The build system allows to split everything into distinct files covering an
# separate issue. Use that!
# Board specific callbacks and initialisations
obj-y += lowlevel_init.o
obj-y += highlevel_init.o
obj-y += phyCore_MCF54xx.o
obj-y += pci-stubs.o

36
arch/m68k/boards/phycore_mcf54xx/env/bin/_update vendored
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@ -1,36 +0,0 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

38
arch/m68k/boards/phycore_mcf54xx/env/bin/boot vendored
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@ -1,38 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xflash ]; then
root=flash
kernel=flash
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xflash ]; then
bootargs="$bootargs root=$rootpart rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot"
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
else
bootm /dev/nor0.kernel
fi

20
arch/m68k/boards/phycore_mcf54xx/env/bin/init vendored
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@ -1,20 +0,0 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
addpart /dev/nor0 $mtdparts
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel [<imagename>] to update kernel into flash"
echo "type udate_root [<imagename>] to update rootfs into flash"
echo
exit
fi
boot

14
arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop vendored
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@ -1,14 +0,0 @@
pci stat
pci stat -c
while true; do
pci readm 32 0xA1000000 32 -s
pci readm 32 0xA2000000 256 -s
pci dmatx 2000 a2000100 128 -s
pci writem 32 0xa2000100 0x12345678 4 -s
pci readm 32 0xA3000000 256 -s
pci dmatx 2000 a3000040 128 -s
pci writem 32 0xa3000100 0x12345678 4 -s
pci readm 32 0xA4000000 16 -s
pci dmatx 2000 a4000080 4 -s
pci writem 32 0xa4000080 0x12345678 4 -s
done

13
arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop vendored
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@ -1,13 +0,0 @@
pci stat
pci stat -c
while true; do
pci readm 32 0xA1000000 32 -s
pci readm 32 0xA2000000 256 -s
pci writem 32 0xa2000100 0x12345678 4 -s
pci readm 32 0xA3000000 256 -s
pci writem 32 0xa3000100 0x12345678 4 -s
pci readm 32 0xA4000000 16 -s
pci writem 32 0xa4000080 0x12345678 4 -s
# pci dmatx 2000 a3000040 128 -s
done

8
arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel vendored
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@ -1,8 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
part=/dev/nor0.kernel
. /env/bin/_update $1

8
arch/m68k/boards/phycore_mcf54xx/env/bin/update_root vendored
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@ -1,8 +0,0 @@
#!/bin/sh
. /env/config
image=$jffs2
part=/dev/nor0.root
. /env/bin/_update $1

32
arch/m68k/boards/phycore_mcf54xx/env/config vendored
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@ -1,32 +0,0 @@
#!/bin/sh
# can be either 'net' or 'flash'
kernel=net
root=net
# use 'dhcp' todo dhcp in barebox and in kernel
ip=dhcp
#
# setup default ethernet address
#
eth0.ipaddr=192.168.0.99
eth0.netmask=255.255.255.0
eth0.gateway=192.168.0.110
eth0.serverip=192.168.0.110
uimage=uImage-mcf5485
jffs2=root-mcf5485-ptx.jffs2
autoboot_timeout=3
#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs"
nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3"
bootargs="console=ttyS0 rw initcall_debug debug"
#
# setup the partitions in the main flash
#
mtdparts=512k(self),256k(env),3M(kernel),-(root)
rootpart="/dev/mtdblock3"

124
arch/m68k/boards/phycore_mcf54xx/highlevel_init.c
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@ -1,124 +0,0 @@
/*
* (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains high-level init functions.
*
*/
#include <common.h>
#include <reloc.h>
#include <config.h>
#include <mach/mcf54xx-regs.h>
static void board_gpio_init(void)
{
/*
* Enable Ethernet signals so that, if a cable is plugged into
* the ports, the lines won't be floating and potentially cause
* erroneous transmissions
*/
MCF_GPIO_PAR_FECI2CIRQ = 0
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E17
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII
| MCF_GPIO_PAR_FECI2CIRQ_PAR_E07;
}
static void board_psc_init(void)
{
#if (CFG_EARLY_UART_PORT == 0)
MCF_GPIO_PAR_PSC0 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS
| MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS
#endif
| MCF_GPIO_PAR_PSC0_PAR_TXD0
| MCF_GPIO_PAR_PSC0_PAR_RXD0);
#elif (CFG_EARLY_UART_PORT == 1)
MCF_GPIO_PAR_PSC1 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS
| MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS
#endif
| MCF_GPIO_PAR_PSC1_PAR_TXD1
| MCF_GPIO_PAR_PSC1_PAR_RXD1);
#elif (CFG_EARLY_UART_PORT == 2)
MCF_GPIO_PAR_PSC2 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS
| MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS
#endif
| MCF_GPIO_PAR_PSC2_PAR_TXD2
| MCF_GPIO_PAR_PSC2_PAR_RXD2);
#elif (CFG_EARLY_UART_PORT == 3)
MCF_GPIO_PAR_PSC3 = (0
#ifdef HARDWARE_FLOW_CONTROL
| MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS
| MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS
#endif
| MCF_GPIO_PAR_PSC3_PAR_TXD3
| MCF_GPIO_PAR_PSC3_PAR_RXD3);
#else
#error "Invalid CFG_EARLY_UART_PORT setting"
#endif
/* Put PSC in UART mode */
MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART;
/* Call generic UART initialization */
// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud());
}
/** Do board specific early init
*
* @note We run at link address now, you can now call other code
*/
void board_init_highlevel(void)
{
/* Initialize platform specific GPIOs */
board_gpio_init();
/* Init UART GPIOs and Modes */
board_psc_init();
/* Setup the early init data */
#ifdef CONFIG_HAS_EARLY_INIT
early_init();
#endif
/* Configure the early debug output facility */
#ifdef CONFIG_DEBUG_LL
early_debug_init();
#endif
}
/** Provide address of early debug low-level output
*
* @todo Should return real address for UART register map.
*/
void *get_early_console_base(const char *name)
{
return (void*)1 + CFG_EARLY_UART_PORT;
}

194
arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c
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@ -1,194 +0,0 @@
/*
* (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains ...
*
*/
#include <common.h>
#include <config.h>
#include <mach/mcf54xx-regs.h>
/** Initialize board specific very early inits
*
* @note This code is not allowed to call other code - just init
* your Chipselects and SDRAM stuff here!
*/
void board_init_lowlevel(void)
{
/*
* The phyCORE-MCF548x has a 32MB or 64MB boot flash.
* The is a CF Card and ControlRegs on CS1 and CS2
*/
/* Setup SysGlue Chip-Select for user IOs */
MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS);
MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES));
MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M
| MCF_FBCS_CSMR_V);
/* Setup SysGlue Chip-Select for CFCARD */
MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS);
MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES));
MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M
| MCF_FBCS_CSMR_V);
/* Setup boot flash chip-select */
MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);
MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));
MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
| MCF_FBCS_CSMR_V);
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
{
/*
* Basic configuration and initialization
*/
// 0x000002AA
MCF_SDRAMC_SDRAMDS = (0
| MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
);
// 0x0000001A
MCF_SDRAMC_CS0CFG = (0
| MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
| MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
);
MCF_SDRAMC_CS1CFG = 0;
MCF_SDRAMC_CS2CFG = 0;
MCF_SDRAMC_CS3CFG = 0;
// 0x73611730
MCF_SDRAMC_SDCFG1 = (0
| MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
| MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
| MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
| MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_WTLAT(3)
);
// 0x46770000
MCF_SDRAMC_SDCFG2 = (0
| MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
| MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
| MCF_SDRAMC_SDCFG2_BRD2WT(7)
| MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
);
/*
* Precharge and enable write to SDMR
*/
// 0xE10B0002
MCF_SDRAMC_SDCR = (0
| MCF_SDRAMC_SDCR_MODE_EN
| MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_DDR
| MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1
| MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
| MCF_SDRAMC_SDCR_IPALL
);
/*
* Write extended mode register
*/
// 0x40010000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Write mode register and reset DLL
*/
// 0x048d0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Execute a PALL command
*/
// 0xE10B0002
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
/*
* Perform two REF cycles
*/
// 0xE10B0004
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
/*
* Write mode register and clear reset DLL
*/
// 0x008D0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Enable auto refresh and lock SDMR
*/
// 0x610B0000
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
// 0x710B0F00
MCF_SDRAMC_SDCR |= (0
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_DQS_OE(0xF)
);
}
}
/** @file
*
* Target specific early chipselect and SDRAM init.
*/

41
arch/m68k/boards/phycore_mcf54xx/pci-stubs.c
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@ -1,41 +0,0 @@
/*
* (C) 2007,2008 Carsten Schlote <schlote@vahanus.net>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains callbacks for the PCI subsystem
*
*/
#include <common.h>
#include <config.h>
/** Returns mapping from PCI slot to CPU irq for the target board
* @return Coldfire IRQ vector number, or -1 for no irq
*/
int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin)
{
int rc = -1;
switch (slot)
{
case 16 : break;
case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7
}
return rc;
}

139
arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c
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@ -1,139 +0,0 @@
/*
* (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief This file contains ...
*
*/
#include <common.h>
#include <init.h>
#include <driver.h>
#include <fec.h>
#include <environment.h>
#include <mach/mcf54xx-regs.h>
#include <mach/clocks.h>
#include <asm/io.h>
#include <partition.h>
/*
* Return board clock in MHz FIXME move to clocks file
*/
ulong mcfv4e_get_bus_clk(void)
{
return CFG_SYSTEM_CORE_CLOCK;
}
/*
* Up to 64MiB NOR type flash, connected to
* CS line 0, data width is 32 bit
*/
static struct device_d cfi_dev =
{
.id = -1,
.name = "cfi_flash",
.map_base = CFG_FLASH_ADDRESS,
.size = CFG_FLASH_SIZE,
};
/*
* Build in FastEthernetControllers (FECs)
*/
static struct fec_platform_data fec_info =
{
.xcv_type = MII100,
};
static struct device_d network_dev0 =
{
.id = -1,
.name = "fec_mcf54xx",
.map_base = MCF_FEC_ADDR(0),
.size = MCF_FEC_SIZE(0), /* area size */
.platform_data = &fec_info,
};
static struct device_d network_dev1 =
{
.id = -1,
.name = "fec_mcf54xx",
.map_base = MCF_FEC_ADDR(1),
.size = MCF_FEC_SIZE(1), /* area size */
.platform_data = &fec_info,
};
/*
* 128MiB of SDRAM, data width is 32 bit
*/
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev =
{
.id = -1,
.name = "mem",
.map_base = CFG_SDRAM_ADDRESS,
.size = CFG_SDRAM_SIZE,
.platform_data = &ram_pdata,
};
static int mcfv4e_devices_init(void)
{
printf("FIXME - setup board devices...\n");
register_device(&cfi_dev);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
register_device(&network_dev0);
//register_device(&network_dev1);
register_device(&sdram_dev);
return 0;
}
device_initcall(mcfv4e_devices_init);
static struct device_d mcfv4e_serial_device =
{
.id = -1,
.name = "mcfv4e_serial",
.map_base = 1 + CFG_EARLY_UART_PORT,
.size = 16 * 1024,
};
static int mcfv4e_console_init(void)
{
/* init gpios for serial port */
/* Already set in lowlevel_init.c */
register_device(&mcfv4e_serial_device);
return 0;
}
console_initcall(mcfv4e_console_init);

14
arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox
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@ -1,14 +0,0 @@
/** @page phycore_mcf54xx Phytec's phyCORE-MCF54x5
This target is based on a PhyTec PhyCore MCF54x5 CPU module. The card is shipped with:
- up to 64MiB NOR type Flash Memory
- 128MiB synchronous dynamic RAM
- PCI USB 2.0 Host
- PCCard Controller
- MiniPCI Parallel
- MiniPCIe (USB lane only)
- ...
*/

36
arch/m68k/configs/phycore_kpukdr1_5475num_defconfig
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@ -1,36 +0,0 @@
CONFIG_MACH_KPUKDR1_NUM=y
CONFIG_INITRD_TAG=y
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
CONFIG_LONGHELP=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/kp_ukd_r1_num/env/"
CONFIG_DEBUG_INFO=y
CONFIG_ENABLE_DEVICE_NOISE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_FS_CRAMFS=y

36
arch/m68k/configs/phycore_mcf54xx_defconfig
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@ -1,36 +0,0 @@
CONFIG_MACH_PCM982_5485=y
CONFIG_INITRD_TAG=y
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
CONFIG_LONGHELP=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/phycore_mcf54xx/env"
CONFIG_DEBUG_INFO=y
CONFIG_ENABLE_DEVICE_NOISE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_FS_CRAMFS=y

41
arch/m68k/cpu/Makefile
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@ -1,41 +0,0 @@
#
# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
# See file CREDITS for list of people who contributed to this project.
#
# This file is part of barebox.
#
# barebox is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# barebox is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with barebox. If not, see <http://www.gnu.org/licenses/>.
#
obj-y += cpu.o
obj-y += interrupts.o
#
# Support code for early IO over BDM wigglers
#
# obj-y += early_init_support.o
#
# Support for relocated early initdata
#
obj-$(CONFIG_HAS_EARLY_INIT) += early_init_support.o
#
# Startup codes - try to merge them into single file!
#
obj-$(CONFIG_ARCH_MCF54xx) += start-mcfv4e.o
obj-$(CONFIG_ARCH_MCF5445x) += start-mcfv4m.o
start-mcfv4e.o : start-mcfv4e.s

185
arch/m68k/cpu/cpu.c
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@ -1,185 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* A few helper functions for M6kK/Coldfire
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <proc/processor.h> // FIXME -stup place
#include <mach/mcf54xx-regs.h>
static uint32_t CACR_shadow = MCF5XXX_CACR_BEC;
/*
* Reset init value := 0x010C0100
* MCF5XXX_CACR_DCINVA
* MCF5XXX_CACR_BEC
* MCF5XXX_CACR_BCINVA
* MCF5XXX_CACR_ICINVA
*/
/**
* Enable processor's instruction cache
*/
void icache_enable (void)
{
CACR_shadow |= MCF5XXX_CACR_IEC;
mcf5xxx_wr_cacr( CACR_shadow );
}
/**
* Disable processor's instruction cache
*/
void icache_disable (void)
{
CACR_shadow &= ~MCF5XXX_CACR_IEC;
mcf5xxx_wr_cacr( CACR_shadow );
}
/**
* Detect processor's current instruction cache status
* @return 0=disabled, 1=enabled
*/
int icache_status (void)
{
return (CACR_shadow & MCF5XXX_CACR_IEC)?1:0;
}
/**
* Enable processor's data cache
*/
void dcache_enable (void)
{
CACR_shadow |= MCF5XXX_CACR_DEC;
mcf5xxx_wr_cacr( CACR_shadow );
}
/**
* Disable processor's data cache
*/
void dcache_disable (void)
{
CACR_shadow &= ~MCF5XXX_CACR_DEC;
mcf5xxx_wr_cacr( CACR_shadow );
}
/**
* Detect processor's current instruction cache status
* @return 0=disabled, 1=enabled
*/
int dcache_status (void)
{
return (CACR_shadow & MCF5XXX_CACR_DEC)?1:0;
}
/**
* Flush CPU caches to memory
*/
void cpu_cache_flush(void)
{
uint32_t way, set;
void *addr;
for ( way=0; way < 4; way++ ) {
addr = (void*)way;
for ( set=0; set < 512; set++ ) {
mcf5xxx_cpushl_bc ( addr );
addr += 0x10;
}
}
}
/**
* Flush CPU caches to memory and disable them.
*/
void cpu_cache_disable(void)
{
uint32_t lastipl;
lastipl = asm_set_ipl( 7 );
cpu_cache_flush();
mcf5xxx_wr_acr0( 0 );
mcf5xxx_wr_acr1( 0 );
mcf5xxx_wr_acr2( 0 );
mcf5xxx_wr_acr3( 0 );
CACR_shadow &= ~MCF5XXX_CACR_IEC;
CACR_shadow &= ~MCF5XXX_CACR_DEC;
mcf5xxx_wr_cacr( CACR_shadow | (MCF5XXX_CACR_DCINVA|MCF5XXX_CACR_ICINVA));
lastipl = asm_set_ipl( lastipl );
}
/**
* Prepare a "clean" CPU for Linux to run
* @return 0 (always)
*
* This function is called by the generic barebox part just before we call
* Linux. It prepares the processor for Linux.
*/
int cleanup_before_linux (void)
{
/*
* we never enable dcache so we do not need to disable
* it. Linux can be called with icache enabled, so just
* do nothing here
*/
/* flush I/D-cache */
cpu_cache_disable();
/* reenable icache */
icache_enable();
return (0);
}
/** @page m68k_boot_preparation Linux Preparation on M68k/Coldfire
*
* For M68K we never enable data cache so we do not need to disable it again.
*
* Linux can be called with instruction cache enabled. As this is the
* default setting we are running in barebox, there's no special preparation
* required.
*/
/** Early init of Coldfire V4E CPU
*/
static int cpu_init (void)
{
/* Enable ICache - branch cache is already on */
icache_enable();
/*
* setup up stacks if necessary
* setup other CPU specifics here to prepare
* handling of exceptions and interrupts
*/
#ifdef CONFIG_USE_IRQ
printf("Prepare CPU interrupts for handlers\n");
mcf_interrupts_initialize();
#endif
return 0;
}
core_initcall(cpu_init);

116
arch/m68k/cpu/cw_console_io.c
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@ -1,116 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Debug output stubs over BDM for Codewarrior
*/
#include <common.h>
#include <command.h>
#include <console.h>
#include <reloc.h>
#include <init.h>
#ifdef CONFIG_HAS_EARLY_INIT
#if 0 // FIXME - make a CW debug port serial driver for barebox
/*
* The result of an I/O command can be any one of the following.
*/
typedef enum DSIOResult
{
kDSIONoError = 0x00,
kDSIOError = 0x01,
kDSIOEOF = 0x02
} DSIOResult;
/*
* MessageCommandID
*/
typedef enum MessageCommandID
{
/*
* target->host support commands
*/
kDSWriteFile = 0xD0, /* L2 L3 */
kDSReadFile = 0xD1 /* L2 L3 */
} MessageCommandID;
enum DSIOResult TransferData(
MessageCommandID msg,
unsigned char *buffer, int size,
int * txsize
)
{
enum DSIOResult iores = kDSIOError;
unsigned long sized2=0;
/* -- Call codewarrior stub -- */
__asm__ __volatile__ (
" move.l %[cmd],%%d0 \n"
" move.l #0,%%d1 \n"
" move.l %[size],%%d2 \n"
" move.l %[buffer],%%d3 \n"
" trap #14 \n"
" move.l %%d1,%[txsize] \n"
" move.l %%d0,%[res] \n"
: [res] "=r" (iores), [txsize] "=g" (sized2)
: [cmd] "g" (msg), [size] "g" (size), [buffer] "g" (buffer)
: "d2","d3" );
if (txsize!=NULL) *txsize=sized2;
return iores;
}
void *get_early_console_base(const char *name)
{
return (void*)0xdeadbeef;
}
static unsigned char early_iobuffer[80];
static int early_iobuffer_cnt;
void early_console_putc(void *base, char c)
{
early_iobuffer[early_iobuffer_cnt++] = c;
if ( ( early_iobuffer_cnt >= sizeof(early_iobuffer)) ||
(c == '\n') )
{
TransferData(kDSWriteFile,early_iobuffer,early_iobuffer_cnt, NULL);
early_iobuffer_cnt = 0;
}
}
void early_console_init(void *base, int baudrate)
{
early_iobuffer_cnt = 0;
}
//void early_console_start(const char *name, int baudrate)
//{
//}
#endif
#endif

41
arch/m68k/cpu/early_init_support.c
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@ -1,41 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Early InitData support routines
*/
#include <common.h>
#include <command.h>
#include <console.h>
#include <reloc.h>
#include <init.h>
#ifdef CONFIG_HAS_EARLY_INIT
/** Returns relocation offset to early init data
*/
unsigned long reloc_offset(void)
{
//extern char __early_init_data_begin[];
//FIXME: return (unsigned long)init_data_ptr - (unsigned long)__early_init_data_begin;
return 0;
}
#endif

246
arch/m68k/cpu/interrupts.c
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@ -1,246 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Interrupt routines and supporting code for Coldfire V4E
*/
#include <common.h>
#include <asm/ptrace.h>
#include <mach/mcf54xx-regs.h>
#ifdef CONFIG_USE_IRQ
void enable_interrupts(void)
{
asm_set_ipl(0);
}
int disable_interrupts(void)
{
return asm_set_ipl(7) ? 1 : 0;
}
#endif
/**
*/
static void mcf_bad_mode (void)
{
panic ("Resetting CPU ...\n");
mdelay(3000);
reset_cpu (0);
}
/**
*/
static void mcf_show_regs (struct pt_regs *regs)
{
unsigned long flags;
flags = condition_codes (regs);
printf ("pc : [<%08lx>]\n"
"sp : %08lx fp : %08lx\n",
instruction_pointer (regs),
regs->M68K_sp, regs->M68K_a6);
printf ("d0-d3 : %08lx %08lx %08lx %08lx\n",
regs->M68K_d0, regs->M68K_d1, regs->M68K_d2, regs->M68K_d3);
printf ("d3-d7 : %08lx %08lx %08lx %08lx\n",
regs->M68K_d3, regs->M68K_d4, regs->M68K_d5, regs->M68K_d6);
printf ("a0-d3 : %08lx %08lx %08lx %08lx\n",
regs->M68K_a0, regs->M68K_a1, regs->M68K_a2, regs->M68K_a3);
printf ("a3-d7 : %08lx %08lx %08lx %08lx\n",
regs->M68K_a3, regs->M68K_a4, regs->M68K_a5, regs->M68K_a6);
printf ("fp0 : %08lx%08lx fp1 : %08lx%08lx\n",
regs->M68K_fp0+1, regs->M68K_fp0, regs->M68K_fp1+1, regs->M68K_fp1);
printf ("fp2 : %08lx%08lx fp3 : %08lx%08lx\n",
regs->M68K_fp2+1, regs->M68K_fp2, regs->M68K_fp3+1, regs->M68K_fp3);
printf ("fp4 : %08lx%08lx fp5 : %08lx%08lx\n",
regs->M68K_fp4+1, regs->M68K_fp4, regs->M68K_fp5+1, regs->M68K_fp5);
printf ("fp6 : %08lx%08lx fp7 : %08lx%08lx\n",
regs->M68K_fp6+1, regs->M68K_fp6, regs->M68K_fp7+1, regs->M68K_fp7);
printf ("Flags: %c%c%c%c",
flags & CC_X_BIT ? 'X' : 'x',
flags & CC_N_BIT ? 'N' : 'n',
flags & CC_Z_BIT ? 'Z' : 'z',
flags & CC_V_BIT ? 'V' : 'v',
flags & CC_C_BIT ? 'C' : 'c' );
printf (" IRQs %s (%0x) Mode %s\n",
interrupts_enabled (regs) ? "on" : "off", interrupts_enabled (regs),
user_mode (regs) ? "user" : "supervisor");
}
void mcf_execute_exception_handler (struct pt_regs *pt_regs)
{
printf ("unhandled exception\n");
mcf_show_regs (pt_regs);
mcf_bad_mode ();
}
#ifndef CONFIG_USE_IRQ
void mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector)
{
printf ("interrupt request\n");
mcf_show_regs (pt_regs);
mcf_bad_mode ();
}
#else
#ifndef CONFIG_MAX_ISR_HANDLERS
#define CONFIG_MAX_ISR_HANDLERS (20)
#endif
typedef struct
{
int vector;
int (*handler)(void *, void *);
void *hdev;
void *harg;
}
mcfv4e_irq_handler_s;
mcfv4e_irq_handler_s irq_handler_table[CONFIG_MAX_ISR_HANDLERS];
/** Initialize an empty interrupt handler list
*/
void mcf_interrupts_initialize (void)
{
int index;
for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++)
{
irq_handler_table[index].vector = 0;
irq_handler_table[index].handler = 0;
irq_handler_table[index].hdev = 0;
irq_handler_table[index].harg = 0;
}
}
/** Add an interrupt handler to the handler list
*
* @param vector : M68k exception/interrupt vector number
* @param handler : Pointer to handler function
* @param hdev : Handler specific data
* @param harg : Handler specific arg
*/
int mcf_interrupts_register_handler(
int vector,
int (*handler)(void *, void *), void *hdev, void *harg)
{
/*
* This function places an interrupt handler in the ISR table,
* thereby registering it so that the low-level handler may call it.
*
* The two parameters are intended for the first arg to be a
* pointer to the device itself, and the second a pointer to a data
* structure used by the device driver for that particular device.
*/
int index;
if ((vector == 0) || (handler == NULL))
{
return 0;
}
for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++)
{
if (irq_handler_table[index].vector == vector)
{
/* only one entry of each type per vector */
return 0;
}
if (irq_handler_table[index].vector == 0)
{
irq_handler_table[index].vector = vector;
irq_handler_table[index].handler = handler;
irq_handler_table[index].hdev = hdev;
irq_handler_table[index].harg = harg;
return 1;
}
}
return 0; /* no available slots */
}
/** Remove an interrupt handler from the handler list
*
* @param type : FIXME
* @param handler : Pointer of handler function to remove.
*/
void mcf_interrupts_remove_handler (int type ,int (*handler)(void *, void *))
{
/*
* This routine removes from the ISR table all
* entries that matches 'handler'.
*/
int index;
for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++)
{
if (irq_handler_table[index].handler == handler)
{
irq_handler_table[index].vector = 0;
irq_handler_table[index].handler = 0;
irq_handler_table[index].hdev = 0;
irq_handler_table[index].harg = 0;
}
}
}
/** Traverse list of registered interrupts and call matching handlers.
*
* @param pt_regs : Pointer to saved register context
* @param vector : M68k exception/interrupt vector number
*/
int mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector)
{
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*/
int index, retval = 0;
/*
* Try to locate a user-registered Interrupt Service Routine handler.
*/
for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++)
{
if (irq_handler_table[index].handler == NULL)
{
printf("\nFault: No handler for IRQ vector %ld found.\n", vector);
break;
}
if (irq_handler_table[index].vector == vector)
{
if (irq_handler_table[index].handler(irq_handler_table[index].hdev,irq_handler_table[index].harg))
{
retval = 1;
break;
}
}
}
return retval;
}
#endif

677
arch/m68k/cpu/start-mcfv4e.S
View File

@ -1,677 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Resetcode and exception/interrupt shells for Coldfire V4E
*
* This file contains the common startup code for use on at least Coldfire
* V4E cores:
* - MCF547x
* - MCF548x
*/
#include <config.h>
.section ".vectors","a"
/*
* Define some addresses from your board configuration file
*/
.equ __MBAR,CFG_MBAR_ADDRESS
.globl __MBAR
.equ __CORE_SRAM0,CFG_CORE0_SRAM_ADDRESS
.equ __CORE_SRAM0_SIZE,CFG_CORE0_SRAM_SIZE
.equ __CORE_SRAM1,CFG_CORE1_SRAM_ADDRESS
.equ __CORE_SRAM1_SIZE,CFG_CORE1_SRAM_SIZE
/*
* Preload stack pointer with end of Core SRAM - useable _after_ you have
* setup the MBR register in reset code!
*
* The upper 4 LW of the Core SRAM are left spare - it can be used as
* fixed address temporay storage in the code below (ok, well also to
* fix up stack traces in the debugger)
*
* So we have a stack usable for C code, before we even started SDRAM!
*/
.equ ___SP_INIT,__CORE_SRAM1+__CORE_SRAM1_SIZE-16
/*
* Vector table for M68k and barebox Link Address
*
* On M68k/Coldfire cores all exceptions and interrupts are routed through
* a vector array. This vector is by default at address 0x0000_0000, but
* can be moved to any other 1MB aligned address.
*
* We take advantage of this to move barebox out of low memory. Some BDM
* debuggers won't like a moved vector base and might need tweaking to
* work.
*
* Note: Respect alignment restrictions for TEXT_BASE, which must be
* 1MB aligned.
*/
.globl _barebox_start
_barebox_start:
VECTOR_TABLE:
_VECTOR_TABLE:
INITSP: .long ___SP_INIT /* Initial SP */
INITPC: .long 0x410 /* Initial PC */
vector02: .long _asm_exception_handler /* Access Error */
vector03: .long _asm_exception_handler /* Address Error */
vector04: .long _asm_exception_handler /* Illegal Instruction */
vector05: .long _asm_exception_handler /* Divide by Zero */
vector06: .long _asm_exception_handler /* Reserved */
vector07: .long _asm_exception_handler /* Reserved */
vector08: .long _asm_exception_handler /* Privilege Violation */
vector09: .long _asm_exception_handler /* Trace */
vector0A: .long _asm_exception_handler /* Unimplemented A-Line */
vector0B: .long _asm_exception_handler /* Unimplemented F-Line */
vector0C: .long _asm_exception_handler /* Non-PC Brkpt Debug Int */
vector0D: .long _asm_exception_handler /* PC Brkpt Debug Int */
vector0E: .long _asm_exception_handler /* Format Error */
vector0F: .long _asm_exception_handler /* Unitialized Int */
vector10: .long _asm_exception_handler /* Reserved */
vector11: .long _asm_exception_handler /* Reserved */
vector12: .long _asm_exception_handler /* Reserved */
vector13: .long _asm_exception_handler /* Reserved */
vector14: .long _asm_exception_handler /* Reserved */
vector15: .long _asm_exception_handler /* Reserved */
vector16: .long _asm_exception_handler /* Reserved */
vector17: .long _asm_exception_handler /* Reserved */
vector18: .long _asm_exception_handler /* Spurious Interrupt */
vector19: .long _asm_isr_handler /* Autovector Level 1 */
vector1A: .long _asm_isr_handler /* Autovector Level 2 */
vector1B: .long _asm_isr_handler /* Autovector Level 3 */
vector1C: .long _asm_isr_handler /* Autovector Level 4 */
vector1D: .long _asm_isr_handler /* Autovector Level 5 */
vector1E: .long _asm_isr_handler /* Autovector Level 6 */
vector1F: .long _asm_isr_handler /* Autovector Level 7 */
vector20: .long _asm_exception_handler /* TRAP #0 */
vector21: .long _asm_exception_handler /* TRAP #1 */
vector22: .long _asm_exception_handler /* TRAP #2 */
vector23: .long _asm_exception_handler /* TRAP #3 */
vector24: .long _asm_exception_handler /* TRAP #4 */
vector25: .long _asm_exception_handler /* TRAP #5 */
vector26: .long _asm_exception_handler /* TRAP #6 */
vector27: .long _asm_exception_handler /* TRAP #7 */
vector28: .long _asm_exception_handler /* TRAP #8 */
vector29: .long _asm_exception_handler /* TRAP #9 */
vector2A: .long _asm_exception_handler /* TRAP #10 */
vector2B: .long _asm_exception_handler /* TRAP #11 */
vector2C: .long _asm_exception_handler /* TRAP #12 */
vector2D: .long _asm_exception_handler /* TRAP #13 */
vector2E: .long _asm_exception_handler /* TRAP #14 */
vector2F: .long _dbug_sc_handler /* TRAP #15 - System Call */
vector30: .long _asm_exception_handler /* Reserved */
vector31: .long _asm_exception_handler /* Reserved */
vector32: .long _asm_exception_handler /* Reserved */
vector33: .long _asm_exception_handler /* Reserved */
vector34: .long _asm_exception_handler /* Reserved */
vector35: .long _asm_exception_handler /* Reserved */
vector36: .long _asm_exception_handler /* Reserved */
vector37: .long _asm_exception_handler /* Reserved */
vector38: .long _asm_exception_handler /* Reserved */
vector39: .long _asm_exception_handler /* Reserved */
vector3A: .long _asm_exception_handler /* Reserved */
vector3B: .long _asm_exception_handler /* Reserved */
vector3C: .long _asm_exception_handler /* Reserved */
vector3D: .long _asm_exception_handler /* Unsupported Instruction */
vector3E: .long _asm_exception_handler /* Reserved */
vector3F: .long _asm_exception_handler /* Reserved */
vector40: .long _asm_isr_handler /* User Defined Interrupts */
vector41: .long _asm_isr_handler
vector42: .long _asm_isr_handler
vector43: .long _asm_isr_handler
vector44: .long _asm_isr_handler
vector45: .long _asm_isr_handler
vector46: .long _asm_isr_handler
vector47: .long _asm_isr_handler
vector48: .long _asm_isr_handler
vector49: .long _asm_isr_handler
vector4A: .long _asm_isr_handler
vector4B: .long _asm_isr_handler
vector4C: .long _asm_isr_handler
vector4D: .long _asm_isr_handler
vector4E: .long _asm_isr_handler
vector4F: .long _asm_isr_handler
vector50: .long _asm_isr_handler
vector51: .long _asm_isr_handler
vector52: .long _asm_isr_handler
vector53: .long _asm_isr_handler
vector54: .long _asm_isr_handler
vector55: .long _asm_isr_handler
vector56: .long _asm_isr_handler
vector57: .long _asm_isr_handler
vector58: .long _asm_isr_handler
vector59: .long _asm_isr_handler
vector5A: .long _asm_isr_handler
vector5B: .long _asm_isr_handler
vector5C: .long _asm_isr_handler
vector5D: .long _asm_isr_handler
vector5E: .long _asm_isr_handler
vector5F: .long _asm_isr_handler
vector60: .long _asm_isr_handler
vector61: .long _asm_isr_handler
vector62: .long _asm_isr_handler
vector63: .long _asm_isr_handler
vector64: .long _asm_isr_handler
vector65: .long _asm_isr_handler
vector66: .long _asm_isr_handler
vector67: .long _asm_isr_handler
vector68: .long _asm_isr_handler
vector69: .long _asm_isr_handler
vector6A: .long _asm_isr_handler
vector6B: .long _asm_isr_handler
vector6C: .long _asm_isr_handler
vector6D: .long _asm_isr_handler
vector6E: .long _asm_isr_handler
vector6F: .long _asm_isr_handler
vector70: .long _asm_isr_handler
vector71: .long _asm_isr_handler
vector72: .long _asm_isr_handler
vector73: .long _asm_isr_handler
vector74: .long _asm_isr_handler
vector75: .long _asm_isr_handler
vector76: .long _asm_isr_handler
vector77: .long _asm_isr_handler
vector78: .long _asm_isr_handler
vector79: .long _asm_isr_handler
vector7A: .long _asm_isr_handler
vector7B: .long _asm_isr_handler
vector7C: .long _asm_isr_handler
vector7D: .long _asm_isr_handler
vector7E: .long _asm_isr_handler
vector7F: .long _asm_isr_handler
vector80: .long _asm_isr_handler
vector81: .long _asm_isr_handler
vector82: .long _asm_isr_handler
vector83: .long _asm_isr_handler
vector84: .long _asm_isr_handler
vector85: .long _asm_isr_handler
vector86: .long _asm_isr_handler
vector87: .long _asm_isr_handler
vector88: .long _asm_isr_handler
vector89: .long _asm_isr_handler
vector8A: .long _asm_isr_handler
vector8B: .long _asm_isr_handler
vector8C: .long _asm_isr_handler
vector8D: .long _asm_isr_handler
vector8E: .long _asm_isr_handler
vector8F: .long _asm_isr_handler
vector90: .long _asm_isr_handler
vector91: .long _asm_isr_handler
vector92: .long _asm_isr_handler
vector93: .long _asm_isr_handler
vector94: .long _asm_isr_handler
vector95: .long _asm_isr_handler
vector96: .long _asm_isr_handler
vector97: .long _asm_isr_handler
vector98: .long _asm_isr_handler
vector99: .long _asm_isr_handler
vector9A: .long _asm_isr_handler
vector9B: .long _asm_isr_handler
vector9C: .long _asm_isr_handler
vector9D: .long _asm_isr_handler
vector9E: .long _asm_isr_handler
vector9F: .long _asm_isr_handler
vectorA0: .long _asm_isr_handler
vectorA1: .long _asm_isr_handler
vectorA2: .long _asm_isr_handler
vectorA3: .long _asm_isr_handler
vectorA4: .long _asm_isr_handler
vectorA5: .long _asm_isr_handler
vectorA6: .long _asm_isr_handler
vectorA7: .long _asm_isr_handler
vectorA8: .long _asm_isr_handler
vectorA9: .long _asm_isr_handler
vectorAA: .long _asm_isr_handler
vectorAB: .long _asm_isr_handler
vectorAC: .long _asm_isr_handler
vectorAD: .long _asm_isr_handler
vectorAE: .long _asm_isr_handler
vectorAF: .long _asm_isr_handler
vectorB0: .long _asm_isr_handler
vectorB1: .long _asm_isr_handler
vectorB2: .long _asm_isr_handler
vectorB3: .long _asm_isr_handler
vectorB4: .long _asm_isr_handler
vectorB5: .long _asm_isr_handler
vectorB6: .long _asm_isr_handler
vectorB7: .long _asm_isr_handler
vectorB8: .long _asm_isr_handler
vectorB9: .long _asm_isr_handler
vectorBA: .long _asm_isr_handler
vectorBB: .long _asm_isr_handler
vectorBC: .long _asm_isr_handler
vectorBD: .long _asm_isr_handler
vectorBE: .long _asm_isr_handler
vectorBF: .long _asm_isr_handler
vectorC0: .long _asm_isr_handler
vectorC1: .long _asm_isr_handler
vectorC2: .long _asm_isr_handler
vectorC3: .long _asm_isr_handler
vectorC4: .long _asm_isr_handler
vectorC5: .long _asm_isr_handler
vectorC6: .long _asm_isr_handler
vectorC7: .long _asm_isr_handler
vectorC8: .long _asm_isr_handler
vectorC9: .long _asm_isr_handler
vectorCA: .long _asm_isr_handler
vectorCB: .long _asm_isr_handler
vectorCC: .long _asm_isr_handler
vectorCD: .long _asm_isr_handler
vectorCE: .long _asm_isr_handler
vectorCF: .long _asm_isr_handler
vectorD0: .long _asm_isr_handler
vectorD1: .long _asm_isr_handler
vectorD2: .long _asm_isr_handler
vectorD3: .long _asm_isr_handler
vectorD4: .long _asm_isr_handler
vectorD5: .long _asm_isr_handler
vectorD6: .long _asm_isr_handler
vectorD7: .long _asm_isr_handler
vectorD8: .long _asm_isr_handler
vectorD9: .long _asm_isr_handler
vectorDA: .long _asm_isr_handler
vectorDB: .long _asm_isr_handler
vectorDC: .long _asm_isr_handler
vectorDD: .long _asm_isr_handler
vectorDE: .long _asm_isr_handler
vectorDF: .long _asm_isr_handler
vectorE0: .long _asm_isr_handler
vectorE1: .long _asm_isr_handler
vectorE2: .long _asm_isr_handler
vectorE3: .long _asm_isr_handler
vectorE4: .long _asm_isr_handler
vectorE5: .long _asm_isr_handler
vectorE6: .long _asm_isr_handler
vectorE7: .long _asm_isr_handler
vectorE8: .long _asm_isr_handler
vectorE9: .long _asm_isr_handler
vectorEA: .long _asm_isr_handler
vectorEB: .long _asm_isr_handler
vectorEC: .long _asm_isr_handler
vectorED: .long _asm_isr_handler
vectorEE: .long _asm_isr_handler
vectorEF: .long _asm_isr_handler
vectorF0: .long _asm_isr_handler
vectorF1: .long _asm_isr_handler
vectorF2: .long _asm_isr_handler
vectorF3: .long _asm_isr_handler
vectorF4: .long _asm_isr_handler
vectorF5: .long _asm_isr_handler
vectorF6: .long _asm_isr_handler
vectorF7: .long _asm_isr_handler
vectorF8: .long _asm_isr_handler
vectorF9: .long _asm_isr_handler
vectorFA: .long _asm_isr_handler
vectorFB: .long _asm_isr_handler
vectorFC: .long _asm_isr_handler
vectorFD: .long _asm_isr_handler
vectorFE: .long _asm_isr_handler
vectorFF: .long _asm_isr_handler
/*
* Leave some bytes spare here for CW debugger (console IO stuff)
*/
.rept 4
.long 0xdeadbeef
.endr
/** @func reset Startup Code (reset vector)
*
* The vector array is mapped to address 0 at reset and SP and PC are
* fetched from adress 0 and 4.
*
* For debugger uploads this image will reside in the middle of RAM, leaving
* as much memory for other stuff in low memory available, e.g. Linux and
* an init ramdisk.
*
* For real system resets, the boot rom is mapped to all addresses in
* system, as long as somebody sets up the CS. Now the trick part until
* relocation to RAM is that we must code at the start of your bootrom
* - all link addresses are wrong, so we need the reloc.h stuff to find the
* right address.
*
* The following things happen here:
* * do important init, like SDRAM, only if we don't start from memory!
* * setup Memory and board specific bits prior to relocation.
* * Setup stack
* * relocate barebox to ram
*
*/
.globl _start
_start:
.global reset
reset:
/* Mask all IRQs */
move.w #0x2700,%sr
/* Initialize MBAR - keep D0/D1 registers */
move.l #__MBAR,%d2
movec %d2,%MBAR
nop
/* Initialize RAMBAR0 - locate it on the data bus */
move.l #__CORE_SRAM0,%d2
add.l #0x21,%d2
movec %d2,%RAMBAR0
nop
/* Initialize RAMBAR1 - locate it on the data bus */
move.l #__CORE_SRAM1,%d2
add.l #0x21,%d2
movec %d2,%RAMBAR1
nop
/* Point Stack Pointer into Core SRAM temporarily */
move.l #___SP_INIT,%d2
move.l %d2,%sp
nop
/* Invalidate the data, instruction, and branch caches */
/* Turn on the branch cache */
move.l #0x010C0100,%d2
movec %d2,%cacr
nop
/* Prepare stack top */
clr.l %sp@(0)
move.l %d0,%sp@(4)
move.l %d1,%sp@(8)
clr.l %sp@(12)
/*
* This call is intended to give all developers a chance to use a
* standard reset vector file, but also do some special things
* required only on their specific CPU.
*/
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
bsr.l arch_init_lowlevel
nop
#endif
/*
* If the code vector table is not at TEXT_BASE and so this code
* as well, jump to the address mirror at FLASH ROM start address
*
* So load your image to TEXT_BASE for debugging or flash a binary
* image to your bootflash - code below will take proper action.
*/
lea.l %pc@(VECTOR_TABLE),%a0
move.l #TEXT_BASE,%a1
cmp.l %a0,%a1
beq.s saveland
/*
* Execution is not at TEXT_BASE. We assume entry to this code by
* a hardware reset and change execution to address of _FLASH_ rom.
*/
lea.l %pc@(saveland),%a0 // Effective ! Address of label below
move.l %a0,%d0
and.l #0x00ffffff,%d0 // Cut away address high byte
move.l #CFG_FLASH_ADDRESS,%d1 // Get flash address
and.l #0xff000000,%d1 // and just take base for CS0
or.l %d1,%d0 // Compose new address
move.l %d0,%a0
jmp %a0@ // Jump to flash rom address!
nop
/* We now either in SDRAM or FLASH START addresses, save to
change chip selects */
saveland:
nop
/*
* Before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.[c|S] in your board directory.
*
* Do not jump/call other barebox code here!
*/
#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
bsr.l board_init_lowlevel
nop
#endif
/*
* relocate barebox Code to RAM (including copy of vectors)
*/
relocate:
lea.l %pc@(VECTOR_TABLE),%a0
move.l #TEXT_BASE,%a1
move.l #__bss_start,%a3
cmp.l %a0,%a1
beq.s skip_relocate
/*
* Calculate number of long words, and copy them to RAM
*/
move.l %a3,%d2
sub.l %a1,%d2
asr.l #2,%d2
copy_loop:
move.l %a0@+,%a1@+
subq.l #1,%d2
bne.s copy_loop
skip_relocate:
/* Clear BSS segment in RAM */
clear_bss:
move.l #__bss_end,%a4
moveq.l #0,%d2
clear_loop:
move.l %d2,%a3@+
cmp.l %a4,%a3
ble.s clear_loop
/*
* Relocate Vectors to memory start (address 0)
*
* NOTE: It could be at other places, but debuggers expect
* this table to be at address 0.
*/
#ifdef CONFIG_COPY_LOWMEM_VECTORS
reloc_vectors:
lea.l %pc@(VECTOR_TABLE),%a0
move.l #0,%a1
cmp.l %a0,%a1
beq.s skip_copy_vectors
move.l #0x100,%d2
copy_loop_vectors:
move.l %a0@+,%a1@+
subq.l #1,%d2
bne.s copy_loop_vectors
skip_copy_vectors:
#endif
#ifndef CONFIG_USE_LOWMEM_VECTORS
move.l #TEXT_BASE,%d0
movec %d0,%vbr
nop
#endif
#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
/*
* Call other half of initcode in relocated code
*
* You allowed to call other barebox code from here
*/
jsr.l board_init_highlevel
nop
#endif
/*
* Now jump to real link address and barebox entry point
*/
nop
jmp.l start_barebox
nop
nop
/*
* Interrupt handling
*/
/*
* IRQ stack frame.
*/
#define S_FRAME_SIZE 148
#define S_SP S_A7
#define S_SR 144
#define S_PC 140
#define S_FPIAR 136
#define S_FPSR 132
#define S_FPCR 128
#define S_FP7 120
#define S_FP6 112
#define S_FP5 104
#define S_FP4 96
#define S_FP3 88
#define S_FP2 80
#define S_FP1 72
#define S_FP0 64
#define S_A7 60
#define S_A6 56
#define S_A5 52
#define S_A4 48
#define S_A3 44
#define S_A2 40
#define S_A1 36
#define S_A0 32
#define S_D7 28
#define S_D6 24
#define S_D5 20
#define S_D4 16
#define S_D3 12
#define S_D2 8
#define S_D1 4
#define S_D0 0
/*
* exception handlers
*/
#ifdef CONFIG_USE_IRQ
.global _dbug_sc_handler
_dbug_sc_handler:
.global _asm_exception_handler
_asm_exception_handler:
move.w #0x2700,%sr /* Disable IRQs */
move.l %sp,___SP_INIT /* Remember on top of stack */
move.l #___SP_INIT,%sp /* Set stack to known area */
move.l %a0,%sp@-
lea _asm_context,%a0
movem.l %d0-%d7/%a0-%a7,%a0@
fmovem %fp0-%fp7,%a0@(S_FP0)
fmove.l %fpcr,%a0@(S_FPCR)
fmove.l %fpsr,%a0@(S_FPSR)
fmove.l %fpiar,%a0@(S_FPIAR)
move.l %sp@+,%a0@(S_A0)
move.l %sp@,%a1
move.l %a1,%a0@(S_SP)
move.l %a1@(4),%a0@(S_PC)
move.w %a1@(2),%a0@(S_SR)
jsr cpu_cache_flush
nop
move.l %a1,%sp@-
jsr mcf_execute_exception_handler
lea _asm_context,%a0
move.l %a0@(S_SP),%sp
move.l %a0@(S_D1),%d1
move.l %a0@(S_D0),%d0
move.l %a0@(S_A1),%a1
move.l %a0@(S_A0),%a0
rte
nop
nop
.global _asm_isr_handler
_asm_isr_handler:
link %a6,#-16
movem.l %d0-%d1/%a0-%a1,%sp@
move.w %a6@(4),%d0
lsr.l #2,%d0
andi.l #0x0000FF,%d0
move.l %d0,%sp@-
move.l #0,%a0
move.l %a0,%sp@-
jsr mcf_execute_irq_handler
lea %sp@(8),%sp
cmpi.l #1,%d0
beq handled
nothandled:
movem.l %sp@,%d0-%d1/%a0-%a1
unlk %a6
jmp _asm_exception_handler
nop
handled:
movem.l %sp@,%d0-%d1/%a0-%a1
unlk %a6
rte
nop
nop
#else
.global _dbug_sc_handler
_dbug_sc_handler:
.global _asm_exception_handler
_asm_exception_handler:
nop
// FIXME - do something useful here
rte
.global _asm_isr_handler
_asm_isr_handler:
nop
// FIXME - do something useful here
rte
#endif
.data
_asm_context:
.space S_FRAME_SIZE,0x55
.end

25
arch/m68k/include/asm/atomic.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Declaration for atomic operations
*/
/* Empty dummy FIXME */

40
arch/m68k/include/asm/barebox-m68k.h
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@ -1,40 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Arch dependant barebox defines
*/
#ifndef _BAREBOX_M68K_H_
#define _BAREBOX_M68K_H_ 1
/* for the following variables, see start.S */
//extern ulong _armboot_start; /* code start */
//extern ulong _bss_start; /* code + data end == BSS start */
//extern ulong _bss_end; /* BSS end */
//extern ulong IRQ_STACK_START; /* top of IRQ stack */
/* cpu/.../cpu.c */
int cleanup_before_linux(void);
/* board/.../... */
//int board_init(void);
//int dram_init (void);
#endif /* _BAREBOX_M68K_H_ */

33
arch/m68k/include/asm/barebox.h
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@ -1,33 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @note This header file defines an interface to barebox. Including
* this (unmodified) header file in another file is considered normal
* use of barebox, and does *not* fall under the heading of "derived
* work".
*/
#ifndef _BAREBOX_H_
#define _BAREBOX_H_ 1
//typedef struct bd_info {} bd_t;
#endif /* _BAREBOX_H_ */

141
arch/m68k/include/asm/bitops.h
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@ -1,141 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Bitops helper functions and defines for M68k
*
* bit 0 is the LSB of addr; bit 32 is the HSB.
*
* Please note that the code in this file should never be included
* from user space. Many of these are not implemented in assembler
* since they would be too costly. Also, they require priviledged
* instructions (which are not available from user mode) to ensure
* that they are atomic.
*/
#ifndef __ASM_M68K_BITOPS_H
#define __ASM_M68K_BITOPS_H
/*
* Function prototypes to keep gcc -Wall happy.
*/
extern void set_bit(int nr, volatile void * addr);
static inline void __set_bit(int nr, volatile void *addr)
{
((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7));
}
extern void clear_bit(int nr, volatile void * addr);
static inline void __clear_bit(int nr, volatile void *addr)
{
((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7));
}
extern void change_bit(int nr, volatile void * addr);
static inline void __change_bit(int nr, volatile void *addr)
{
((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7));
}
extern int test_and_set_bit(int nr, volatile void * addr);
static inline int __test_and_set_bit(int nr, volatile void *addr)
{
unsigned int mask = 1 << (nr & 7);
unsigned int oldval;
oldval = ((unsigned char *) addr)[nr >> 3];
((unsigned char *) addr)[nr >> 3] = oldval | mask;
return oldval & mask;
}
extern int test_and_clear_bit(int nr, volatile void * addr);
static inline int __test_and_clear_bit(int nr, volatile void *addr)
{
unsigned int mask = 1 << (nr & 7);
unsigned int oldval;
oldval = ((unsigned char *) addr)[nr >> 3];
((unsigned char *) addr)[nr >> 3] = oldval & ~mask;
return oldval & mask;
}
extern int test_and_change_bit(int nr, volatile void * addr);
static inline int __test_and_change_bit(int nr, volatile void *addr)
{
unsigned int mask = 1 << (nr & 7);
unsigned int oldval;
oldval = ((unsigned char *) addr)[nr >> 3];
((unsigned char *) addr)[nr >> 3] = oldval ^ mask;
return oldval & mask;
}
extern int find_first_zero_bit(void * addr, unsigned size);
extern int find_next_zero_bit(void * addr, int size, int offset);
/*
* This routine doesn't need to be atomic.
*/
static inline int test_bit(int nr, const void * addr)
{
return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
}
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long word)
{
int k;
word = ~word;
k = 31;
if (word & 0x0000ffff) { k -= 16; word <<= 16; }
if (word & 0x00ff0000) { k -= 8; word <<= 8; }
if (word & 0x0f000000) { k -= 4; word <<= 4; }
if (word & 0x30000000) { k -= 2; word <<= 2; }
if (word & 0x40000000) { k -= 1; }
return k;
}
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/hweight.h>
#define ext2_set_bit test_and_set_bit
#define ext2_clear_bit test_and_clear_bit
#define ext2_test_bit test_bit
#define ext2_find_first_zero_bit find_first_zero_bit
#define ext2_find_next_zero_bit find_next_zero_bit
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
#define minix_set_bit(nr,addr) set_bit(nr,addr)
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
#endif /* __ASM_M68K_BITOPS_H */

381
arch/m68k/include/asm/bootinfo.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Definition of the Linux/m68k boot information structure.
*
* Taken from Linux includes. See there for latest version, and update
* if needed
*/
#ifndef _M68K_BOOTINFO_H
#define _M68K_BOOTINFO_H
/*
* Bootinfo definitions
*
* This is an easily parsable and extendable structure containing all
* information to be passed from the bootstrap to the kernel.
*
* This way I hope to keep all future changes back/forewards compatible.
* Thus, keep your fingers crossed...
*
* This structure is copied right after the kernel bss by the bootstrap
* routine.
*/
#ifndef __ASSEMBLY__
struct bi_record {
unsigned short tag; /* tag ID */
unsigned short size; /* size of record (in bytes) */
unsigned long data[0]; /* data */
};
#endif /* __ASSEMBLY__ */
/*
* Tag Definitions
*
* Machine independent tags start counting from 0x0000
* Machine dependent tags start counting from 0x8000
*/
#define BI_LAST 0x0000 /* last record (sentinel) */
#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
/* (struct mem_info) */
#define BI_RAMDISK 0x0006 /* ramdisk address and size */
/* (struct mem_info) */
#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
/* (string) */
/*
* Amiga-specific tags
*/
#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */
#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */
/* (struct ConfigDev) */
#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */
#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */
#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */
#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */
#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */
#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */
/*
* Atari-specific tags
*/
#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */
#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */
/* (values are ATARI_MACH_* defines */
/* mch_cookie values (upper word) */
#define ATARI_MCH_ST 0
#define ATARI_MCH_STE 1
#define ATARI_MCH_TT 2
#define ATARI_MCH_FALCON 3
/* mch_type values */
#define ATARI_MACH_NORMAL 0 /* no special machine type */
#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */
#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */
#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */
/*
* VME-specific tags
*/
#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */
#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */
/* BI_VME_TYPE codes */
#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */
#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */
#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */
#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */
#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */
#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */
#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */
#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */
#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */
/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on
* Motorola VME boards. Contains board number, Bug version, board
* configuration options, etc. See include/asm/mvme16xhw.h for details.
*/
/*
* Macintosh-specific tags (all u_long)
*/
#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
#define BI_MAC_VADDR 0x8001 /* Mac video base address */
#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
#define BI_MAC_BTIME 0x8007 /* Mac boot time */
#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
/*
* Macintosh hardware profile data - unused, see macintosh.h for
* resonable type values
*/
#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
/*
* Mac: compatibility with old booter data format (temporarily)
* Fields unused with the new bootinfo can be deleted now; instead of
* adding new fields the struct might be splitted into a hardware address
* part and a hardware type part
*/
#ifndef __ASSEMBLY__
struct mac_booter_data
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
extern struct mac_booter_data
mac_bi_data;
#endif
/*
* Apollo-specific tags
*/
#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */
/*
* HP300-specific tags
*/
#define BI_HP300_MODEL 0x8000 /* model (u_long) */
#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */
#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */
/*
* Stuff for bootinfo interface versioning
*
* At the start of kernel code, a 'struct bootversion' is located.
* bootstrap checks for a matching version of the interface before booting
* a kernel, to avoid user confusion if kernel and bootstrap don't work
* together :-)
*
* If incompatible changes are made to the bootinfo interface, the major
* number below should be stepped (and the minor reset to 0) for the
* appropriate machine. If a change is backward-compatible, the minor
* should be stepped. "Backwards-compatible" means that booting will work,
* but certain features may not.
*/
#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor))
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
#ifndef __ASSEMBLY__
struct bootversion {
unsigned short branch;
unsigned long magic;
struct {
unsigned long machtype;
unsigned long version;
} machversions[0];
};
#endif /* __ASSEMBLY__ */
#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 )
#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#ifdef BOOTINFO_COMPAT_1_0
/*
* Backwards compatibility with bootinfo interface version 1.0
*/
#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#include <linux/zorro.h>
#define COMPAT_NUM_AUTO 16
struct compat_bi_Amiga {
int model;
int num_autocon;
struct ConfigDev autocon[COMPAT_NUM_AUTO];
unsigned long chip_size;
unsigned char vblank;
unsigned char psfreq;
unsigned long eclock;
unsigned long chipset;
unsigned long hw_present;
};
struct compat_bi_Atari {
unsigned long hw_present;
unsigned long mch_cookie;
};
#ifndef __ASSEMBLY__
struct compat_bi_Macintosh
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
#endif
struct compat_mem_info {
unsigned long addr;
unsigned long size;
};
#define COMPAT_NUM_MEMINFO 4
#define COMPAT_CPUB_68020 0
#define COMPAT_CPUB_68030 1
#define COMPAT_CPUB_68040 2
#define COMPAT_CPUB_68060 3
#define COMPAT_FPUB_68881 5
#define COMPAT_FPUB_68882 6
#define COMPAT_FPUB_68040 7
#define COMPAT_FPUB_68060 8
#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020)
#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030)
#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040)
#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060)
#define COMPAT_CPU_MASK (31)
#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881)
#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882)
#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040)
#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060)
#define COMPAT_FPU_MASK (0xfe0)
#define COMPAT_CL_SIZE (256)
struct compat_bootinfo {
unsigned long machtype;
unsigned long cputype;
struct compat_mem_info memory[COMPAT_NUM_MEMINFO];
int num_memory;
unsigned long ramdisk_size;
unsigned long ramdisk_addr;
char command_line[COMPAT_CL_SIZE];
union {
struct compat_bi_Amiga bi_ami;
struct compat_bi_Atari bi_ata;
struct compat_bi_Macintosh bi_mac;
} bi_un;
};
#define bi_amiga bi_un.bi_ami
#define bi_atari bi_un.bi_ata
#define bi_mac bi_un.bi_mac
#endif /* BOOTINFO_COMPAT_1_0 */
#endif /* _M68K_BOOTINFO_H */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Define byte order of target
*
* M68K is always big-endian mode.
*
* When in big endian mode, byte accesses appear as:
* 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
* and word accesses (data or instruction) appear as:
* d0...d31
*/
#ifndef __ASM_M68K_BYTEORDER_H
#define __ASM_M68K_BYTEORDER_H
#include <asm/types.h>
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#include <linux/byteorder/big_endian.h>
#endif

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF547X and MCF548X processors
*/
#ifndef __MCF548X_H__
#define __MCF548X_H__
/*
* useful padding structure for register maps
*/
typedef struct
{
vuint8_t a;
vuint16_t b;
} __attribute ((packed)) vuint24_t;
/*
* Include all internal hardware register macros and defines for this CPU.
*/
#include "asm/coldfire/mcf548x/mcf548x_fec.h"
#include "asm/coldfire/mcf548x/mcf548x_siu.h"
#include "asm/coldfire/mcf548x/mcf548x_ctm.h"
#include "asm/coldfire/mcf548x/mcf548x_dspi.h"
#include "asm/coldfire/mcf548x/mcf548x_eport.h"
#include "asm/coldfire/mcf548x/mcf548x_fbcs.h"
#include "asm/coldfire/mcf548x/mcf548x_gpio.h"
#include "asm/coldfire/mcf548x/mcf548x_gpt.h"
#include "asm/coldfire/mcf548x/mcf548x_i2c.h"
#include "asm/coldfire/mcf548x/mcf548x_intc.h"
#include "asm/coldfire/mcf548x/mcf548x_sdramc.h"
#include "asm/coldfire/mcf548x/mcf548x_sec.h"
#include "asm/coldfire/mcf548x/mcf548x_slt.h"
#include "asm/coldfire/mcf548x/mcf548x_usb.h"
#include "asm/coldfire/mcf548x/mcf548x_psc.h"
#include "asm/coldfire/mcf548x/mcf548x_uart.h"
#include "asm/coldfire/mcf548x/mcf548x_sram.h"
#include "asm/coldfire/mcf548x/mcf548x_pci.h"
#include "asm/coldfire/mcf548x/mcf548x_pciarb.h"
#include "asm/coldfire/mcf548x/mcf548x_dma.h"
#include "asm/coldfire/mcf548x/mcf548x_dma_ereq.h"
#include "asm/coldfire/mcf548x/mcf548x_can.h"
#include "asm/coldfire/mcf548x/mcf548x_xlbarb.h"
#endif /* __MCF548X_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* CAN controllers
*/
#ifndef __MCF548X_CAN_H__
#define __MCF548X_CAN_H__
/*
* FlexCAN Module (CAN)
*/
/* Register read/write macros */
#define MCF_CAN_CANMCR0 (*(vuint32_t*)(&__MBAR[0x00A000]))
#define MCF_CAN_CANCTRL0 (*(vuint32_t*)(&__MBAR[0x00A004]))
#define MCF_CAN_TIMER0 (*(vuint32_t*)(&__MBAR[0x00A008]))
#define MCF_CAN_RXGMASK0 (*(vuint32_t*)(&__MBAR[0x00A010]))
#define MCF_CAN_RX14MASK0 (*(vuint32_t*)(&__MBAR[0x00A014]))
#define MCF_CAN_RX15MASK0 (*(vuint32_t*)(&__MBAR[0x00A018]))
#define MCF_CAN_ERRCNT0 (*(vuint32_t*)(&__MBAR[0x00A01C]))
#define MCF_CAN_ERRSTAT0 (*(vuint32_t*)(&__MBAR[0x00A020]))
#define MCF_CAN_IMASK0 (*(vuint16_t*)(&__MBAR[0x00A02A]))
#define MCF_CAN_IFLAG0 (*(vuint16_t*)(&__MBAR[0x00A032]))
#define MCF_CAN_CANMCR1 (*(vuint32_t*)(&__MBAR[0x00A800]))
#define MCF_CAN_CANCTRL1 (*(vuint32_t*)(&__MBAR[0x00A804]))
#define MCF_CAN_TIMER1 (*(vuint32_t*)(&__MBAR[0x00A808]))
#define MCF_CAN_RXGMASK1 (*(vuint32_t*)(&__MBAR[0x00A810]))
#define MCF_CAN_RX14MASK1 (*(vuint32_t*)(&__MBAR[0x00A814]))
#define MCF_CAN_RX15MASK1 (*(vuint32_t*)(&__MBAR[0x00A818]))
#define MCF_CAN_ERRCNT1 (*(vuint32_t*)(&__MBAR[0x00A81C]))
#define MCF_CAN_ERRSTAT1 (*(vuint32_t*)(&__MBAR[0x00A820]))
#define MCF_CAN_IMASK1 (*(vuint16_t*)(&__MBAR[0x00A82A]))
#define MCF_CAN_IFLAG1 (*(vuint16_t*)(&__MBAR[0x00A832]))
#define MCF_CAN_CANMCR(x) (*(vuint32_t*)(&__MBAR[0x00A000+((x)*0x800)]))
#define MCF_CAN_CANCTRL(x) (*(vuint32_t*)(&__MBAR[0x00A004+((x)*0x800)]))
#define MCF_CAN_TIMER(x) (*(vuint32_t*)(&__MBAR[0x00A008+((x)*0x800)]))
#define MCF_CAN_RXGMASK(x) (*(vuint32_t*)(&__MBAR[0x00A010+((x)*0x800)]))
#define MCF_CAN_RX14MASK(x) (*(vuint32_t*)(&__MBAR[0x00A014+((x)*0x800)]))
#define MCF_CAN_RX15MASK(x) (*(vuint32_t*)(&__MBAR[0x00A018+((x)*0x800)]))
#define MCF_CAN_ERRCNT(x) (*(vuint32_t*)(&__MBAR[0x00A01C+((x)*0x800)]))
#define MCF_CAN_ERRSTAT(x) (*(vuint32_t*)(&__MBAR[0x00A020+((x)*0x800)]))
#define MCF_CAN_IMASK(x) (*(vuint16_t*)(&__MBAR[0x00A02A+((x)*0x800)]))
#define MCF_CAN_IFLAG(x) (*(vuint16_t*)(&__MBAR[0x00A032+((x)*0x800)]))
/* Bit definitions and macros for MCF_CAN_CANMCR */
#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
#define MCF_CAN_CANMCR_SUPV (0x00800000)
#define MCF_CAN_CANMCR_FRZACK (0x01000000)
#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
#define MCF_CAN_CANMCR_HALT (0x10000000)
#define MCF_CAN_CANMCR_FRZ (0x40000000)
#define MCF_CAN_CANMCR_MDIS (0x80000000)
/* Bit definitions and macros for MCF_CAN_CANCTRL */
#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
#define MCF_CAN_CANCTRL_LOM (0x00000008)
#define MCF_CAN_CANCTRL_LBUF (0x00000010)
#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
#define MCF_CAN_CANCTRL_SAMP (0x00000080)
#define MCF_CAN_CANCTRL_LPB (0x00001000)
#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_CAN_TIMER */
#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RXGMASK */
#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RX14MASK */
#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_RX15MASK */
#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
/* Bit definitions and macros for MCF_CAN_ERRCNT */
#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
/* Bit definitions and macros for MCF_CAN_IMASK */
#define MCF_CAN_IMASK_BUF0M (0x0001)
#define MCF_CAN_IMASK_BUF1M (0x0002)
#define MCF_CAN_IMASK_BUF2M (0x0004)
#define MCF_CAN_IMASK_BUF3M (0x0008)
#define MCF_CAN_IMASK_BUF4M (0x0010)
#define MCF_CAN_IMASK_BUF5M (0x0020)
#define MCF_CAN_IMASK_BUF6M (0x0040)
#define MCF_CAN_IMASK_BUF7M (0x0080)
#define MCF_CAN_IMASK_BUF8M (0x0100)
#define MCF_CAN_IMASK_BUF9M (0x0200)
#define MCF_CAN_IMASK_BUF10M (0x0400)
#define MCF_CAN_IMASK_BUF11M (0x0800)
#define MCF_CAN_IMASK_BUF12M (0x1000)
#define MCF_CAN_IMASK_BUF13M (0x2000)
#define MCF_CAN_IMASK_BUF14M (0x4000)
#define MCF_CAN_IMASK_BUF15M (0x8000)
/* Bit definitions and macros for MCF_CAN_IFLAG */
#define MCF_CAN_IFLAG_BUF0I (0x0001)
#define MCF_CAN_IFLAG_BUF1I (0x0002)
#define MCF_CAN_IFLAG_BUF2I (0x0004)
#define MCF_CAN_IFLAG_BUF3I (0x0008)
#define MCF_CAN_IFLAG_BUF4I (0x0010)
#define MCF_CAN_IFLAG_BUF5I (0x0020)
#define MCF_CAN_IFLAG_BUF6I (0x0040)
#define MCF_CAN_IFLAG_BUF7I (0x0080)
#define MCF_CAN_IFLAG_BUF8I (0x0100)
#define MCF_CAN_IFLAG_BUF9I (0x0200)
#define MCF_CAN_IFLAG_BUF10I (0x0400)
#define MCF_CAN_IFLAG_BUF11I (0x0800)
#define MCF_CAN_IFLAG_BUF12I (0x1000)
#define MCF_CAN_IFLAG_BUF13I (0x2000)
#define MCF_CAN_IFLAG_BUF14I (0x4000)
#define MCF_CAN_IFLAG_BUF15I (0x8000)
#endif /* __MCF548X_CAN_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Common Timer Module
*/
#ifndef __MCF548X_CTM_H__
#define __MCF548X_CTM_H__
/*
* Comm Timer Module (CTM)
*/
/* Register read/write macros */
#define MCF_CTM_CTCRF0 (*(vuint32_t*)(&__MBAR[0x007F00]))
#define MCF_CTM_CTCRF1 (*(vuint32_t*)(&__MBAR[0x007F04]))
#define MCF_CTM_CTCRF2 (*(vuint32_t*)(&__MBAR[0x007F08]))
#define MCF_CTM_CTCRF3 (*(vuint32_t*)(&__MBAR[0x007F0C]))
#define MCF_CTM_CTCRFn(x) (*(vuint32_t*)(&__MBAR[0x007F00+((x)*0x004)]))
#define MCF_CTM_CTCRV4 (*(vuint32_t*)(&__MBAR[0x007F10]))
#define MCF_CTM_CTCRV5 (*(vuint32_t*)(&__MBAR[0x007F14]))
#define MCF_CTM_CTCRV6 (*(vuint32_t*)(&__MBAR[0x007F18]))
#define MCF_CTM_CTCRV7 (*(vuint32_t*)(&__MBAR[0x007F1C]))
#define MCF_CTM_CTCRVn(x) (*(vuint32_t*)(&__MBAR[0x007F10+((x)*0x004)]))
/* Bit definitions and macros for MCF_CTM_CTCRFn */
#define MCF_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0)
#define MCF_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16)
#define MCF_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20)
#define MCF_CTM_CTCRFn_M (0x00800000)
#define MCF_CTM_CTCRFn_IM (0x01000000)
#define MCF_CTM_CTCRFn_I (0x80000000)
#define MCF_CTM_CTCRFn_PCT_100 (0x00000000)
#define MCF_CTM_CTCRFn_PCT_50 (0x00100000)
#define MCF_CTM_CTCRFn_PCT_25 (0x00200000)
#define MCF_CTM_CTCRFn_PCT_12p5 (0x00300000)
#define MCF_CTM_CTCRFn_PCT_6p25 (0x00400000)
#define MCF_CTM_CTCRFn_PCT_OFF (0x00500000)
#define MCF_CTM_CTCRFn_S_CLK_1 (0x00000000)
#define MCF_CTM_CTCRFn_S_CLK_2 (0x00010000)
#define MCF_CTM_CTCRFn_S_CLK_4 (0x00020000)
#define MCF_CTM_CTCRFn_S_CLK_8 (0x00030000)
#define MCF_CTM_CTCRFn_S_CLK_16 (0x00040000)
#define MCF_CTM_CTCRFn_S_CLK_32 (0x00050000)
#define MCF_CTM_CTCRFn_S_CLK_64 (0x00060000)
#define MCF_CTM_CTCRFn_S_CLK_128 (0x00070000)
#define MCF_CTM_CTCRFn_S_CLK_256 (0x00080000)
/* Bit definitions and macros for MCF_CTM_CTCRVn */
#define MCF_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0)
#define MCF_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24)
#define MCF_CTM_CTCRVn_M (0x08000000)
#define MCF_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28)
#define MCF_CTM_CTCRVn_S_CLK_1 (0x00000000)
#define MCF_CTM_CTCRVn_S_CLK_2 (0x10000000)
#define MCF_CTM_CTCRVn_S_CLK_4 (0x20000000)
#define MCF_CTM_CTCRVn_S_CLK_8 (0x30000000)
#define MCF_CTM_CTCRVn_S_CLK_16 (0x40000000)
#define MCF_CTM_CTCRVn_S_CLK_32 (0x50000000)
#define MCF_CTM_CTCRVn_S_CLK_64 (0x60000000)
#define MCF_CTM_CTCRVn_S_CLK_128 (0x70000000)
#define MCF_CTM_CTCRVn_S_CLK_256 (0x80000000)
#define MCF_CTM_CTCRVn_PCT_100 (0x00000000)
#define MCF_CTM_CTCRVn_PCT_50 (0x01000000)
#define MCF_CTM_CTCRVn_PCT_25 (0x02000000)
#define MCF_CTM_CTCRVn_PCT_12p5 (0x03000000)
#define MCF_CTM_CTCRVn_PCT_6p25 (0x04000000)
#define MCF_CTM_CTCRVn_PCT_OFF (0x05000000)
#endif /* __MCF548X_CTM_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Multichannel DMA
*/
#ifndef __MCF548X_DMA_H__
#define __MCF548X_DMA_H__
/*
* Multi-Channel DMA (DMA)
*/
/* Register read/write macros */
#define MCF_DMA_DIPR (*(vuint32_t*)(&__MBAR[0x008014]))
#define MCF_DMA_DIMR (*(vuint32_t*)(&__MBAR[0x008018]))
#define MCF_DMA_IMCR (*(vuint32_t*)(&__MBAR[0x00805C]))
/* Bit definitions and macros for MCF_DMA_DIPR */
#define MCF_DMA_DIPR_TASK0 (0x00000001)
#define MCF_DMA_DIPR_TASK1 (0x00000002)
#define MCF_DMA_DIPR_TASK2 (0x00000004)
#define MCF_DMA_DIPR_TASK3 (0x00000008)
#define MCF_DMA_DIPR_TASK4 (0x00000010)
#define MCF_DMA_DIPR_TASK5 (0x00000020)
#define MCF_DMA_DIPR_TASK6 (0x00000040)
#define MCF_DMA_DIPR_TASK7 (0x00000080)
#define MCF_DMA_DIPR_TASK8 (0x00000100)
#define MCF_DMA_DIPR_TASK9 (0x00000200)
#define MCF_DMA_DIPR_TASK10 (0x00000400)
#define MCF_DMA_DIPR_TASK11 (0x00000800)
#define MCF_DMA_DIPR_TASK12 (0x00001000)
#define MCF_DMA_DIPR_TASK13 (0x00002000)
#define MCF_DMA_DIPR_TASK14 (0x00004000)
#define MCF_DMA_DIPR_TASK15 (0x00008000)
/* Bit definitions and macros for MCF_DMA_DIMR */
#define MCF_DMA_DIMR_TASK0 (0x00000001)
#define MCF_DMA_DIMR_TASK1 (0x00000002)
#define MCF_DMA_DIMR_TASK2 (0x00000004)
#define MCF_DMA_DIMR_TASK3 (0x00000008)
#define MCF_DMA_DIMR_TASK4 (0x00000010)
#define MCF_DMA_DIMR_TASK5 (0x00000020)
#define MCF_DMA_DIMR_TASK6 (0x00000040)
#define MCF_DMA_DIMR_TASK7 (0x00000080)
#define MCF_DMA_DIMR_TASK8 (0x00000100)
#define MCF_DMA_DIMR_TASK9 (0x00000200)
#define MCF_DMA_DIMR_TASK10 (0x00000400)
#define MCF_DMA_DIMR_TASK11 (0x00000800)
#define MCF_DMA_DIMR_TASK12 (0x00001000)
#define MCF_DMA_DIMR_TASK13 (0x00002000)
#define MCF_DMA_DIMR_TASK14 (0x00004000)
#define MCF_DMA_DIMR_TASK15 (0x00008000)
/* Bit definitions and macros for MCF_DMA_IMCR */
#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0)
#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2)
#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4)
#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6)
#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8)
#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10)
#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12)
#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14)
#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16)
#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18)
#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20)
#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22)
#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24)
#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26)
#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28)
#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30)
#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000)
#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000)
#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020)
#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080)
#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100)
#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000)
#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400)
#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000)
#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000)
#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000)
#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000)
#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000)
#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000)
#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000)
#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000)
#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000)
#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000)
#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000)
#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000)
#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000)
#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000)
#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000)
#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000)
#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000)
#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000)
#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000)
#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000)
#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000)
#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000)
#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000)
#endif /* __MCF548X_DMA_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Multi-Channel DMA External Requests (DMA_EREQ)
*/
#ifndef __MCF548X_DMA_EREQ_H__
#define __MCF548X_DMA_EREQ_H__
/*
* Multi-Channel DMA External Requests (DMA_EREQ)
*/
/* Register read/write macros */
#define MCF_DMA_EREQ_EREQBAR0 (*(vuint32_t*)(&__MBAR[0x000D00]))
#define MCF_DMA_EREQ_EREQMASK0 (*(vuint32_t*)(&__MBAR[0x000D04]))
#define MCF_DMA_EREQ_EREQCTRL0 (*(vuint32_t*)(&__MBAR[0x000D08]))
#define MCF_DMA_EREQ_EREQBAR1 (*(vuint32_t*)(&__MBAR[0x000D10]))
#define MCF_DMA_EREQ_EREQMASK1 (*(vuint32_t*)(&__MBAR[0x000D14]))
#define MCF_DMA_EREQ_EREQCTRL1 (*(vuint32_t*)(&__MBAR[0x000D18]))
#define MCF_DMA_EREQ_EREQBAR(x) (*(vuint32_t*)(&__MBAR[0x000D00+((x)*0x010)]))
#define MCF_DMA_EREQ_EREQMASK(x) (*(vuint32_t*)(&__MBAR[0x000D04+((x)*0x010)]))
#define MCF_DMA_EREQ_EREQCTRL(x) (*(vuint32_t*)(&__MBAR[0x000D08+((x)*0x010)]))
/* Bit definitions and macros for MCF_DMA_EREQ_EREQCTRL */
#define MCF_DMA_EREQ_EREQCTRL_EN (0x00000001)
#define MCF_DMA_EREQ_EREQCTRL_SYNC (0x00000002)
#define MCF_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2)
#define MCF_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4)
#define MCF_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6)
#define MCF_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000)
#define MCF_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040)
#define MCF_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080)
#define MCF_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0)
#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000)
#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010)
#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020)
#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030)
#define MCF_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000)
#define MCF_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004)
#define MCF_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008)
#define MCF_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C)
#endif /* __MCF548X_DMA_EREQ_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* DMA Serial Peripheral Interface (DSPI)
*/
#ifndef __MCF548X_DSPI_H__
#define __MCF548X_DSPI_H__
/*
* DMA Serial Peripheral Interface (DSPI)
*/
/* Register read/write macros */
#define MCF_DSPI_DMCR (*(vuint32_t*)(&__MBAR[0x008A00]))
#define MCF_DSPI_DTCR (*(vuint32_t*)(&__MBAR[0x008A08]))
#define MCF_DSPI_DCTAR0 (*(vuint32_t*)(&__MBAR[0x008A0C]))
#define MCF_DSPI_DCTAR1 (*(vuint32_t*)(&__MBAR[0x008A10]))
#define MCF_DSPI_DCTAR2 (*(vuint32_t*)(&__MBAR[0x008A14]))
#define MCF_DSPI_DCTAR3 (*(vuint32_t*)(&__MBAR[0x008A18]))
#define MCF_DSPI_DCTAR4 (*(vuint32_t*)(&__MBAR[0x008A1C]))
#define MCF_DSPI_DCTAR5 (*(vuint32_t*)(&__MBAR[0x008A20]))
#define MCF_DSPI_DCTAR6 (*(vuint32_t*)(&__MBAR[0x008A24]))
#define MCF_DSPI_DCTAR7 (*(vuint32_t*)(&__MBAR[0x008A28]))
#define MCF_DSPI_DCTARn(x) (*(vuint32_t*)(&__MBAR[0x008A0C+((x)*0x004)]))
#define MCF_DSPI_DSR (*(vuint32_t*)(&__MBAR[0x008A2C]))
#define MCF_DSPI_DIRSR (*(vuint32_t*)(&__MBAR[0x008A30]))
#define MCF_DSPI_DTFR (*(vuint32_t*)(&__MBAR[0x008A34]))
#define MCF_DSPI_DRFR (*(vuint32_t*)(&__MBAR[0x008A38]))
#define MCF_DSPI_DTFDR0 (*(vuint32_t*)(&__MBAR[0x008A3C]))
#define MCF_DSPI_DTFDR1 (*(vuint32_t*)(&__MBAR[0x008A40]))
#define MCF_DSPI_DTFDR2 (*(vuint32_t*)(&__MBAR[0x008A44]))
#define MCF_DSPI_DTFDR3 (*(vuint32_t*)(&__MBAR[0x008A48]))
#define MCF_DSPI_DTFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A3C+((x)*0x004)]))
#define MCF_DSPI_DRFDR0 (*(vuint32_t*)(&__MBAR[0x008A7C]))
#define MCF_DSPI_DRFDR1 (*(vuint32_t*)(&__MBAR[0x008A80]))
#define MCF_DSPI_DRFDR2 (*(vuint32_t*)(&__MBAR[0x008A84]))
#define MCF_DSPI_DRFDR3 (*(vuint32_t*)(&__MBAR[0x008A88]))
#define MCF_DSPI_DRFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A7C+((x)*0x004)]))
/* Bit definitions and macros for MCF_DSPI_DMCR */
#define MCF_DSPI_DMCR_HALT (0x00000001)
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
#define MCF_DSPI_DMCR_CRXF (0x00000400)
#define MCF_DSPI_DMCR_CTXF (0x00000800)
#define MCF_DSPI_DMCR_DRXF (0x00001000)
#define MCF_DSPI_DMCR_DTXF (0x00002000)
#define MCF_DSPI_DMCR_CSIS0 (0x00010000)
#define MCF_DSPI_DMCR_CSIS2 (0x00040000)
#define MCF_DSPI_DMCR_CSIS3 (0x00080000)
#define MCF_DSPI_DMCR_CSIS5 (0x00200000)
#define MCF_DSPI_DMCR_ROOE (0x01000000)
#define MCF_DSPI_DMCR_PCSSE (0x02000000)
#define MCF_DSPI_DMCR_MTFE (0x04000000)
#define MCF_DSPI_DMCR_FRZ (0x08000000)
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
#define MCF_DSPI_DMCR_CSCK (0x40000000)
#define MCF_DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTCR */
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_DSPI_DCTARn */
#define MCF_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0)
#define MCF_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4)
#define MCF_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8)
#define MCF_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12)
#define MCF_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16)
#define MCF_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18)
#define MCF_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20)
#define MCF_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22)
#define MCF_DSPI_DCTARn_LSBFE (0x01000000)
#define MCF_DSPI_DCTARn_CPHA (0x02000000)
#define MCF_DSPI_DCTARn_CPOL (0x04000000)
#define MCF_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27)
#define MCF_DSPI_DCTARn_PCSSCK_1CLK (0x00000000)
#define MCF_DSPI_DCTARn_PCSSCK_3CLK (0x00400000)
#define MCF_DSPI_DCTARn_PCSSCK_5CLK (0x00800000)
#define MCF_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000)
#define MCF_DSPI_DCTARn_PASC_1CLK (0x00000000)
#define MCF_DSPI_DCTARn_PASC_3CLK (0x00100000)
#define MCF_DSPI_DCTARn_PASC_5CLK (0x00200000)
#define MCF_DSPI_DCTARn_PASC_7CLK (0x00300000)
#define MCF_DSPI_DCTARn_PDT_1CLK (0x00000000)
#define MCF_DSPI_DCTARn_PDT_3CLK (0x00040000)
#define MCF_DSPI_DCTARn_PDT_5CLK (0x00080000)
#define MCF_DSPI_DCTARn_PDT_7CLK (0x000A0000)
#define MCF_DSPI_DCTARn_PBR_1CLK (0x00000000)
#define MCF_DSPI_DCTARn_PBR_3CLK (0x00010000)
#define MCF_DSPI_DCTARn_PBR_5CLK (0x00020000)
#define MCF_DSPI_DCTARn_PBR_7CLK (0x00030000)
/* Bit definitions and macros for MCF_DSPI_DSR */
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0)
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
#define MCF_DSPI_DSR_RFDF (0x00020000)
#define MCF_DSPI_DSR_RFOF (0x00080000)
#define MCF_DSPI_DSR_TFFF (0x02000000)
#define MCF_DSPI_DSR_TFUF (0x08000000)
#define MCF_DSPI_DSR_EOQF (0x10000000)
#define MCF_DSPI_DSR_TXRXS (0x40000000)
#define MCF_DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DIRSR */
#define MCF_DSPI_DIRSR_RFDFS (0x00010000)
#define MCF_DSPI_DIRSR_RFDFE (0x00020000)
#define MCF_DSPI_DIRSR_RFOFE (0x00080000)
#define MCF_DSPI_DIRSR_TFFFS (0x01000000)
#define MCF_DSPI_DIRSR_TFFFE (0x02000000)
#define MCF_DSPI_DIRSR_TFUFE (0x08000000)
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTFR */
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0)
#define MCF_DSPI_DTFR_CS0 (0x00010000)
#define MCF_DSPI_DTFR_CS2 (0x00040000)
#define MCF_DSPI_DTFR_CS3 (0x00080000)
#define MCF_DSPI_DTFR_CS5 (0x00200000)
#define MCF_DSPI_DTFR_CTCNT (0x04000000)
#define MCF_DSPI_DTFR_EOQ (0x08000000)
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
#define MCF_DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRFR */
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0)
/* Bit definitions and macros for MCF_DSPI_DTFDRn */
#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0)
#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_DSPI_DRFDRn */
#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0)
#endif /* __MCF548X_DSPI_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Edge Port Module (EPORT)
*/
#ifndef __MCF548X_EPORT_H__
#define __MCF548X_EPORT_H__
/*
* Edge Port Module (EPORT)
*/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(vuint16_t*)(&__MBAR[0x000F00]))
#define MCF_EPORT_EPDDR (*(vuint8_t *)(&__MBAR[0x000F04]))
#define MCF_EPORT_EPIER (*(vuint8_t *)(&__MBAR[0x000F05]))
#define MCF_EPORT_EPDR (*(vuint8_t *)(&__MBAR[0x000F08]))
#define MCF_EPORT_EPPDR (*(vuint8_t *)(&__MBAR[0x000F09]))
#define MCF_EPORT_EPFR (*(vuint8_t *)(&__MBAR[0x000F0C]))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x02)
#define MCF_EPORT_EPIER_EPIE2 (0x04)
#define MCF_EPORT_EPIER_EPIE3 (0x08)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x02)
#define MCF_EPORT_EPDR_EPD2 (0x04)
#define MCF_EPORT_EPDR_EPD3 (0x08)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x02)
#define MCF_EPORT_EPFR_EPF2 (0x04)
#define MCF_EPORT_EPFR_EPF3 (0x08)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF548X_EPORT_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* FlexBus Chip Selects (FBCS)
*/
#ifndef __MCF548X_FBCS_H__
#define __MCF548X_FBCS_H__
/*
* FlexBus Chip Selects (FBCS)
*/
/* Register read/write macros */
#define MCF_FBCS_CSAR0 (*(vuint32_t*)(&__MBAR[0x000500]))
#define MCF_FBCS_CSMR0 (*(vuint32_t*)(&__MBAR[0x000504]))
#define MCF_FBCS_CSCR0 (*(vuint32_t*)(&__MBAR[0x000508]))
#define MCF_FBCS_CSAR1 (*(vuint32_t*)(&__MBAR[0x00050C]))
#define MCF_FBCS_CSMR1 (*(vuint32_t*)(&__MBAR[0x000510]))
#define MCF_FBCS_CSCR1 (*(vuint32_t*)(&__MBAR[0x000514]))
#define MCF_FBCS_CSAR2 (*(vuint32_t*)(&__MBAR[0x000518]))
#define MCF_FBCS_CSMR2 (*(vuint32_t*)(&__MBAR[0x00051C]))
#define MCF_FBCS_CSCR2 (*(vuint32_t*)(&__MBAR[0x000520]))
#define MCF_FBCS_CSAR3 (*(vuint32_t*)(&__MBAR[0x000524]))
#define MCF_FBCS_CSMR3 (*(vuint32_t*)(&__MBAR[0x000528]))
#define MCF_FBCS_CSCR3 (*(vuint32_t*)(&__MBAR[0x00052C]))
#define MCF_FBCS_CSAR4 (*(vuint32_t*)(&__MBAR[0x000530]))
#define MCF_FBCS_CSMR4 (*(vuint32_t*)(&__MBAR[0x000534]))
#define MCF_FBCS_CSCR4 (*(vuint32_t*)(&__MBAR[0x000538]))
#define MCF_FBCS_CSAR5 (*(vuint32_t*)(&__MBAR[0x00053C]))
#define MCF_FBCS_CSMR5 (*(vuint32_t*)(&__MBAR[0x000540]))
#define MCF_FBCS_CSCR5 (*(vuint32_t*)(&__MBAR[0x000544]))
#define MCF_FBCS_CSAR(x) (*(vuint32_t*)(&__MBAR[0x000500+((x)*0x00C)]))
#define MCF_FBCS_CSMR(x) (*(vuint32_t*)(&__MBAR[0x000504+((x)*0x00C)]))
#define MCF_FBCS_CSCR(x) (*(vuint32_t*)(&__MBAR[0x000508+((x)*0x00C)]))
/* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_FBCS_CSMR */
#define MCF_FBCS_CSMR_V (0x00000001)
#define MCF_FBCS_CSMR_WP (0x00000100)
#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for MCF_FBCS_CSCR */
#define MCF_FBCS_CSCR_BSTW (0x00000008)
#define MCF_FBCS_CSCR_BSTR (0x00000010)
#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
#define MCF_FBCS_CSCR_AA (0x00000100)
#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
#define MCF_FBCS_CSCR_SWSEN (0x00800000)
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
#define MCF_FBCS_CSCR_PS_8 (0x0040)
#define MCF_FBCS_CSCR_PS_16 (0x0080)
#define MCF_FBCS_CSCR_PS_32 (0x0000)
#endif /* __MCF548X_FBCS_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h
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@ -1,623 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Fast Ethernet Controller (FEC)
*/
#ifndef __MCF548X_FEC_H__
#define __MCF548X_FEC_H__
/*
* Fast Ethernet Controller (FEC)
*/
/* Register read/write macros */
#define MCF_FEC_EIR0 (*(vuint32_t*)(&__MBAR[0x009004]))
#define MCF_FEC_EIMR0 (*(vuint32_t*)(&__MBAR[0x009008]))
#define MCF_FEC_ECR0 (*(vuint32_t*)(&__MBAR[0x009024]))
#define MCF_FEC_MMFR0 (*(vuint32_t*)(&__MBAR[0x009040]))
#define MCF_FEC_MSCR0 (*(vuint32_t*)(&__MBAR[0x009044]))
#define MCF_FEC_MIBC0 (*(vuint32_t*)(&__MBAR[0x009064]))
#define MCF_FEC_RCR0 (*(vuint32_t*)(&__MBAR[0x009084]))
#define MCF_FEC_R_HASH0 (*(vuint32_t*)(&__MBAR[0x009088]))
#define MCF_FEC_TCR0 (*(vuint32_t*)(&__MBAR[0x0090C4]))
#define MCF_FEC_PALR0 (*(vuint32_t*)(&__MBAR[0x0090E4]))
#define MCF_FEC_PAUR0 (*(vuint32_t*)(&__MBAR[0x0090E8]))
#define MCF_FEC_OPD0 (*(vuint32_t*)(&__MBAR[0x0090EC]))
#define MCF_FEC_IAUR0 (*(vuint32_t*)(&__MBAR[0x009118]))
#define MCF_FEC_IALR0 (*(vuint32_t*)(&__MBAR[0x00911C]))
#define MCF_FEC_GAUR0 (*(vuint32_t*)(&__MBAR[0x009120]))
#define MCF_FEC_GALR0 (*(vuint32_t*)(&__MBAR[0x009124]))
#define MCF_FEC_FECTFWR0 (*(vuint32_t*)(&__MBAR[0x009144]))
#define MCF_FEC_FECRFDR0 (*(vuint32_t*)(&__MBAR[0x009184]))
#define MCF_FEC_FECRFSR0 (*(vuint32_t*)(&__MBAR[0x009188]))
#define MCF_FEC_FECRFCR0 (*(vuint32_t*)(&__MBAR[0x00918C]))
#define MCF_FEC_FECRLRFP0 (*(vuint32_t*)(&__MBAR[0x009190]))
#define MCF_FEC_FECRLWFP0 (*(vuint32_t*)(&__MBAR[0x009194]))
#define MCF_FEC_FECRFAR0 (*(vuint32_t*)(&__MBAR[0x009198]))
#define MCF_FEC_FECRFRP0 (*(vuint32_t*)(&__MBAR[0x00919C]))
#define MCF_FEC_FECRFWP0 (*(vuint32_t*)(&__MBAR[0x0091A0]))
#define MCF_FEC_FECTFDR0 (*(vuint32_t*)(&__MBAR[0x0091A4]))
#define MCF_FEC_FECTFSR0 (*(vuint32_t*)(&__MBAR[0x0091A8]))
#define MCF_FEC_FECTFCR0 (*(vuint32_t*)(&__MBAR[0x0091AC]))
#define MCF_FEC_FECTLRFP0 (*(vuint32_t*)(&__MBAR[0x0091B0]))
#define MCF_FEC_FECTLWFP0 (*(vuint32_t*)(&__MBAR[0x0091B4]))
#define MCF_FEC_FECTFAR0 (*(vuint32_t*)(&__MBAR[0x0091B8]))
#define MCF_FEC_FECTFRP0 (*(vuint32_t*)(&__MBAR[0x0091BC]))
#define MCF_FEC_FECTFWP0 (*(vuint32_t*)(&__MBAR[0x0091C0]))
#define MCF_FEC_FRST0 (*(vuint32_t*)(&__MBAR[0x0091C4]))
#define MCF_FEC_CTCWR0 (*(vuint32_t*)(&__MBAR[0x0091C8]))
#define MCF_FEC_RMON_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009200]))
#define MCF_FEC_RMON_T_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009204]))
#define MCF_FEC_RMON_T_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009208]))
#define MCF_FEC_RMON_T_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00920C]))
#define MCF_FEC_RMON_T_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009210]))
#define MCF_FEC_RMON_T_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009214]))
#define MCF_FEC_RMON_T_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009218]))
#define MCF_FEC_RMON_T_FRAG0 (*(vuint32_t*)(&__MBAR[0x00921C]))
#define MCF_FEC_RMON_T_JAB0 (*(vuint32_t*)(&__MBAR[0x009220]))
#define MCF_FEC_RMON_T_COL0 (*(vuint32_t*)(&__MBAR[0x009224]))
#define MCF_FEC_RMON_T_P640 (*(vuint32_t*)(&__MBAR[0x009228]))
#define MCF_FEC_RMON_T_P65TO1270 (*(vuint32_t*)(&__MBAR[0x00922C]))
#define MCF_FEC_RMON_T_P128TO2550 (*(vuint32_t*)(&__MBAR[0x009230]))
#define MCF_FEC_RMON_T_P256TO5110 (*(vuint32_t*)(&__MBAR[0x009234]))
#define MCF_FEC_RMON_T_P512TO10230 (*(vuint32_t*)(&__MBAR[0x009238]))
#define MCF_FEC_RMON_T_P1024TO20470 (*(vuint32_t*)(&__MBAR[0x00923C]))
#define MCF_FEC_RMON_T_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x009240]))
#define MCF_FEC_RMON_T_OCTETS0 (*(vuint32_t*)(&__MBAR[0x009244]))
#define MCF_FEC_IEEE_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009248]))
#define MCF_FEC_IEEE_T_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x00924C]))
#define MCF_FEC_IEEE_T_1COL0 (*(vuint32_t*)(&__MBAR[0x009250]))
#define MCF_FEC_IEEE_T_MCOL0 (*(vuint32_t*)(&__MBAR[0x009254]))
#define MCF_FEC_IEEE_T_DEF0 (*(vuint32_t*)(&__MBAR[0x009258]))
#define MCF_FEC_IEEE_T_LCOL0 (*(vuint32_t*)(&__MBAR[0x00925C]))
#define MCF_FEC_IEEE_T_EXCOL0 (*(vuint32_t*)(&__MBAR[0x009260]))
#define MCF_FEC_IEEE_T_MACERR0 (*(vuint32_t*)(&__MBAR[0x009264]))
#define MCF_FEC_IEEE_T_CSERR0 (*(vuint32_t*)(&__MBAR[0x009268]))
#define MCF_FEC_IEEE_T_SQE0 (*(vuint32_t*)(&__MBAR[0x00926C]))
#define MCF_FEC_IEEE_T_FDXFC0 (*(vuint32_t*)(&__MBAR[0x009270]))
#define MCF_FEC_IEEE_T_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x009274]))
#define MCF_FEC_RMON_R_DROP0 (*(vuint32_t*)(&__MBAR[0x009280]))
#define MCF_FEC_RMON_R_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009284]))
#define MCF_FEC_RMON_R_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009288]))
#define MCF_FEC_RMON_R_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00928C]))
#define MCF_FEC_RMON_R_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009290]))
#define MCF_FEC_RMON_R_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009294]))
#define MCF_FEC_RMON_R_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009298]))
#define MCF_FEC_RMON_R_FRAG0 (*(vuint32_t*)(&__MBAR[0x00929C]))
#define MCF_FEC_RMON_R_JAB0 (*(vuint32_t*)(&__MBAR[0x0092A0]))
#define MCF_FEC_RMON_R_RESVD_00 (*(vuint32_t*)(&__MBAR[0x0092A4]))
#define MCF_FEC_RMON_R_P640 (*(vuint32_t*)(&__MBAR[0x0092A8]))
#define MCF_FEC_RMON_R_P65TO1270 (*(vuint32_t*)(&__MBAR[0x0092AC]))
#define MCF_FEC_RMON_R_P128TO2550 (*(vuint32_t*)(&__MBAR[0x0092B0]))
#define MCF_FEC_RMON_R_P256TO5110 (*(vuint32_t*)(&__MBAR[0x0092B4]))
#define MCF_FEC_RMON_R_512TO10230 (*(vuint32_t*)(&__MBAR[0x0092B8]))
#define MCF_FEC_RMON_R_1024TO20470 (*(vuint32_t*)(&__MBAR[0x0092BC]))
#define MCF_FEC_RMON_R_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x0092C0]))
#define MCF_FEC_RMON_R_OCTETS0 (*(vuint32_t*)(&__MBAR[0x0092C4]))
#define MCF_FEC_IEEE_R_DROP0 (*(vuint32_t*)(&__MBAR[0x0092C8]))
#define MCF_FEC_IEEE_R_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x0092CC]))
#define MCF_FEC_IEEE_R_CRC0 (*(vuint32_t*)(&__MBAR[0x0092D0]))
#define MCF_FEC_IEEE_R_ALIGN0 (*(vuint32_t*)(&__MBAR[0x0092D4]))
#define MCF_FEC_IEEE_R_MACERR0 (*(vuint32_t*)(&__MBAR[0x0092D8]))
#define MCF_FEC_IEEE_R_FDXFC0 (*(vuint32_t*)(&__MBAR[0x0092DC]))
#define MCF_FEC_IEEE_R_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x0092E0]))
#define MCF_FEC_EIR1 (*(vuint32_t*)(&__MBAR[0x009804]))
#define MCF_FEC_EIMR1 (*(vuint32_t*)(&__MBAR[0x009808]))
#define MCF_FEC_ECR1 (*(vuint32_t*)(&__MBAR[0x009824]))
#define MCF_FEC_MMFR1 (*(vuint32_t*)(&__MBAR[0x009840]))
#define MCF_FEC_MSCR1 (*(vuint32_t*)(&__MBAR[0x009844]))
#define MCF_FEC_MIBC1 (*(vuint32_t*)(&__MBAR[0x009864]))
#define MCF_FEC_RCR1 (*(vuint32_t*)(&__MBAR[0x009884]))
#define MCF_FEC_R_HASH1 (*(vuint32_t*)(&__MBAR[0x009888]))
#define MCF_FEC_TCR1 (*(vuint32_t*)(&__MBAR[0x0098C4]))
#define MCF_FEC_PALR1 (*(vuint32_t*)(&__MBAR[0x0098E4]))
#define MCF_FEC_PAUR1 (*(vuint32_t*)(&__MBAR[0x0098E8]))
#define MCF_FEC_OPD1 (*(vuint32_t*)(&__MBAR[0x0098EC]))
#define MCF_FEC_IAUR1 (*(vuint32_t*)(&__MBAR[0x009918]))
#define MCF_FEC_IALR1 (*(vuint32_t*)(&__MBAR[0x00991C]))
#define MCF_FEC_GAUR1 (*(vuint32_t*)(&__MBAR[0x009920]))
#define MCF_FEC_GALR1 (*(vuint32_t*)(&__MBAR[0x009924]))
#define MCF_FEC_FECTFWR1 (*(vuint32_t*)(&__MBAR[0x009944]))
#define MCF_FEC_FECRFDR1 (*(vuint32_t*)(&__MBAR[0x009984]))
#define MCF_FEC_FECRFSR1 (*(vuint32_t*)(&__MBAR[0x009988]))
#define MCF_FEC_FECRFCR1 (*(vuint32_t*)(&__MBAR[0x00998C]))
#define MCF_FEC_FECRLRFP1 (*(vuint32_t*)(&__MBAR[0x009990]))
#define MCF_FEC_FECRLWFP1 (*(vuint32_t*)(&__MBAR[0x009994]))
#define MCF_FEC_FECRFAR1 (*(vuint32_t*)(&__MBAR[0x009998]))
#define MCF_FEC_FECRFRP1 (*(vuint32_t*)(&__MBAR[0x00999C]))
#define MCF_FEC_FECRFWP1 (*(vuint32_t*)(&__MBAR[0x0099A0]))
#define MCF_FEC_FECTFDR1 (*(vuint32_t*)(&__MBAR[0x0099A4]))
#define MCF_FEC_FECTFSR1 (*(vuint32_t*)(&__MBAR[0x0099A8]))
#define MCF_FEC_FECTFCR1 (*(vuint32_t*)(&__MBAR[0x0099AC]))
#define MCF_FEC_FECTLRFP1 (*(vuint32_t*)(&__MBAR[0x0099B0]))
#define MCF_FEC_FECTLWFP1 (*(vuint32_t*)(&__MBAR[0x0099B4]))
#define MCF_FEC_FECTFAR1 (*(vuint32_t*)(&__MBAR[0x0099B8]))
#define MCF_FEC_FECTFRP1 (*(vuint32_t*)(&__MBAR[0x0099BC]))
#define MCF_FEC_FECTFWP1 (*(vuint32_t*)(&__MBAR[0x0099C0]))
#define MCF_FEC_FRST1 (*(vuint32_t*)(&__MBAR[0x0099C4]))
#define MCF_FEC_CTCWR1 (*(vuint32_t*)(&__MBAR[0x0099C8]))
#define MCF_FEC_RMON_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A00]))
#define MCF_FEC_RMON_T_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A04]))
#define MCF_FEC_RMON_T_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A08]))
#define MCF_FEC_RMON_T_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A0C]))
#define MCF_FEC_RMON_T_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A10]))
#define MCF_FEC_RMON_T_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A14]))
#define MCF_FEC_RMON_T_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A18]))
#define MCF_FEC_RMON_T_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A1C]))
#define MCF_FEC_RMON_T_JAB1 (*(vuint32_t*)(&__MBAR[0x009A20]))
#define MCF_FEC_RMON_T_COL1 (*(vuint32_t*)(&__MBAR[0x009A24]))
#define MCF_FEC_RMON_T_P641 (*(vuint32_t*)(&__MBAR[0x009A28]))
#define MCF_FEC_RMON_T_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009A2C]))
#define MCF_FEC_RMON_T_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009A30]))
#define MCF_FEC_RMON_T_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009A34]))
#define MCF_FEC_RMON_T_P512TO10231 (*(vuint32_t*)(&__MBAR[0x009A38]))
#define MCF_FEC_RMON_T_P1024TO20471 (*(vuint32_t*)(&__MBAR[0x009A3C]))
#define MCF_FEC_RMON_T_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009A40]))
#define MCF_FEC_RMON_T_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009A44]))
#define MCF_FEC_IEEE_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A48]))
#define MCF_FEC_IEEE_T_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009A4C]))
#define MCF_FEC_IEEE_T_1COL1 (*(vuint32_t*)(&__MBAR[0x009A50]))
#define MCF_FEC_IEEE_T_MCOL1 (*(vuint32_t*)(&__MBAR[0x009A54]))
#define MCF_FEC_IEEE_T_DEF1 (*(vuint32_t*)(&__MBAR[0x009A58]))
#define MCF_FEC_IEEE_T_LCOL1 (*(vuint32_t*)(&__MBAR[0x009A5C]))
#define MCF_FEC_IEEE_T_EXCOL1 (*(vuint32_t*)(&__MBAR[0x009A60]))
#define MCF_FEC_IEEE_T_MACERR1 (*(vuint32_t*)(&__MBAR[0x009A64]))
#define MCF_FEC_IEEE_T_CSERR1 (*(vuint32_t*)(&__MBAR[0x009A68]))
#define MCF_FEC_IEEE_T_SQE1 (*(vuint32_t*)(&__MBAR[0x009A6C]))
#define MCF_FEC_IEEE_T_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009A70]))
#define MCF_FEC_IEEE_T_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009A74]))
#define MCF_FEC_RMON_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009A80]))
#define MCF_FEC_RMON_R_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A84]))
#define MCF_FEC_RMON_R_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A88]))
#define MCF_FEC_RMON_R_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A8C]))
#define MCF_FEC_RMON_R_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A90]))
#define MCF_FEC_RMON_R_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A94]))
#define MCF_FEC_RMON_R_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A98]))
#define MCF_FEC_RMON_R_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A9C]))
#define MCF_FEC_RMON_R_JAB1 (*(vuint32_t*)(&__MBAR[0x009AA0]))
#define MCF_FEC_RMON_R_RESVD_01 (*(vuint32_t*)(&__MBAR[0x009AA4]))
#define MCF_FEC_RMON_R_P641 (*(vuint32_t*)(&__MBAR[0x009AA8]))
#define MCF_FEC_RMON_R_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009AAC]))
#define MCF_FEC_RMON_R_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009AB0]))
#define MCF_FEC_RMON_R_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009AB4]))
#define MCF_FEC_RMON_R_512TO10231 (*(vuint32_t*)(&__MBAR[0x009AB8]))
#define MCF_FEC_RMON_R_1024TO20471 (*(vuint32_t*)(&__MBAR[0x009ABC]))
#define MCF_FEC_RMON_R_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009AC0]))
#define MCF_FEC_RMON_R_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009AC4]))
#define MCF_FEC_IEEE_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009AC8]))
#define MCF_FEC_IEEE_R_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009ACC]))
#define MCF_FEC_IEEE_R_CRC1 (*(vuint32_t*)(&__MBAR[0x009AD0]))
#define MCF_FEC_IEEE_R_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009AD4]))
#define MCF_FEC_IEEE_R_MACERR1 (*(vuint32_t*)(&__MBAR[0x009AD8]))
#define MCF_FEC_IEEE_R_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009ADC]))
#define MCF_FEC_IEEE_R_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009AE0]))
#define MCF_FEC_EIR(x) (*(vuint32_t*)(&__MBAR[0x009004+((x)*0x800)]))
#define MCF_FEC_EIMR(x) (*(vuint32_t*)(&__MBAR[0x009008+((x)*0x800)]))
#define MCF_FEC_ECR(x) (*(vuint32_t*)(&__MBAR[0x009024+((x)*0x800)]))
#define MCF_FEC_MMFR(x) (*(vuint32_t*)(&__MBAR[0x009040+((x)*0x800)]))
#define MCF_FEC_MSCR(x) (*(vuint32_t*)(&__MBAR[0x009044+((x)*0x800)]))
#define MCF_FEC_MIBC(x) (*(vuint32_t*)(&__MBAR[0x009064+((x)*0x800)]))
#define MCF_FEC_RCR(x) (*(vuint32_t*)(&__MBAR[0x009084+((x)*0x800)]))
#define MCF_FEC_R_HASH(x) (*(vuint32_t*)(&__MBAR[0x009088+((x)*0x800)]))
#define MCF_FEC_TCR(x) (*(vuint32_t*)(&__MBAR[0x0090C4+((x)*0x800)]))
#define MCF_FEC_PALR(x) (*(vuint32_t*)(&__MBAR[0x0090E4+((x)*0x800)]))
#define MCF_FEC_PAUR(x) (*(vuint32_t*)(&__MBAR[0x0090E8+((x)*0x800)]))
#define MCF_FEC_OPD(x) (*(vuint32_t*)(&__MBAR[0x0090EC+((x)*0x800)]))
#define MCF_FEC_IAUR(x) (*(vuint32_t*)(&__MBAR[0x009118+((x)*0x800)]))
#define MCF_FEC_IALR(x) (*(vuint32_t*)(&__MBAR[0x00911C+((x)*0x800)]))
#define MCF_FEC_GAUR(x) (*(vuint32_t*)(&__MBAR[0x009120+((x)*0x800)]))
#define MCF_FEC_GALR(x) (*(vuint32_t*)(&__MBAR[0x009124+((x)*0x800)]))
#define MCF_FEC_FECTFWR(x) (*(vuint32_t*)(&__MBAR[0x009144+((x)*0x800)]))
#define MCF_FEC_FECRFDR(x) (*(vuint32_t*)(&__MBAR[0x009184+((x)*0x800)]))
#define MCF_FEC_FECRFSR(x) (*(vuint32_t*)(&__MBAR[0x009188+((x)*0x800)]))
#define MCF_FEC_FECRFCR(x) (*(vuint32_t*)(&__MBAR[0x00918C+((x)*0x800)]))
#define MCF_FEC_FECRLRFP(x) (*(vuint32_t*)(&__MBAR[0x009190+((x)*0x800)]))
#define MCF_FEC_FECRLWFP(x) (*(vuint32_t*)(&__MBAR[0x009194+((x)*0x800)]))
#define MCF_FEC_FECRFAR(x) (*(vuint32_t*)(&__MBAR[0x009198+((x)*0x800)]))
#define MCF_FEC_FECRFRP(x) (*(vuint32_t*)(&__MBAR[0x00919C+((x)*0x800)]))
#define MCF_FEC_FECRFWP(x) (*(vuint32_t*)(&__MBAR[0x0091A0+((x)*0x800)]))
#define MCF_FEC_FECTFDR(x) (*(vuint32_t*)(&__MBAR[0x0091A4+((x)*0x800)]))
#define MCF_FEC_FECTFSR(x) (*(vuint32_t*)(&__MBAR[0x0091A8+((x)*0x800)]))
#define MCF_FEC_FECTFCR(x) (*(vuint32_t*)(&__MBAR[0x0091AC+((x)*0x800)]))
#define MCF_FEC_FECTLRFP(x) (*(vuint32_t*)(&__MBAR[0x0091B0+((x)*0x800)]))
#define MCF_FEC_FECTLWFP(x) (*(vuint32_t*)(&__MBAR[0x0091B4+((x)*0x800)]))
#define MCF_FEC_FECTFAR(x) (*(vuint32_t*)(&__MBAR[0x0091B8+((x)*0x800)]))
#define MCF_FEC_FECTFRP(x) (*(vuint32_t*)(&__MBAR[0x0091BC+((x)*0x800)]))
#define MCF_FEC_FECTFWP(x) (*(vuint32_t*)(&__MBAR[0x0091C0+((x)*0x800)]))
#define MCF_FEC_FRST(x) (*(vuint32_t*)(&__MBAR[0x0091C4+((x)*0x800)]))
#define MCF_FEC_CTCWR(x) (*(vuint32_t*)(&__MBAR[0x0091C8+((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009200+((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009204+((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009208+((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00920C+((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009210+((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009214+((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009218+((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00921C+((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x) (*(vuint32_t*)(&__MBAR[0x009220+((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x) (*(vuint32_t*)(&__MBAR[0x009224+((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x) (*(vuint32_t*)(&__MBAR[0x009228+((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x00922C+((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x009230+((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x009234+((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32_t*)(&__MBAR[0x009238+((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x00923C+((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x009240+((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x009244+((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009248+((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x00924C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32_t*)(&__MBAR[0x009250+((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32_t*)(&__MBAR[0x009254+((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32_t*)(&__MBAR[0x009258+((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32_t*)(&__MBAR[0x00925C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32_t*)(&__MBAR[0x009260+((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32_t*)(&__MBAR[0x009264+((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32_t*)(&__MBAR[0x009268+((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32_t*)(&__MBAR[0x00926C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x009270+((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x009274+((x)*0x800)]))
#define MCF_FEC_RMON_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x009280+((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009284+((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009288+((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00928C+((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009290+((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009294+((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009298+((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00929C+((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x) (*(vuint32_t*)(&__MBAR[0x0092A0+((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32_t*)(&__MBAR[0x0092A4+((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x) (*(vuint32_t*)(&__MBAR[0x0092A8+((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x0092AC+((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x0092B0+((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x0092B4+((x)*0x800)]))
#define MCF_FEC_RMON_R_512TO1023(x) (*(vuint32_t*)(&__MBAR[0x0092B8+((x)*0x800)]))
#define MCF_FEC_RMON_R_1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x0092BC+((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x0092C0+((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x0092C4+((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x0092C8+((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x0092CC+((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32_t*)(&__MBAR[0x0092D0+((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x0092D4+((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32_t*)(&__MBAR[0x0092D8+((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x0092DC+((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x0092E0+((x)*0x800)]))
/* Bit definitions and macros for MCF_FEC_EIR */
#define MCF_FEC_EIR_RFERR (0x00020000)
#define MCF_FEC_EIR_XFERR (0x00040000)
#define MCF_FEC_EIR_XFUN (0x00080000)
#define MCF_FEC_EIR_RL (0x00100000)
#define MCF_FEC_EIR_LC (0x00200000)
#define MCF_FEC_EIR_MII (0x00800000)
#define MCF_FEC_EIR_TXF (0x08000000)
#define MCF_FEC_EIR_GRA (0x10000000)
#define MCF_FEC_EIR_BABT (0x20000000)
#define MCF_FEC_EIR_BABR (0x40000000)
#define MCF_FEC_EIR_HBERR (0x80000000)
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_EIMR */
#define MCF_FEC_EIMR_RFERR (0x00020000)
#define MCF_FEC_EIMR_XFERR (0x00040000)
#define MCF_FEC_EIMR_XFUN (0x00080000)
#define MCF_FEC_EIMR_RL (0x00100000)
#define MCF_FEC_EIMR_LC (0x00200000)
#define MCF_FEC_EIMR_MII (0x00800000)
#define MCF_FEC_EIMR_TXF (0x08000000)
#define MCF_FEC_EIMR_GRA (0x10000000)
#define MCF_FEC_EIMR_BABT (0x20000000)
#define MCF_FEC_EIMR_BABR (0x40000000)
#define MCF_FEC_EIMR_HBERR (0x80000000)
#define MCF_FEC_EIMR_MASK_ALL (0x00000000)
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_ECR */
#define MCF_FEC_ECR_RESET (0x00000001)
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
/* Bit definitions and macros for MCF_FEC_MMFR */
#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
#define MCF_FEC_MMFR_ST_01 (0x40000000)
#define MCF_FEC_MMFR_OP_READ (0x20000000)
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
#define MCF_FEC_MMFR_TA_10 (0x00020000)
/* Bit definitions and macros for MCF_FEC_MSCR */
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<1)
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<1)
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<1)
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<1)
/* Bit definitions and macros for MCF_FEC_MIBC */
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
/* Bit definitions and macros for MCF_FEC_RCR */
#define MCF_FEC_RCR_LOOP (0x00000001)
#define MCF_FEC_RCR_DRT (0x00000002)
#define MCF_FEC_RCR_MII_MODE (0x00000004)
#define MCF_FEC_RCR_PROM (0x00000008)
#define MCF_FEC_RCR_BC_REJ (0x00000010)
#define MCF_FEC_RCR_FCE (0x00000020)
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
/* Bit definitions and macros for MCF_FEC_R_HASH */
#define MCF_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24)
#define MCF_FEC_R_HASH_MULTCAST (0x40000000)
#define MCF_FEC_R_HASH_FCE_DC (0x80000000)
/* Bit definitions and macros for MCF_FEC_TCR */
#define MCF_FEC_TCR_GTS (0x00000001)
#define MCF_FEC_TCR_HBC (0x00000002)
#define MCF_FEC_TCR_FDEN (0x00000004)
#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
/* Bit definitions and macros for MCF_FEC_PAUR */
#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_FEC_OPD */
#define MCF_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0)
#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_FEC_FECTFWR */
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0)
#define MCF_FEC_FECTFWR_X_WMRK_64 (0x00000000)
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x00000001)
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x00000002)
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x00000003)
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x00000004)
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x00000005)
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x00000006)
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x00000007)
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x00000008)
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x00000009)
#define MCF_FEC_FECTFWR_X_WMRK_704 (0x0000000A)
#define MCF_FEC_FECTFWR_X_WMRK_768 (0x0000000B)
#define MCF_FEC_FECTFWR_X_WMRK_832 (0x0000000C)
#define MCF_FEC_FECTFWR_X_WMRK_896 (0x0000000D)
#define MCF_FEC_FECTFWR_X_WMRK_960 (0x0000000E)
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0x0000000F)
/* Bit definitions and macros for MCF_FEC_FECRFDR */
#define MCF_FEC_FECRFDR_ADDR0 ((void*)(&__MBAR[0x009184]))
#define MCF_FEC_FECRFDR_ADDR1 ((void*)(&__MBAR[0x009984]))
#define MCF_FEC_FECRFDR_ADDR(x) ((void*)(&__MBAR[0x009184+(0x800*ch)]))
/* Bit definitions and macros for MCF_FEC_FECRFSR */
#define MCF_FEC_FECRFSR_EMT (0x00010000)
#define MCF_FEC_FECRFSR_ALARM (0x00020000)
#define MCF_FEC_FECRFSR_FU (0x00040000)
#define MCF_FEC_FECRFSR_FR (0x00080000)
#define MCF_FEC_FECRFSR_OF (0x00100000)
#define MCF_FEC_FECRFSR_UF (0x00200000)
#define MCF_FEC_FECRFSR_RXW (0x00400000)
#define MCF_FEC_FECRFSR_FAE (0x00800000)
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24)
#define MCF_FEC_FECRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECRFCR */
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0)
#define MCF_FEC_FECRFCR_OF_MSK (0x00080000)
#define MCF_FEC_FECRFCR_UF_MSK (0x00100000)
#define MCF_FEC_FECRFCR_RXW_MSK (0x00200000)
#define MCF_FEC_FECRFCR_FAE_MSK (0x00400000)
#define MCF_FEC_FECRFCR_IP_MSK (0x00800000)
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_FEC_FECRFCR_FRM (0x08000000)
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
#define MCF_FEC_FECRFCR_WFR (0x20000000)
#define MCF_FEC_FECRFCR_WCTL (0x40000000)
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFAR */
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFRP */
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFWP */
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFDR */
#define MCF_FEC_FECTFDR_TFCW_TC (0x04000000)
#define MCF_FEC_FECTFDR_TFCW_ABC (0x02000000)
#define MCF_FEC_FECTFDR_ADDR0 ((void*)(&__MBAR[0x0091A4]))
#define MCF_FEC_FECTFDR_ADDR1 ((void*)(&__MBAR[0x0099A4]))
#define MCF_FEC_FECTFDR_ADDR(x) ((void*)(&__MBAR[0x0091A4+(0x800*ch)]))
/* Bit definitions and macros for MCF_FEC_FECTFSR */
#define MCF_FEC_FECTFSR_EMT (0x00010000)
#define MCF_FEC_FECTFSR_ALARM (0x00020000)
#define MCF_FEC_FECTFSR_FU (0x00040000)
#define MCF_FEC_FECTFSR_FR (0x00080000)
#define MCF_FEC_FECTFSR_OF (0x00100000)
#define MCF_FEC_FECTFSR_UP (0x00200000)
#define MCF_FEC_FECTFSR_FAE (0x00800000)
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24)
#define MCF_FEC_FECTFSR_TXW (0x40000000)
#define MCF_FEC_FECTFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECTFCR */
#define MCF_FEC_FECTFCR_RESERVED (0x00200000)
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000)
#define MCF_FEC_FECTFCR_TXW_MSK (0x00240000)
#define MCF_FEC_FECTFCR_OF_MSK (0x00280000)
#define MCF_FEC_FECTFCR_UF_MSK (0x00300000)
#define MCF_FEC_FECTFCR_FAE_MSK (0x00600000)
#define MCF_FEC_FECTFCR_IP_MSK (0x00A00000)
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000)
#define MCF_FEC_FECTFCR_FRM (0x08200000)
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
#define MCF_FEC_FECTFCR_WFR (0x20200000)
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFAR */
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFRP */
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWP */
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_FEC_FRST */
#define MCF_FEC_FRST_RST_CTL (0x01000000)
#define MCF_FEC_FRST_SW_RST (0x02000000)
/* Bit definitions and macros for MCF_FEC_CTCWR */
#define MCF_FEC_CTCWR_TFCW (0x01000000)
#define MCF_FEC_CTCWR_CRC (0x02000000)
struct mcf54xx_fec
{
vuint32_t RES0;
vuint32_t eir; // 004
vuint32_t eimr; // 008
vuint32_t RES1[6];
vuint32_t ecr; // 024
vuint32_t RES2[6];
vuint32_t mmfr; // 040
vuint32_t mscr; // 044
vuint32_t RES3[7];
vuint32_t mibc; // 064
vuint32_t RES4[7];
vuint32_t rcr; // 084
vuint32_t r_hash; // 088
vuint32_t RES5[14];
vuint32_t tcr; // 0c4
vuint32_t RES6[7];
vuint32_t palr; // 0e4
vuint32_t paur; // 0e8
vuint32_t opd; // 0ec
vuint32_t RES7[10];
vuint32_t iaur; // 118
vuint32_t ialr; // 11c
vuint32_t gaur; // 120
vuint32_t galr; // 124
vuint32_t RES8[7];
vuint32_t fectfwr; // 144
vuint32_t RES8a[15];
vuint32_t fecrfdr; // 184
vuint32_t fecrfsr; // 188
vuint32_t fecrfcr; // 18c
vuint32_t fecrlrfp; // 190
vuint32_t fecrlwfp; // 194
vuint32_t fecrfar; // 198
vuint32_t fecrfrp; // 19c
vuint32_t fecrfwp; // 1a0
vuint32_t fectfdr; // 1a4
vuint32_t fectfsr; // 1a8
vuint32_t fectfcr; // 1ac
vuint32_t fectlrfp; // 1b0
vuint32_t fectlwfp; // 1b4
vuint32_t fectfar; // 1b8
vuint32_t fectfrp; // 1bc
vuint32_t fectfwp; // 1c0
vuint32_t frst; // 1c4
vuint32_t ctcwr; // 1c8
vuint32_t RES9[13];
/* MIB Counters Memory Map */
vuint32_t rmon_t_drop; // 200
vuint32_t rmon_t_packets; // 204
vuint32_t rmon_t_bc_pkt; // 208
vuint32_t rmon_t_mc_pkt; // 20C
vuint32_t rmon_t_crc_align; // 210
vuint32_t rmon_t_undersize; // 214
vuint32_t rmon_t_oversize; // 218
vuint32_t rmon_t_frag; // 21C
vuint32_t rmon_t_jab; // 220
vuint32_t rmon_t_col; // 224
vuint32_t rmon_t_p64; // 228
vuint32_t rmon_t_p65to127; // 22C
vuint32_t rmon_t_p128to255; // 230
vuint32_t rmon_t_p256to511; // 234
vuint32_t rmon_t_p512to1023; // 238
vuint32_t rmon_t_p1024to2047; // 23C
vuint32_t rmon_t_p_gte2048; // 240
vuint32_t rmon_t_octets; // 244
vuint32_t ieee_t_drop; // 248
vuint32_t ieee_t_frame_ok; // 24C
vuint32_t ieee_t_1col; // 250
vuint32_t ieee_t_mcol; // 254
vuint32_t ieee_t_def; // 258
vuint32_t ieee_t_lcol; // 25C
vuint32_t ieee_t_excol; // 260
vuint32_t ieee_t_macerr; // 264
vuint32_t ieee_t_cserr; // 268
vuint32_t ieee_t_sqe; // 26C
vuint32_t ieee_t_fdxfc; // 270
vuint32_t ieee_t_octets_ok; // 274
vuint32_t RES10[2];
vuint32_t rmon_r_drop; // 280
vuint32_t rmon_r_packets; // 284
vuint32_t rmon_r_bc_pkt; // 288
vuint32_t rmon_r_mc_pkt; // 28C
vuint32_t rmon_r_crc_align; // 290
vuint32_t rmon_r_undersize; // 294
vuint32_t rmon_r_oversize; // 298
vuint32_t rmon_r_frag; // 29C
vuint32_t rmon_r_jab; // 2A0
vuint32_t rmon_r_resvd_0; // 2A4
vuint32_t rmon_r_p64; // 2A8
vuint32_t rmon_r_p65to127; // 2AC
vuint32_t rmon_r_p128to255; // 2B0
vuint32_t rmon_r_p256to511; // 2B4
vuint32_t rmon_r_512to1023; // 2B8
vuint32_t rmon_r_1024to2047; // 2BC
vuint32_t rmon_r_p_gte2048; // 2C0
vuint32_t rmon_r_octets; // 2C4
vuint32_t ieee_r_drop; // 2C8
vuint32_t ieee_r_frame_ok; // 2CC
vuint32_t ieee_r_crc; // 2D0
vuint32_t ieee_r_align; // 2D4
vuint32_t ieee_r_macerr; // 2D8
vuint32_t ieee_r_fdxfc; // 2DC
vuint32_t ieee_r_octets_ok; // 2e0
};
#define MCF_FEC_ADDR(ch) ((void*)(&__MBAR[0x009000+(0x800*ch)]))
#define MCF_FEC_SIZE(ch) ((uint32_t)(0x800))
#endif /* __MCF548X_FEC_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h
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@ -1,708 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* General Purpose I/O (GPIO)
*/
#ifndef __MCF548X_GPIO_H__
#define __MCF548X_GPIO_H__
/*
* General Purpose I/O (GPIO)
*/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A00]))
#define MCF_GPIO_PODR_FBCS (*(vuint8_t *)(&__MBAR[0x000A01]))
#define MCF_GPIO_PODR_DMA (*(vuint8_t *)(&__MBAR[0x000A02]))
#define MCF_GPIO_PODR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A04]))
#define MCF_GPIO_PODR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A05]))
#define MCF_GPIO_PODR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A06]))
#define MCF_GPIO_PODR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A07]))
#define MCF_GPIO_PODR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A08]))
#define MCF_GPIO_PODR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A09]))
#define MCF_GPIO_PODR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A0A]))
#define MCF_GPIO_PODR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A0C]))
#define MCF_GPIO_PODR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A0D]))
#define MCF_GPIO_PODR_DSPI (*(vuint8_t *)(&__MBAR[0x000A0E]))
#define MCF_GPIO_PDDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A10]))
#define MCF_GPIO_PDDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A11]))
#define MCF_GPIO_PDDR_DMA (*(vuint8_t *)(&__MBAR[0x000A12]))
#define MCF_GPIO_PDDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A14]))
#define MCF_GPIO_PDDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A15]))
#define MCF_GPIO_PDDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A16]))
#define MCF_GPIO_PDDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A17]))
#define MCF_GPIO_PDDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A18]))
#define MCF_GPIO_PDDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A19]))
#define MCF_GPIO_PDDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A1A]))
#define MCF_GPIO_PDDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A1C]))
#define MCF_GPIO_PDDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A1D]))
#define MCF_GPIO_PDDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A1E]))
#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A20]))
#define MCF_GPIO_PPDSDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A21]))
#define MCF_GPIO_PPDSDR_DMA (*(vuint8_t *)(&__MBAR[0x000A22]))
#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A24]))
#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A25]))
#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A26]))
#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A27]))
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A28]))
#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A29]))
#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A2A]))
#define MCF_GPIO_PPDSDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A2C]))
#define MCF_GPIO_PPDSDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A2D]))
#define MCF_GPIO_PPDSDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A2E]))
#define MCF_GPIO_PCLRR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A30]))
#define MCF_GPIO_PCLRR_FBCS (*(vuint8_t *)(&__MBAR[0x000A31]))
#define MCF_GPIO_PCLRR_DMA (*(vuint8_t *)(&__MBAR[0x000A32]))
#define MCF_GPIO_PCLRR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A34]))
#define MCF_GPIO_PCLRR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A35]))
#define MCF_GPIO_PCLRR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A36]))
#define MCF_GPIO_PCLRR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A37]))
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A38]))
#define MCF_GPIO_PCLRR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A39]))
#define MCF_GPIO_PCLRR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A3A]))
#define MCF_GPIO_PCLRR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A3C]))
#define MCF_GPIO_PCLRR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A3D]))
#define MCF_GPIO_PCLRR_DSPI (*(vuint8_t *)(&__MBAR[0x000A3E]))
#define MCF_GPIO_PAR_FBCTL (*(vuint16_t*)(&__MBAR[0x000A40]))
#define MCF_GPIO_PAR_FBCS (*(vuint8_t *)(&__MBAR[0x000A42]))
#define MCF_GPIO_PAR_DMA (*(vuint8_t *)(&__MBAR[0x000A43]))
#define MCF_GPIO_PAR_FECI2CIRQ (*(vuint16_t*)(&__MBAR[0x000A44]))
#define MCF_GPIO_PAR_PCIBG (*(vuint16_t*)(&__MBAR[0x000A48]))
#define MCF_GPIO_PAR_PCIBR (*(vuint16_t*)(&__MBAR[0x000A4A]))
#define MCF_GPIO_PAR_PSC3 (*(vuint8_t *)(&__MBAR[0x000A4C]))
#define MCF_GPIO_PAR_PSC2 (*(vuint8_t *)(&__MBAR[0x000A4D]))
#define MCF_GPIO_PAR_PSC1 (*(vuint8_t *)(&__MBAR[0x000A4E]))
#define MCF_GPIO_PAR_PSC0 (*(vuint8_t *)(&__MBAR[0x000A4F]))
#define MCF_GPIO_PAR_DSPI (*(vuint16_t*)(&__MBAR[0x000A50]))
#define MCF_GPIO_PAR_TIMER (*(vuint8_t *)(&__MBAR[0x000A52]))
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x02)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x04)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x08)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x01)
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x02)
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x04)
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40)
#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40)
#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x01)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x02)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x04)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x08)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x01)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x02)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x04)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08)
#define MCF_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01)
#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08)
#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10)
#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20)
#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04)
#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08)
#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08)
#define MCF_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
#define MCF_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01)
#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02)
#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04)
#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08)
#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20)
#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40)
#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20)
#define MCF_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40)
#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004)
#define MCF_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000)
#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2)
#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3)
#define MCF_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000)
#define MCF_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020)
#define MCF_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030)
/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02)
#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04)
#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08)
#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10)
#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2)
#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2)
#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3)
/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080)
#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04)
#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80)
#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30)
#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04)
#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80)
#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
#endif /* __MCF548X_GPIO_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* General Purpose Timers (GPT)
*/
#ifndef __MCF548X_GPT_H__
#define __MCF548X_GPT_H__
/*
* General Purpose Timers (GPT)
*/
/* Register read/write macros */
#define MCF_GPT_GMS0 (*(vuint32_t*)(&__MBAR[0x000800]))
#define MCF_GPT_GCIR0 (*(vuint32_t*)(&__MBAR[0x000804]))
#define MCF_GPT_GPWM0 (*(vuint32_t*)(&__MBAR[0x000808]))
#define MCF_GPT_GSR0 (*(vuint32_t*)(&__MBAR[0x00080C]))
#define MCF_GPT_GMS1 (*(vuint32_t*)(&__MBAR[0x000810]))
#define MCF_GPT_GCIR1 (*(vuint32_t*)(&__MBAR[0x000814]))
#define MCF_GPT_GPWM1 (*(vuint32_t*)(&__MBAR[0x000818]))
#define MCF_GPT_GSR1 (*(vuint32_t*)(&__MBAR[0x00081C]))
#define MCF_GPT_GMS2 (*(vuint32_t*)(&__MBAR[0x000820]))
#define MCF_GPT_GCIR2 (*(vuint32_t*)(&__MBAR[0x000824]))
#define MCF_GPT_GPWM2 (*(vuint32_t*)(&__MBAR[0x000828]))
#define MCF_GPT_GSR2 (*(vuint32_t*)(&__MBAR[0x00082C]))
#define MCF_GPT_GMS3 (*(vuint32_t*)(&__MBAR[0x000830]))
#define MCF_GPT_GCIR3 (*(vuint32_t*)(&__MBAR[0x000834]))
#define MCF_GPT_GPWM3 (*(vuint32_t*)(&__MBAR[0x000838]))
#define MCF_GPT_GSR3 (*(vuint32_t*)(&__MBAR[0x00083C]))
#define MCF_GPT_GMS(x) (*(vuint32_t*)(&__MBAR[0x000800+((x)*0x010)]))
#define MCF_GPT_GCIR(x) (*(vuint32_t*)(&__MBAR[0x000804+((x)*0x010)]))
#define MCF_GPT_GPWM(x) (*(vuint32_t*)(&__MBAR[0x000808+((x)*0x010)]))
#define MCF_GPT_GSR(x) (*(vuint32_t*)(&__MBAR[0x00080C+((x)*0x010)]))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
#define MCF_GPT_GMS_IEN (0x00000100)
#define MCF_GPT_GMS_OD (0x00000200)
#define MCF_GPT_GMS_SC (0x00000400)
#define MCF_GPT_GMS_CE (0x00001000)
#define MCF_GPT_GMS_WDEN (0x00008000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
#define MCF_GPT_GMS_ICT_ANY (0x00000000)
#define MCF_GPT_GMS_ICT_RISE (0x00010000)
#define MCF_GPT_GMS_ICT_FALL (0x00020000)
#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
#define MCF_GPT_GMS_TMS_PWM (0x00000003)
#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x00000001)
#define MCF_GPT_GPWM_PWMOP (0x00000100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x00000001)
#define MCF_GPT_GSR_COMP (0x00000002)
#define MCF_GPT_GSR_PWMP (0x00000004)
#define MCF_GPT_GSR_TEXP (0x00000008)
#define MCF_GPT_GSR_PIN (0x00000100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
#endif /* __MCF548X_GPT_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* I2C Module (I2C)
*/
#ifndef __MCF548X_I2C_H__
#define __MCF548X_I2C_H__
/*
* I2C Module (I2C)
*/
/* Register read/write macros */
#define MCF_I2C_I2AR (*(vuint8_t *)(&__MBAR[0x008F00]))
#define MCF_I2C_I2FDR (*(vuint8_t *)(&__MBAR[0x008F04]))
#define MCF_I2C_I2CR (*(vuint8_t *)(&__MBAR[0x008F08]))
#define MCF_I2C_I2SR (*(vuint8_t *)(&__MBAR[0x008F0C]))
#define MCF_I2C_I2DR (*(vuint8_t *)(&__MBAR[0x008F10]))
#define MCF_I2C_I2ICR (*(vuint8_t *)(&__MBAR[0x008F20]))
/* Bit definitions and macros for MCF_I2C_I2AR */
#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x04)
#define MCF_I2C_I2CR_TXAK (0x08)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x01)
#define MCF_I2C_I2SR_IIF (0x02)
#define MCF_I2C_I2SR_SRW (0x04)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2ICR */
#define MCF_I2C_I2ICR_IE (0x01)
#define MCF_I2C_I2ICR_RE (0x02)
#define MCF_I2C_I2ICR_TE (0x04)
#define MCF_I2C_I2ICR_BNBE (0x08)
#endif /* __MCF548X_I2C_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Interrupt Controller (INTC)
*/
#ifndef __MCF548X_INTC_H__
#define __MCF548X_INTC_H__
/*
* Interrupt Controller (INTC)
*/
/* Register read/write macros */
#define MCF_INTC_IPRH (*(vuint32_t*)(&__MBAR[0x000700]))
#define MCF_INTC_IPRL (*(vuint32_t*)(&__MBAR[0x000704]))
#define MCF_INTC_IMRH (*(vuint32_t*)(&__MBAR[0x000708]))
#define MCF_INTC_IMRL (*(vuint32_t*)(&__MBAR[0x00070C]))
#define MCF_INTC_INTFRCH (*(vuint32_t*)(&__MBAR[0x000710]))
#define MCF_INTC_INTFRCL (*(vuint32_t*)(&__MBAR[0x000714]))
#define MCF_INTC_IRLR (*(vuint8_t *)(&__MBAR[0x000718]))
#define MCF_INTC_IACKLPR (*(vuint8_t *)(&__MBAR[0x000719]))
#define MCF_INTC_ICR0 (*(vuint8_t *)(&__MBAR[0x000740]))
#define MCF_INTC_ICR1 (*(vuint8_t *)(&__MBAR[0x000741]))
#define MCF_INTC_ICR2 (*(vuint8_t *)(&__MBAR[0x000742]))
#define MCF_INTC_ICR3 (*(vuint8_t *)(&__MBAR[0x000743]))
#define MCF_INTC_ICR4 (*(vuint8_t *)(&__MBAR[0x000744]))
#define MCF_INTC_ICR5 (*(vuint8_t *)(&__MBAR[0x000745]))
#define MCF_INTC_ICR6 (*(vuint8_t *)(&__MBAR[0x000746]))
#define MCF_INTC_ICR7 (*(vuint8_t *)(&__MBAR[0x000747]))
#define MCF_INTC_ICR8 (*(vuint8_t *)(&__MBAR[0x000748]))
#define MCF_INTC_ICR9 (*(vuint8_t *)(&__MBAR[0x000749]))
#define MCF_INTC_ICR10 (*(vuint8_t *)(&__MBAR[0x00074A]))
#define MCF_INTC_ICR11 (*(vuint8_t *)(&__MBAR[0x00074B]))
#define MCF_INTC_ICR12 (*(vuint8_t *)(&__MBAR[0x00074C]))
#define MCF_INTC_ICR13 (*(vuint8_t *)(&__MBAR[0x00074D]))
#define MCF_INTC_ICR14 (*(vuint8_t *)(&__MBAR[0x00074E]))
#define MCF_INTC_ICR15 (*(vuint8_t *)(&__MBAR[0x00074F]))
#define MCF_INTC_ICR16 (*(vuint8_t *)(&__MBAR[0x000750]))
#define MCF_INTC_ICR17 (*(vuint8_t *)(&__MBAR[0x000751]))
#define MCF_INTC_ICR18 (*(vuint8_t *)(&__MBAR[0x000752]))
#define MCF_INTC_ICR19 (*(vuint8_t *)(&__MBAR[0x000753]))
#define MCF_INTC_ICR20 (*(vuint8_t *)(&__MBAR[0x000754]))
#define MCF_INTC_ICR21 (*(vuint8_t *)(&__MBAR[0x000755]))
#define MCF_INTC_ICR22 (*(vuint8_t *)(&__MBAR[0x000756]))
#define MCF_INTC_ICR23 (*(vuint8_t *)(&__MBAR[0x000757]))
#define MCF_INTC_ICR24 (*(vuint8_t *)(&__MBAR[0x000758]))
#define MCF_INTC_ICR25 (*(vuint8_t *)(&__MBAR[0x000759]))
#define MCF_INTC_ICR26 (*(vuint8_t *)(&__MBAR[0x00075A]))
#define MCF_INTC_ICR27 (*(vuint8_t *)(&__MBAR[0x00075B]))
#define MCF_INTC_ICR28 (*(vuint8_t *)(&__MBAR[0x00075C]))
#define MCF_INTC_ICR29 (*(vuint8_t *)(&__MBAR[0x00075D]))
#define MCF_INTC_ICR30 (*(vuint8_t *)(&__MBAR[0x00075E]))
#define MCF_INTC_ICR31 (*(vuint8_t *)(&__MBAR[0x00075F]))
#define MCF_INTC_ICR32 (*(vuint8_t *)(&__MBAR[0x000760]))
#define MCF_INTC_ICR33 (*(vuint8_t *)(&__MBAR[0x000761]))
#define MCF_INTC_ICR34 (*(vuint8_t *)(&__MBAR[0x000762]))
#define MCF_INTC_ICR35 (*(vuint8_t *)(&__MBAR[0x000763]))
#define MCF_INTC_ICR36 (*(vuint8_t *)(&__MBAR[0x000764]))
#define MCF_INTC_ICR37 (*(vuint8_t *)(&__MBAR[0x000765]))
#define MCF_INTC_ICR38 (*(vuint8_t *)(&__MBAR[0x000766]))
#define MCF_INTC_ICR39 (*(vuint8_t *)(&__MBAR[0x000767]))
#define MCF_INTC_ICR40 (*(vuint8_t *)(&__MBAR[0x000768]))
#define MCF_INTC_ICR41 (*(vuint8_t *)(&__MBAR[0x000769]))
#define MCF_INTC_ICR42 (*(vuint8_t *)(&__MBAR[0x00076A]))
#define MCF_INTC_ICR43 (*(vuint8_t *)(&__MBAR[0x00076B]))
#define MCF_INTC_ICR44 (*(vuint8_t *)(&__MBAR[0x00076C]))
#define MCF_INTC_ICR45 (*(vuint8_t *)(&__MBAR[0x00076D]))
#define MCF_INTC_ICR46 (*(vuint8_t *)(&__MBAR[0x00076E]))
#define MCF_INTC_ICR47 (*(vuint8_t *)(&__MBAR[0x00076F]))
#define MCF_INTC_ICR48 (*(vuint8_t *)(&__MBAR[0x000770]))
#define MCF_INTC_ICR49 (*(vuint8_t *)(&__MBAR[0x000771]))
#define MCF_INTC_ICR50 (*(vuint8_t *)(&__MBAR[0x000772]))
#define MCF_INTC_ICR51 (*(vuint8_t *)(&__MBAR[0x000773]))
#define MCF_INTC_ICR52 (*(vuint8_t *)(&__MBAR[0x000774]))
#define MCF_INTC_ICR53 (*(vuint8_t *)(&__MBAR[0x000775]))
#define MCF_INTC_ICR54 (*(vuint8_t *)(&__MBAR[0x000776]))
#define MCF_INTC_ICR55 (*(vuint8_t *)(&__MBAR[0x000777]))
#define MCF_INTC_ICR56 (*(vuint8_t *)(&__MBAR[0x000778]))
#define MCF_INTC_ICR57 (*(vuint8_t *)(&__MBAR[0x000779]))
#define MCF_INTC_ICR58 (*(vuint8_t *)(&__MBAR[0x00077A]))
#define MCF_INTC_ICR59 (*(vuint8_t *)(&__MBAR[0x00077B]))
#define MCF_INTC_ICR60 (*(vuint8_t *)(&__MBAR[0x00077C]))
#define MCF_INTC_ICR61 (*(vuint8_t *)(&__MBAR[0x00077D]))
#define MCF_INTC_ICR62 (*(vuint8_t *)(&__MBAR[0x00077E]))
#define MCF_INTC_ICR63 (*(vuint8_t *)(&__MBAR[0x00077F]))
#define MCF_INTC_ICRn(x) (*(vuint8_t *)(&__MBAR[0x000740+((x)*0x001)]))
#define MCF_INTC_SWIACK (*(vuint8_t *)(&__MBAR[0x0007E0]))
#define MCF_INTC_L1IACK (*(vuint8_t *)(&__MBAR[0x0007E4]))
#define MCF_INTC_L2IACK (*(vuint8_t *)(&__MBAR[0x0007E8]))
#define MCF_INTC_L3IACK (*(vuint8_t *)(&__MBAR[0x0007EC]))
#define MCF_INTC_L4IACK (*(vuint8_t *)(&__MBAR[0x0007F0]))
#define MCF_INTC_L5IACK (*(vuint8_t *)(&__MBAR[0x0007F4]))
#define MCF_INTC_L6IACK (*(vuint8_t *)(&__MBAR[0x0007F8]))
#define MCF_INTC_L7IACK (*(vuint8_t *)(&__MBAR[0x0007FC]))
#define MCF_INTC_LnIACK(x) (*(vuint8_t *)(&__MBAR[0x0007E4+((x)*0x004)]))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x00000001)
#define MCF_INTC_IPRH_INT33 (0x00000002)
#define MCF_INTC_IPRH_INT34 (0x00000004)
#define MCF_INTC_IPRH_INT35 (0x00000008)
#define MCF_INTC_IPRH_INT36 (0x00000010)
#define MCF_INTC_IPRH_INT37 (0x00000020)
#define MCF_INTC_IPRH_INT38 (0x00000040)
#define MCF_INTC_IPRH_INT39 (0x00000080)
#define MCF_INTC_IPRH_INT40 (0x00000100)
#define MCF_INTC_IPRH_INT41 (0x00000200)
#define MCF_INTC_IPRH_INT42 (0x00000400)
#define MCF_INTC_IPRH_INT43 (0x00000800)
#define MCF_INTC_IPRH_INT44 (0x00001000)
#define MCF_INTC_IPRH_INT45 (0x00002000)
#define MCF_INTC_IPRH_INT46 (0x00004000)
#define MCF_INTC_IPRH_INT47 (0x00008000)
#define MCF_INTC_IPRH_INT48 (0x00010000)
#define MCF_INTC_IPRH_INT49 (0x00020000)
#define MCF_INTC_IPRH_INT50 (0x00040000)
#define MCF_INTC_IPRH_INT51 (0x00080000)
#define MCF_INTC_IPRH_INT52 (0x00100000)
#define MCF_INTC_IPRH_INT53 (0x00200000)
#define MCF_INTC_IPRH_INT54 (0x00400000)
#define MCF_INTC_IPRH_INT55 (0x00800000)
#define MCF_INTC_IPRH_INT56 (0x01000000)
#define MCF_INTC_IPRH_INT57 (0x02000000)
#define MCF_INTC_IPRH_INT58 (0x04000000)
#define MCF_INTC_IPRH_INT59 (0x08000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1 (0x00000002)
#define MCF_INTC_IPRL_INT2 (0x00000004)
#define MCF_INTC_IPRL_INT3 (0x00000008)
#define MCF_INTC_IPRL_INT4 (0x00000010)
#define MCF_INTC_IPRL_INT5 (0x00000020)
#define MCF_INTC_IPRL_INT6 (0x00000040)
#define MCF_INTC_IPRL_INT7 (0x00000080)
#define MCF_INTC_IPRL_INT8 (0x00000100)
#define MCF_INTC_IPRL_INT9 (0x00000200)
#define MCF_INTC_IPRL_INT10 (0x00000400)
#define MCF_INTC_IPRL_INT11 (0x00000800)
#define MCF_INTC_IPRL_INT12 (0x00001000)
#define MCF_INTC_IPRL_INT13 (0x00002000)
#define MCF_INTC_IPRL_INT14 (0x00004000)
#define MCF_INTC_IPRL_INT15 (0x00008000)
#define MCF_INTC_IPRL_INT16 (0x00010000)
#define MCF_INTC_IPRL_INT17 (0x00020000)
#define MCF_INTC_IPRL_INT18 (0x00040000)
#define MCF_INTC_IPRL_INT19 (0x00080000)
#define MCF_INTC_IPRL_INT20 (0x00100000)
#define MCF_INTC_IPRL_INT21 (0x00200000)
#define MCF_INTC_IPRL_INT22 (0x00400000)
#define MCF_INTC_IPRL_INT23 (0x00800000)
#define MCF_INTC_IPRL_INT24 (0x01000000)
#define MCF_INTC_IPRL_INT25 (0x02000000)
#define MCF_INTC_IPRL_INT26 (0x04000000)
#define MCF_INTC_IPRL_INT27 (0x08000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL (0x00000001)
#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
#define MCF_INTC_INTFRCL_INT6 (0x00000040)
#define MCF_INTC_INTFRCL_INT7 (0x00000080)
#define MCF_INTC_INTFRCL_INT8 (0x00000100)
#define MCF_INTC_INTFRCL_INT9 (0x00000200)
#define MCF_INTC_INTFRCL_INT10 (0x00000400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
#define MCF_INTC_INTFRCL_INT15 (0x00008000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
/* Bit definitions and macros for MCF_INTC_ICRn */
#define MCF_INTC_ICRn_IP(x) (((x)&0x07)<<0)
#define MCF_INTC_ICRn_IL(x) (((x)&0x07)<<3)
#endif /* __MCF548X_INTC_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h
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@ -1,349 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* PCI Bus Controller (PCI)
*/
#ifndef __MCF548X_PCI_H__
#define __MCF548X_PCI_H__
/*
* PCI Bus Controller (PCI)
*/
#define MCF_PCI_HDR_BASE (&__MBAR[0x000B00])
/* Register read/write macros */
/* type 0 header */
#define MCF_PCI_PCIIDR (*(vuint32_t*)(&__MBAR[0x000B00]))
#define MCF_PCI_PCISCR (*(vuint32_t*)(&__MBAR[0x000B04]))
#define MCF_PCI_PCICCRIR (*(vuint32_t*)(&__MBAR[0x000B08]))
#define MCF_PCI_PCICR1 (*(vuint32_t*)(&__MBAR[0x000B0C]))
#define MCF_PCI_PCIBAR0 (*(vuint32_t*)(&__MBAR[0x000B10]))
#define MCF_PCI_PCIBAR1 (*(vuint32_t*)(&__MBAR[0x000B14]))
#define MCF_PCI_PCISID (*(vuint32_t*)(&__MBAR[0x000B2c]))
#define MCF_PCI_PCICR2 (*(vuint32_t*)(&__MBAR[0x000B3C]))
/* Target Controls */
#define MCF_PCI_PCIGSCR (*(vuint32_t*)(&__MBAR[0x000B60]))
#define MCF_PCI_PCITBATR0 (*(vuint32_t*)(&__MBAR[0x000B64]))
#define MCF_PCI_PCITBATR1 (*(vuint32_t*)(&__MBAR[0x000B68]))
#define MCF_PCI_PCITCR (*(vuint32_t*)(&__MBAR[0x000B6C]))
#define MCF_PCI_PCIIW0BTAR (*(vuint32_t*)(&__MBAR[0x000B70]))
#define MCF_PCI_PCIIW1BTAR (*(vuint32_t*)(&__MBAR[0x000B74]))
#define MCF_PCI_PCIIW2BTAR (*(vuint32_t*)(&__MBAR[0x000B78]))
#define MCF_PCI_PCIIWCR (*(vuint32_t*)(&__MBAR[0x000B80]))
#define MCF_PCI_PCIICR (*(vuint32_t*)(&__MBAR[0x000B84]))
#define MCF_PCI_PCIISR (*(vuint32_t*)(&__MBAR[0x000B88]))
#define MCF_PCI_PCICAR (*(vuint32_t*)(&__MBAR[0x000BF8]))
#define MCF_PCI_PCITPSR (*(vuint32_t*)(&__MBAR[0x008400]))
#define MCF_PCI_PCITSAR (*(vuint32_t*)(&__MBAR[0x008404]))
#define MCF_PCI_PCITTCR (*(vuint32_t*)(&__MBAR[0x008408]))
#define MCF_PCI_PCITER (*(vuint32_t*)(&__MBAR[0x00840C]))
#define MCF_PCI_PCITNAR (*(vuint32_t*)(&__MBAR[0x008410]))
#define MCF_PCI_PCITLWR (*(vuint32_t*)(&__MBAR[0x008414]))
#define MCF_PCI_PCITDCR (*(vuint32_t*)(&__MBAR[0x008418]))
#define MCF_PCI_PCITSR (*(vuint32_t*)(&__MBAR[0x00841C]))
#define MCF_PCI_PCITFDR (*(vuint32_t*)(&__MBAR[0x008440]))
#define MCF_PCI_PCITFSR (*(vuint32_t*)(&__MBAR[0x008444]))
#define MCF_PCI_PCITFCR (*(vuint32_t*)(&__MBAR[0x008448]))
#define MCF_PCI_PCITFAR (*(vuint32_t*)(&__MBAR[0x00844C]))
#define MCF_PCI_PCITFRPR (*(vuint32_t*)(&__MBAR[0x008450]))
#define MCF_PCI_PCITFWPR (*(vuint32_t*)(&__MBAR[0x008454]))
#define MCF_PCI_PCIRPSR (*(vuint32_t*)(&__MBAR[0x008480]))
#define MCF_PCI_PCIRSAR (*(vuint32_t*)(&__MBAR[0x008484]))
#define MCF_PCI_PCIRTCR (*(vuint32_t*)(&__MBAR[0x008488]))
#define MCF_PCI_PCIRER (*(vuint32_t*)(&__MBAR[0x00848C]))
#define MCF_PCI_PCIRNAR (*(vuint32_t*)(&__MBAR[0x008490]))
#define MCF_PCI_PCIRDCR (*(vuint32_t*)(&__MBAR[0x008498]))
#define MCF_PCI_PCIRSR (*(vuint32_t*)(&__MBAR[0x00849C]))
#define MCF_PCI_PCIRFDR (*(vuint32_t*)(&__MBAR[0x0084C0]))
#define MCF_PCI_PCIRFSR (*(vuint32_t*)(&__MBAR[0x0084C4]))
#define MCF_PCI_PCIRFCR (*(vuint32_t*)(&__MBAR[0x0084C8]))
#define MCF_PCI_PCIRFAR (*(vuint32_t*)(&__MBAR[0x0084CC]))
#define MCF_PCI_PCIRFRPR (*(vuint32_t*)(&__MBAR[0x0084D0]))
#define MCF_PCI_PCIRFWPR (*(vuint32_t*)(&__MBAR[0x0084D4]))
/*
* Type 0 Config Header Regs
*/
/* Bit definitions and macros for MCF_PCI_PCIIDR */
#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCI_PCISCR */
#define MCF_PCI_PCISCR_M (0x00000002)
#define MCF_PCI_PCISCR_B (0x00000004)
#define MCF_PCI_PCISCR_SP (0x00000008)
#define MCF_PCI_PCISCR_MW (0x00000010)
#define MCF_PCI_PCISCR_PER (0x00000040)
#define MCF_PCI_PCISCR_S (0x00000100)
#define MCF_PCI_PCISCR_F (0x00000200)
#define MCF_PCI_PCISCR_C (0x00100000)
#define MCF_PCI_PCISCR_66M (0x00200000)
#define MCF_PCI_PCISCR_R (0x00400000)
#define MCF_PCI_PCISCR_FC (0x00800000)
#define MCF_PCI_PCISCR_DP (0x01000000)
#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25)
#define MCF_PCI_PCISCR_TS (0x08000000)
#define MCF_PCI_PCISCR_TR (0x10000000)
#define MCF_PCI_PCISCR_MA (0x20000000)
#define MCF_PCI_PCISCR_SE (0x40000000)
#define MCF_PCI_PCISCR_PE (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCICCRIR */
#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
/* Bit definitions and macros for MCF_PCI_PCICR1 */
#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
#define MCF_PCI_PCIBAR0_IO (0x00000001)
#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1)
#define MCF_PCI_PCIBAR0_PREF (0x00000008)
#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
#define MCF_PCI_PCIBAR1_IO (0x00000001)
#define MCF_PCI_PCIBAR1_PREF (0x00000008)
#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for MCF_PCI_PCICR2 */
#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCI_PCIGSCR */
#define MCF_PCI_PCIGSCR_PR (0x00000001)
#define MCF_PCI_PCIGSCR_SEE (0x00001000)
#define MCF_PCI_PCIGSCR_PEE (0x00002000)
#define MCF_PCI_PCIGSCR_SE (0x10000000)
#define MCF_PCI_PCIGSCR_PE (0x20000000)
/*
* Target device controls
*/
/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
#define MCF_PCI_PCITBATR0_EN (0x00000001)
#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
#define MCF_PCI_PCITBATR1_EN (0x00000001)
#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for MCF_PCI_PCITCR */
#define MCF_PCI_PCITCR_P (0x00010000)
#define MCF_PCI_PCITCR_LD (0x01000000)
/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PCI_PCIIWCR */
#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900)
/* Bit definitions and macros for MCF_PCI_PCIICR */
#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
#define MCF_PCI_PCIICR_TAE (0x01000000)
#define MCF_PCI_PCIICR_IAE (0x02000000)
#define MCF_PCI_PCIICR_REE (0x04000000)
/* Bit definitions and macros for MCF_PCI_PCIISR */
#define MCF_PCI_PCIISR_TA (0x01000000)
#define MCF_PCI_PCIISR_IA (0x02000000)
#define MCF_PCI_PCIISR_RE (0x04000000)
/* Bit definitions and macros for MCF_PCI_PCICAR */
#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCICAR_E (0x80000000)
/*
* PCI Fifos
*/
/* Bit definitions and macros for MCF_PCI_PCITPSR */
#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCI_PCITTCR */
#define MCF_PCI_PCITTCR_DI (0x00000001)
#define MCF_PCI_PCITTCR_W (0x00000010)
#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_PCI_PCITER */
#define MCF_PCI_PCITER_NE (0x00010000)
#define MCF_PCI_PCITER_IAE (0x00020000)
#define MCF_PCI_PCITER_TAE (0x00040000)
#define MCF_PCI_PCITER_RE (0x00080000)
#define MCF_PCI_PCITER_SE (0x00100000)
#define MCF_PCI_PCITER_FEE (0x00200000)
#define MCF_PCI_PCITER_ME (0x01000000)
#define MCF_PCI_PCITER_BE (0x08000000)
#define MCF_PCI_PCITER_CM (0x10000000)
#define MCF_PCI_PCITER_RF (0x40000000)
#define MCF_PCI_PCITER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITDCR */
#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCI_PCITSR */
#define MCF_PCI_PCITSR_IA (0x00010000)
#define MCF_PCI_PCITSR_TA (0x00020000)
#define MCF_PCI_PCITSR_RE (0x00040000)
#define MCF_PCI_PCITSR_SE (0x00080000)
#define MCF_PCI_PCITSR_FE (0x00100000)
#define MCF_PCI_PCITSR_BE1 (0x00200000)
#define MCF_PCI_PCITSR_BE2 (0x00400000)
#define MCF_PCI_PCITSR_BE3 (0x00800000)
#define MCF_PCI_PCITSR_NT (0x01000000)
/* Bit definitions and macros for MCF_PCI_PCITFSR */
#define MCF_PCI_PCITFSR_EMT (0x00010000)
#define MCF_PCI_PCITFSR_ALARM (0x00020000)
#define MCF_PCI_PCITFSR_FU (0x00040000)
#define MCF_PCI_PCITFSR_FR (0x00080000)
#define MCF_PCI_PCITFSR_OF (0x00100000)
#define MCF_PCI_PCITFSR_UF (0x00200000)
#define MCF_PCI_PCITFSR_RXW (0x00400000)
/* Bit definitions and macros for MCF_PCI_PCITFCR */
#define MCF_PCI_PCITFCR_OF_MSK (0x00080000)
#define MCF_PCI_PCITFCR_UF_MSK (0x00100000)
#define MCF_PCI_PCITFCR_RXW_MSK (0x00200000)
#define MCF_PCI_PCITFCR_FAE_MSK (0x00400000)
#define MCF_PCI_PCITFCR_IP_MSK (0x00800000)
#define MCF_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24)
/* Bit definitions and macros for MCF_PCI_PCITFAR */
#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFRPR */
#define MCF_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFWPR */
#define MCF_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRPSR */
#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCI_PCIRTCR */
#define MCF_PCI_PCIRTCR_DI (0x00000001)
#define MCF_PCI_PCIRTCR_W (0x00000010)
#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
#define MCF_PCI_PCIRTCR_FB (0x00001000)
#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_PCI_PCIRER */
#define MCF_PCI_PCIRER_NE (0x00010000)
#define MCF_PCI_PCIRER_IAE (0x00020000)
#define MCF_PCI_PCIRER_TAE (0x00040000)
#define MCF_PCI_PCIRER_RE (0x00080000)
#define MCF_PCI_PCIRER_SE (0x00100000)
#define MCF_PCI_PCIRER_FEE (0x00200000)
#define MCF_PCI_PCIRER_ME (0x01000000)
#define MCF_PCI_PCIRER_BE (0x08000000)
#define MCF_PCI_PCIRER_CM (0x10000000)
#define MCF_PCI_PCIRER_FE (0x20000000)
#define MCF_PCI_PCIRER_RF (0x40000000)
#define MCF_PCI_PCIRER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCIRDCR */
#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PCI_PCIRSR */
#define MCF_PCI_PCIRSR_IA (0x00010000)
#define MCF_PCI_PCIRSR_TA (0x00020000)
#define MCF_PCI_PCIRSR_RE (0x00040000)
#define MCF_PCI_PCIRSR_SE (0x00080000)
#define MCF_PCI_PCIRSR_FE (0x00100000)
#define MCF_PCI_PCIRSR_BE1 (0x00200000)
#define MCF_PCI_PCIRSR_BE2 (0x00400000)
#define MCF_PCI_PCIRSR_BE3 (0x00800000)
#define MCF_PCI_PCIRSR_NT (0x01000000)
/* Bit definitions and macros for MCF_PCI_PCIRFSR */
#define MCF_PCI_PCIRFSR_EMT (0x00010000)
#define MCF_PCI_PCIRFSR_ALARM (0x00020000)
#define MCF_PCI_PCIRFSR_FU (0x00040000)
#define MCF_PCI_PCIRFSR_FR (0x00080000)
#define MCF_PCI_PCIRFSR_OF (0x00100000)
#define MCF_PCI_PCIRFSR_UF (0x00200000)
#define MCF_PCI_PCIRFSR_RXW (0x00400000)
/* Bit definitions and macros for MCF_PCI_PCIRFCR */
#define MCF_PCI_PCIRFCR_OF_MSK (0x00080000)
#define MCF_PCI_PCIRFCR_UF_MSK (0x00100000)
#define MCF_PCI_PCIRFCR_RXW_MSK (0x00200000)
#define MCF_PCI_PCIRFCR_FAE_MSK (0x00400000)
#define MCF_PCI_PCIRFCR_IP_MSK (0x00800000)
#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
/* Bit definitions and macros for MCF_PCI_PCIRFAR */
#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
#define MCF_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
#define MCF_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
#endif /* __MCF548X_PCI_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h
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@ -1,50 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* PCI Arbiter Module (PCIARB)
*/
#ifndef __MCF548X_PCIARB_H__
#define __MCF548X_PCIARB_H__
/*
* PCI Arbiter Module (PCIARB)
*/
/* Register read/write macros */
#define MCF_PCIARB_PACR (*(vuint32_t*)(&__MBAR[0x000C00]))
#define MCF_PCIARB_PASR (*(vuint32_t*)(&__MBAR[0x000C04]))
/* Bit definitions and macros for MCF_PCIARB_PACR */
#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
/* Not documented!
* #define MCF_PCIARB_PACR_PKMD (0x40000000)
*/
#define MCF_PCIARB_PACR_DS (0x80000000)
/* Bit definitions and macros for MCF_PCIARB_PASR */
#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
#endif /* __MCF548X_PCIARB_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Programmable Serial Controller (PSC)
*/
#ifndef __MCF548X_PSC_H__
#define __MCF548X_PSC_H__
/*
* Programmable Serial Controller (PSC)
*/
/* Register read/write macros */
#define MCF_PSC_MR0 (*(vuint8_t *)(&__MBAR[0x008600]))
#define MCF_PSC_SR0 (*(vuint16_t*)(&__MBAR[0x008604]))
#define MCF_PSC_CSR0 (*(vuint8_t *)(&__MBAR[0x008604]))
#define MCF_PSC_CR0 (*(vuint8_t *)(&__MBAR[0x008608]))
#define MCF_PSC_RB0 (*(vuint32_t*)(&__MBAR[0x00860C]))
#define MCF_PSC_TB0 (*(vuint32_t*)(&__MBAR[0x00860C]))
#define MCF_PSC_TB_8BIT0 (*(vuint32_t*)(&__MBAR[0x00860C]))
#define MCF_PSC_TB_16BIT0 (*(vuint32_t*)(&__MBAR[0x00860C]))
#define MCF_PSC_TB_AC970 (*(vuint32_t*)(&__MBAR[0x00860C]))
#define MCF_PSC_IPCR0 (*(vuint8_t *)(&__MBAR[0x008610]))
#define MCF_PSC_ACR0 (*(vuint8_t *)(&__MBAR[0x008610]))
#define MCF_PSC_ISR0 (*(vuint16_t*)(&__MBAR[0x008614]))
#define MCF_PSC_IMR0 (*(vuint16_t*)(&__MBAR[0x008614]))
#define MCF_PSC_CTUR0 (*(vuint8_t *)(&__MBAR[0x008618]))
#define MCF_PSC_CTLR0 (*(vuint8_t *)(&__MBAR[0x00861C]))
#define MCF_PSC_IP0 (*(vuint8_t *)(&__MBAR[0x008634]))
#define MCF_PSC_OPSET0 (*(vuint8_t *)(&__MBAR[0x008638]))
#define MCF_PSC_OPRESET0 (*(vuint8_t *)(&__MBAR[0x00863C]))
#define MCF_PSC_SICR0 (*(vuint8_t *)(&__MBAR[0x008640]))
#define MCF_PSC_IRCR10 (*(vuint8_t *)(&__MBAR[0x008644]))
#define MCF_PSC_IRCR20 (*(vuint8_t *)(&__MBAR[0x008648]))
#define MCF_PSC_IRSDR0 (*(vuint8_t *)(&__MBAR[0x00864C]))
#define MCF_PSC_IRMDR0 (*(vuint8_t *)(&__MBAR[0x008650]))
#define MCF_PSC_IRFDR0 (*(vuint8_t *)(&__MBAR[0x008654]))
#define MCF_PSC_RFCNT0 (*(vuint16_t*)(&__MBAR[0x008658]))
#define MCF_PSC_TFCNT0 (*(vuint16_t*)(&__MBAR[0x00865C]))
#define MCF_PSC_RFSR0 (*(vuint16_t*)(&__MBAR[0x008664]))
#define MCF_PSC_TFSR0 (*(vuint16_t*)(&__MBAR[0x008684]))
#define MCF_PSC_RFCR0 (*(vuint32_t*)(&__MBAR[0x008668]))
#define MCF_PSC_TFCR0 (*(vuint32_t*)(&__MBAR[0x008688]))
#define MCF_PSC_RFAR0 (*(vuint16_t*)(&__MBAR[0x00866E]))
#define MCF_PSC_TFAR0 (*(vuint16_t*)(&__MBAR[0x00868E]))
#define MCF_PSC_RFRP0 (*(vuint16_t*)(&__MBAR[0x008672]))
#define MCF_PSC_TFRP0 (*(vuint16_t*)(&__MBAR[0x008692]))
#define MCF_PSC_RFWP0 (*(vuint16_t*)(&__MBAR[0x008676]))
#define MCF_PSC_TFWP0 (*(vuint16_t*)(&__MBAR[0x008696]))
#define MCF_PSC_RLRFP0 (*(vuint16_t*)(&__MBAR[0x00867A]))
#define MCF_PSC_TLRFP0 (*(vuint16_t*)(&__MBAR[0x00869A]))
#define MCF_PSC_RLWFP0 (*(vuint16_t*)(&__MBAR[0x00867E]))
#define MCF_PSC_TLWFP0 (*(vuint16_t*)(&__MBAR[0x00869E]))
#define MCF_PSC_MR1 (*(vuint8_t *)(&__MBAR[0x008700]))
#define MCF_PSC_SR1 (*(vuint16_t*)(&__MBAR[0x008704]))
#define MCF_PSC_CSR1 (*(vuint8_t *)(&__MBAR[0x008704]))
#define MCF_PSC_CR1 (*(vuint8_t *)(&__MBAR[0x008708]))
#define MCF_PSC_RB1 (*(vuint32_t*)(&__MBAR[0x00870C]))
#define MCF_PSC_TB1 (*(vuint32_t*)(&__MBAR[0x00870C]))
#define MCF_PSC_TB_8BIT1 (*(vuint32_t*)(&__MBAR[0x00870C]))
#define MCF_PSC_TB_16BIT1 (*(vuint32_t*)(&__MBAR[0x00870C]))
#define MCF_PSC_TB_AC971 (*(vuint32_t*)(&__MBAR[0x00870C]))
#define MCF_PSC_IPCR1 (*(vuint8_t *)(&__MBAR[0x008710]))
#define MCF_PSC_ACR1 (*(vuint8_t *)(&__MBAR[0x008710]))
#define MCF_PSC_ISR1 (*(vuint16_t*)(&__MBAR[0x008714]))
#define MCF_PSC_IMR1 (*(vuint16_t*)(&__MBAR[0x008714]))
#define MCF_PSC_CTUR1 (*(vuint8_t *)(&__MBAR[0x008718]))
#define MCF_PSC_CTLR1 (*(vuint8_t *)(&__MBAR[0x00871C]))
#define MCF_PSC_IP1 (*(vuint8_t *)(&__MBAR[0x008734]))
#define MCF_PSC_OPSET1 (*(vuint8_t *)(&__MBAR[0x008738]))
#define MCF_PSC_OPRESET1 (*(vuint8_t *)(&__MBAR[0x00873C]))
#define MCF_PSC_SICR1 (*(vuint8_t *)(&__MBAR[0x008740]))
#define MCF_PSC_IRCR11 (*(vuint8_t *)(&__MBAR[0x008744]))
#define MCF_PSC_IRCR21 (*(vuint8_t *)(&__MBAR[0x008748]))
#define MCF_PSC_IRSDR1 (*(vuint8_t *)(&__MBAR[0x00874C]))
#define MCF_PSC_IRMDR1 (*(vuint8_t *)(&__MBAR[0x008750]))
#define MCF_PSC_IRFDR1 (*(vuint8_t *)(&__MBAR[0x008754]))
#define MCF_PSC_RFCNT1 (*(vuint16_t*)(&__MBAR[0x008758]))
#define MCF_PSC_TFCNT1 (*(vuint16_t*)(&__MBAR[0x00875C]))
#define MCF_PSC_RFSR1 (*(vuint16_t*)(&__MBAR[0x008764]))
#define MCF_PSC_TFSR1 (*(vuint16_t*)(&__MBAR[0x008784]))
#define MCF_PSC_RFCR1 (*(vuint32_t*)(&__MBAR[0x008768]))
#define MCF_PSC_TFCR1 (*(vuint32_t*)(&__MBAR[0x008788]))
#define MCF_PSC_RFAR1 (*(vuint16_t*)(&__MBAR[0x00876E]))
#define MCF_PSC_TFAR1 (*(vuint16_t*)(&__MBAR[0x00878E]))
#define MCF_PSC_RFRP1 (*(vuint16_t*)(&__MBAR[0x008772]))
#define MCF_PSC_TFRP1 (*(vuint16_t*)(&__MBAR[0x008792]))
#define MCF_PSC_RFWP1 (*(vuint16_t*)(&__MBAR[0x008776]))
#define MCF_PSC_TFWP1 (*(vuint16_t*)(&__MBAR[0x008796]))
#define MCF_PSC_RLRFP1 (*(vuint16_t*)(&__MBAR[0x00877A]))
#define MCF_PSC_TLRFP1 (*(vuint16_t*)(&__MBAR[0x00879A]))
#define MCF_PSC_RLWFP1 (*(vuint16_t*)(&__MBAR[0x00877E]))
#define MCF_PSC_TLWFP1 (*(vuint16_t*)(&__MBAR[0x00879E]))
#define MCF_PSC_MR2 (*(vuint8_t *)(&__MBAR[0x008800]))
#define MCF_PSC_SR2 (*(vuint16_t*)(&__MBAR[0x008804]))
#define MCF_PSC_CSR2 (*(vuint8_t *)(&__MBAR[0x008804]))
#define MCF_PSC_CR2 (*(vuint8_t *)(&__MBAR[0x008808]))
#define MCF_PSC_RB2 (*(vuint32_t*)(&__MBAR[0x00880C]))
#define MCF_PSC_TB2 (*(vuint32_t*)(&__MBAR[0x00880C]))
#define MCF_PSC_TB_8BIT2 (*(vuint32_t*)(&__MBAR[0x00880C]))
#define MCF_PSC_TB_16BIT2 (*(vuint32_t*)(&__MBAR[0x00880C]))
#define MCF_PSC_TB_AC972 (*(vuint32_t*)(&__MBAR[0x00880C]))
#define MCF_PSC_IPCR2 (*(vuint8_t *)(&__MBAR[0x008810]))
#define MCF_PSC_ACR2 (*(vuint8_t *)(&__MBAR[0x008810]))
#define MCF_PSC_ISR2 (*(vuint16_t*)(&__MBAR[0x008814]))
#define MCF_PSC_IMR2 (*(vuint16_t*)(&__MBAR[0x008814]))
#define MCF_PSC_CTUR2 (*(vuint8_t *)(&__MBAR[0x008818]))
#define MCF_PSC_CTLR2 (*(vuint8_t *)(&__MBAR[0x00881C]))
#define MCF_PSC_IP2 (*(vuint8_t *)(&__MBAR[0x008834]))
#define MCF_PSC_OPSET2 (*(vuint8_t *)(&__MBAR[0x008838]))
#define MCF_PSC_OPRESET2 (*(vuint8_t *)(&__MBAR[0x00883C]))
#define MCF_PSC_SICR2 (*(vuint8_t *)(&__MBAR[0x008840]))
#define MCF_PSC_IRCR12 (*(vuint8_t *)(&__MBAR[0x008844]))
#define MCF_PSC_IRCR22 (*(vuint8_t *)(&__MBAR[0x008848]))
#define MCF_PSC_IRSDR2 (*(vuint8_t *)(&__MBAR[0x00884C]))
#define MCF_PSC_IRMDR2 (*(vuint8_t *)(&__MBAR[0x008850]))
#define MCF_PSC_IRFDR2 (*(vuint8_t *)(&__MBAR[0x008854]))
#define MCF_PSC_RFCNT2 (*(vuint16_t*)(&__MBAR[0x008858]))
#define MCF_PSC_TFCNT2 (*(vuint16_t*)(&__MBAR[0x00885C]))
#define MCF_PSC_RFSR2 (*(vuint16_t*)(&__MBAR[0x008864]))
#define MCF_PSC_TFSR2 (*(vuint16_t*)(&__MBAR[0x008884]))
#define MCF_PSC_RFCR2 (*(vuint32_t*)(&__MBAR[0x008868]))
#define MCF_PSC_TFCR2 (*(vuint32_t*)(&__MBAR[0x008888]))
#define MCF_PSC_RFAR2 (*(vuint16_t*)(&__MBAR[0x00886E]))
#define MCF_PSC_TFAR2 (*(vuint16_t*)(&__MBAR[0x00888E]))
#define MCF_PSC_RFRP2 (*(vuint16_t*)(&__MBAR[0x008872]))
#define MCF_PSC_TFRP2 (*(vuint16_t*)(&__MBAR[0x008892]))
#define MCF_PSC_RFWP2 (*(vuint16_t*)(&__MBAR[0x008876]))
#define MCF_PSC_TFWP2 (*(vuint16_t*)(&__MBAR[0x008896]))
#define MCF_PSC_RLRFP2 (*(vuint16_t*)(&__MBAR[0x00887A]))
#define MCF_PSC_TLRFP2 (*(vuint16_t*)(&__MBAR[0x00889A]))
#define MCF_PSC_RLWFP2 (*(vuint16_t*)(&__MBAR[0x00887E]))
#define MCF_PSC_TLWFP2 (*(vuint16_t*)(&__MBAR[0x00889E]))
#define MCF_PSC_MR3 (*(vuint8_t *)(&__MBAR[0x008900]))
#define MCF_PSC_SR3 (*(vuint16_t*)(&__MBAR[0x008904]))
#define MCF_PSC_CSR3 (*(vuint8_t *)(&__MBAR[0x008904]))
#define MCF_PSC_CR3 (*(vuint8_t *)(&__MBAR[0x008908]))
#define MCF_PSC_RB3 (*(vuint32_t*)(&__MBAR[0x00890C]))
#define MCF_PSC_TB3 (*(vuint32_t*)(&__MBAR[0x00890C]))
#define MCF_PSC_TB_8BIT3 (*(vuint32_t*)(&__MBAR[0x00890C]))
#define MCF_PSC_TB_16BIT3 (*(vuint32_t*)(&__MBAR[0x00890C]))
#define MCF_PSC_TB_AC973 (*(vuint32_t*)(&__MBAR[0x00890C]))
#define MCF_PSC_IPCR3 (*(vuint8_t *)(&__MBAR[0x008910]))
#define MCF_PSC_ACR3 (*(vuint8_t *)(&__MBAR[0x008910]))
#define MCF_PSC_ISR3 (*(vuint16_t*)(&__MBAR[0x008914]))
#define MCF_PSC_IMR3 (*(vuint16_t*)(&__MBAR[0x008914]))
#define MCF_PSC_CTUR3 (*(vuint8_t *)(&__MBAR[0x008918]))
#define MCF_PSC_CTLR3 (*(vuint8_t *)(&__MBAR[0x00891C]))
#define MCF_PSC_IP3 (*(vuint8_t *)(&__MBAR[0x008934]))
#define MCF_PSC_OPSET3 (*(vuint8_t *)(&__MBAR[0x008938]))
#define MCF_PSC_OPRESET3 (*(vuint8_t *)(&__MBAR[0x00893C]))
#define MCF_PSC_SICR3 (*(vuint8_t *)(&__MBAR[0x008940]))
#define MCF_PSC_IRCR13 (*(vuint8_t *)(&__MBAR[0x008944]))
#define MCF_PSC_IRCR23 (*(vuint8_t *)(&__MBAR[0x008948]))
#define MCF_PSC_IRSDR3 (*(vuint8_t *)(&__MBAR[0x00894C]))
#define MCF_PSC_IRMDR3 (*(vuint8_t *)(&__MBAR[0x008950]))
#define MCF_PSC_IRFDR3 (*(vuint8_t *)(&__MBAR[0x008954]))
#define MCF_PSC_RFCNT3 (*(vuint16_t*)(&__MBAR[0x008958]))
#define MCF_PSC_TFCNT3 (*(vuint16_t*)(&__MBAR[0x00895C]))
#define MCF_PSC_RFSR3 (*(vuint16_t*)(&__MBAR[0x008964]))
#define MCF_PSC_TFSR3 (*(vuint16_t*)(&__MBAR[0x008984]))
#define MCF_PSC_RFCR3 (*(vuint32_t*)(&__MBAR[0x008968]))
#define MCF_PSC_TFCR3 (*(vuint32_t*)(&__MBAR[0x008988]))
#define MCF_PSC_RFAR3 (*(vuint16_t*)(&__MBAR[0x00896E]))
#define MCF_PSC_TFAR3 (*(vuint16_t*)(&__MBAR[0x00898E]))
#define MCF_PSC_RFRP3 (*(vuint16_t*)(&__MBAR[0x008972]))
#define MCF_PSC_TFRP3 (*(vuint16_t*)(&__MBAR[0x008992]))
#define MCF_PSC_RFWP3 (*(vuint16_t*)(&__MBAR[0x008976]))
#define MCF_PSC_TFWP3 (*(vuint16_t*)(&__MBAR[0x008996]))
#define MCF_PSC_RLRFP3 (*(vuint16_t*)(&__MBAR[0x00897A]))
#define MCF_PSC_TLRFP3 (*(vuint16_t*)(&__MBAR[0x00899A]))
#define MCF_PSC_RLWFP3 (*(vuint16_t*)(&__MBAR[0x00897E]))
#define MCF_PSC_TLWFP3 (*(vuint16_t*)(&__MBAR[0x00899E]))
#define MCF_PSC_MR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)]))
#define MCF_PSC_SR(x) (*(vuint16_t*)(&__MBAR[0x008604+((x)*0x100)]))
#define MCF_PSC_CSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)]))
#define MCF_PSC_CR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)]))
#define MCF_PSC_RB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_PSC_TB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_PSC_TB_8BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_PSC_TB_16BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_PSC_TB_AC97(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_PSC_IPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)]))
#define MCF_PSC_ACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)]))
#define MCF_PSC_ISR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)]))
#define MCF_PSC_IMR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)]))
#define MCF_PSC_CTUR(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)]))
#define MCF_PSC_CTLR(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)]))
#define MCF_PSC_IP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)]))
#define MCF_PSC_OPSET(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)]))
#define MCF_PSC_OPRESET(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)]))
#define MCF_PSC_SICR(x) (*(vuint8_t *)(&__MBAR[0x008640+((x)*0x100)]))
#define MCF_PSC_IRCR1(x) (*(vuint8_t *)(&__MBAR[0x008644+((x)*0x100)]))
#define MCF_PSC_IRCR2(x) (*(vuint8_t *)(&__MBAR[0x008648+((x)*0x100)]))
#define MCF_PSC_IRSDR(x) (*(vuint8_t *)(&__MBAR[0x00864C+((x)*0x100)]))
#define MCF_PSC_IRMDR(x) (*(vuint8_t *)(&__MBAR[0x008650+((x)*0x100)]))
#define MCF_PSC_IRFDR(x) (*(vuint8_t *)(&__MBAR[0x008654+((x)*0x100)]))
#define MCF_PSC_RFCNT(x) (*(vuint16_t*)(&__MBAR[0x008658+((x)*0x100)]))
#define MCF_PSC_TFCNT(x) (*(vuint16_t*)(&__MBAR[0x00865C+((x)*0x100)]))
#define MCF_PSC_RFSR(x) (*(vuint16_t*)(&__MBAR[0x008664+((x)*0x100)]))
#define MCF_PSC_TFSR(x) (*(vuint16_t*)(&__MBAR[0x008684+((x)*0x100)]))
#define MCF_PSC_RFCR(x) (*(vuint32_t*)(&__MBAR[0x008668+((x)*0x100)]))
#define MCF_PSC_TFCR(x) (*(vuint32_t*)(&__MBAR[0x008688+((x)*0x100)]))
#define MCF_PSC_RFAR(x) (*(vuint16_t*)(&__MBAR[0x00866E+((x)*0x100)]))
#define MCF_PSC_TFAR(x) (*(vuint16_t*)(&__MBAR[0x00868E+((x)*0x100)]))
#define MCF_PSC_RFRP(x) (*(vuint16_t*)(&__MBAR[0x008672+((x)*0x100)]))
#define MCF_PSC_TFRP(x) (*(vuint16_t*)(&__MBAR[0x008692+((x)*0x100)]))
#define MCF_PSC_RFWP(x) (*(vuint16_t*)(&__MBAR[0x008676+((x)*0x100)]))
#define MCF_PSC_TFWP(x) (*(vuint16_t*)(&__MBAR[0x008696+((x)*0x100)]))
#define MCF_PSC_RLRFP(x) (*(vuint16_t*)(&__MBAR[0x00867A+((x)*0x100)]))
#define MCF_PSC_TLRFP(x) (*(vuint16_t*)(&__MBAR[0x00869A+((x)*0x100)]))
#define MCF_PSC_RLWFP(x) (*(vuint16_t*)(&__MBAR[0x00867E+((x)*0x100)]))
#define MCF_PSC_TLWFP(x) (*(vuint16_t*)(&__MBAR[0x00869E+((x)*0x100)]))
/* Bit definitions and macros for MCF_PSC_MR */
#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0)
#define MCF_PSC_MR_PT (0x04)
#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3)
#define MCF_PSC_MR_ERR (0x20)
#define MCF_PSC_MR_RXIRQ (0x40)
#define MCF_PSC_MR_RXRTS (0x80)
#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0)
#define MCF_PSC_MR_TXCTS (0x10)
#define MCF_PSC_MR_TXRTS (0x20)
#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6)
#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C)
#define MCF_PSC_MR_PM_MULTI_DATA (0x18)
#define MCF_PSC_MR_PM_NONE (0x10)
#define MCF_PSC_MR_PM_FORCE_HI (0x0C)
#define MCF_PSC_MR_PM_FORCE_LO (0x08)
#define MCF_PSC_MR_PM_ODD (0x04)
#define MCF_PSC_MR_PM_EVEN (0x00)
#define MCF_PSC_MR_BC_5 (0x00)
#define MCF_PSC_MR_BC_6 (0x01)
#define MCF_PSC_MR_BC_7 (0x02)
#define MCF_PSC_MR_BC_8 (0x03)
#define MCF_PSC_MR_CM_NORMAL (0x00)
#define MCF_PSC_MR_CM_ECHO (0x40)
#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80)
#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0)
#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07)
#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08)
#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for MCF_PSC_SR */
#define MCF_PSC_SR_ERR (0x0040)
#define MCF_PSC_SR_CDE_DEOF (0x0080)
#define MCF_PSC_SR_RXRDY (0x0100)
#define MCF_PSC_SR_FU (0x0200)
#define MCF_PSC_SR_TXRDY (0x0400)
#define MCF_PSC_SR_TXEMP_URERR (0x0800)
#define MCF_PSC_SR_OE (0x1000)
#define MCF_PSC_SR_PE_CRCERR (0x2000)
#define MCF_PSC_SR_FE_PHYERR (0x4000)
#define MCF_PSC_SR_RB_NEOF (0x8000)
/* Bit definitions and macros for MCF_PSC_CSR */
#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0)
#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4)
#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0)
#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0)
#define MCF_PSC_CSR_RCSEL_CTM (0xF0)
#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D)
#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E)
#define MCF_PSC_CSR_TCSEL_CTM (0x0F)
/* Bit definitions and macros for MCF_PSC_CR */
#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0)
#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2)
#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4)
#define MCF_PSC_CR_NONE (0x00)
#define MCF_PSC_CR_STOP_BREAK (0x70)
#define MCF_PSC_CR_START_BREAK (0x60)
#define MCF_PSC_CR_BKCHGINT (0x50)
#define MCF_PSC_CR_RESET_ERROR (0x40)
#define MCF_PSC_CR_RESET_TX (0x30)
#define MCF_PSC_CR_RESET_RX (0x20)
#define MCF_PSC_CR_RESET_MR (0x10)
#define MCF_PSC_CR_TX_DISABLED (0x08)
#define MCF_PSC_CR_TX_ENABLED (0x04)
#define MCF_PSC_CR_RX_DISABLED (0x02)
#define MCF_PSC_CR_RX_ENABLED (0x01)
/* Bit definitions and macros for MCF_PSC_TB_8BIT */
#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0)
#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8)
#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16)
#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_PSC_TB_16BIT */
#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_PSC_TB_AC97 */
#define MCF_PSC_TB_AC97_SOF (0x00000800)
#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12)
/* Bit definitions and macros for MCF_PSC_IPCR */
#define MCF_PSC_IPCR_RESERVED (0x0C)
#define MCF_PSC_IPCR_CTS (0x0D)
#define MCF_PSC_IPCR_D_CTS (0x1C)
#define MCF_PSC_IPCR_SYNC (0x8C)
/* Bit definitions and macros for MCF_PSC_ACR */
#define MCF_PSC_ACR_IEC0 (0x01)
#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4)
#define MCF_PSC_ACR_BRG (0x80)
/* Bit definitions and macros for MCF_PSC_ISR */
#define MCF_PSC_ISR_ERR (0x0040)
#define MCF_PSC_ISR_DEOF (0x0080)
#define MCF_PSC_ISR_TXRDY (0x0100)
#define MCF_PSC_ISR_RXRDY_FU (0x0200)
#define MCF_PSC_ISR_DB (0x0400)
#define MCF_PSC_ISR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_IMR */
#define MCF_PSC_IMR_ERR (0x0040)
#define MCF_PSC_IMR_DEOF (0x0080)
#define MCF_PSC_IMR_TXRDY (0x0100)
#define MCF_PSC_IMR_RXRDY_FU (0x0200)
#define MCF_PSC_IMR_DB (0x0400)
#define MCF_PSC_IMR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_IP */
#define MCF_PSC_IP_CTS (0x01)
#define MCF_PSC_IP_TGL (0x40)
#define MCF_PSC_IP_LWPR_B (0x80)
/* Bit definitions and macros for MCF_PSC_OPSET */
#define MCF_PSC_OPSET_RTS (0x01)
/* Bit definitions and macros for MCF_PSC_OPRESET */
#define MCF_PSC_OPRESET_RTS (0x01)
/* Bit definitions and macros for MCF_PSC_SICR */
#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0)
#define MCF_PSC_SICR_SHDIR (0x10)
#define MCF_PSC_SICR_DTS (0x20)
#define MCF_PSC_SICR_AWR (0x40)
#define MCF_PSC_SICR_ACRB (0x80)
#define MCF_PSC_SICR_SIM_UART (0x00)
#define MCF_PSC_SICR_SIM_MODEM8 (0x01)
#define MCF_PSC_SICR_SIM_MODEM16 (0x02)
#define MCF_PSC_SICR_SIM_AC97 (0x03)
#define MCF_PSC_SICR_SIM_SIR (0x04)
#define MCF_PSC_SICR_SIM_MIR (0x05)
#define MCF_PSC_SICR_SIM_FIR (0x06)
/* Bit definitions and macros for MCF_PSC_IRCR1 */
#define MCF_PSC_IRCR1_SPUL (0x01)
#define MCF_PSC_IRCR1_SIPEN (0x02)
#define MCF_PSC_IRCR1_FD (0x04)
/* Bit definitions and macros for MCF_PSC_IRCR2 */
#define MCF_PSC_IRCR2_NXTEOF (0x01)
#define MCF_PSC_IRCR2_ABORT (0x02)
#define MCF_PSC_IRCR2_SIPREQ (0x04)
/* Bit definitions and macros for MCF_PSC_IRMDR */
#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0)
#define MCF_PSC_IRMDR_FREQ (0x80)
/* Bit definitions and macros for MCF_PSC_IRFDR */
#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0)
/* Bit definitions and macros for MCF_PSC_RFCNT */
#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFCNT */
#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFSR */
#define MCF_PSC_RFSR_EMT (0x0001)
#define MCF_PSC_RFSR_ALARM (0x0002)
#define MCF_PSC_RFSR_FU (0x0004)
#define MCF_PSC_RFSR_FRMRY (0x0008)
#define MCF_PSC_RFSR_OF (0x0010)
#define MCF_PSC_RFSR_UF (0x0020)
#define MCF_PSC_RFSR_RXW (0x0040)
#define MCF_PSC_RFSR_FAE (0x0080)
#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8)
#define MCF_PSC_RFSR_TAG (0x1000)
#define MCF_PSC_RFSR_TXW (0x4000)
#define MCF_PSC_RFSR_IP (0x8000)
#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800)
#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400)
#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200)
#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100)
/* Bit definitions and macros for MCF_PSC_TFSR */
#define MCF_PSC_TFSR_EMT (0x0001)
#define MCF_PSC_TFSR_ALARM (0x0002)
#define MCF_PSC_TFSR_FU (0x0004)
#define MCF_PSC_TFSR_FRMRY (0x0008)
#define MCF_PSC_TFSR_OF (0x0010)
#define MCF_PSC_TFSR_UF (0x0020)
#define MCF_PSC_TFSR_RXW (0x0040)
#define MCF_PSC_TFSR_FAE (0x0080)
#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8)
#define MCF_PSC_TFSR_TAG (0x1000)
#define MCF_PSC_TFSR_TXW (0x4000)
#define MCF_PSC_TFSR_IP (0x8000)
#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800)
#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400)
#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200)
#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100)
/* Bit definitions and macros for MCF_PSC_RFCR */
#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_RFCR_TXW_MSK (0x00040000)
#define MCF_PSC_RFCR_OF_MSK (0x00080000)
#define MCF_PSC_RFCR_UF_MSK (0x00100000)
#define MCF_PSC_RFCR_RXW_MSK (0x00200000)
#define MCF_PSC_RFCR_FAE_MSK (0x00400000)
#define MCF_PSC_RFCR_IP_MSK (0x00800000)
#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_PSC_RFCR_FRMEN (0x08000000)
#define MCF_PSC_RFCR_TIMER (0x10000000)
#define MCF_PSC_RFCR_WRITETAG (0x20000000)
#define MCF_PSC_RFCR_SHADOW (0x80000000)
/* Bit definitions and macros for MCF_PSC_TFCR */
#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
#define MCF_PSC_TFCR_TXW_MSK (0x00040000)
#define MCF_PSC_TFCR_OF_MSK (0x00080000)
#define MCF_PSC_TFCR_UF_MSK (0x00100000)
#define MCF_PSC_TFCR_RXW_MSK (0x00200000)
#define MCF_PSC_TFCR_FAE_MSK (0x00400000)
#define MCF_PSC_TFCR_IP_MSK (0x00800000)
#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_PSC_TFCR_FRMEN (0x08000000)
#define MCF_PSC_TFCR_TIMER (0x10000000)
#define MCF_PSC_TFCR_WRITETAG (0x20000000)
#define MCF_PSC_TFCR_SHADOW (0x80000000)
/* Bit definitions and macros for MCF_PSC_RFAR */
#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFAR */
#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFRP */
#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFRP */
#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RFWP */
#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TFWP */
#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RLRFP */
#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TLRFP */
#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_RLWFP */
#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0)
/* Bit definitions and macros for MCF_PSC_TLWFP */
#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0)
#endif /* __MCF548X_PSC_H__ */

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@ -1,109 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* SDRAM Controller (SDRAMC)
*/
#ifndef __MCF548X_SDRAMC_H__
#define __MCF548X_SDRAMC_H__
/*
* SDRAM Controller (SDRAMC)
*/
/* Register read/write macros */
#define MCF_SDRAMC_SDRAMDS (*(vuint32_t*)(&__MBAR[0x000004]))
#define MCF_SDRAMC_CS0CFG (*(vuint32_t*)(&__MBAR[0x000020]))
#define MCF_SDRAMC_CS1CFG (*(vuint32_t*)(&__MBAR[0x000024]))
#define MCF_SDRAMC_CS2CFG (*(vuint32_t*)(&__MBAR[0x000028]))
#define MCF_SDRAMC_CS3CFG (*(vuint32_t*)(&__MBAR[0x00002C]))
#define MCF_SDRAMC_CSnCFG(x) (*(vuint32_t*)(&__MBAR[0x000020+((x)*0x004)]))
#define MCF_SDRAMC_SDMR (*(vuint32_t*)(&__MBAR[0x000100]))
#define MCF_SDRAMC_SDCR (*(vuint32_t*)(&__MBAR[0x000104]))
#define MCF_SDRAMC_SDCFG1 (*(vuint32_t*)(&__MBAR[0x000108]))
#define MCF_SDRAMC_SDCFG2 (*(vuint32_t*)(&__MBAR[0x00010C]))
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0)
#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2)
#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4)
#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6)
#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8)
#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x02)
#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x01)
#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0x00)
#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x03)
/* Bit definitions and macros for MCF_SDRAMC_CSnCFG */
#define MCF_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0)
#define MCF_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20)
#define MCF_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000)
#define MCF_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013)
#define MCF_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014)
#define MCF_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015)
#define MCF_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016)
#define MCF_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017)
#define MCF_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018)
#define MCF_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019)
#define MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A)
#define MCF_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B)
#define MCF_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C)
#define MCF_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D)
#define MCF_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E)
#define MCF_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F)
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x00010000)
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
#define MCF_SDRAMC_SDCR_IREF (0x00000004)
#define MCF_SDRAMC_SDCR_BUFF (0x00000010)
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
#define MCF_SDRAMC_SDCR_DRIVE (0x00400000)
#define MCF_SDRAMC_SDCR_AP (0x00800000)
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
#define MCF_SDRAMC_SDCR_REF (0x10000000)
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
#endif /* __MCF548X_SDRAMC_H__ */

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@ -1,389 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Integrated Security Engine (SEC)
*/
#ifndef __MCF548X_SEC_H__
#define __MCF548X_SEC_H__
/*
* Integrated Security Engine (SEC)
*/
/* Register read/write macros */
#define MCF_SEC_EUACRH (*(vuint32_t*)(&__MBAR[0x021000]))
#define MCF_SEC_EUACRL (*(vuint32_t*)(&__MBAR[0x021004]))
#define MCF_SEC_EUASRH (*(vuint32_t*)(&__MBAR[0x021028]))
#define MCF_SEC_EUASRL (*(vuint32_t*)(&__MBAR[0x02102C]))
#define MCF_SEC_SIMRH (*(vuint32_t*)(&__MBAR[0x021008]))
#define MCF_SEC_SIMRL (*(vuint32_t*)(&__MBAR[0x02100C]))
#define MCF_SEC_SISRH (*(vuint32_t*)(&__MBAR[0x021010]))
#define MCF_SEC_SISRL (*(vuint32_t*)(&__MBAR[0x021014]))
#define MCF_SEC_SICRH (*(vuint32_t*)(&__MBAR[0x021018]))
#define MCF_SEC_SICRL (*(vuint32_t*)(&__MBAR[0x02101C]))
#define MCF_SEC_SIDR (*(vuint32_t*)(&__MBAR[0x021020]))
#define MCF_SEC_SMCR (*(vuint32_t*)(&__MBAR[0x021030]))
#define MCF_SEC_MEAR (*(vuint32_t*)(&__MBAR[0x021038]))
#define MCF_SEC_CCCR0 (*(vuint32_t*)(&__MBAR[0x02200C]))
#define MCF_SEC_CCCR1 (*(vuint32_t*)(&__MBAR[0x02300C]))
#define MCF_SEC_CCPSRH0 (*(vuint32_t*)(&__MBAR[0x022010]))
#define MCF_SEC_CCPSRH1 (*(vuint32_t*)(&__MBAR[0x023010]))
#define MCF_SEC_CCPSRL0 (*(vuint32_t*)(&__MBAR[0x022014]))
#define MCF_SEC_CCPSRL1 (*(vuint32_t*)(&__MBAR[0x023014]))
#define MCF_SEC_CDPR0 (*(vuint32_t*)(&__MBAR[0x022044]))
#define MCF_SEC_CDPR1 (*(vuint32_t*)(&__MBAR[0x023044]))
#define MCF_SEC_FR0 (*(vuint32_t*)(&__MBAR[0x02204C]))
#define MCF_SEC_FR1 (*(vuint32_t*)(&__MBAR[0x02304C]))
#define MCF_SEC_AFRCR (*(vuint32_t*)(&__MBAR[0x028018]))
#define MCF_SEC_AFSR (*(vuint32_t*)(&__MBAR[0x028028]))
#define MCF_SEC_AFISR (*(vuint32_t*)(&__MBAR[0x028030]))
#define MCF_SEC_AFIMR (*(vuint32_t*)(&__MBAR[0x028038]))
#define MCF_SEC_DRCR (*(vuint32_t*)(&__MBAR[0x02A018]))
#define MCF_SEC_DSR (*(vuint32_t*)(&__MBAR[0x02A028]))
#define MCF_SEC_DISR (*(vuint32_t*)(&__MBAR[0x02A030]))
#define MCF_SEC_DIMR (*(vuint32_t*)(&__MBAR[0x02A038]))
#define MCF_SEC_MDRCR (*(vuint32_t*)(&__MBAR[0x02C018]))
#define MCF_SEC_MDSR (*(vuint32_t*)(&__MBAR[0x02C028]))
#define MCF_SEC_MDISR (*(vuint32_t*)(&__MBAR[0x02C030]))
#define MCF_SEC_MDIMR (*(vuint32_t*)(&__MBAR[0x02C038]))
#define MCF_SEC_RNGRCR (*(vuint32_t*)(&__MBAR[0x02E018]))
#define MCF_SEC_RNGSR (*(vuint32_t*)(&__MBAR[0x02E028]))
#define MCF_SEC_RNGISR (*(vuint32_t*)(&__MBAR[0x02E030]))
#define MCF_SEC_RNGIMR (*(vuint32_t*)(&__MBAR[0x02E038]))
#define MCF_SEC_AESRCR (*(vuint32_t*)(&__MBAR[0x032018]))
#define MCF_SEC_AESSR (*(vuint32_t*)(&__MBAR[0x032028]))
#define MCF_SEC_AESISR (*(vuint32_t*)(&__MBAR[0x032030]))
#define MCF_SEC_AESIMR (*(vuint32_t*)(&__MBAR[0x032038]))
/* Bit definitions and macros for MCF_SEC_EUACRH */
#define MCF_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0)
#define MCF_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8)
#define MCF_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24)
#define MCF_SEC_EUACRH_RNG_NOASSIGN (0x00000000)
#define MCF_SEC_EUACRH_RNG_CHA0 (0x01000000)
#define MCF_SEC_EUACRH_RNG_CHA1 (0x02000000)
#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0x00000000)
#define MCF_SEC_EUACRH_MDEU_CHA0 (0x00000100)
#define MCF_SEC_EUACRH_MDEU_CHA1 (0x00000200)
#define MCF_SEC_EUACRH_AFEU_NOASSIGN (0x00000000)
#define MCF_SEC_EUACRH_AFEU_CHA0 (0x00000001)
#define MCF_SEC_EUACRH_AFEU_CHA1 (0x00000002)
/* Bit definitions and macros for MCF_SEC_EUACRL */
#define MCF_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16)
#define MCF_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24)
#define MCF_SEC_EUACRL_DEU_NOASSIGN (0x00000000)
#define MCF_SEC_EUACRL_DEU_CHA0 (0x01000000)
#define MCF_SEC_EUACRL_DEU_CHA1 (0x02000000)
#define MCF_SEC_EUACRL_AESU_NOASSIGN (0x00000000)
#define MCF_SEC_EUACRL_AESU_CHA0 (0x00010000)
#define MCF_SEC_EUACRL_AESU_CHA1 (0x00020000)
/* Bit definitions and macros for MCF_SEC_EUASRH */
#define MCF_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0)
#define MCF_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8)
#define MCF_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_SEC_EUASRL */
#define MCF_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16)
#define MCF_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_SEC_SIMRH */
#define MCF_SEC_SIMRH_AERR (0x08000000)
#define MCF_SEC_SIMRH_CHA0DN (0x10000000)
#define MCF_SEC_SIMRH_CHA0ERR (0x20000000)
#define MCF_SEC_SIMRH_CHA1DN (0x40000000)
#define MCF_SEC_SIMRH_CHA1ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SIMRL */
#define MCF_SEC_SIMRL_TEA (0x00000040)
#define MCF_SEC_SIMRL_DEUDN (0x00000100)
#define MCF_SEC_SIMRL_DEUERR (0x00000200)
#define MCF_SEC_SIMRL_AESUDN (0x00001000)
#define MCF_SEC_SIMRL_AESUERR (0x00002000)
#define MCF_SEC_SIMRL_MDEUDN (0x00010000)
#define MCF_SEC_SIMRL_MDEUERR (0x00020000)
#define MCF_SEC_SIMRL_AFEUDN (0x00100000)
#define MCF_SEC_SIMRL_AFEUERR (0x00200000)
#define MCF_SEC_SIMRL_RNGDN (0x01000000)
#define MCF_SEC_SIMRL_RNGERR (0x02000000)
/* Bit definitions and macros for MCF_SEC_SISRH */
#define MCF_SEC_SISRH_AERR (0x08000000)
#define MCF_SEC_SISRH_CHA0DN (0x10000000)
#define MCF_SEC_SISRH_CHA0ERR (0x20000000)
#define MCF_SEC_SISRH_CHA1DN (0x40000000)
#define MCF_SEC_SISRH_CHA1ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SISRL */
#define MCF_SEC_SISRL_TEA (0x00000040)
#define MCF_SEC_SISRL_DEUDN (0x00000100)
#define MCF_SEC_SISRL_DEUERR (0x00000200)
#define MCF_SEC_SISRL_AESUDN (0x00001000)
#define MCF_SEC_SISRL_AESUERR (0x00002000)
#define MCF_SEC_SISRL_MDEUDN (0x00010000)
#define MCF_SEC_SISRL_MDEUERR (0x00020000)
#define MCF_SEC_SISRL_AFEUDN (0x00100000)
#define MCF_SEC_SISRL_AFEUERR (0x00200000)
#define MCF_SEC_SISRL_RNGDN (0x01000000)
#define MCF_SEC_SISRL_RNGERR (0x02000000)
/* Bit definitions and macros for MCF_SEC_SICRH */
#define MCF_SEC_SICRH_AERR (0x08000000)
#define MCF_SEC_SICRH_CHA0DN (0x10000000)
#define MCF_SEC_SICRH_CHA0ERR (0x20000000)
#define MCF_SEC_SICRH_CHA1DN (0x40000000)
#define MCF_SEC_SICRH_CHA1ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SICRL */
#define MCF_SEC_SICRL_TEA (0x00000040)
#define MCF_SEC_SICRL_DEUDN (0x00000100)
#define MCF_SEC_SICRL_DEUERR (0x00000200)
#define MCF_SEC_SICRL_AESUDN (0x00001000)
#define MCF_SEC_SICRL_AESUERR (0x00002000)
#define MCF_SEC_SICRL_MDEUDN (0x00010000)
#define MCF_SEC_SICRL_MDEUERR (0x00020000)
#define MCF_SEC_SICRL_AFEUDN (0x00100000)
#define MCF_SEC_SICRL_AFEUERR (0x00200000)
#define MCF_SEC_SICRL_RNGDN (0x01000000)
#define MCF_SEC_SICRL_RNGERR (0x02000000)
/* Bit definitions and macros for MCF_SEC_SMCR */
#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4)
#define MCF_SEC_SMCR_SWR (0x01000000)
#define MCF_SEC_SMCR_CURR_CHAN_1 (0x00000010)
#define MCF_SEC_SMCR_CURR_CHAN_2 (0x00000020)
/* Bit definitions and macros for MCF_SEC_CCCRn */
#define MCF_SEC_CCCRn_RST (0x00000001)
#define MCF_SEC_CCCRn_CDIE (0x00000002)
#define MCF_SEC_CCCRn_NT (0x00000004)
#define MCF_SEC_CCCRn_NE (0x00000008)
#define MCF_SEC_CCCRn_WE (0x00000010)
#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8)
#define MCF_SEC_CCCRn_BURST_SIZE_2 (0x00000000)
#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x00000100)
#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x00000200)
#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x00000300)
#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x00000400)
#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x00000500)
#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x00000600)
#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x00000700)
/* Bit definitions and macros for MCF_SEC_CCPSRHn */
#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0)
/* Bit definitions and macros for MCF_SEC_CCPSRLn */
#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0)
#define MCF_SEC_CCPSRLn_EUERR (0x00000100)
#define MCF_SEC_CCPSRLn_SERR (0x00000200)
#define MCF_SEC_CCPSRLn_DERR (0x00000400)
#define MCF_SEC_CCPSRLn_PERR (0x00001000)
#define MCF_SEC_CCPSRLn_TEA (0x00002000)
#define MCF_SEC_CCPSRLn_SD (0x00010000)
#define MCF_SEC_CCPSRLn_PD (0x00020000)
#define MCF_SEC_CCPSRLn_SRD (0x00040000)
#define MCF_SEC_CCPSRLn_PRD (0x00080000)
#define MCF_SEC_CCPSRLn_SG (0x00100000)
#define MCF_SEC_CCPSRLn_PG (0x00200000)
#define MCF_SEC_CCPSRLn_SR (0x00400000)
#define MCF_SEC_CCPSRLn_PR (0x00800000)
#define MCF_SEC_CCPSRLn_MO (0x01000000)
#define MCF_SEC_CCPSRLn_MI (0x02000000)
#define MCF_SEC_CCPSRLn_STAT (0x04000000)
/* Bit definitions and macros for MCF_SEC_AFRCR */
#define MCF_SEC_AFRCR_SR (0x01000000)
#define MCF_SEC_AFRCR_MI (0x02000000)
#define MCF_SEC_AFRCR_RI (0x04000000)
/* Bit definitions and macros for MCF_SEC_AFSR */
#define MCF_SEC_AFSR_RD (0x01000000)
#define MCF_SEC_AFSR_ID (0x02000000)
#define MCF_SEC_AFSR_IE (0x04000000)
#define MCF_SEC_AFSR_OFE (0x08000000)
#define MCF_SEC_AFSR_IFW (0x10000000)
#define MCF_SEC_AFSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AFISR */
#define MCF_SEC_AFISR_DSE (0x00010000)
#define MCF_SEC_AFISR_KSE (0x00020000)
#define MCF_SEC_AFISR_CE (0x00040000)
#define MCF_SEC_AFISR_ERE (0x00080000)
#define MCF_SEC_AFISR_IE (0x00100000)
#define MCF_SEC_AFISR_OFU (0x02000000)
#define MCF_SEC_AFISR_IFO (0x04000000)
#define MCF_SEC_AFISR_IFE (0x10000000)
#define MCF_SEC_AFISR_OFE (0x20000000)
#define MCF_SEC_AFISR_AE (0x40000000)
#define MCF_SEC_AFISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AFIMR */
#define MCF_SEC_AFIMR_DSE (0x00010000)
#define MCF_SEC_AFIMR_KSE (0x00020000)
#define MCF_SEC_AFIMR_CE (0x00040000)
#define MCF_SEC_AFIMR_ERE (0x00080000)
#define MCF_SEC_AFIMR_IE (0x00100000)
#define MCF_SEC_AFIMR_OFU (0x02000000)
#define MCF_SEC_AFIMR_IFO (0x04000000)
#define MCF_SEC_AFIMR_IFE (0x10000000)
#define MCF_SEC_AFIMR_OFE (0x20000000)
#define MCF_SEC_AFIMR_AE (0x40000000)
#define MCF_SEC_AFIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DRCR */
#define MCF_SEC_DRCR_SR (0x01000000)
#define MCF_SEC_DRCR_MI (0x02000000)
#define MCF_SEC_DRCR_RI (0x04000000)
/* Bit definitions and macros for MCF_SEC_DSR */
#define MCF_SEC_DSR_RD (0x01000000)
#define MCF_SEC_DSR_ID (0x02000000)
#define MCF_SEC_DSR_IE (0x04000000)
#define MCF_SEC_DSR_OFR (0x08000000)
#define MCF_SEC_DSR_IFW (0x10000000)
#define MCF_SEC_DSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_DISR */
#define MCF_SEC_DISR_DSE (0x00010000)
#define MCF_SEC_DISR_KSE (0x00020000)
#define MCF_SEC_DISR_CE (0x00040000)
#define MCF_SEC_DISR_ERE (0x00080000)
#define MCF_SEC_DISR_IE (0x00100000)
#define MCF_SEC_DISR_KPE (0x00200000)
#define MCF_SEC_DISR_OFU (0x02000000)
#define MCF_SEC_DISR_IFO (0x04000000)
#define MCF_SEC_DISR_IFE (0x10000000)
#define MCF_SEC_DISR_OFE (0x20000000)
#define MCF_SEC_DISR_AE (0x40000000)
#define MCF_SEC_DISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DIMR */
#define MCF_SEC_DIMR_DSE (0x00010000)
#define MCF_SEC_DIMR_KSE (0x00020000)
#define MCF_SEC_DIMR_CE (0x00040000)
#define MCF_SEC_DIMR_ERE (0x00080000)
#define MCF_SEC_DIMR_IE (0x00100000)
#define MCF_SEC_DIMR_KPE (0x00200000)
#define MCF_SEC_DIMR_OFU (0x02000000)
#define MCF_SEC_DIMR_IFO (0x04000000)
#define MCF_SEC_DIMR_IFE (0x10000000)
#define MCF_SEC_DIMR_OFE (0x20000000)
#define MCF_SEC_DIMR_AE (0x40000000)
#define MCF_SEC_DIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDRCR */
#define MCF_SEC_MDRCR_SR (0x01000000)
#define MCF_SEC_MDRCR_MI (0x02000000)
#define MCF_SEC_MDRCR_RI (0x04000000)
/* Bit definitions and macros for MCF_SEC_MDSR */
#define MCF_SEC_MDSR_RD (0x01000000)
#define MCF_SEC_MDSR_ID (0x02000000)
#define MCF_SEC_MDSR_IE (0x04000000)
#define MCF_SEC_MDSR_IFW (0x10000000)
#define MCF_SEC_MDSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_MDISR */
#define MCF_SEC_MDISR_DSE (0x00010000)
#define MCF_SEC_MDISR_KSE (0x00020000)
#define MCF_SEC_MDISR_CE (0x00040000)
#define MCF_SEC_MDISR_ERE (0x00080000)
#define MCF_SEC_MDISR_IE (0x00100000)
#define MCF_SEC_MDISR_IFO (0x04000000)
#define MCF_SEC_MDISR_AE (0x40000000)
#define MCF_SEC_MDISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDIMR */
#define MCF_SEC_MDIMR_DSE (0x00010000)
#define MCF_SEC_MDIMR_KSE (0x00020000)
#define MCF_SEC_MDIMR_CE (0x00040000)
#define MCF_SEC_MDIMR_ERE (0x00080000)
#define MCF_SEC_MDIMR_IE (0x00100000)
#define MCF_SEC_MDIMR_IFO (0x04000000)
#define MCF_SEC_MDIMR_AE (0x40000000)
#define MCF_SEC_MDIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGRCR */
#define MCF_SEC_RNGRCR_SR (0x01000000)
#define MCF_SEC_RNGRCR_MI (0x02000000)
#define MCF_SEC_RNGRCR_RI (0x04000000)
/* Bit definitions and macros for MCF_SEC_RNGSR */
#define MCF_SEC_RNGSR_RD (0x01000000)
#define MCF_SEC_RNGSR_O (0x02000000)
#define MCF_SEC_RNGSR_IE (0x04000000)
#define MCF_SEC_RNGSR_OFR (0x08000000)
#define MCF_SEC_RNGSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_RNGISR */
#define MCF_SEC_RNGISR_IE (0x00100000)
#define MCF_SEC_RNGISR_OFU (0x02000000)
#define MCF_SEC_RNGISR_AE (0x40000000)
#define MCF_SEC_RNGISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGIMR */
#define MCF_SEC_RNGIMR_IE (0x00100000)
#define MCF_SEC_RNGIMR_OFU (0x02000000)
#define MCF_SEC_RNGIMR_AE (0x40000000)
#define MCF_SEC_RNGIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESRCR */
#define MCF_SEC_AESRCR_SR (0x01000000)
#define MCF_SEC_AESRCR_MI (0x02000000)
#define MCF_SEC_AESRCR_RI (0x04000000)
/* Bit definitions and macros for MCF_SEC_AESSR */
#define MCF_SEC_AESSR_RD (0x01000000)
#define MCF_SEC_AESSR_ID (0x02000000)
#define MCF_SEC_AESSR_IE (0x04000000)
#define MCF_SEC_AESSR_OFR (0x08000000)
#define MCF_SEC_AESSR_IFW (0x10000000)
#define MCF_SEC_AESSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AESISR */
#define MCF_SEC_AESISR_DSE (0x00010000)
#define MCF_SEC_AESISR_KSE (0x00020000)
#define MCF_SEC_AESISR_CE (0x00040000)
#define MCF_SEC_AESISR_ERE (0x00080000)
#define MCF_SEC_AESISR_IE (0x00100000)
#define MCF_SEC_AESISR_OFU (0x02000000)
#define MCF_SEC_AESISR_IFO (0x04000000)
#define MCF_SEC_AESISR_IFE (0x10000000)
#define MCF_SEC_AESISR_OFE (0x20000000)
#define MCF_SEC_AESISR_AE (0x40000000)
#define MCF_SEC_AESISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESIMR */
#define MCF_SEC_AESIMR_DSE (0x00010000)
#define MCF_SEC_AESIMR_KSE (0x00020000)
#define MCF_SEC_AESIMR_CE (0x00040000)
#define MCF_SEC_AESIMR_ERE (0x00080000)
#define MCF_SEC_AESIMR_IE (0x00100000)
#define MCF_SEC_AESIMR_OFU (0x02000000)
#define MCF_SEC_AESIMR_IFO (0x04000000)
#define MCF_SEC_AESIMR_IFE (0x10000000)
#define MCF_SEC_AESIMR_OFE (0x20000000)
#define MCF_SEC_AESIMR_AE (0x40000000)
#define MCF_SEC_AESIMR_ME (0x80000000)
#endif /* __MCF548X_SEC_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* DMA Serial Peripheral Interface (DSPI)
*/
#ifndef __MCF548X_SIU_H__
#define __MCF548X_SIU_H__
/*
* System Integration Unit (SIU)
*/
/* Register read/write macros */
#define MCF_SIU_SBCR (*(vuint32_t*)(&__MBAR[0x000010]))
#define MCF_SIU_SECSACR (*(vuint32_t*)(&__MBAR[0x000038]))
#define MCF_SIU_RSR (*(vuint32_t*)(&__MBAR[0x000044]))
#define MCF_SIU_JTAGID (*(vuint32_t*)(&__MBAR[0x000050]))
/* Bit definitions and macros for MCF_SIU_SBCR */
#define MCF_SIU_SBCR_PIN2DSPI (0x08000000)
#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
/* Bit definitions and macros for MCF_SIU_SECSACR */
#define MCF_SIU_SECSACR_SEQEN (0x00000001)
/* Bit definitions and macros for MCF_SIU_RSR */
#define MCF_SIU_RSR_RST (0x00000001)
#define MCF_SIU_RSR_RSTWD (0x00000002)
#define MCF_SIU_RSR_RSTJTG (0x00000008)
/* Bit definitions and macros for MCF_SIU_JTAGID */
#define MCF_SIU_JTAGID_REV (0xF0000000)
#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF)
#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D)
#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D)
#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D)
#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D)
#define MCF_SIU_JTAGID_MCF5481 (0x0801001D)
#define MCF_SIU_JTAGID_MCF5480 (0x0801101D)
#define MCF_SIU_JTAGID_MCF5475 (0x0801201D)
#define MCF_SIU_JTAGID_MCF5474 (0x0801301D)
#define MCF_SIU_JTAGID_MCF5473 (0x0801401D)
#define MCF_SIU_JTAGID_MCF5472 (0x0801501D)
#define MCF_SIU_JTAGID_MCF5471 (0x0801601D)
#define MCF_SIU_JTAGID_MCF5470 (0x0801701D)
#endif /* __MCF548X_SIU_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Slice Timers (SLT)
*/
#ifndef __MCF548X_SLT_H__
#define __MCF548X_SLT_H__
/*
* Slice Timers (SLT)
*/
/* Register read/write macros */
#define MCF_SLT_SLTCNT0 (*(vuint32_t*)(&__MBAR[0x000900]))
#define MCF_SLT_SCR0 (*(vuint32_t*)(&__MBAR[0x000904]))
#define MCF_SLT_SCNT0 (*(vuint32_t*)(&__MBAR[0x000908]))
#define MCF_SLT_SSR0 (*(vuint32_t*)(&__MBAR[0x00090C]))
#define MCF_SLT_SLTCNT1 (*(vuint32_t*)(&__MBAR[0x000910]))
#define MCF_SLT_SCR1 (*(vuint32_t*)(&__MBAR[0x000914]))
#define MCF_SLT_SCNT1 (*(vuint32_t*)(&__MBAR[0x000918]))
#define MCF_SLT_SSR1 (*(vuint32_t*)(&__MBAR[0x00091C]))
#define MCF_SLT_SLTCNT(x) (*(vuint32_t*)(&__MBAR[0x000900+((x)*0x010)]))
#define MCF_SLT_SCR(x) (*(vuint32_t*)(&__MBAR[0x000904+((x)*0x010)]))
#define MCF_SLT_SCNT(x) (*(vuint32_t*)(&__MBAR[0x000908+((x)*0x010)]))
#define MCF_SLT_SSR(x) (*(vuint32_t*)(&__MBAR[0x00090C+((x)*0x010)]))
/* Bit definitions and macros for MCF_SLT_SCR */
#define MCF_SLT_SCR_TEN (0x01000000)
#define MCF_SLT_SCR_IEN (0x02000000)
#define MCF_SLT_SCR_RUN (0x04000000)
/* Bit definitions and macros for MCF_SLT_SSR */
#define MCF_SLT_SSR_ST (0x01000000)
#define MCF_SLT_SSR_BE (0x02000000)
#ifndef __ASSEMBLY__
#define MCF_SLT_Address(x) ((struct mcf5xxx_slt*)(void*)(&__MBAR[0x000900+((x)*0x010)]))
struct mcf5xxx_slt {
vuint32_t STCNT; /* Slice Terminal Count */
vuint32_t SCR; /* Slice Timer Control Register */
vuint32_t SCNT; /* Slice Count Value */
vuint32_t SSR; /* Slice Timer Status Register */
};
#endif
#endif /* __MCF548X_SLT_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* 32KByte System SRAM (SRAM)
*/
#ifndef __MCF548X_SRAM_H__
#define __MCF548X_SRAM_H__
/*
* 32KByte System SRAM (SRAM)
*/
/* Register read/write macros */
#define MCF_SRAM_SSCR (*(vuint32_t*)(&__MBAR[0x01FFC0]))
#define MCF_SRAM_TCCR (*(vuint32_t*)(&__MBAR[0x01FFC4]))
#define MCF_SRAM_TCCRDR (*(vuint32_t*)(&__MBAR[0x01FFC8]))
#define MCF_SRAM_TCCRDW (*(vuint32_t*)(&__MBAR[0x01FFCC]))
#define MCF_SRAM_TCCRSEC (*(vuint32_t*)(&__MBAR[0x01FFD0]))
/* Bit definitions and macros for MCF_SRAM_SSCR */
#define MCF_SRAM_SSCR_INLV (0x00010000)
/* Bit definitions and macros for MCF_SRAM_TCCR */
#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0)
#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8)
#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16)
#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_SRAM_TCCRDR */
#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0)
#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8)
#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16)
#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_SRAM_TCCRDW */
#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0)
#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8)
#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16)
#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24)
/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0)
#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8)
#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16)
#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24)
#endif /* __MCF548X_SRAM_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Programmable Serial Controller (UART Compatible Definitions) (UART)
*/
#ifndef __MCF548X_UART_H__
#define __MCF548X_UART_H__
/*
* Programmable Serial Controller (UART Compatible Definitions) (UART)
*/
/* Register read/write macros */
#define MCF_UART_UMR0 (*(vuint8_t *)(&__MBAR[0x008600]))
#define MCF_UART_USR0 (*(vuint8_t *)(&__MBAR[0x008604]))
#define MCF_UART_UCSR0 (*(vuint8_t *)(&__MBAR[0x008604]))
#define MCF_UART_UCR0 (*(vuint8_t *)(&__MBAR[0x008608]))
#define MCF_UART_URB0 (*(vuint8_t *)(&__MBAR[0x00860C]))
#define MCF_UART_UTB0 (*(vuint8_t *)(&__MBAR[0x00860C]))
#define MCF_UART_UIPCR0 (*(vuint8_t *)(&__MBAR[0x008610]))
#define MCF_UART_UACR0 (*(vuint8_t *)(&__MBAR[0x008610]))
#define MCF_UART_UISR0 (*(vuint8_t *)(&__MBAR[0x008614]))
#define MCF_UART_UIMR0 (*(vuint8_t *)(&__MBAR[0x008614]))
#define MCF_UART_UBG10 (*(vuint8_t *)(&__MBAR[0x008618]))
#define MCF_UART_UBG20 (*(vuint8_t *)(&__MBAR[0x00861C]))
#define MCF_UART_UIP0 (*(vuint8_t *)(&__MBAR[0x008634]))
#define MCF_UART_UOP10 (*(vuint8_t *)(&__MBAR[0x008638]))
#define MCF_UART_UOP00 (*(vuint8_t *)(&__MBAR[0x00863C]))
#define MCF_UART_UMR1 (*(vuint8_t *)(&__MBAR[0x008700]))
#define MCF_UART_USR1 (*(vuint8_t *)(&__MBAR[0x008704]))
#define MCF_UART_UCSR1 (*(vuint8_t *)(&__MBAR[0x008704]))
#define MCF_UART_UCR1 (*(vuint8_t *)(&__MBAR[0x008708]))
#define MCF_UART_URB1 (*(vuint8_t *)(&__MBAR[0x00870C]))
#define MCF_UART_UTB1 (*(vuint8_t *)(&__MBAR[0x00870C]))
#define MCF_UART_UIPCR1 (*(vuint8_t *)(&__MBAR[0x008710]))
#define MCF_UART_UACR1 (*(vuint8_t *)(&__MBAR[0x008710]))
#define MCF_UART_UISR1 (*(vuint8_t *)(&__MBAR[0x008714]))
#define MCF_UART_UIMR1 (*(vuint8_t *)(&__MBAR[0x008714]))
#define MCF_UART_UBG11 (*(vuint8_t *)(&__MBAR[0x008718]))
#define MCF_UART_UBG21 (*(vuint8_t *)(&__MBAR[0x00871C]))
#define MCF_UART_UIP1 (*(vuint8_t *)(&__MBAR[0x008734]))
#define MCF_UART_UOP11 (*(vuint8_t *)(&__MBAR[0x008738]))
#define MCF_UART_UOP01 (*(vuint8_t *)(&__MBAR[0x00873C]))
#define MCF_UART_UMR2 (*(vuint8_t *)(&__MBAR[0x008800]))
#define MCF_UART_USR2 (*(vuint8_t *)(&__MBAR[0x008804]))
#define MCF_UART_UCSR2 (*(vuint8_t *)(&__MBAR[0x008804]))
#define MCF_UART_UCR2 (*(vuint8_t *)(&__MBAR[0x008808]))
#define MCF_UART_URB2 (*(vuint8_t *)(&__MBAR[0x00880C]))
#define MCF_UART_UTB2 (*(vuint8_t *)(&__MBAR[0x00880C]))
#define MCF_UART_UIPCR2 (*(vuint8_t *)(&__MBAR[0x008810]))
#define MCF_UART_UACR2 (*(vuint8_t *)(&__MBAR[0x008810]))
#define MCF_UART_UISR2 (*(vuint8_t *)(&__MBAR[0x008814]))
#define MCF_UART_UIMR2 (*(vuint8_t *)(&__MBAR[0x008814]))
#define MCF_UART_UBG12 (*(vuint8_t *)(&__MBAR[0x008818]))
#define MCF_UART_UBG22 (*(vuint8_t *)(&__MBAR[0x00881C]))
#define MCF_UART_UIP2 (*(vuint8_t *)(&__MBAR[0x008834]))
#define MCF_UART_UOP12 (*(vuint8_t *)(&__MBAR[0x008838]))
#define MCF_UART_UOP02 (*(vuint8_t *)(&__MBAR[0x00883C]))
#define MCF_UART_UMR3 (*(vuint8_t *)(&__MBAR[0x008900]))
#define MCF_UART_USR3 (*(vuint8_t *)(&__MBAR[0x008904]))
#define MCF_UART_UCSR3 (*(vuint8_t *)(&__MBAR[0x008904]))
#define MCF_UART_UCR3 (*(vuint8_t *)(&__MBAR[0x008908]))
#define MCF_UART_URB3 (*(vuint8_t *)(&__MBAR[0x00890C]))
#define MCF_UART_UTB3 (*(vuint8_t *)(&__MBAR[0x00890C]))
#define MCF_UART_UIPCR3 (*(vuint8_t *)(&__MBAR[0x008910]))
#define MCF_UART_UACR3 (*(vuint8_t *)(&__MBAR[0x008910]))
#define MCF_UART_UISR3 (*(vuint8_t *)(&__MBAR[0x008914]))
#define MCF_UART_UIMR3 (*(vuint8_t *)(&__MBAR[0x008914]))
#define MCF_UART_UBG13 (*(vuint8_t *)(&__MBAR[0x008918]))
#define MCF_UART_UBG23 (*(vuint8_t *)(&__MBAR[0x00891C]))
#define MCF_UART_UIP3 (*(vuint8_t *)(&__MBAR[0x008934]))
#define MCF_UART_UOP13 (*(vuint8_t *)(&__MBAR[0x008938]))
#define MCF_UART_UOP03 (*(vuint8_t *)(&__MBAR[0x00893C]))
#define MCF_UART_UMR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)]))
#define MCF_UART_USR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)]))
#define MCF_UART_UCSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)]))
#define MCF_UART_UCR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)]))
#define MCF_UART_URB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_UART_UTB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)]))
#define MCF_UART_UIPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)]))
#define MCF_UART_UACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)]))
#define MCF_UART_UISR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)]))
#define MCF_UART_UIMR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)]))
#define MCF_UART_UBG1(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)]))
#define MCF_UART_UBG2(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)]))
#define MCF_UART_UIP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)]))
#define MCF_UART_UOP1(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)]))
#define MCF_UART_UOP0(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)]))
/* Bit definitions and macros for MCF_UART_UMR */
#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
#define MCF_UART_UMR_PT (0x04)
#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
#define MCF_UART_UMR_ERR (0x20)
#define MCF_UART_UMR_RXIRQ (0x40)
#define MCF_UART_UMR_RXRTS (0x80)
#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
#define MCF_UART_UMR_TXCTS (0x10)
#define MCF_UART_UMR_TXRTS (0x20)
#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
#define MCF_UART_UMR_PM_NONE (0x10)
#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
#define MCF_UART_UMR_PM_FORCE_LO (0x08)
#define MCF_UART_UMR_PM_ODD (0x04)
#define MCF_UART_UMR_PM_EVEN (0x00)
#define MCF_UART_UMR_BC_5 (0x00)
#define MCF_UART_UMR_BC_6 (0x01)
#define MCF_UART_UMR_BC_7 (0x02)
#define MCF_UART_UMR_BC_8 (0x03)
#define MCF_UART_UMR_CM_NORMAL (0x00)
#define MCF_UART_UMR_CM_ECHO (0x40)
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
/* Bit definitions and macros for MCF_UART_USR */
#define MCF_UART_USR_RXRDY (0x01)
#define MCF_UART_USR_FFULL (0x02)
#define MCF_UART_USR_TXRDY (0x04)
#define MCF_UART_USR_TXEMP (0x08)
#define MCF_UART_USR_OE (0x10)
#define MCF_UART_USR_PE (0x20)
#define MCF_UART_USR_FE (0x40)
#define MCF_UART_USR_RB (0x80)
/* Bit definitions and macros for MCF_UART_UCSR */
#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
#define MCF_UART_UCSR_RCS_CTM (0xF0)
#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
#define MCF_UART_UCSR_TCS_CTM (0x0F)
/* Bit definitions and macros for MCF_UART_UCR */
#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
#define MCF_UART_UCR_NONE (0x00)
#define MCF_UART_UCR_STOP_BREAK (0x70)
#define MCF_UART_UCR_START_BREAK (0x60)
#define MCF_UART_UCR_BKCHGINT (0x50)
#define MCF_UART_UCR_RESET_ERROR (0x40)
#define MCF_UART_UCR_RESET_TX (0x30)
#define MCF_UART_UCR_RESET_RX (0x20)
#define MCF_UART_UCR_RESET_MR (0x10)
#define MCF_UART_UCR_TX_DISABLED (0x08)
#define MCF_UART_UCR_TX_ENABLED (0x04)
#define MCF_UART_UCR_RX_DISABLED (0x02)
#define MCF_UART_UCR_RX_ENABLED (0x01)
/* Bit definitions and macros for MCF_UART_UIPCR */
#define MCF_UART_UIPCR_CTS (0x01)
#define MCF_UART_UIPCR_COS (0x10)
/* Bit definitions and macros for MCF_UART_UACR */
#define MCF_UART_UACR_IEC (0x01)
/* Bit definitions and macros for MCF_UART_UISR */
#define MCF_UART_UISR_TXRDY (0x01)
#define MCF_UART_UISR_RXRDY_FU (0x02)
#define MCF_UART_UISR_DB (0x04)
#define MCF_UART_UISR_RXFTO (0x08)
#define MCF_UART_UISR_TXFIFO (0x10)
#define MCF_UART_UISR_RXFIFO (0x20)
#define MCF_UART_UISR_COS (0x80)
/* Bit definitions and macros for MCF_UART_UIMR */
#define MCF_UART_UIMR_TXRDY (0x01)
#define MCF_UART_UIMR_RXRDY_FU (0x02)
#define MCF_UART_UIMR_DB (0x04)
#define MCF_UART_UIMR_COS (0x80)
/* Bit definitions and macros for MCF_UART_UIP */
#define MCF_UART_UIP_CTS (0x01)
/* Bit definitions and macros for MCF_UART_UOP1 */
#define MCF_UART_UOP1_RTS (0x01)
/* Bit definitions and macros for MCF_UART_UOP0 */
#define MCF_UART_UOP0_RTS (0x01)
/* The UART registers for mem mapped access */
struct m5407uart
{
vuint8_t umr; vuint24_t reserved0;
vuint8_t usr; vuint24_t reserved1; /* ucsr */
vuint8_t ucr; vuint24_t reserved2;
vuint8_t urb; vuint24_t reserved3; /* utb */
vuint8_t uipcr; vuint24_t reserved4; /* uacr */
vuint8_t uisr; vuint24_t reserved5; /* uimr */
vuint8_t udu; vuint24_t reserved6;
vuint8_t ubg1; vuint24_t reserved7;
vuint8_t ubg2; vuint24_t reserved8;
const uint8_t uip; vuint24_t reserved9;
vuint8_t uop1; vuint24_t reserved10;
vuint8_t uop0; vuint24_t reserved11;
} __attribute((packed));
#define MCF_UART(x) (*(struct m5407uart *)(&__MBAR[0x008600+((x)*0x100)]))
#endif /* __MCF548X_UART_H__ */

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arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h
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@ -1,509 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* Universal Serial Bus (USB)
*
* @note According to FreeScale errata sheet, the USB controller
* isn't really usable on MCF54xx V4E CPUs.
* Check V4M cores or wait for errata fixed
* Last update: 25.02.2008 10:55:00
*/
#ifndef __MCF548X_USB_H__
#define __MCF548X_USB_H__
/*
* Universal Serial Bus (USB)
*/
/* Register read/write macros */
#define MCF_USB_USBAISR (*(vuint8_t *)(&__MBAR[0x00B000]))
#define MCF_USB_USBAIMR (*(vuint8_t *)(&__MBAR[0x00B001]))
#define MCF_USB_EPINFO (*(vuint8_t *)(&__MBAR[0x00B003]))
#define MCF_USB_CFGR (*(vuint8_t *)(&__MBAR[0x00B004]))
#define MCF_USB_CFGAR (*(vuint8_t *)(&__MBAR[0x00B005]))
#define MCF_USB_SPEEDR (*(vuint8_t *)(&__MBAR[0x00B006]))
#define MCF_USB_FRMNUMR (*(vuint16_t*)(&__MBAR[0x00B00E]))
#define MCF_USB_EPTNR (*(vuint16_t*)(&__MBAR[0x00B010]))
#define MCF_USB_IFUR (*(vuint16_t*)(&__MBAR[0x00B014]))
#define MCF_USB_IFR0 (*(vuint16_t*)(&__MBAR[0x00B040]))
#define MCF_USB_IFR1 (*(vuint16_t*)(&__MBAR[0x00B042]))
#define MCF_USB_IFR2 (*(vuint16_t*)(&__MBAR[0x00B044]))
#define MCF_USB_IFR3 (*(vuint16_t*)(&__MBAR[0x00B046]))
#define MCF_USB_IFR4 (*(vuint16_t*)(&__MBAR[0x00B048]))
#define MCF_USB_IFR5 (*(vuint16_t*)(&__MBAR[0x00B04A]))
#define MCF_USB_IFR6 (*(vuint16_t*)(&__MBAR[0x00B04C]))
#define MCF_USB_IFR7 (*(vuint16_t*)(&__MBAR[0x00B04E]))
#define MCF_USB_IFR8 (*(vuint16_t*)(&__MBAR[0x00B050]))
#define MCF_USB_IFR9 (*(vuint16_t*)(&__MBAR[0x00B052]))
#define MCF_USB_IFR10 (*(vuint16_t*)(&__MBAR[0x00B054]))
#define MCF_USB_IFR11 (*(vuint16_t*)(&__MBAR[0x00B056]))
#define MCF_USB_IFR12 (*(vuint16_t*)(&__MBAR[0x00B058]))
#define MCF_USB_IFR13 (*(vuint16_t*)(&__MBAR[0x00B05A]))
#define MCF_USB_IFR14 (*(vuint16_t*)(&__MBAR[0x00B05C]))
#define MCF_USB_IFR15 (*(vuint16_t*)(&__MBAR[0x00B05E]))
#define MCF_USB_IFR16 (*(vuint16_t*)(&__MBAR[0x00B060]))
#define MCF_USB_IFR17 (*(vuint16_t*)(&__MBAR[0x00B062]))
#define MCF_USB_IFR18 (*(vuint16_t*)(&__MBAR[0x00B064]))
#define MCF_USB_IFR19 (*(vuint16_t*)(&__MBAR[0x00B066]))
#define MCF_USB_IFR20 (*(vuint16_t*)(&__MBAR[0x00B068]))
#define MCF_USB_IFR21 (*(vuint16_t*)(&__MBAR[0x00B06A]))
#define MCF_USB_IFR22 (*(vuint16_t*)(&__MBAR[0x00B06C]))
#define MCF_USB_IFR23 (*(vuint16_t*)(&__MBAR[0x00B06E]))
#define MCF_USB_IFR24 (*(vuint16_t*)(&__MBAR[0x00B070]))
#define MCF_USB_IFR25 (*(vuint16_t*)(&__MBAR[0x00B072]))
#define MCF_USB_IFR26 (*(vuint16_t*)(&__MBAR[0x00B074]))
#define MCF_USB_IFR27 (*(vuint16_t*)(&__MBAR[0x00B076]))
#define MCF_USB_IFR28 (*(vuint16_t*)(&__MBAR[0x00B078]))
#define MCF_USB_IFR29 (*(vuint16_t*)(&__MBAR[0x00B07A]))
#define MCF_USB_IFR30 (*(vuint16_t*)(&__MBAR[0x00B07C]))
#define MCF_USB_IFR31 (*(vuint16_t*)(&__MBAR[0x00B07E]))
#define MCF_USB_IFRn(x) (*(vuint16_t*)(&__MBAR[0x00B040+((x)*0x002)]))
#define MCF_USB_PPCNT (*(vuint16_t*)(&__MBAR[0x00B080]))
#define MCF_USB_DPCNT (*(vuint16_t*)(&__MBAR[0x00B082]))
#define MCF_USB_CRCECNT (*(vuint16_t*)(&__MBAR[0x00B084]))
#define MCF_USB_BSECNT (*(vuint16_t*)(&__MBAR[0x00B086]))
#define MCF_USB_PIDECNT (*(vuint16_t*)(&__MBAR[0x00B088]))
#define MCF_USB_FRMECNT (*(vuint16_t*)(&__MBAR[0x00B08A]))
#define MCF_USB_TXPCNT (*(vuint16_t*)(&__MBAR[0x00B08C]))
#define MCF_USB_CNTOVR (*(vuint8_t *)(&__MBAR[0x00B08E]))
#define MCF_USB_EP0ACR (*(vuint8_t *)(&__MBAR[0x00B101]))
#define MCF_USB_EP0MPSR (*(vuint16_t*)(&__MBAR[0x00B102]))
#define MCF_USB_EP0IFR (*(vuint8_t *)(&__MBAR[0x00B104]))
#define MCF_USB_EP0SR (*(vuint8_t *)(&__MBAR[0x00B105]))
#define MCF_USB_BMRTR (*(vuint8_t *)(&__MBAR[0x00B106]))
#define MCF_USB_BRTR (*(vuint8_t *)(&__MBAR[0x00B107]))
#define MCF_USB_WVALUER (*(vuint16_t*)(&__MBAR[0x00B108]))
#define MCF_USB_WINDEXR (*(vuint16_t*)(&__MBAR[0x00B10A]))
#define MCF_USB_WLENGTH (*(vuint16_t*)(&__MBAR[0x00B10C]))
#define MCF_USB_EP1OUTACR (*(vuint8_t *)(&__MBAR[0x00B131]))
#define MCF_USB_EP2OUTACR (*(vuint8_t *)(&__MBAR[0x00B161]))
#define MCF_USB_EP3OUTACR (*(vuint8_t *)(&__MBAR[0x00B191]))
#define MCF_USB_EP4OUTACR (*(vuint8_t *)(&__MBAR[0x00B1C1]))
#define MCF_USB_EP5OUTACR (*(vuint8_t *)(&__MBAR[0x00B1F1]))
#define MCF_USB_EP6OUTACR (*(vuint8_t *)(&__MBAR[0x00B221]))
#define MCF_USB_EPnOUTACR(x) (*(vuint8_t *)(&__MBAR[0x00B131+((x)*0x030)]))
#define MCF_USB_EP1OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B132]))
#define MCF_USB_EP2OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B162]))
#define MCF_USB_EP3OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B192]))
#define MCF_USB_EP4OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1C2]))
#define MCF_USB_EP5OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1F2]))
#define MCF_USB_EP6OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B222]))
#define MCF_USB_EPnOUTMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B132+((x)*0x030)]))
#define MCF_USB_EP1OUTIFR (*(vuint8_t *)(&__MBAR[0x00B134]))
#define MCF_USB_EP2OUTIFR (*(vuint8_t *)(&__MBAR[0x00B164]))
#define MCF_USB_EP3OUTIFR (*(vuint8_t *)(&__MBAR[0x00B194]))
#define MCF_USB_EP4OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1C4]))
#define MCF_USB_EP5OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1F4]))
#define MCF_USB_EP6OUTIFR (*(vuint8_t *)(&__MBAR[0x00B224]))
#define MCF_USB_EPnOUTIFR(x) (*(vuint8_t *)(&__MBAR[0x00B134+((x)*0x030)]))
#define MCF_USB_EP1OUTSR (*(vuint8_t *)(&__MBAR[0x00B135]))
#define MCF_USB_EP2OUTSR (*(vuint8_t *)(&__MBAR[0x00B165]))
#define MCF_USB_EP3OUTSR (*(vuint8_t *)(&__MBAR[0x00B195]))
#define MCF_USB_EP4OUTSR (*(vuint8_t *)(&__MBAR[0x00B1C5]))
#define MCF_USB_EP5OUTSR (*(vuint8_t *)(&__MBAR[0x00B1F5]))
#define MCF_USB_EP6OUTSR (*(vuint8_t *)(&__MBAR[0x00B225]))
#define MCF_USB_EPnOUTSR(x) (*(vuint8_t *)(&__MBAR[0x00B135+((x)*0x030)]))
#define MCF_USB_EP1OUTSFR (*(vuint16_t*)(&__MBAR[0x00B13E]))
#define MCF_USB_EP2OUTSFR (*(vuint16_t*)(&__MBAR[0x00B16E]))
#define MCF_USB_EP3OUTSFR (*(vuint16_t*)(&__MBAR[0x00B19E]))
#define MCF_USB_EP4OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1CE]))
#define MCF_USB_EP5OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1FE]))
#define MCF_USB_EP6OUTSFR (*(vuint16_t*)(&__MBAR[0x00B22E]))
#define MCF_USB_EPnOUTSFR(x) (*(vuint16_t*)(&__MBAR[0x00B13E+((x)*0x030)]))
#define MCF_USB_EP1INACR (*(vuint8_t *)(&__MBAR[0x00B149]))
#define MCF_USB_EP2INACR (*(vuint8_t *)(&__MBAR[0x00B179]))
#define MCF_USB_EP3INACR (*(vuint8_t *)(&__MBAR[0x00B1A9]))
#define MCF_USB_EP4INACR (*(vuint8_t *)(&__MBAR[0x00B1D9]))
#define MCF_USB_EP5INACR (*(vuint8_t *)(&__MBAR[0x00B209]))
#define MCF_USB_EP6INACR (*(vuint8_t *)(&__MBAR[0x00B239]))
#define MCF_USB_EPnINACR(x) (*(vuint8_t *)(&__MBAR[0x00B149+((x)*0x030)]))
#define MCF_USB_EP1INMPSR (*(vuint16_t*)(&__MBAR[0x00B14A]))
#define MCF_USB_EP2INMPSR (*(vuint16_t*)(&__MBAR[0x00B17A]))
#define MCF_USB_EP3INMPSR (*(vuint16_t*)(&__MBAR[0x00B1AA]))
#define MCF_USB_EP4INMPSR (*(vuint16_t*)(&__MBAR[0x00B1DA]))
#define MCF_USB_EP5INMPSR (*(vuint16_t*)(&__MBAR[0x00B20A]))
#define MCF_USB_EP6INMPSR (*(vuint16_t*)(&__MBAR[0x00B23A]))
#define MCF_USB_EPnINMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B14A+((x)*0x030)]))
#define MCF_USB_EP1INIFR (*(vuint8_t *)(&__MBAR[0x00B14C]))
#define MCF_USB_EP2INIFR (*(vuint8_t *)(&__MBAR[0x00B17C]))
#define MCF_USB_EP3INIFR (*(vuint8_t *)(&__MBAR[0x00B1AC]))
#define MCF_USB_EP4INIFR (*(vuint8_t *)(&__MBAR[0x00B1DC]))
#define MCF_USB_EP5INIFR (*(vuint8_t *)(&__MBAR[0x00B20C]))
#define MCF_USB_EP6INIFR (*(vuint8_t *)(&__MBAR[0x00B23C]))
#define MCF_USB_EPnINIFR(x) (*(vuint8_t *)(&__MBAR[0x00B14C+((x)*0x030)]))
#define MCF_USB_EP1INSR (*(vuint8_t *)(&__MBAR[0x00B14D]))
#define MCF_USB_EP2INSR (*(vuint8_t *)(&__MBAR[0x00B17D]))
#define MCF_USB_EP3INSR (*(vuint8_t *)(&__MBAR[0x00B1AD]))
#define MCF_USB_EP4INSR (*(vuint8_t *)(&__MBAR[0x00B1DD]))
#define MCF_USB_EP5INSR (*(vuint8_t *)(&__MBAR[0x00B20D]))
#define MCF_USB_EP6INSR (*(vuint8_t *)(&__MBAR[0x00B23D]))
#define MCF_USB_EPnINSR(x) (*(vuint8_t *)(&__MBAR[0x00B14D+((x)*0x030)]))
#define MCF_USB_EP1INSFR (*(vuint16_t*)(&__MBAR[0x00B15A]))
#define MCF_USB_EP2INSFR (*(vuint16_t*)(&__MBAR[0x00B18A]))
#define MCF_USB_EP3INSFR (*(vuint16_t*)(&__MBAR[0x00B1BA]))
#define MCF_USB_EP4INSFR (*(vuint16_t*)(&__MBAR[0x00B1EA]))
#define MCF_USB_EP5INSFR (*(vuint16_t*)(&__MBAR[0x00B21A]))
#define MCF_USB_EP6INSFR (*(vuint16_t*)(&__MBAR[0x00B24A]))
#define MCF_USB_EPnINSFR(x) (*(vuint16_t*)(&__MBAR[0x00B15A+((x)*0x030)]))
#define MCF_USB_USBSR (*(vuint32_t*)(&__MBAR[0x00B400]))
#define MCF_USB_USBCR (*(vuint32_t*)(&__MBAR[0x00B404]))
#define MCF_USB_DRAMCR (*(vuint32_t*)(&__MBAR[0x00B408]))
#define MCF_USB_DRAMDR (*(vuint32_t*)(&__MBAR[0x00B40C]))
#define MCF_USB_USBISR (*(vuint32_t*)(&__MBAR[0x00B410]))
#define MCF_USB_USBIMR (*(vuint32_t*)(&__MBAR[0x00B414]))
#define MCF_USB_EP0STAT (*(vuint32_t*)(&__MBAR[0x00B440]))
#define MCF_USB_EP1STAT (*(vuint32_t*)(&__MBAR[0x00B470]))
#define MCF_USB_EP2STAT (*(vuint32_t*)(&__MBAR[0x00B4A0]))
#define MCF_USB_EP3STAT (*(vuint32_t*)(&__MBAR[0x00B4D0]))
#define MCF_USB_EP4STAT (*(vuint32_t*)(&__MBAR[0x00B500]))
#define MCF_USB_EP5STAT (*(vuint32_t*)(&__MBAR[0x00B530]))
#define MCF_USB_EP6STAT (*(vuint32_t*)(&__MBAR[0x00B560]))
#define MCF_USB_EPnSTAT(x) (*(vuint32_t*)(&__MBAR[0x00B440+((x)*0x030)]))
#define MCF_USB_EP0ISR (*(vuint32_t*)(&__MBAR[0x00B444]))
#define MCF_USB_EP1ISR (*(vuint32_t*)(&__MBAR[0x00B474]))
#define MCF_USB_EP2ISR (*(vuint32_t*)(&__MBAR[0x00B4A4]))
#define MCF_USB_EP3ISR (*(vuint32_t*)(&__MBAR[0x00B4D4]))
#define MCF_USB_EP4ISR (*(vuint32_t*)(&__MBAR[0x00B504]))
#define MCF_USB_EP5ISR (*(vuint32_t*)(&__MBAR[0x00B534]))
#define MCF_USB_EP6ISR (*(vuint32_t*)(&__MBAR[0x00B564]))
#define MCF_USB_EPnISR(x) (*(vuint32_t*)(&__MBAR[0x00B444+((x)*0x030)]))
#define MCF_USB_EP0IMR (*(vuint32_t*)(&__MBAR[0x00B448]))
#define MCF_USB_EP1IMR (*(vuint32_t*)(&__MBAR[0x00B478]))
#define MCF_USB_EP2IMR (*(vuint32_t*)(&__MBAR[0x00B4A8]))
#define MCF_USB_EP3IMR (*(vuint32_t*)(&__MBAR[0x00B4D8]))
#define MCF_USB_EP4IMR (*(vuint32_t*)(&__MBAR[0x00B508]))
#define MCF_USB_EP5IMR (*(vuint32_t*)(&__MBAR[0x00B538]))
#define MCF_USB_EP6IMR (*(vuint32_t*)(&__MBAR[0x00B568]))
#define MCF_USB_EPnIMR(x) (*(vuint32_t*)(&__MBAR[0x00B448+((x)*0x030)]))
#define MCF_USB_EP0FRCFGR (*(vuint32_t*)(&__MBAR[0x00B44C]))
#define MCF_USB_EP1FRCFGR (*(vuint32_t*)(&__MBAR[0x00B47C]))
#define MCF_USB_EP2FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4AC]))
#define MCF_USB_EP3FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4DC]))
#define MCF_USB_EP4FRCFGR (*(vuint32_t*)(&__MBAR[0x00B50C]))
#define MCF_USB_EP5FRCFGR (*(vuint32_t*)(&__MBAR[0x00B53C]))
#define MCF_USB_EP6FRCFGR (*(vuint32_t*)(&__MBAR[0x00B56C]))
#define MCF_USB_EPnFRCFGR(x) (*(vuint32_t*)(&__MBAR[0x00B44C+((x)*0x030)]))
#define MCF_USB_EP0FDR (*(vuint32_t*)(&__MBAR[0x00B450]))
#define MCF_USB_EP1FDR (*(vuint32_t*)(&__MBAR[0x00B480]))
#define MCF_USB_EP2FDR (*(vuint32_t*)(&__MBAR[0x00B4B0]))
#define MCF_USB_EP3FDR (*(vuint32_t*)(&__MBAR[0x00B4E0]))
#define MCF_USB_EP4FDR (*(vuint32_t*)(&__MBAR[0x00B510]))
#define MCF_USB_EP5FDR (*(vuint32_t*)(&__MBAR[0x00B540]))
#define MCF_USB_EP6FDR (*(vuint32_t*)(&__MBAR[0x00B570]))
#define MCF_USB_EPnFDR(x) (*(vuint32_t*)(&__MBAR[0x00B450+((x)*0x030)]))
#define MCF_USB_EP0FSR (*(vuint32_t*)(&__MBAR[0x00B454]))
#define MCF_USB_EP1FSR (*(vuint32_t*)(&__MBAR[0x00B484]))
#define MCF_USB_EP2FSR (*(vuint32_t*)(&__MBAR[0x00B4B4]))
#define MCF_USB_EP3FSR (*(vuint32_t*)(&__MBAR[0x00B4E4]))
#define MCF_USB_EP4FSR (*(vuint32_t*)(&__MBAR[0x00B514]))
#define MCF_USB_EP5FSR (*(vuint32_t*)(&__MBAR[0x00B544]))
#define MCF_USB_EP6FSR (*(vuint32_t*)(&__MBAR[0x00B574]))
#define MCF_USB_EPnFSR(x) (*(vuint32_t*)(&__MBAR[0x00B454+((x)*0x030)]))
#define MCF_USB_EP0FCR (*(vuint32_t*)(&__MBAR[0x00B458]))
#define MCF_USB_EP1FCR (*(vuint32_t*)(&__MBAR[0x00B488]))
#define MCF_USB_EP2FCR (*(vuint32_t*)(&__MBAR[0x00B4B8]))
#define MCF_USB_EP3FCR (*(vuint32_t*)(&__MBAR[0x00B4E8]))
#define MCF_USB_EP4FCR (*(vuint32_t*)(&__MBAR[0x00B518]))
#define MCF_USB_EP5FCR (*(vuint32_t*)(&__MBAR[0x00B548]))
#define MCF_USB_EP6FCR (*(vuint32_t*)(&__MBAR[0x00B578]))
#define MCF_USB_EPnFCR(x) (*(vuint32_t*)(&__MBAR[0x00B458+((x)*0x030)]))
#define MCF_USB_EP0FAR (*(vuint32_t*)(&__MBAR[0x00B45C]))
#define MCF_USB_EP1FAR (*(vuint32_t*)(&__MBAR[0x00B48C]))
#define MCF_USB_EP2FAR (*(vuint32_t*)(&__MBAR[0x00B4BC]))
#define MCF_USB_EP3FAR (*(vuint32_t*)(&__MBAR[0x00B4EC]))
#define MCF_USB_EP4FAR (*(vuint32_t*)(&__MBAR[0x00B51C]))
#define MCF_USB_EP5FAR (*(vuint32_t*)(&__MBAR[0x00B54C]))
#define MCF_USB_EP6FAR (*(vuint32_t*)(&__MBAR[0x00B57C]))
#define MCF_USB_EPnFAR(x) (*(vuint32_t*)(&__MBAR[0x00B45C+((x)*0x030)]))
#define MCF_USB_EP0FRP (*(vuint32_t*)(&__MBAR[0x00B460]))
#define MCF_USB_EP1FRP (*(vuint32_t*)(&__MBAR[0x00B490]))
#define MCF_USB_EP2FRP (*(vuint32_t*)(&__MBAR[0x00B4C0]))
#define MCF_USB_EP3FRP (*(vuint32_t*)(&__MBAR[0x00B4F0]))
#define MCF_USB_EP4FRP (*(vuint32_t*)(&__MBAR[0x00B520]))
#define MCF_USB_EP5FRP (*(vuint32_t*)(&__MBAR[0x00B550]))
#define MCF_USB_EP6FRP (*(vuint32_t*)(&__MBAR[0x00B580]))
#define MCF_USB_EPnFRP(x) (*(vuint32_t*)(&__MBAR[0x00B460+((x)*0x030)]))
#define MCF_USB_EP0FWP (*(vuint32_t*)(&__MBAR[0x00B464]))
#define MCF_USB_EP1FWP (*(vuint32_t*)(&__MBAR[0x00B494]))
#define MCF_USB_EP2FWP (*(vuint32_t*)(&__MBAR[0x00B4C4]))
#define MCF_USB_EP3FWP (*(vuint32_t*)(&__MBAR[0x00B4F4]))
#define MCF_USB_EP4FWP (*(vuint32_t*)(&__MBAR[0x00B524]))
#define MCF_USB_EP5FWP (*(vuint32_t*)(&__MBAR[0x00B554]))
#define MCF_USB_EP6FWP (*(vuint32_t*)(&__MBAR[0x00B584]))
#define MCF_USB_EPnFWP(x) (*(vuint32_t*)(&__MBAR[0x00B464+((x)*0x030)]))
#define MCF_USB_EP0LRFP (*(vuint32_t*)(&__MBAR[0x00B468]))
#define MCF_USB_EP1LRFP (*(vuint32_t*)(&__MBAR[0x00B498]))
#define MCF_USB_EP2LRFP (*(vuint32_t*)(&__MBAR[0x00B4C8]))
#define MCF_USB_EP3LRFP (*(vuint32_t*)(&__MBAR[0x00B4F8]))
#define MCF_USB_EP4LRFP (*(vuint32_t*)(&__MBAR[0x00B528]))
#define MCF_USB_EP5LRFP (*(vuint32_t*)(&__MBAR[0x00B558]))
#define MCF_USB_EP6LRFP (*(vuint32_t*)(&__MBAR[0x00B588]))
#define MCF_USB_EPnLRFP(x) (*(vuint32_t*)(&__MBAR[0x00B468+((x)*0x030)]))
#define MCF_USB_EP0LWFP (*(vuint32_t*)(&__MBAR[0x00B46C]))
#define MCF_USB_EP1LWFP (*(vuint32_t*)(&__MBAR[0x00B49C]))
#define MCF_USB_EP2LWFP (*(vuint32_t*)(&__MBAR[0x00B4CC]))
#define MCF_USB_EP3LWFP (*(vuint32_t*)(&__MBAR[0x00B4FC]))
#define MCF_USB_EP4LWFP (*(vuint32_t*)(&__MBAR[0x00B52C]))
#define MCF_USB_EP5LWFP (*(vuint32_t*)(&__MBAR[0x00B55C]))
#define MCF_USB_EP6LWFP (*(vuint32_t*)(&__MBAR[0x00B58C]))
#define MCF_USB_EPnLWFP(x) (*(vuint32_t*)(&__MBAR[0x00B46C+((x)*0x030)]))
/* Bit definitions and macros for MCF_USB_USBAISR */
#define MCF_USB_USBAISR_SETUP (0x01)
#define MCF_USB_USBAISR_IN (0x02)
#define MCF_USB_USBAISR_OUT (0x04)
#define MCF_USB_USBAISR_EPHALT (0x08)
#define MCF_USB_USBAISR_TRANSERR (0x10)
#define MCF_USB_USBAISR_ACK (0x20)
#define MCF_USB_USBAISR_CTROVFL (0x40)
#define MCF_USB_USBAISR_EPSTALL (0x80)
/* Bit definitions and macros for MCF_USB_USBAIMR */
#define MCF_USB_USBAIMR_SETUPEN (0x01)
#define MCF_USB_USBAIMR_INEN (0x02)
#define MCF_USB_USBAIMR_OUTEN (0x04)
#define MCF_USB_USBAIMR_EPHALTEN (0x08)
#define MCF_USB_USBAIMR_TRANSERREN (0x10)
#define MCF_USB_USBAIMR_ACKEN (0x20)
#define MCF_USB_USBAIMR_CTROVFLEN (0x40)
#define MCF_USB_USBAIMR_EPSTALLEN (0x80)
/* Bit definitions and macros for MCF_USB_EPINFO */
#define MCF_USB_EPINFO_EPDIR (0x01)
#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1)
/* Bit definitions and macros for MCF_USB_CFGAR */
#define MCF_USB_CFGAR_RESERVED (0xA0)
#define MCF_USB_CFGAR_RMTWKEUP (0xE0)
/* Bit definitions and macros for MCF_USB_SPEEDR */
#define MCF_USB_SPEEDR_HS (0x01)
#define MCF_USB_SPEEDR_FS (0x02)
/* Bit definitions and macros for MCF_USB_FRMNUMR */
#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0)
/* Bit definitions and macros for MCF_USB_EPTNR */
#define MCF_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0)
#define MCF_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2)
#define MCF_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4)
#define MCF_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6)
#define MCF_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8)
#define MCF_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10)
#define MCF_USB_EPTNR_EPnT1 (0)
#define MCF_USB_EPTNR_EPnT2 (1)
#define MCF_USB_EPTNR_EPnT3 (2)
/* Bit definitions and macros for MCF_USB_IFUR */
#define MCF_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0)
#define MCF_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8)
/* Bit definitions and macros for MCF_USB_IFRn */
#define MCF_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0)
#define MCF_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8)
/* Bit definitions and macros for MCF_USB_CNTOVR */
#define MCF_USB_CNTOVR_PPCNT (0x01)
#define MCF_USB_CNTOVR_DPCNT (0x02)
#define MCF_USB_CNTOVR_CRCECNT (0x04)
#define MCF_USB_CNTOVR_BSECNT (0x08)
#define MCF_USB_CNTOVR_PIDECNT (0x10)
#define MCF_USB_CNTOVR_FRMECNT (0x20)
#define MCF_USB_CNTOVR_TXPCNT (0x40)
/* Bit definitions and macros for MCF_USB_EP0ACR */
#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0)
#define MCF_USB_EP0ACR_TTYPE_CTRL (0)
#define MCF_USB_EP0ACR_TTYPE_ISOC (1)
#define MCF_USB_EP0ACR_TTYPE_BULK (2)
#define MCF_USB_EP0ACR_TTYPE_INT (3)
/* Bit definitions and macros for MCF_USB_EP0MPSR */
#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0)
#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11)
/* Bit definitions and macros for MCF_USB_EP0SR */
#define MCF_USB_EP0SR_HALT (0x01)
#define MCF_USB_EP0SR_ACTIVE (0x02)
#define MCF_USB_EP0SR_PSTALL (0x04)
#define MCF_USB_EP0SR_CCOMP (0x08)
#define MCF_USB_EP0SR_TXZERO (0x20)
#define MCF_USB_EP0SR_INT (0x80)
/* Bit definitions and macros for MCF_USB_BMRTR */
#define MCF_USB_BMRTR_DIR (0x80)
#define MCF_USB_BMRTR_TYPE_STANDARD (0x00)
#define MCF_USB_BMRTR_TYPE_CLASS (0x20)
#define MCF_USB_BMRTR_TYPE_VENDOR (0x40)
#define MCF_USB_BMRTR_REC_DEVICE (0x00)
#define MCF_USB_BMRTR_REC_INTERFACE (0x01)
#define MCF_USB_BMRTR_REC_ENDPOINT (0x02)
#define MCF_USB_BMRTR_REC_OTHER (0x03)
/* Bit definitions and macros for MCF_USB_EPnOUTACR */
#define MCF_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_USB_EPnOUTMPSR */
#define MCF_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0)
#define MCF_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11)
/* Bit definitions and macros for MCF_USB_EPnOUTSR */
#define MCF_USB_EPnOUTSR_HALT (0x01)
#define MCF_USB_EPnOUTSR_ACTIVE (0x02)
#define MCF_USB_EPnOUTSR_PSTALL (0x04)
#define MCF_USB_EPnOUTSR_CCOMP (0x08)
#define MCF_USB_EPnOUTSR_TXZERO (0x20)
#define MCF_USB_EPnOUTSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPnOUTSFR */
#define MCF_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0)
/* Bit definitions and macros for MCF_USB_EPnINACR */
#define MCF_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_USB_EPnINMPSR */
#define MCF_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0)
#define MCF_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11)
/* Bit definitions and macros for MCF_USB_EPnINSR */
#define MCF_USB_EPnINSR_HALT (0x01)
#define MCF_USB_EPnINSR_ACTIVE (0x02)
#define MCF_USB_EPnINSR_PSTALL (0x04)
#define MCF_USB_EPnINSR_CCOMP (0x08)
#define MCF_USB_EPnINSR_TXZERO (0x20)
#define MCF_USB_EPnINSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPnINSFR */
#define MCF_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0)
/* Bit definitions and macros for MCF_USB_USBSR */
#define MCF_USB_USBSR_SUSP (0x00000080)
#define MCF_USB_USBSR_ISOERREP (0x0000000F)
/* Bit definitions and macros for MCF_USB_USBCR */
#define MCF_USB_USBCR_RESUME (0x00000001)
#define MCF_USB_USBCR_APPLOCK (0x00000002)
#define MCF_USB_USBCR_RST (0x00000004)
#define MCF_USB_USBCR_RAMEN (0x00000008)
#define MCF_USB_USBCR_RAMSPLIT (0x00000020)
/* Bit definitions and macros for MCF_USB_DRAMCR */
#define MCF_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0)
#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16)
#define MCF_USB_DRAMCR_BSY (0x40000000)
#define MCF_USB_DRAMCR_START (0x80000000)
/* Bit definitions and macros for MCF_USB_DRAMDR */
#define MCF_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0)
/* Bit definitions and macros for MCF_USB_USBISR */
#define MCF_USB_USBISR_ISOERR (0x00000001)
#define MCF_USB_USBISR_FTUNLCK (0x00000002)
#define MCF_USB_USBISR_SUSP (0x00000004)
#define MCF_USB_USBISR_RES (0x00000008)
#define MCF_USB_USBISR_UPDSOF (0x00000010)
#define MCF_USB_USBISR_RSTSTOP (0x00000020)
#define MCF_USB_USBISR_SOF (0x00000040)
#define MCF_USB_USBISR_MSOF (0x00000080)
/* Bit definitions and macros for MCF_USB_USBIMR */
#define MCF_USB_USBIMR_ISOERR (0x00000001)
#define MCF_USB_USBIMR_FTUNLCK (0x00000002)
#define MCF_USB_USBIMR_SUSP (0x00000004)
#define MCF_USB_USBIMR_RES (0x00000008)
#define MCF_USB_USBIMR_UPDSOF (0x00000010)
#define MCF_USB_USBIMR_RSTSTOP (0x00000020)
#define MCF_USB_USBIMR_SOF (0x00000040)
#define MCF_USB_USBIMR_MSOF (0x00000080)
/* Bit definitions and macros for MCF_USB_EPnSTAT */
#define MCF_USB_EPnSTAT_RST (0x00000001)
#define MCF_USB_EPnSTAT_FLUSH (0x00000002)
#define MCF_USB_EPnSTAT_DIR (0x00000080)
#define MCF_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16)
/* Bit definitions and macros for MCF_USB_EPnISR */
#define MCF_USB_EPnISR_EOF (0x00000001)
#define MCF_USB_EPnISR_EOT (0x00000004)
#define MCF_USB_EPnISR_FIFOLO (0x00000010)
#define MCF_USB_EPnISR_FIFOHI (0x00000020)
#define MCF_USB_EPnISR_ERR (0x00000040)
#define MCF_USB_EPnISR_EMT (0x00000080)
#define MCF_USB_EPnISR_FU (0x00000100)
/* Bit definitions and macros for MCF_USB_EPnIMR */
#define MCF_USB_EPnIMR_EOF (0x00000001)
#define MCF_USB_EPnIMR_EOT (0x00000004)
#define MCF_USB_EPnIMR_FIFOLO (0x00000010)
#define MCF_USB_EPnIMR_FIFOHI (0x00000020)
#define MCF_USB_EPnIMR_ERR (0x00000040)
#define MCF_USB_EPnIMR_EMT (0x00000080)
#define MCF_USB_EPnIMR_FU (0x00000100)
/* Bit definitions and macros for MCF_USB_EPnFRCFGR */
#define MCF_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0)
#define MCF_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16)
/* Bit definitions and macros for MCF_USB_EPnFSR */
#define MCF_USB_EPnFSR_EMT (0x00010000)
#define MCF_USB_EPnFSR_ALRM (0x00020000)
#define MCF_USB_EPnFSR_FR (0x00040000)
#define MCF_USB_EPnFSR_FU (0x00080000)
#define MCF_USB_EPnFSR_OF (0x00100000)
#define MCF_USB_EPnFSR_UF (0x00200000)
#define MCF_USB_EPnFSR_RXW (0x00400000)
#define MCF_USB_EPnFSR_FAE (0x00800000)
#define MCF_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24)
#define MCF_USB_EPnFSR_TXW (0x40000000)
#define MCF_USB_EPnFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_USB_EPnFCR */
#define MCF_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0)
#define MCF_USB_EPnFCR_TXWMSK (0x00040000)
#define MCF_USB_EPnFCR_OFMSK (0x00080000)
#define MCF_USB_EPnFCR_UFMSK (0x00100000)
#define MCF_USB_EPnFCR_RXWMSK (0x00200000)
#define MCF_USB_EPnFCR_FAEMSK (0x00400000)
#define MCF_USB_EPnFCR_IPMSK (0x00800000)
#define MCF_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24)
#define MCF_USB_EPnFCR_FRM (0x08000000)
#define MCF_USB_EPnFCR_TMR (0x10000000)
#define MCF_USB_EPnFCR_WFR (0x20000000)
#define MCF_USB_EPnFCR_SHAD (0x80000000)
/* Bit definitions and macros for MCF_USB_EPnFAR */
#define MCF_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_USB_EPnFRP */
#define MCF_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_USB_EPnFWP */
#define MCF_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_USB_EPnLRFP */
#define MCF_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0)
/* Bit definitions and macros for MCF_USB_EPnLWFP */
#define MCF_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0)
#endif /* __MCF548X_USB_H__ */

45
arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h
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@ -1,45 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Register and bit definitions for the MCF548X and MCF547x
* XLB bus arbiter
*/
#ifndef __MCF548X_XLBARB_H__
#define __MCF548X_XLBARB_H__
/*
* XLB arbiter register
*/
#define MCF_XLBARB_ACFG (*(vuint32*)(&__MBAR[0x000240]))
#define MCF_XLBARB_VER (*(vuint32*)(&__MBAR[0x000244]))
#define MCF_XLBARB_STA (*(vuint32*)(&__MBAR[0x000248]))
#define MCF_XLBARB_INTEN (*(vuint32*)(&__MBAR[0x00024C]))
#define MCF_XLBARB_ADRCAP (*(vuint32*)(&__MBAR[0x000250]))
#define MCF_XLBARB_SIGCAP (*(vuint32*)(&__MBAR[0x000254]))
#define MCF_XLBARB_ADRTO (*(vuint32*)(&__MBAR[0x000258]))
#define MCF_XLBARB_DATTO (*(vuint32*)(&__MBAR[0x00025C]))
#define MCF_XLBARB_BUSTO (*(vuint32*)(&__MBAR[0x000260]))
#define MCF_XLBARB_PRIEN (*(vuint32*)(&__MBAR[0x000264]))
#define MCF_XLBARB_PRI (*(vuint32*)(&__MBAR[0x000268]))
#define MCF_XLBARB_BAR (*(vuint32*)(&__MBAR[0x00026C]))
#endif /* __MCF548X_XLBARB_H__ */

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Definitions common across all ColdFire processors
*/
#ifndef __MCF5XXX__H
#define __MCF5XXX__H
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32_t
#define INSTRUCTION uint16_t
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/*
* Definitions for CPU status register (SR)
*/
#define MCF5XXX_SR_T (0x8000)
#define MCF5XXX_SR_S (0x2000)
#define MCF5XXX_SR_M (0x1000)
#define MCF5XXX_SR_IPL (0x0700)
#define MCF5XXX_SR_IPL_0 (0x0000)
#define MCF5XXX_SR_IPL_1 (0x0100)
#define MCF5XXX_SR_IPL_2 (0x0200)
#define MCF5XXX_SR_IPL_3 (0x0300)
#define MCF5XXX_SR_IPL_4 (0x0400)
#define MCF5XXX_SR_IPL_5 (0x0500)
#define MCF5XXX_SR_IPL_6 (0x0600)
#define MCF5XXX_SR_IPL_7 (0x0700)
#define MCF5XXX_SR_X (0x0010)
#define MCF5XXX_SR_N (0x0008)
#define MCF5XXX_SR_Z (0x0004)
#define MCF5XXX_SR_V (0x0002)
#define MCF5XXX_SR_C (0x0001)
/*
* Definitions for CPU cache control register
*/
#define MCF5XXX_CACR_CENB (0x80000000)
#define MCF5XXX_CACR_DEC (0x80000000)
#define MCF5XXX_CACR_DW (0x40000000)
#define MCF5XXX_CACR_DESB (0x20000000)
#define MCF5XXX_CACR_CPDI (0x10000000)
#define MCF5XXX_CACR_DDPI (0x10000000)
#define MCF5XXX_CACR_CPD (0x10000000)
#define MCF5XXX_CACR_CFRZ (0x08000000)
#define MCF5XXX_CACR_DHLCK (0x08000000)
#define MCF5XXX_CACR_DDCM_WT (0x00000000)
#define MCF5XXX_CACR_DDCM_CB (0x02000000)
#define MCF5XXX_CACR_DDCM_IP (0x04000000)
#define MCF5XXX_CACR_DDCM_II (0x06000000)
#define MCF5XXX_CACR_CINV (0x01000000)
#define MCF5XXX_CACR_DCINVA (0x01000000)
#define MCF5XXX_CACR_DIDI (0x00800000)
#define MCF5XXX_CACR_DDSP (0x00800000)
#define MCF5XXX_CACR_DISD (0x00400000)
#define MCF5XXX_CACR_INVI (0x00200000)
#define MCF5XXX_CACR_INVD (0x00100000)
#define MCF5XXX_CACR_BEC (0x00080000)
#define MCF5XXX_CACR_BCINVA (0x00040000)
#define MCF5XXX_CACR_IEC (0x00008000)
#define MCF5XXX_CACR_DNFB (0x00002000)
#define MCF5XXX_CACR_IDPI (0x00001000)
#define MCF5XXX_CACR_IHLCK (0x00000800)
#define MCF5XXX_CACR_CEIB (0x00000400)
#define MCF5XXX_CACR_IDCM (0x00000400)
#define MCF5XXX_CACR_DCM_WR (0x00000000)
#define MCF5XXX_CACR_DCM_CB (0x00000100)
#define MCF5XXX_CACR_DCM_IP (0x00000200)
#define MCF5XXX_CACR_DCM (0x00000200)
#define MCF5XXX_CACR_DCM_II (0x00000300)
#define MCF5XXX_CACR_DBWE (0x00000100)
#define MCF5XXX_CACR_ICINVA (0x00000100)
#define MCF5XXX_CACR_IDSP (0x00000080)
#define MCF5XXX_CACR_DWP (0x00000020)
#define MCF5XXX_CACR_EUSP (0x00000020)
#define MCF5XXX_CACR_EUST (0x00000020)
#define MCF5XXX_CACR_DF (0x00000010)
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
/*
* Definition for CPU access control register
*/
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
#define MCF5XXX_ACR_EN (0x00008000)
#define MCF5XXX_ACR_SM_USER (0x00000000)
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
#define MCF5XXX_ACR_ENIB (0x00000080)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_DCM_WR (0x00000000)
#define MCF5XXX_ACR_DCM_CB (0x00000020)
#define MCF5XXX_ACR_DCM_IP (0x00000040)
#define MCF5XXX_ACR_DCM_II (0x00000060)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_BWE (0x00000020)
#define MCF5XXX_ACR_WP (0x00000004)
/*
* Definitions for CPU core sram control registers
*/
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
#define MCF5XXX_RAMBAR_WP (0x00000100)
#define MCF5XXX_RAMBAR_CI (0x00000020)
#define MCF5XXX_RAMBAR_SC (0x00000010)
#define MCF5XXX_RAMBAR_SD (0x00000008)
#define MCF5XXX_RAMBAR_UC (0x00000004)
#define MCF5XXX_RAMBAR_UD (0x00000002)
#define MCF5XXX_RAMBAR_V (0x00000001)
#ifndef __ASSEMBLY__
extern char __MBAR[];
/*
* Extention to thhe basic POSIX data types
*/
typedef volatile uint8_t vuint8_t; /* 8 bits */
typedef volatile uint16_t vuint16_t; /* 16 bits */
typedef volatile uint32_t vuint32_t; /* 32 bits */
/*
* Routines and macros for accessing Input/Output devices
*/
#define mcf_iord_8(ADDR) *((vuint8_t *)(ADDR))
#define mcf_iord_16(ADDR) *((vuint16_t *)(ADDR))
#define mcf_iord_32(ADDR) *((vuint32_t *)(ADDR))
#define mcf_iowr_8(ADDR,DATA) *((vuint8_t *)(ADDR)) = (DATA)
#define mcf_iowr_16(ADDR,DATA) *((vuint16_t *)(ADDR)) = (DATA)
#define mcf_iowr_32(ADDR,DATA) *((vuint32_t *)(ADDR)) = (DATA)
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 3322222222221111 111111
* 1098765432109876 5432109876543210
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5XXX_RD_SF_FORMAT(PTR) \
((*((uint16_t *)(PTR)) >> 12) & 0x00FF)
#define MCF5XXX_RD_SF_VECTOR(PTR) \
((*((uint16_t *)(PTR)) >> 2) & 0x00FF)
#define MCF5XXX_RD_SF_FS(PTR) \
( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) )
#define MCF5XXX_SF_SR(PTR) *((uint16_t *)(PTR)+1)
#define MCF5XXX_SF_PC(PTR) *((uint32_t *)(PTR)+1)
/*
* Functions provided as inline code to access supervisor mode
* registers from C.
*
* Note: Most registers are write-only. So you must use shadow registers in
* RAM to track the state of each register!
*/
static __inline__ uint16_t mcf5xxx_rd_sr(void) { uint16_t rc; __asm__ __volatile__( "move.w %%sr,%0\n" : "=r" (rc) ); return rc; }
static __inline__ void mcf5xxx_wr_sr(uint16_t value) { __asm__ __volatile__( "move.w %0,%%sr\n" : : "r" (value) ); }
static __inline__ int asm_set_ipl(uint32_t value)
{
uint32_t oldipl,newipl;
value = (value & 0x7) << 8U;
oldipl = mcf5xxx_rd_sr();
newipl = oldipl & ~0x0700U;
newipl |= value;
mcf5xxx_wr_sr(newipl);
oldipl = (oldipl & 0x0700U) >> 8U;
return oldipl;
}
static __inline__ void mcf5xxx_cpushl_bc(uint32_t* value) { __asm__ __volatile__( " move.l %0,%%a0 \n .word 0xF4E8\n nop\n" : : "a" (value) : "a0"); }
// cpushl bc,%%a0@ ???
static __inline__ void mcf5xxx_wr_cacr(uint32_t value) { __asm__ __volatile__( "movec %0,%%cacr\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_asid(uint32_t value) { __asm__ __volatile__( "movec %0,%%asid\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acr0(uint32_t value) { __asm__ __volatile__( "movec %0,#4\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acr1(uint32_t value) { __asm__ __volatile__( "movec %0,#5\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acr2(uint32_t value) { __asm__ __volatile__( "movec %0,#6\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acr3(uint32_t value) { __asm__ __volatile__( "movec %0,#7\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_mmubar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mmubar\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_other_a7(uint32_t value) { __asm__ __volatile__( "movec %0,%%other_sp\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_vbr(uint32_t value) { __asm__ __volatile__( "movec %0,%%vbr\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_macsr(uint32_t value) { __asm__ __volatile__( "movec %0,%%macsr\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_mask(uint32_t value) { __asm__ __volatile__( "movec %0,%%mask\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acc0(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc0\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_accext01(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext01\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_accext23(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext23\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acc1(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc1\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acc2(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc2\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_acc3(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc3\n nop\n" : : "r" (value) ); }
//static __inline__ void mcf5xxx_wr_sr(uint32_t value) { __asm__ __volatile__( "movec %0,%%sr\n nop\n" : : "r" (value) ); }
//static __inline__ void mcf5xxx_wr_pc(uint32_t value) { __asm__ __volatile__( "movec %0,#0x080F\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_rombar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar0\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_rombar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar1\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_rambar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar0\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_rambar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar1\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_mpcr(uint32_t value) { __asm__ __volatile__( "movec %0,%%mpcr\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_secmbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar1\n nop\n" : : "r" (value) ); }
static __inline__ void mcf5xxx_wr_mbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar0\n nop\n" : : "r" (value) ); }
#endif
/*
* Now do specific ColdFire processor
*/
#if (defined(CONFIG_ARCH_MCF54xx))
#include "asm/coldfire/mcf548x.h"
#else
#error "Error: Yet unsupported ColdFire processor."
#endif
#endif /* __MCF5XXX__H */

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@ -1,25 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Common include file wrapper for m68k architecture
*/
/* nothing */

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@ -1,146 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Defines for M68k ELF Files
*/
#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
/*
* ELF register definitions..
*/
//#include <linux/config.h>
#include <asm/ptrace.h>
//#include <asm/user.h>
/*
* 68k ELF relocation types
*/
#define R_68K_NONE 0
#define R_68K_32 1
#define R_68K_16 2
#define R_68K_8 3
#define R_68K_PC32 4
#define R_68K_PC16 5
#define R_68K_PC8 6
#define R_68K_GOT32 7
#define R_68K_GOT16 8
#define R_68K_GOT8 9
#define R_68K_GOT32O 10
#define R_68K_GOT16O 11
#define R_68K_GOT8O 12
#define R_68K_PLT32 13
#define R_68K_PLT16 14
#define R_68K_PLT8 15
#define R_68K_PLT32O 16
#define R_68K_PLT16O 17
#define R_68K_PLT8O 18
#define R_68K_COPY 19
#define R_68K_GLOB_DAT 20
#define R_68K_JMP_SLOT 21
#define R_68K_RELATIVE 22
typedef unsigned long elf_greg_t;
//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
#define ELF_NGREG 20
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_m68kfp_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_68K)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_68K
/* For SVR4/m68k the function pointer to be registered with `atexit' is
passed in %a1. Although my copy of the ABI has no such statement, it
is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#define USE_ELF_CORE_DUMP
#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
#define ELF_EXEC_PAGESIZE 4096
#else
#define ELF_EXEC_PAGESIZE 8192
#endif
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#ifndef CONFIG_SUN3
#define ELF_ET_DYN_BASE 0xD0000000UL
#else
#define ELF_ET_DYN_BASE 0x0D800000UL
#endif
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[9] = regs->a2; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = regs->orig_d0; \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
pr_reg[19] = (regs->format << 12) | regs->vector; \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#ifdef __KERNEL__
#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
#endif
#endif

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Common hardware definitions
*/
#ifndef __M68K_HARDWARE_H
#define __M68K_HARDWARE_H
#include <mach/hardware.h>
#endif

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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#ifndef __ASM_M68K_IO_H
#define __ASM_M68K_IO_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
/*
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
#define writeb(v,a) __arch_putb(v,a)
#define writew(v,a) __arch_putw(v,a)
#define writel(v,a) __arch_putl(v,a)
#define readb(a) __arch_getb(a)
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
#define __raw_base_readb(base,off) __arch_base_getb(base,off)
#define __raw_base_readw(base,off) __arch_base_getw(base,off)
#define __raw_base_readl(base,off) __arch_base_getl(base,off)
/*
* Now, pick up the machine-defined IO definitions
*/
/*
* IO port access primitives
* -------------------------
*
* The M68k doesn't have special IO access instructions; all IO is memory
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that for a big endian machine, this implies that the following
* big endian mode connectivity is in place, as described by numerious
* ARM documents:
*
* PCI: D0-D7 D8-D15 D16-D23 D24-D31
* ARM: D24-D31 D16-D23 D8-D15 D0-D7
*
* The machine specific io.h include defines __io to translate an "IO"
* address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#ifdef __io
#define outb(v,p) __raw_writeb(v,__io(p))
#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p))
#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
#define insb(p,d,l) __raw_readsb(__io(p),d,l)
#define insw(p,d,l) __raw_readsw(__io(p),d,l)
#define insl(p,d,l) __raw_readsl(__io(p),d,l)
#endif
#define outb_p(val,port) outb((val),(port))
#define outw_p(val,port) outw((val),(port))
#define outl_p(val,port) outl((val),(port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port,from,len) outsb(port,from,len)
#define outsw_p(port,from,len) outsw(port,from,len)
#define outsl_p(port,from,len) outsl(port,from,len)
#define insb_p(port,to,len) insb(port,to,len)
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)
/*
* ioremap and friends.
*
* ioremap takes a PCI memory address, as specified in
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
* Generic ioremap support.
*
* Define:
* iomem_valid_addr(off,size)
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off,sz,nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,0); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
#define ioremap(off,sz) __arch_ioremap((off),(sz),0)
#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1)
#define iounmap(_addr) __arch_iounmap(_addr)
/*
* DMA-consistent mapping functions. These allocate/free a region of
* uncached, unwrite-buffered mapped memory space for use with DMA
* devices. This is the "generic" version. The PCI specific version
* is in pci.h
*/
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
extern void __readwrite_bug(const char *fn);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
#define eth_io_copy_and_sum(s,c,l,b) \
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#elif !defined(readb)
#define readb(addr) (__readwrite_bug("readb"),0)
#define readw(addr) (__readwrite_bug("readw"),0)
#define readl(addr) (__readwrite_bug("readl"),0)
#define writeb(v,addr) __readwrite_bug("writeb")
#define writew(v,addr) __readwrite_bug("writew")
#define writel(v,addr) __readwrite_bug("writel")
#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum")
#define check_signature(io,sig,len) (0)
#endif /* __mem_pci */
/*
* If this architecture has ISA IO, then define the isa_read/isa_write
* macros.
*/
#ifdef __mem_isa
#define isa_readb(addr) __raw_readb(__mem_isa(addr))
#define isa_readw(addr) __raw_readw(__mem_isa(addr))
#define isa_readl(addr) __raw_readl(__mem_isa(addr))
#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr))
#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr))
#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr))
#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c))
#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c))
#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c))
#define isa_eth_io_copy_and_sum(a,b,c,d) \
eth_copy_and_sum((a),__mem_isa(b),(c),(d))
static inline int
isa_check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (isa_readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#else /* __mem_isa */
#define isa_readb(addr) (__readwrite_bug("isa_readb"),0)
#define isa_readw(addr) (__readwrite_bug("isa_readw"),0)
#define isa_readl(addr) (__readwrite_bug("isa_readl"),0)
#define isa_writeb(val,addr) __readwrite_bug("isa_writeb")
#define isa_writew(val,addr) __readwrite_bug("isa_writew")
#define isa_writel(val,addr) __readwrite_bug("isa_writel")
#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io")
#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio")
#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio")
#define isa_eth_io_copy_and_sum(a,b,c,d) \
__readwrite_bug("isa_eth_io_copy_and_sum")
#define isa_check_signature(io,sig,len) (0)
#endif /* __mem_isa */
#endif /* __KERNEL__ */
#endif /* __ASM_M68K_IO_H */

48
arch/m68k/include/asm/mach-types.h
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@ -1,48 +0,0 @@
/*
* This was automagically generated from arch/m68k/tools/mach-types!
* Do NOT edit
*/
#ifndef __ASM_M68K_MACH_TYPE_H
#define __ASM_M68K_MACH_TYPE_H
#ifndef __ASSEMBLY__
/* The type of machine we're running on */
extern unsigned int __machine_arch_type;
#endif
/* see arch/m68k/kernel/arch.c for a description of these */
#define MACH_TYPE_GENERIC 0
#define MACH_TYPE_MCF54xx 1
#define MACH_TYPE_MCF5445x 2
#ifdef CONFIG_ARCH_MCF54xx
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_MCF54xx
# endif
# define machine_is_mcf54xx() (machine_arch_type == MACH_TYPE_MCF54xx)
#else
# define machine_is_mcf54xx() (0)
#endif
#ifdef CONFIG_ARCH_MCF5445x
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_MCF5445x
# endif
# define machine_is_mcf5445x() (machine_arch_type == MACH_TYPE_MCF5445x)
#else
# define machine_is_mcf5445x() (0)
#endif
#ifndef machine_arch_type
#define machine_arch_type __machine_arch_type
#endif
#endif

28
arch/m68k/include/asm/memory.h
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@ -1,28 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Note: this file should not be included by non-asm/.h files
*/
#ifndef __ASM_M68K_MEMORY_H
#define __ASM_M68K_MEMORY_H
#endif /* __ASM_M68K_MEMORY_H */

36
arch/m68k/include/asm/module.h
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@ -1,36 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Defines for the ELF module loader
*/
#ifndef _ASM_M68K_MODULE_H
#define _ASM_M68K_MODULE_H
struct mod_arch_specific
{
int foo;
};
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Ehdr Elf32_Ehdr
#endif /* _ASM_M68K_MODULE_H */

86
arch/m68k/include/asm/posix_types.h
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@ -1,86 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
#ifndef __ARCH_M68K_POSIX_TYPES_H
#define __ARCH_M68K_POSIX_TYPES_H
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
#define __FD_SET(fd, fdsetp) \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
#undef __FD_CLR
#define __FD_CLR(fd, fdsetp) \
(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
#undef __FD_ISSET
#define __FD_ISSET(fd, fdsetp) \
((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) \
(memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp)))
#endif
#endif

46
arch/m68k/include/asm/processor.h
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@ -1,46 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* General processor specific definitions
*/
#ifndef __ASM_M68K_PROCESSOR_H
#define __ASM_M68K_PROCESSOR_H
/*
* Default implementation of macro that returns current
* instruction pointer ("program counter").
*/
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
static inline unsigned long rdusp(void)
{
unsigned long usp;
__asm__ __volatile__("movel %/usp,%0" : "=a" (usp));
return usp;
}
static inline void wrusp(unsigned long usp)
{
__asm__ __volatile__("movel %0,%/usp" : : "a" (usp));
}
#endif /* __ASM_M68K_PROCESSOR_H */

55
arch/m68k/include/asm/ptrace.h
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@ -1,55 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Remains of the pthread stuff...
* @todo Rework these headers....
*/
#ifndef __ASM_M68K_PTRACE_H
#define __ASM_M68K_PTRACE_H
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
#define PTRACE_SETFPREGS 15
#define PTRACE_SETOPTIONS 21
#include <proc/ptrace.h>
#ifndef __ASSEMBLY__
#ifndef PS_S
#define PS_S (0x2000)
#define PS_M (0x1000)
#endif
//#define user_mode(regs) (!((regs)->sr & PS_S))
#define instruction_pointer(regs) ((regs)->M68K_pc)
#define profile_pc(regs) instruction_pointer(regs)
#ifdef __KERNEL__
extern void show_regs(struct pt_regs *);
#endif
#endif /* __ASSEMBLY__ */
#endif

412
arch/m68k/include/asm/setup.h
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@ -1,412 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Arch dependant barebox defines about linux mach types
*/
#ifndef _M68K_SETUP_H
#define _M68K_SETUP_H
#include <config.h>
/*
* Linux/m68k Architectures
*/
#define MACH_AMIGA 1
#define MACH_ATARI 2
#define MACH_MAC 3
#define MACH_APOLLO 4
#define MACH_SUN3 5
#define MACH_MVME147 6
#define MACH_MVME16x 7
#define MACH_BVME6000 8
#define MACH_HP300 9
#define MACH_Q40 10
#define MACH_SUN3X 11
/* ColdFire boards */
#define MACH_FIRE_ENGINE 12
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
extern unsigned long m68k_machtype;
#endif /* !__ASSEMBLY__ */
#if !defined(CONFIG_AMIGA)
# define MACH_IS_AMIGA (0)
#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \
|| defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA)
#else
# define MACH_AMIGA_ONLY
# define MACH_IS_AMIGA (1)
# define MACH_TYPE (MACH_AMIGA)
#endif
#if !defined(CONFIG_ATARI)
# define MACH_IS_ATARI (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \
|| defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_ATARI (m68k_machtype == MACH_ATARI)
#else
# define MACH_ATARI_ONLY
# define MACH_IS_ATARI (1)
# define MACH_TYPE (MACH_ATARI)
#endif
#if !defined(CONFIG_MAC)
# define MACH_IS_MAC (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \
|| defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_MAC (m68k_machtype == MACH_MAC)
#else
# define MACH_MAC_ONLY
# define MACH_IS_MAC (1)
# define MACH_TYPE (MACH_MAC)
#endif
#if defined(CONFIG_SUN3)
#define MACH_IS_SUN3 (1)
#define MACH_SUN3_ONLY (1)
#define MACH_TYPE (MACH_SUN3)
#else
#define MACH_IS_SUN3 (0)
#endif
#if !defined (CONFIG_APOLLO)
# define MACH_IS_APOLLO (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO)
#else
# define MACH_APOLLO_ONLY
# define MACH_IS_APOLLO (1)
# define MACH_TYPE (MACH_APOLLO)
#endif
#if !defined (CONFIG_MVME147)
# define MACH_IS_MVME147 (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x)
# define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147)
#else
# define MACH_MVME147_ONLY
# define MACH_IS_MVME147 (1)
# define MACH_TYPE (MACH_MVME147)
#endif
#if !defined (CONFIG_MVME16x)
# define MACH_IS_MVME16x (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x)
#else
# define MACH_MVME16x_ONLY
# define MACH_IS_MVME16x (1)
# define MACH_TYPE (MACH_MVME16x)
#endif
#if !defined (CONFIG_BVME6000)
# define MACH_IS_BVME6000 (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
|| defined(CONFIG_HP300) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000)
#else
# define MACH_BVME6000_ONLY
# define MACH_IS_BVME6000 (1)
# define MACH_TYPE (MACH_BVME6000)
#endif
#if !defined (CONFIG_HP300)
# define MACH_IS_HP300 (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
|| defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_HP300 (m68k_machtype == MACH_HP300)
#else
# define MACH_HP300_ONLY
# define MACH_IS_HP300 (1)
# define MACH_TYPE (MACH_HP300)
#endif
#if !defined (CONFIG_Q40)
# define MACH_IS_Q40 (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
|| defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \
|| defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
# define MACH_IS_Q40 (m68k_machtype == MACH_Q40)
#else
# define MACH_Q40_ONLY
# define MACH_IS_Q40 (1)
# define MACH_TYPE (MACH_Q40)
#endif
#if !defined (CONFIG_SUN3X)
# define MACH_IS_SUN3X (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
|| defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
|| defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \
|| defined(CONFIG_Q40) || defined(CONFIG_MVME147)
# define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X)
#else
# define CONFIG_SUN3X_ONLY
# define MACH_IS_SUN3X (1)
# define MACH_TYPE (MACH_SUN3X)
#endif
/*
* We only support one ColdFire board for the moment, so we don't do the
* kind of complicated configuration this file does for the other 68k CPUs. --NL
*/
#if !defined (CONFIG_COLDFIRE)
# define MACH_IS_COLDFIRE (0)
#else
# define CONFIG_COLDFIRE_ONLY
# define MACH_IS_COLDFIRE (1)
# define MACH_TYPE (MACH_COLDFIRE)
#endif
#ifndef MACH_TYPE
# define MACH_TYPE (m68k_machtype)
#endif
#endif /* __KERNEL__ */
/*
* CPU, FPU and MMU types
*
* Note: we may rely on the following equalities:
*
* CPU_68020 == MMU_68851
* CPU_68030 == MMU_68030
* CPU_68040 == FPU_68040 == MMU_68040
* CPU_68060 == FPU_68060 == MMU_68060
*/
#define CPUB_68020 0
#define CPUB_68030 1
#define CPUB_68040 2
#define CPUB_68060 3
#define CPUB_CFV4E 4
#define CPU_68020 (1<<CPUB_68020)
#define CPU_68030 (1<<CPUB_68030)
#define CPU_68040 (1<<CPUB_68040)
#define CPU_68060 (1<<CPUB_68060)
#define CPU_CFV4E (1<<CPUB_CFV4E)
#define FPUB_68881 0
#define FPUB_68882 1
#define FPUB_68040 2 /* Internal FPU */
#define FPUB_68060 3 /* Internal FPU */
#define FPUB_SUNFPA 4 /* Sun-3 FPA */
#define FPUB_CFV4E 5
#define FPU_68881 (1<<FPUB_68881)
#define FPU_68882 (1<<FPUB_68882)
#define FPU_68040 (1<<FPUB_68040)
#define FPU_68060 (1<<FPUB_68060)
#define FPU_SUNFPA (1<<FPUB_SUNFPA)
#define FPU_CFV4E (1<<FPUB_CFV4E)
#define MMUB_68851 0
#define MMUB_68030 1 /* Internal MMU */
#define MMUB_68040 2 /* Internal MMU */
#define MMUB_68060 3 /* Internal MMU */
#define MMUB_APOLLO 4 /* Custom Apollo */
#define MMUB_SUN3 5 /* Custom Sun-3 */
#define MMUB_CFV4E 6
#define MMU_68851 (1<<MMUB_68851)
#define MMU_68030 (1<<MMUB_68030)
#define MMU_68040 (1<<MMUB_68040)
#define MMU_68060 (1<<MMUB_68060)
#define MMU_SUN3 (1<<MMUB_SUN3)
#define MMU_APOLLO (1<<MMUB_APOLLO)
#define MMU_CFV4E (1<<MMUB_CFV4E)
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
extern unsigned long m68k_cputype;
extern unsigned long m68k_fputype;
extern unsigned long m68k_mmutype; /* Not really used yet */
#ifdef CONFIG_VME
extern unsigned long vme_brdtype;
#endif
/*
* m68k_is040or060 is != 0 for a '040 or higher;
* used numbers are 4 for 68040 and 6 for 68060.
*/
extern int m68k_is040or060;
#endif /* !__ASSEMBLY__ */
#if !defined(CONFIG_M68020)
# define CPU_IS_020 (0)
# define MMU_IS_851 (0)
# define MMU_IS_SUN3 (0)
#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_020 (m68k_cputype & CPU_68020)
# define MMU_IS_851 (m68k_mmutype & MMU_68851)
# define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */
#else
# define CPU_M68020_ONLY
# define CPU_IS_020 (1)
#ifdef MACH_SUN3_ONLY
# define MMU_IS_SUN3 (1)
# define MMU_IS_851 (0)
#else
# define MMU_IS_SUN3 (0)
# define MMU_IS_851 (1)
#endif
#endif
#if !defined(CONFIG_M68030)
# define CPU_IS_030 (0)
# define MMU_IS_030 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_030 (m68k_cputype & CPU_68030)
# define MMU_IS_030 (m68k_mmutype & MMU_68030)
#else
# define CPU_M68030_ONLY
# define CPU_IS_030 (1)
# define MMU_IS_030 (1)
#endif
#if !defined(CONFIG_M68040)
# define CPU_IS_040 (0)
# define MMU_IS_040 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060)
# define CPU_IS_040 (m68k_cputype & CPU_68040)
# define MMU_IS_040 (m68k_mmutype & MMU_68040)
#else
# define CPU_M68040_ONLY
# define CPU_IS_040 (1)
# define MMU_IS_040 (1)
#endif
#if !defined(CONFIG_M68060)
# define CPU_IS_060 (0)
# define MMU_IS_060 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040)
# define CPU_IS_060 (m68k_cputype & CPU_68060)
# define MMU_IS_060 (m68k_mmutype & MMU_68060)
#else
# define CPU_M68060_ONLY
# define CPU_IS_060 (1)
# define MMU_IS_060 (1)
#endif
#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030)
# define CPU_IS_020_OR_030 (0)
#else
# define CPU_M68020_OR_M68030
# if defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_020_OR_030 (!m68k_is040or060)
# else
# define CPU_M68020_OR_M68030_ONLY
# define CPU_IS_020_OR_030 (1)
# endif
#endif
#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060)
# define CPU_IS_040_OR_060 (0)
#else
# define CPU_M68040_OR_M68060
# if defined(CONFIG_M68020) || defined(CONFIG_M68030)
# define CPU_IS_040_OR_060 (m68k_is040or060)
# else
# define CPU_M68040_OR_M68060_ONLY
# define CPU_IS_040_OR_060 (1)
# endif
#endif
#if !defined(CONFIG_CFV4E)
# define CPU_IS_COLDFIRE (0)
#else
# define CPU_IS_COLDFIRE (1)
# define CPU_IS_CFV4E (1)
# define MMU_IS_CFV4E (1)
#endif
#define CPU_TYPE (m68k_cputype)
#ifdef CONFIG_M68KFPU_EMU
# ifdef CONFIG_M68KFPU_EMU_ONLY
# define FPU_IS_EMU (1)
# else
# define FPU_IS_EMU (!m68k_fputype)
# endif
#else
# define FPU_IS_EMU (0)
#endif
/*
* Miscellaneous
*/
#define NUM_MEMINFO 4
#define CL_SIZE 256
#define COMMAND_LINE_SIZE CL_SIZE
#ifndef __ASSEMBLY__
struct mem_info {
unsigned long addr; /* physical address of memory chunk */
unsigned long size; /* length of memory chunk (in bytes) */
};
extern int m68k_num_memory; /* # of memory blocks found (and used) */
extern int m68k_realnum_memory; /* real # of memory blocks found */
extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */
#endif
#ifdef CONFIG_COLDFIRE
#define QCHIP_RESTORE_DIRECTIVE ".chip 547x"
#define CHIP_RESTORE_DIRECTIVE .chip 547x
#else
#define QCHIP_RESTORE_DIRECTIVE ".chip 68k"
#define CHIP_RESTORE_DIRECTIVE .chip 68k
#endif
#endif /* __KERNEL__ */
#endif /* _M68K_SETUP_H */

32
arch/m68k/include/asm/string.h
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/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Arch dependant configuration of std libc string and memory functions.
*/
#ifndef __ASM_M68K_STRING_H
#define __ASM_M68K_STRING_H
/*
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
*/
#endif

82
arch/m68k/include/asm/types.h
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@ -1,82 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Arch dependant types definitions
*/
#ifndef __ASM_M68K_TYPES_H
#define __ASM_M68K_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
#endif /* __ASSEMBLY__ */
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
#define BITS_PER_LONG 32
#ifndef __ASSEMBLY__
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
typedef u32 dma64_addr_t;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif

31
arch/m68k/lib/Makefile
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@ -1,31 +0,0 @@
#
# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
# See file CREDITS for list of people who contributed to this project.
#
# This file is part of barebox.
#
# barebox is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# barebox is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with barebox. If not, see <http://www.gnu.org/licenses/>.
#
#
# Architecture dependant stubs and callbacks
#
obj-y += m68k-meminit.o
obj-$(CONFIG_CMD_BOOTM) += m68k-linuxboot.o
obj-$(CONFIG_MODULES) += m68k-module.o
extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds

92
arch/m68k/lib/barebox.lds.S
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@ -1,92 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Generic Linker file for M68k targets
*/
#include <asm-generic/barebox.lds.h>
OUTPUT_FORMAT("elf32-m68k", "elf32-m68k",
"elf32-m68k")
OUTPUT_ARCH(m68k)
ENTRY(_start)
SECTIONS
{
. = TEXT_BASE;
. = ALIGN(4);
/* Start of vector, text and rodata section */
_stext = .;
_text = .;
/* M68k/CF style vector table */
.vectors :
{
*(.vectors)
}
.text :
{
*(.text .stub .text.*)
} =0x4e754e75
. = ALIGN(4);
.rodata :
{
*(.rodata .rodata.*)
} =0xdeadbeef
. = ALIGN(4);
__barebox_cmd_start = .;
.barebox_cmd : { BAREBOX_CMDS }
__barebox_cmd_end = .;
__barebox_initcalls_start = .;
.barebox_initcalls : { INITCALLS }
__barebox_initcalls_end = .;
__usymtab_start = .;
__usymtab : { BAREBOX_SYMS }
__usymtab_end = .;
/* End of text and rodata section */
. = ALIGN(4);
_etext = .;
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
. = ALIGN(4);
__early_init_data_begin = .;
.early_init_data : { *(.early_init_data) }
__early_init_data_end = .;
.data : { *(.data .data.*) }
. = ALIGN(4);
__bss_start = .;
.bss (NOLOAD) : { *(.bss .bass.*) }
__bss_end =.;
_end = .;
. = ALIGN(4);
_barebox_heap_start = .;
}

177
arch/m68k/lib/m68k-linuxboot.c
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@ -1,177 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* @brief Linux boot preparation code.
*
* This file is responsible to start a linux kernel on
* Coldfire targets.
*
* @note Only Colilo mode supported yet.
*/
#include <common.h>
#include <command.h>
#include <driver.h>
#include <image.h>
#include <zlib.h>
#include <init.h>
#include <asm/byteorder.h>
#include <asm/setup.h>
#include <environment.h>
#include <boot.h>
#include <asm/barebox-m68k.h>
#include <asm/bootinfo.h>
static int m68k_architecture = MACH_TYPE_GENERIC;
/*
* Setup M68k/Coldfire bootrecord info
*/
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
defined (CONFIG_CMDLINE_TAG) || \
defined (CONFIG_INITRD_TAG)
static void setup_boot_record(char* start_boot_rec, const char* command_line)
{
struct bi_record* record;
*start_boot_rec++ = 'C';
*start_boot_rec++ = 'o';
*start_boot_rec++ = 'L';
*start_boot_rec++ = 'i';
*start_boot_rec++ = 'L';
*start_boot_rec++ = 'o';
record = (struct bi_record*) start_boot_rec;
/* specify memory layout */
#ifdef CONFIG_SETUP_MEMORY_TAGS
record->tag = BI_MEMCHUNK;
record->data[0] = 0;
record->data[1] = 64 * 1024 * 1024; // TODO: to be changed for different boards
record->size = sizeof (record->tag) + sizeof (record->size)
+ sizeof (record->data[0]) + sizeof (record->data[0]);
record = (struct bi_record *) ((void *) record + record->size);
#endif
/* add a kernel command line */
#ifdef CONFIG_CMDLINE_TAG
record->tag = BI_COMMAND_LINE;
strcpy ((char *) &record->data, command_line);
record->size = sizeof (record->tag) + sizeof (record->size)
+ max (sizeof (record->data[0]), strlen (command_line)+1);
record = (struct bi_record *) ((void *) record + record->size);
#endif
/* Add reference to initrd */
#ifdef CONFIG_INITRD_TAG
#endif
/* Mark end of tags */
record->tag = 0;
record->data[0] = 0;
record->data[1] = 0;
record->size = sizeof(record->tag) + sizeof (record->size)
+ sizeof (record->data[0]) + sizeof (record->data[0]);
}
#else
#define setup_boot_record(start_boot_rec,command_line) while (0) { }
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
static int do_bootm_linux(struct image_data *data)
{
image_header_t *os_header = &data->os->header;
void (*theKernel)(int zero, int arch, uint params);
const char *commandline = getenv ("bootargs");
uint32_t loadaddr,loadsize;
if (image_get_type(os_header) == IH_TYPE_MULTI) {
printf("Multifile images not handled at the moment\n");
return -1;
}
printf("commandline: %s\n", commandline);
theKernel = (void (*)(int,int,uint))image_get_ep(os_header);
debug ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong) theKernel);
loadaddr = (uint32_t)image_get_load(os_header);
loadsize = (uint32_t)image_get_size(os_header);
setup_boot_record( (char*)(loadaddr+loadsize),(char*)commandline);
if (relocate_image(data->os, (void *)loadaddr))
return -1;
/* we assume that the kernel is in place */
printf ("\nStarting kernel image at 0x%08x size 0x%08x eentry 0x%08x\n\n",
loadaddr, loadsize, (ulong) theKernel);
/* Bring board into inactive post-reset state again */
cleanup_before_linux ();
/* Jump to kernel entry point */
theKernel (0, m68k_architecture, 0xdeadbeaf);
enable_interrupts();
printf("Error: Loaded kernel returned. Probably it couldn't\n"
"find it's bootrecord.\n");
return -1;
}
/*
* Register handler for m68k Kernel Images
*/
static int image_handle_cmdline_parse(struct image_data *data, int opt, char *optarg)
{
switch (opt)
{
case 'a':
m68k_architecture = simple_strtoul(optarg, NULL, 0);
return 0;
default:
return 1;
}
}
static struct image_handler handler =
{
.cmdline_options = "a:",
.cmdline_parse = image_handle_cmdline_parse,
.help_string = " -a <arch> use architecture number <arch>",
.bootm = do_bootm_linux,
.image_type = IH_OS_LINUX,
};
static int m68klinux_register_image_handler(void)
{
return register_image_handler(&handler);
}
late_initcall(m68klinux_register_image_handler);

43
arch/m68k/lib/m68k-meminit.c
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@ -1,43 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Init for memory allocator on m68k/Coldfire
*/
#include <common.h>
#include <init.h>
#include <mem_malloc.h>
#include <asm/barebox-m68k.h>
#include <reloc.h>
#include <asm-generic/memory_layout.h>
/** Initialize mem allocator on M68k/Coldfire
*/
int m68k_mem_malloc_init(void)
{
/* Pass start and end address of managed memory */
mem_malloc_init((void *)MALLOC_BASE,
(void *)(MALLOC_BASE + MALLOC_SIZE));
return 0;
}
core_initcall(m68k_mem_malloc_init);

110
arch/m68k/lib/m68k-module.c
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@ -1,110 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Moduleloader Subsystem
*
* These relocation stubs are taken from Linux 2.6.10 They are used by the
* higher level ELF loader code to place ELF files to arbitrary addresses.
*/
#include <common.h>
#include <elf.h>
#include <module.h>
#include <errno.h>
int apply_relocate(Elf32_Shdr *sechdrs,
const char *strtab,
unsigned int symindex,
unsigned int relsec,
struct module *me)
{
unsigned int i;
Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr;
Elf32_Sym *sym;
uint32_t *location;
DEBUGP("Applying relocate section %u to %u\n", relsec,
sechdrs[relsec].sh_info);
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
/* This is where to make the change */
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+ rel[i].r_offset;
/* This is the symbol it is referring to. Note that all
undefined symbols have been resolved. */
sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
+ ELF32_R_SYM(rel[i].r_info);
switch (ELF32_R_TYPE(rel[i].r_info)) {
case R_68K_32:
/* We add the value into the location given */
*location += sym->st_value;
break;
case R_68K_PC32:
/* Add the value, subtract its postition */
*location += sym->st_value - (uint32_t)location;
break;
default:
printk(KERN_ERR "module %s: Unknown relocation: %u\n",
me->name, ELF32_R_TYPE(rel[i].r_info));
return -ENOEXEC;
}
}
return 0;
}
int apply_relocate_add(Elf32_Shdr *sechdrs,
const char *strtab,
unsigned int symindex,
unsigned int relsec,
struct module *me)
{
unsigned int i;
Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
Elf32_Sym *sym;
uint32_t *location;
DEBUGP("Applying relocate_add section %u to %u\n", relsec,
sechdrs[relsec].sh_info);
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
/* This is where to make the change */
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+ rel[i].r_offset;
/* This is the symbol it is referring to. Note that all
undefined symbols have been resolved. */
sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
+ ELF32_R_SYM(rel[i].r_info);
switch (ELF32_R_TYPE(rel[i].r_info)) {
case R_68K_32:
/* We add the value into the location given */
*location = rel[i].r_addend + sym->st_value;
break;
case R_68K_PC32:
/* Add the value, subtract its postition */
*location = rel[i].r_addend + sym->st_value - (uint32_t)location;
break;
default:
printk(KERN_ERR "module %s: Unknown relocation: %u\n",
me->name, ELF32_R_TYPE(rel[i].r_info));
return -ENOEXEC;
}
}
return 0;
}

39
arch/m68k/mach-mcfv4e.dox
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@ -1,39 +0,0 @@
/* This document is intended to provide the developer with information
* how to integrate a new CPU (MACH) into this part of the barebox tree
*/
/** @page dev_m68k_mach M68k/Coldfire based CPU (MACH) into the tree
FIXME - fill in further info about Coldfire and so on. Check code
for compliance with the specs given below - move code otherwise.
@par What's happens when the reset signal is gone
@note Code running immediately after reset runs at an address it is not linked
to: "runtime address != link address". You should only use branches and
do not refer to fixed data. This implies the use of assembler code only.
The M68k CPU starts at lable \<reset\> in one of the corresponding start-*.S
files. After some basic hardware setup it can call a function
\<arch_init_lowlevel\> if not disabled. This call is intended to give all
developers a chance to use a standard reset vector file, but also do some
special things required only on their specific CPU.
After handling some MMU, Stack or similiar issues, \<board_init_lowlevel\> can
be called (if not disabled). This is a board specific function for SDRAM setup
for example. As its board specific, your can do whatever you need to bring
your board up. As stack is already set to internal core RAM, this routine can
be C.
@note: You are not allowed to call other code here, because we are not running
at link address.
When \<board_init_lowlevel\> returns it will be assumed that there is now
working RAM that can be used for all further steps.
Next step is relocation of barebox itself. It gets copied to the end of
available RAM and the last assembly instruction is a jump to \<start_barebox\>.
At this point of time: "runtime address == link address".
*/

18
arch/m68k/mach-mcfv4e/Kconfig
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@ -1,18 +0,0 @@
menu "M68k/Coldfire V4E specific settings"
config COPY_LOWMEM_VECTORS
bool "Copy vectors to SDRAM address 0"
default y
help
This copies the vector table to SDRAM address 0 (default address)
config USE_LOWMEM_VECTORS
bool "Use vectors at SDRAM address 0"
default n
depends on COPY_LOWMEM_VECTORS
help
This copies the vector table to SDRAM address 0 (default address) and
also uses this vector location
endmenu

19
arch/m68k/mach-mcfv4e/Makefile
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@ -1,19 +0,0 @@
#
# Generic code for Coldfire V4E targets (MCF547x/MCF548x)
#
obj-y += mcf_clocksource.o
obj-y += mcf_reset_cpu.o
#
# FEC support
#
obj-y += multichannel_dma.o
obj-y += dma_utils.o
obj-y += fec.o
obj-y += fecbd.o
#
# FreeScale MultiDMA Library
#
obj-y += mcdapi/
obj-y += net/

502
arch/m68k/mach-mcfv4e/dma_utils.c
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@ -1,502 +0,0 @@
/*
* File: dma_utils.c
* Purpose: General purpose utilities for the multi-channel DMA
*
* Notes: The methodology used in these utilities assumes that
* no single initiator will be tied to more than one
* task/channel
*/
#include <common.h>
#include <init.h>
#include <linux/types.h>
#include <mach/mcf54xx-regs.h>
#include <proc/mcdapi/MCD_dma.h>
#include <proc/dma_utils.h>
/*
* This global keeps track of which initiators have been
* used of the available assignments. Initiators 0-15 are
* hardwired. Initiators 16-31 are multiplexed and controlled
* via the Initiatior Mux Control Registe (IMCR). The
* assigned requestor is stored with the associated initiator
* number.
*/
static int8_t used_reqs[32] =
{
DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0,
DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1,
DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX,
DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0
};
/*
* This global keeps track of which channels have been assigned
* to tasks. This methology assumes that no single initiator
* will be tied to more than one task/channel
*/
typedef struct
{
int req;
void (*handler)(void);
} DMA_CHANNEL_STRUCT;
static DMA_CHANNEL_STRUCT dma_channel[NCHANNELS] =
{
{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}
};
/*
* Enable all DMA interrupts
*
* Parameters:
* pri Interrupt Priority
* lvl Interrupt Level
*/
void
dma_irq_enable(uint8_t lvl, uint8_t pri)
{
//FIXME ASSERT(lvl > 0 && lvl < 8);
//FIXME ASSERT(pri < 8);
/* Setup the DMA ICR (#48) */
MCF_INTC_ICR48 = 0
| MCF_INTC_ICRn_IP(pri)
| MCF_INTC_ICRn_IL(lvl);
/* Unmask all task interrupts */
MCF_DMA_DIMR = 0;
/* Clear the interrupt pending register */
MCF_DMA_DIPR = 0;
/* Unmask the DMA interrupt in the interrupt controller */
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
}
/*
* Disable all DMA interrupts
*/
void
dma_irq_disable(void)
{
/* Mask all task interrupts */
MCF_DMA_DIMR = (uint32_t)~0;
/* Clear any pending task interrupts */
MCF_DMA_DIPR = (uint32_t)~0;
/* Mask the DMA interrupt in the interrupt controller */
MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
}
/*
* Attempt to enable the provided Initiator in the Initiator
* Mux Control Register
*
* Parameters:
* initiator Initiator identifier
*
* Return Value:
* 1 if unable to make the assignment
* 0 successful
*/
int
dma_set_initiator(int initiator)
{
switch (initiator)
{
/* These initiators are always active */
case DMA_ALWAYS:
case DMA_DSPI_RX:
case DMA_DSPI_TX:
case DMA_DREQ0:
case DMA_PSC0_RX:
case DMA_PSC0_TX:
case DMA_USBEP0:
case DMA_USBEP1:
case DMA_USBEP2:
case DMA_USBEP3:
case DMA_PCI_TX:
case DMA_PCI_RX:
case DMA_PSC1_RX:
case DMA_PSC1_TX:
case DMA_I2C_RX:
case DMA_I2C_TX:
break;
case DMA_FEC0_RX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3))
| MCF_DMA_IMCR_SRC16_FEC0RX;
used_reqs[16] = DMA_FEC0_RX;
break;
case DMA_FEC0_TX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3))
| MCF_DMA_IMCR_SRC17_FEC0TX;
used_reqs[17] = DMA_FEC0_TX;
break;
case DMA_FEC1_RX:
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3))
| MCF_DMA_IMCR_SRC20_FEC1RX;
used_reqs[20] = DMA_FEC1_RX;
break;
case DMA_FEC1_TX:
if (used_reqs[21] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
| MCF_DMA_IMCR_SRC21_FEC1TX;
used_reqs[21] = DMA_FEC1_TX;
}
else if (used_reqs[25] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
| MCF_DMA_IMCR_SRC25_FEC1TX;
used_reqs[25] = DMA_FEC1_TX;
}
else if (used_reqs[31] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_FEC1TX;
used_reqs[31] = DMA_FEC1_TX;
}
else /* No empty slots */
return 1;
break;
case DMA_DREQ1:
if (used_reqs[29] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_DREQ1;
used_reqs[29] = DMA_DREQ1;
}
else if (used_reqs[21] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
| MCF_DMA_IMCR_SRC21_DREQ1;
used_reqs[21] = DMA_DREQ1;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM0:
if (used_reqs[24] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3))
| MCF_DMA_IMCR_SRC24_CTM0;
used_reqs[24] = DMA_CTM0;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM1:
if (used_reqs[25] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
| MCF_DMA_IMCR_SRC25_CTM1;
used_reqs[25] = DMA_CTM1;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM2:
if (used_reqs[26] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
| MCF_DMA_IMCR_SRC26_CTM2;
used_reqs[26] = DMA_CTM2;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM3:
if (used_reqs[27] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
| MCF_DMA_IMCR_SRC27_CTM3;
used_reqs[27] = DMA_CTM3;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM4:
if (used_reqs[28] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_CTM4;
used_reqs[28] = DMA_CTM4;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM5:
if (used_reqs[29] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_CTM5;
used_reqs[29] = DMA_CTM5;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM6:
if (used_reqs[30] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
| MCF_DMA_IMCR_SRC30_CTM6;
used_reqs[30] = DMA_CTM6;
}
else /* No empty slots */
return 1;
break;
case DMA_CTM7:
if (used_reqs[31] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_CTM7;
used_reqs[31] = DMA_CTM7;
}
else /* No empty slots */
return 1;
break;
case DMA_USBEP4:
if (used_reqs[26] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
| MCF_DMA_IMCR_SRC26_USBEP4;
used_reqs[26] = DMA_USBEP4;
}
else /* No empty slots */
return 1;
break;
case DMA_USBEP5:
if (used_reqs[27] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
| MCF_DMA_IMCR_SRC27_USBEP5;
used_reqs[27] = DMA_USBEP5;
}
else /* No empty slots */
return 1;
break;
case DMA_USBEP6:
if (used_reqs[28] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_USBEP6;
used_reqs[28] = DMA_USBEP6;
}
else /* No empty slots */
return 1;
break;
case DMA_PSC2_RX:
if (used_reqs[28] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
| MCF_DMA_IMCR_SRC28_PSC2RX;
used_reqs[28] = DMA_PSC2_RX;
}
else /* No empty slots */
return 1;
break;
case DMA_PSC2_TX:
if (used_reqs[29] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
| MCF_DMA_IMCR_SRC29_PSC2TX;
used_reqs[29] = DMA_PSC2_TX;
}
else /* No empty slots */
return 1;
break;
case DMA_PSC3_RX:
if (used_reqs[30] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
| MCF_DMA_IMCR_SRC30_PSC3RX;
used_reqs[30] = DMA_PSC3_RX;
}
else /* No empty slots */
return 1;
break;
case DMA_PSC3_TX:
if (used_reqs[31] == 0)
{
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
| MCF_DMA_IMCR_SRC31_PSC3TX;
used_reqs[31] = DMA_PSC3_TX;
}
else /* No empty slots */
return 1;
break;
default:
return 1;
}
return 0;
}
/*
* Return the initiator number for the given requestor
*
* Parameters:
* requestor Initiator/Requestor identifier
*
* Return Value:
* The initiator number (0-31) if initiator has been assigned
* 0 (always initiator) otherwise
*/
uint32_t
dma_get_initiator(int requestor)
{
uint32_t i;
for (i=0; i<sizeof(used_reqs); ++i)
{
if (used_reqs[i] == requestor)
return i;
}
return 0;
}
/*
* Remove the given initiator from the active list
*
* Parameters:
* requestor Initiator/Requestor identifier
*/
void
dma_free_initiator(int requestor)
{
uint32_t i;
for (i=16; i<sizeof(used_reqs); ++i)
{
if (used_reqs[i] == requestor)
{
used_reqs[i] = 0;
break;
}
}
}
/*
* Attempt to find an available channel and mark it as used
*
* Parameters:
* requestor Initiator/Requestor identifier
*
* Return Value:
* First available channel or -1 if they are all occupied
*/
int
dma_set_channel(int requestor, void (*handler)(void))
{
int i;
/* Check to see if this requestor is already assigned to a channel */
if ((i = dma_get_channel(requestor)) != -1)
return i;
for (i=0; i<NCHANNELS; ++i)
{
if (dma_channel[i].req == -1)
{
dma_channel[i].req = requestor;
dma_channel[i].handler = handler;
return i;
}
}
/* All channels taken */
return -1;
}
/*
* Return the channel being initiated by the given requestor
*
* Parameters:
* requestor Initiator/Requestor identifier
*
* Return Value:
* Channel that the requestor is controlling or -1 if hasn't been
* activated
*/
int
dma_get_channel(int requestor)
{
uint32_t i;
for (i=0; i<NCHANNELS; ++i)
{
if (dma_channel[i].req == requestor)
return i;
}
return -1;
}
/*
* Remove the channel being initiated by the given requestor from
* the active list
*
* Parameters:
* requestor Initiator/Requestor identifier
*/
void
dma_free_channel(int requestor)
{
uint32_t i;
for (i=0; i<NCHANNELS; ++i)
{
if (dma_channel[i].req == requestor)
{
dma_channel[i].req = -1;
dma_channel[i].handler = NULL;
break;
}
}
}
/*
* This is the catch-all interrupt handler for the mult-channel DMA
*/
int
dma_interrupt_handler (void *arg1, void *arg2)
{
uint32_t i, interrupts;
(void)arg1;
(void)arg2;
disable_interrupts(); // was: board_irq_disable();
/*
* Determine which interrupt(s) triggered by AND'ing the
* pending interrupts with those that aren't masked.
*/
interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
/* Make sure we are here for a reason */
// ASSERT(interrupts != 0);
/* Clear the interrupt in the pending register */
MCF_DMA_DIPR = interrupts;
for (i=0; i<16; ++i, interrupts>>=1)
{
if (interrupts & 0x1)
{
/* If there is a handler, call it */
if (dma_channel[i].handler != NULL)
dma_channel[i].handler();
}
}
enable_interrupts(); // board_irq_enable();
return 1;
}

1440
arch/m68k/mach-mcfv4e/fec.c
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File diff suppressed because it is too large Load Diff

232
arch/m68k/mach-mcfv4e/fecbd.c
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@ -1,232 +0,0 @@
/*
* File: fecbd.c
* Purpose: Provide a simple buffer management driver
*
* Notes:
*/
#include <common.h>
#include <linux/types.h>
#include <mach/mcf54xx-regs.h>
#include <proc/mcdapi/MCD_dma.h>
#include <proc/net/net.h>
#include <proc/fecbd.h>
#include <proc/fec.h>
#include <proc/dma_utils.h>
#define ASSERT(x) if (!(x)) hang();
/*
* This implements a simple static buffer descriptor
* ring for each channel and each direction
*
* FEC Buffer Descriptors need to be aligned to a 4-byte boundary.
* In order to accomplish this, data is over-allocated and manually
* aligned at runtime
*
* Enough space is allocated for each of the two FEC channels to have
* NRXBD Rx BDs and NTXBD Tx BDs
*
*/
FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1];
/*
* These pointers are used to reference into the chunck of data set
* aside for buffer descriptors
*/
FECBD *RxBD;
FECBD *TxBD;
/*
* Macros to easier access to the BD ring
*/
#define RxBD(ch,i) RxBD[(ch * NRXBD) + i]
#define TxBD(ch,i) TxBD[(ch * NTXBD) + i]
/*
* Buffer descriptor indexes
*/
static int iTxbd_new;
static int iTxbd_old;
static int iRxbd;
/*
* Initialize the FEC Buffer Descriptor ring
* Buffer Descriptor format is defined by the MCDAPI
*
* Parameters:
* ch FEC channel
*/
void
fecbd_init(uint8_t ch)
{
NBUF *nbuf;
int i;
/*
* Align Buffer Descriptors to 4-byte boundary
*/
RxBD = (FECBD *)(((int)unaligned_bds + 3) & 0xFFFFFFFC);
TxBD = (FECBD *)((int)RxBD + (sizeof(FECBD) * 2 * NRXBD));
/*
* Initialize the Rx Buffer Descriptor ring
*/
for (i = 0; i < NRXBD; ++i)
{
/* Grab a network buffer from the free list */
nbuf = nbuf_alloc();
ASSERT(nbuf);
/* Initialize the BD */
RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
RxBD(ch,i).length = RX_BUF_SZ;
RxBD(ch,i).data = nbuf->data;
/* Add the network buffer to the Rx queue */
nbuf_add(NBUF_RX_RING, nbuf);
}
/*
* Set the WRAP bit on the last one
*/
RxBD(ch,i-1).status |= RX_BD_W;
/*
* Initialize the Tx Buffer Descriptor ring
*/
for (i = 0; i < NTXBD; ++i)
{
TxBD(ch,i).status = TX_BD_INTERRUPT;
TxBD(ch,i).length = 0;
TxBD(ch,i).data = NULL;
}
/*
* Set the WRAP bit on the last one
*/
TxBD(ch,i-1).status |= TX_BD_W;
/*
* Initialize the buffer descriptor indexes
*/
iTxbd_new = iTxbd_old = iRxbd = 0;
}
void
fecbd_dump(uint8_t ch)
{
#ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG
int i;
printf("\n------------ FEC%d BDs -----------\n",ch);
printf("RxBD Ring\n");
for (i=0; i<NRXBD; i++)
{
printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &RxBD(ch,i),
RxBD(ch,i).status,
RxBD(ch,i).length,
RxBD(ch,i).data);
}
printf("TxBD Ring\n");
for (i=0; i<NTXBD; i++)
{
printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &TxBD(ch,i),
TxBD(ch,i).status,
TxBD(ch,i).length,
TxBD(ch,i).data);
}
printf("--------------------------------\n\n");
#endif
}
/*
* Return the address of the first buffer descriptor in the ring.
*
* Parameters:
* ch FEC channel
* direction Rx or Tx Macro
*
* Return Value:
* The start address of the selected Buffer Descriptor ring
*/
uint32_t
fecbd_get_start(uint8_t ch, uint8_t direction)
{
switch (direction)
{
case Rx:
return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
case Tx:
default:
return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
}
}
FECBD *
fecbd_rx_alloc(uint8_t ch)
{
int i = iRxbd;
/* Check to see if the ring of BDs is full */
if (RxBD(ch,i).status & RX_BD_E)
return NULL;
/* Increment the circular index */
iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
return &RxBD(ch,i);
}
/*
* This function keeps track of the next available Tx BD in the ring
*
* Parameters:
* ch FEC channel
*
* Return Value:
* Pointer to next available buffer descriptor.
* NULL if the BD ring is full
*/
FECBD *
fecbd_tx_alloc(uint8_t ch)
{
int i = iTxbd_new;
/* Check to see if the ring of BDs is full */
if (TxBD(ch,i).status & TX_BD_R)
return NULL;
/* Increment the circular index */
iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
return &TxBD(ch,i);
}
/*
* This function keeps track of the Tx BDs that have already been
* processed by the FEC
*
* Parameters:
* ch FEC channel
*
* Return Value:
* Pointer to the oldest buffer descriptor that has already been sent
* by the FEC, NULL if the BD ring is empty
*/
FECBD *
fecbd_tx_free(uint8_t ch)
{
int i = iTxbd_old;
/* Check to see if the ring of BDs is empty */
if ((TxBD(ch,i).data == NULL) || (TxBD(ch,i).status & TX_BD_R))
return NULL;
/* Increment the circular index */
iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
return &TxBD(ch,i);
}

30
arch/m68k/mach-mcfv4e/include/mach/clocks.h
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@ -1,30 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* This File contains functions to query clock settings for the actual
* board.
*/
#ifndef __ASM_ARCH_CLOCKS_H
#define __ASM_ARCH_CLOCKS_H
ulong mcfv4e_get_bus_clk(void);
#endif /* __ASM_ARCH_CLOCKS_H */

33
arch/m68k/mach-mcfv4e/include/mach/debug_ll.h
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@ -1,33 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* This File contains declaration for early output support
*/
#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
#define __INCLUDE_ARCH_DEBUG_LL_H__
extern __inline__ void putc( char ch )
{
//extern int early_console_putc( char ch);
early_console_putc(NULL,ch);
}
#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */

33
arch/m68k/mach-mcfv4e/include/mach/hardware.h
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@ -1,33 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* This File contains declaration for early output support
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
#include <sizes.h>
#ifdef CONFIG_ARCH_MCF54xx
#include "mcf54xx-regs.h"
#endif
#endif /* __ASM_ARCH_HARDWARE_H__ */

30
arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h
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@ -1,30 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* This File contains declaration for early output support
*/
#ifndef __MCF54xx_REGS_H__
#define __MCF54xx_REGS_H__
/* System Registers for V4E cores (MCF547x and MCF548x) */
#include <asm/coldfire/mcf5xxx.h>
#endif /* __MCF54xx_REGS_H__ */

80
arch/m68k/mach-mcfv4e/include/proc/dma_utils.h
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@ -1,80 +0,0 @@
/*
* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
* See file CREDITS for list of people who contributed to this project.
*
* This file is part of barebox.
*
* barebox is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* barebox is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with barebox. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
* Declaration of support function used with the MultiChannel DMA
*/
#ifndef _DMA_UTILS_H_
#define _DMA_UTILS_H_
void dma_irq_enable(uint8_t, uint8_t);
void dma_irq_disable(void);
int dma_set_initiator(int);
uint32_t dma_get_initiator(int);
void dma_free_initiator(int);
int dma_set_channel(int, void (*)(void));
int dma_get_channel(int);
void dma_free_channel(int);
int dma_interrupt_handler(void *, void *);
/*
* Create identifiers for each initiator/requestor
*/
#define DMA_ALWAYS (0)
#define DMA_DSPI_RX (1)
#define DMA_DSPI_TX (2)
#define DMA_DREQ0 (3)
#define DMA_PSC0_RX (4)
#define DMA_PSC0_TX (5)
#define DMA_USBEP0 (6)
#define DMA_USBEP1 (7)
#define DMA_USBEP2 (8)
#define DMA_USBEP3 (9)
#define DMA_PCI_TX (10)
#define DMA_PCI_RX (11)
#define DMA_PSC1_RX (12)
#define DMA_PSC1_TX (13)
#define DMA_I2C_RX (14)
#define DMA_I2C_TX (15)
#define DMA_FEC0_RX (16)
#define DMA_FEC0_TX (17)
#define DMA_FEC1_RX (18)
#define DMA_FEC1_TX (19)
#define DMA_DREQ1 (20)
#define DMA_CTM0 (21)
#define DMA_CTM1 (22)
#define DMA_CTM2 (23)
#define DMA_CTM3 (24)
#define DMA_CTM4 (25)
#define DMA_CTM5 (26)
#define DMA_CTM6 (27)
#define DMA_CTM7 (28)
#define DMA_USBEP4 (29)
#define DMA_USBEP5 (30)
#define DMA_USBEP6 (31)
#define DMA_PSC2_RX (32)
#define DMA_PSC2_TX (33)
#define DMA_PSC3_RX (34)
#define DMA_PSC3_TX (35)
#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
#endif /* _DMA_UTILS_H_ */

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