As the real value is 2^p a input value of 0 is
actually valid.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegra124 extended the mux by 1bit to allow for
more PLL sources.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some peripherals have a double wide divider in front
of them.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that we have a proper reset controller, it
isn't necessary anymore to keep the device reset
hack coupled to the clock.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The console devices are the only ones that can't
use the reset controller properly, as they get
registered from platform code. Reset those devices
from the clock controller.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows us to drop the hack in the clock controller
and implement proper reset at device level.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Clock gates having the CLK_GATE_HIWORD_MASK flag set use the upper 16
bits of the register as a "write enable" mask for the value in the
lower 16 bits.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To avoid code duplication and make easier to introduce new flags.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegra3 has some new clocks and resets. The new
registers don't form a linear range with the
old ones.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This most likely doesn't fix any real bugs, but it's the
right thing to do and reduces the noise level with static
checkers.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows to make relationship between DT and driver
more explicit and avoids duplication.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This updates the clk-divider to Kernel code, but without power-of-two
divider support which we do not need yet. This also adds table based
divider support to the divider.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
drivers/clk/clk-divider-table.c:81:16: warning: symbol 'clk_divider_table_ops' was not declared. Should it be static?
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
drivers/clk/clk-gate.c:79:16: warning: symbol 'clk_gate_ops' was not declared. Should it be static?
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
drivers/clk/clk-mux.c:53:16: warning: symbol 'clk_mux_ops' was not declared. Should it be static?
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
drivers/clk/clk-fixed-factor.c:38:16: warning: symbol 'clk_fixed_factor_ops' was not declared. Should it be static?
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
drivers/clk/clk-fixed.c:35:16: warning: symbol 'clk_fixed_ops' was not declared. Should it be static?
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a DT init function to clk-fixed and corresponding CLK_OF_DECLARE
to put it into the DT clock provider table.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This add barebox versions of of_clk_init for parsing and registering
clock providers from DT. Also, a macro CLK_OF_DECLARE is added, that
allows to put init callbacks into its own section that can be linked
in the binary.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The SoCFPGA currently has all clocks described in the devicetree which
makes common clock support a straight forward task.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
since the switch to common clock, ethernet driver doesn't works and
and access to the network leads to :
eth0: Read MDIO failed...
unable to handle NULL pointer dereference at address 0x000000c7
The problem is that bit 31 (SLEEP) of register HW_CLKCTRL_ENET is kept
to its default value (1) which means : "put Ethernet block in sleep mode.
CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET0(1)_TX are gated off.
Ethernet can be wakeup remotely in sleep mode"
In that case the FEC don't get its clock.
This patch fix the problem by toggling this bit when FEC's clock is
enabled.
Tested on i.MX28EVK.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds of_clk_providers for core clocks and clock gates found on
Marvell MVEBU SoCs (Armada 370, Armada XP, Dove, and Kirkwood).
It is based on Linux clock providers with clock flags removed, as they
are not used on Barebox.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format.
No functional changes.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When changing the rates of the ssp clocks we have to poll the
busy bit, but only when they are enabled. The current code can
not check this properly since the gates are registered as children
of the dividers. This has the effect that when the gate is disabled
the busy bit will be set forever resulting in a freezed system.
Fix this by making the gates parents of the dividers which allows
clk_is_enabled to return the correct result.
The Kernel has the same problem, but here the busy polling is
limited to 10ms, so probably noone noticed this.
The datasheet mentions that the ssp dividers shall only be changed
when the clocks are enabled. The kernel and barebox currently ignore
this. I don't know what effect violating this rule has.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sebastian Hesselbarth
Lucas Stach
Sascha Hauer
Beniamino Galvani
Antony Pavlov
Alexander Shiyan
Eric Bénard