The fec has multiple clock inputs:
- 50MHz clock for generating the (R)MII clock
- bus clock
The MDIO clock is derived from the bus clock, not the 50MHz clock,
so pass this into the driver so that it can correctly configure
the MDIO clock divider.
This fixes several wrong MDIO register read problems on i.MX28 boards.
Reported-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds the glue code for the i.MX SATA controller. This controller
needs some i.MX specific setup and some SoC specific setting outside
the controller itself. The code for setting up the correct clock source
for the SATA phy has been taken from U-Boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds ahci controller support based on U-Boot ahci support. Unlike
U-Boot we do not push the SCSI layer in between, but use the ata interface
directly. Tested on a Freescale i.MX53.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ATA devices using DMA may need a sufficiently aligned buffer, so use
dma_alloc instead of regular malloc.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently we only support oldschool IDE SFF devices. This is done
by registering a register layout struct and everything else is done
by the generic IDE SFF driver. Since modern ATA devices still use
ATA, but not the SFF interface anymore, split out the IDE SFF support
to a separate file to allow for other types of ata interfaces.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some status flags are wrong, fix them. All of them are currently unused,
so no functional change included.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Using /dev/disk* for every type of device is not helpful. It increases
the chance that the user doesn't know which file corresponds to which
device. So rename ata device files to /dev/ata*. Also add a dev_info
about which device just has been registered.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
mtd->write is supposed to loop around pages internally, no need
to do this in mtd_write. This fixes a huge write performance drop
with the m25p80 driver when it was converted to a mtd driver recently.
Since mtd->writesize is 1 for this driver mtd_write ended up doing
single byte writes on the flash.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The nand layer handles partial page writes just fine. If the start or
end of the data is not page aligned, the nand layer will copy the data
to a temporary page buffer.
Remove the check which disallows partial page writes since this is what
we want to do on barebox when for example an image is written to nand
which is not padded to page size.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Straight forward driver, we only have to configure some additional
bits and then use the generic ide support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for the Garz+Fricke Vincell board. This has
a i.MX53 Processor with 512MB of DDR3 RAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for initializing DDR3 RAMs on the i.MX53 type
SDRAM controller. The code automatically detects size/layout of
the connected RAM, detects the bus width and which chipselects are
populated.
While I believe this code is not 100% generic, it is far too
sophisticated to stay in a single board directory. I'm sure
other boards could make use of this aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pll setup function is exported, so it makes sense to export
the convenience wrappers for specific frequencies aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards do not have a DCD table since they initialize everything
in code, so allow to skip it and leave the corresponding pointers
empty.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The code initializing the SDRAM controller is not at the same
place where SDRAM is registered with barebox. To reduce the
risk of registering wrong SDRAM sizes this patch adds a
driver for the ESDCTL which reads back the configured SDRAM
size and registers the memory found with barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In recent reference manuals the plls were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ethernet PLL has a fixed frequency of 500MHz. What is adjustable
are additional dividers which we better describe separately.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It could happen (1 out of 100 times) that NAND did not start up
correctly after warm rebooting, so barebox could not find its
environment or DMA timed out due to a stalled BCH. When resetting BCH
together with GPMI, the issue could not be observed anymore. We probably
need the consistent state already before sending commands to NAND.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
During card probe the mci core may send commands to the card
which the card doesn't understand. This is intended, so do not
print an error message here.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add and use meaningful macro names for OMAP4 GPIO addresses, and add a
comment to explain the 0x100 offset for OMAP4.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In addition, collapse adjacent comment blocks into one and remove
extraneous blank lines.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds lowlevel debug functions for i.MX. As we have a great variety
of different UARTs on i.MX currently no Kconfig support for chosing the
correct one is added. Instead we expect the user to add the correct
define and issue a compiler warning if he hasn't.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Wolfram Sang
Antony Pavlov
Fabio Porcedda
Robert P. J. Day
Jan Luebbe