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11 Commits

Author SHA1 Message Date
Lucas Stach acbecd1987 ARM: tegra30: slow down CPU to 600 MHz
It's not safe to ramp up the CPU clock speed to
1,4 GHz on all T30 SKUs, as this may result in failure
to start the kernel properly. Start CPU at 600 MHz,
which is safe even for the slowest SKUs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-08 09:35:50 +02:00
Lucas Stach 0fe976103e tegra: source MSELECT clock from CLK_M
We need to reprogram PLL_P at a later time, so
we have to make sure MSELECT is able to operate
correctly when we stop PLL_P.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach df1d5326a9 tegra: add Tegra3 startup
Sets up MSELECT to let main CPUs talk to peripheral devices and starts
high performance A9 CPU cluster.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-02-27 10:42:09 +01:00
Lucas Stach 880869e55f tegra: set AHB clock rate early
Avoids glitches in later starup phases.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-02-27 10:42:09 +01:00
Lucas Stach af155f74aa tegra: add lowlevel delay function
For proper startup we need to give clocks and IO signals some time to
stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit
pickier.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-02-19 11:03:48 +01:00
Lucas Stach c50a17104c tegra: fix fallout from relocatable code changes in PLLX init
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-12-04 14:59:39 +01:00
Lucas Stach f93b5f8eb9 tegra: switch to multi image
To keep things clean I removed all support for the old way to build
images. There is now a single tegra_v7 defconfig which builds both
supported Tegra boards as images.
The new image generation also paves the way for integration of the
tegra-cbootimage tool to produce directly flashable images.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-10-02 10:24:05 +02:00
Lucas Stach c05a80c825 tegra: fix PBL build
Drop useless BUG(), we are too early for them to be of any use.
Make sure we build the AVP code as ARMv4 even in PBL case.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-10-02 10:24:04 +02:00
Lucas Stach 02568520ee tegra: start maincomplex execution at correct offset
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-10-02 10:24:04 +02:00
Lucas Stach acc791fb10 tegra: deduplicate clk defines
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-07-02 08:36:09 +02:00
Lucas Stach 789c55b8bd tegra: add common lowlevel startup
All Tegra20 boards have a common startup sequence. Also there is an
agreement on how to find out about the installed amount of RAM and other
information needed by early startup. So as there is really no need to do
any lowlevel stuff per board, we can just do it at the ARCH level.

This also enables the first stage loading of barebox by detecting the
currently running CPU and booting the main CPU cluster if neccesary.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-04-14 10:45:24 +02:00