Code-paths responsible for initializing CPU's stack pointer and variable
used in stack memory resource reservation got out of sync which resulted
in actual stack being 64K off from what "stack" struct resource
registered by arm_request_stack() thought it was.
At least one issue resulting from that can be easily triggered by
running:
memtest -t
This commit unifies the aforementioned code to a certain degree which
solves the problem and hopefuly makes it less likely to become an issue
again.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
PBL is another feature, which needs some love to work on ARM64.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We don't yet have an implementation for those two features on ARM64, so move
them to a place where they are only selected for a 32bit barebox.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current ARM64 lowlevel code needs the exception vector to set
up all the ELs. Select ARM_EXCEPTIONS to make sure this is always
present.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arm_mem_barebox_image() is used to pick a suitable place where to
put the final image to. This is called from both the PBL uncompression
code and also from the final image. To make it work properly it is
crucial that it's called with the same arguments both times. Currently
it is called with the wrong image size from the PBL uncompression code.
The size passed to arm_mem_barebox_image() has to be the size of the
whole uncompressed image including the BSS segment size. The PBL code
calls it with the compressed image size instead and without the BSS
segment. This patch fixes this by reading the uncompressed image size
from the compressed binary (the uncompressed size is appended to the
end of the compressed binary by our compression wrappers). The size
of the BSS segment is unknown though by the PBL uncompression code,
so we introduce a maximum BSS size which is used instead.
The code before this patch worked by accident because the base address
of the final image was aligned down to a 1MiB boundary. The alignment
was sufficient already to make enough space. This breaks though when
the uncompressed image including BSS becomes bigger than 1MiB while
the compressed image is smaller.
Fixes: 65071bd0: arm: Clarify memory layout calculation
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Of_unflatten_dtb returns a ERR_PTR value so checking it against NULL is
incorrect. Fix it in all of the places where this was happening.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The second level page tables can only start at a 1MiB section boundary,
so instead of calling arm_create_pte() with the high vector address
(which is 0xffff0000, not 1MiB aligned) we have to call it with
0xfff00000 to correctly create a second level page table.
The old values broke SoCs which have peripherals in the upper 1MiB
area, like for example the Atmel AT91RM9200. On these Socs we correctly
created the vector page, but the pages around it did not have a 1:1
mapping anymore which led to unreachable peripherals.
Fixes: f6b77fe9: ARM: Rework vector table setup
Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Peter Kardos <kardos.peter.sk@gmail.com>
This commit adds basic mmu support, ie:
- DMA cache handling is not supported
- Remapping memory region also
The current mmu setting is:
- 4KB granularity
- 3 level lookup (skipping L0)
- 33 bits per VA
This is based on coreboot and u-boot mmu configuration.
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Enclosed by #if directive OMAP specific code
and mmu_disable (ARMv8 code will implemented it somewhere else).
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds arm64 specific codes, which are:
- exception support
- cache support
- rework Makefile to support arm64
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
No need anymore to store arm_head_bottom globally as it's only used
in barebox_non_pbl_start(). Also rename the variable to malloc_end
which is more meaningful.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We already have a pointer for barebox_boarddata, so use it to
request the corresponding SDRAM region instead of calculating
it again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox_boarddata should stay the original boarddata and not
be modified. Keep a local pointer in barebox_arm_boot_dtb()
instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current vector table setup has some shortcomings. First of all
currently the case when the high vectors are inside SDRAM (that is,
SDRAM reaches the end of the address space) is not supported. In this
case we create a secondary page table for the section containing the
vectors which gets overwritten by the general SDRAM secondary page
table entries creation afterwards. On ARMv7 and later the exception
table setup can be improved: Here the vector table address is configurable
in the VBAR register. We can use this register to skip remapping the
vector table.
With this patch we first try to use the VBAR register before doing
something else. Also, when we have to use the high vectors we first
try a request_sdram_region to test if the vector table memory is already
mapped. While at it sprinkle some comments into the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The last 64KiB of address space may be used for the vector table at
0xffff0000, so we cannot use it for barebox. The easiest way to archieve
this is to never use the last 64KiB of memory.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When SDRAM reaches to the end of the address space the comparison
membase + memsize evaluates to 0, so pc - membase < memsize can never
be true. Fix this by substracting membase on both sides of the
comparison.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a re-application of fix 17644b55.
arm_cpu_lowlevel_init() will set the processor mode to 0x13 (supervisor).
When this function is entered via a different processor mode, register
banking will happen to lr (r14), resulting in an invalid return address.
This fix will preserve the return address manually.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add code necessary for correct initialization of exception vector
table when MMU is disabled.
Note: Only ARMv7 support is implemented
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add code to make sure that normal vector exception table, when it is
used due to unavailability of the high vector table, was not re-mapped
from 0x0 via VBAR by someone else before us.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
RAMOOPS is a driver that uses a reserved static memory region to store
the data from the last panic or boot. This helps to debug crashes at the
next boot while preserving the boot messages.
To guarantee a memory area that is not altered by barebox or the kernel,
this area is located at the end of the RAM right after barebox and
before the STACK. This ensures that changing barebox sizes do not
interfere with RAMOOPS.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This helps to understand and find problems with the memory layout of
barebox. It adds another entry for the board data that barebox
allocated.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The memory calculations used are all hardcoded into three different
files, start-pbl.c, uncompress.c and start.c. To make this more readable
and reliable, this patch gathers these information in barebox-arm.h with
static inline functions for the calculation of the memory offsets.
This patch also adds proper handling of different barebox/board data
sizes. Currently only 1MB+Alignment of RAM is reserved for Barebox and
board data. This could be too small for bigger devicetrees and barebox.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit 104a6a7ccf support was added
for Thumb2. It added do_execute() as a way to provide arch dependent
calling veneers for use in "go" and thumb2_execute() as the thumb2 to
arm veneer.
But thumb2_execute() isn't necessary as gcc generates a proper calling
sequence from a standard function pointer call. Thumb2 barebox is
compiled with the AAPCS ABI which requires this.
It also had a bug and didn't pass the arguments properly, but code
execute via "go" rarely uses arguments so this wasn't very noticeable.
Since thumb2 was always the only user of do_execute(), go ahead and
delete that too.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
remap_range takes generic MAP_CACHED/MAP_UNCACHED flags which are then
translated into the corresponding ARM specific bits. We call remap_range
internally from dma_alloc_* aswell, but instead of passing the generic
flags we pass the ARM specific bits.
Fix this by creating an internal __remap_range function which takes the
ARM specific bits and use it where appropriate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To be able to use dump_stack() without support exception handling the
definition of dump_stack has to move to a file that is actually compiled
without ARM_EXCEPTIONS.
Fixes: d332597c7c ("ARM: make exception handling optional")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
remap_range is for remapping regions with different cache attributes.
It is implemented for ARM and PowerPC only, the other architectures only
provide stubs.
Currently the new cache attributes are passed in an architecture specific
way and the attributes have to be retrieved by calls to
mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags().
Make this simpler by providing architecture independent flags which can
be directly passed to remap_range()
Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function.
The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture
has as default. the arch_can_remap() function returns true if the
architecture can change the cache attributes, false otherwise. This
allows the memtest code to better find out what it has to do.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
All versions of barebox_arm_entry (in uncompress.c, start.c and
start-pbl.c) appear to be doing exacty the same thing. So move the
definition into a separate file and use IS_ENABLED macro to avoid
re-definition.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Both barebox_boarddata and barebox_boot_dtb perform essentially the
same function -- hold a pointer to a chunk of private data. Since only
one variable is ever used at any given time we may as well merge those
two variable into one. This also allows us to share more code between
two boot paths (board data vs. device tree)
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In the current multi image build process the DTBs end up uncompressed
in the PBL. This can be annoying because the PBL is often very size
constrained.
This patch allows to put the DTBs in as lzo compressed binary into
the PBL. Since lzo offers quite good compression ratios for DTBs no
other compression algorithm has been implemented for now.
Boards which want to use the compressed DTBs only have to change
the __dtb_ prefix in the DTB name to __dtb_z_. Also they should select
ARM_USE_COMPRESSED_DTB to make sure barebox supports uncompressing
the DTB.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are systems like the Calxeda Highbank, which need to do SMC
calls in order to access the secure L2C registers, which means they
want to replace the outer cache disable function with their own.
As the cache flush before entering the boot target is still needed
and to avoid exposing L2C internals to the architectures move the
flush before disable into the only current user.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox uses 4KiB pages so that number of PTEs is 'size >> 12', not
'size >> 10'.
Thie 'size >> 10' limit is not an immediate problem because it allocates
too much PTEs only which are not used. But it can overflow an integer
multiplication ('i * PAGE_SIZE') which causes undefined behaviour with
gcc5.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
dma_flush_range() expects an address as second argument, not a size.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arm_ignore_data_abort can be set to nonzero to ignore data aborts. The
default should be not to ignore data aborts. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
