This gets rid of some of the special cases in the bus scanning function
by splitting hierarchy enumeration and configuration and the actual
device registration into 2 passes.
This ensures that the PCI hierarchy below a root port is completely
set up before any device driver is probed.
This simplifies the code and makes it less error prone, while moving
the PCI address space layout closer to the one used by Linux.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
PCI BARs require their address to be at least aligned to their
size, otherwise address decoding will fail as the base address
gets rounded down.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Otherwise we may end up with a too low base address and push
requests for the upstream bus onto the downstream side.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The memory type may include other flags, so just check for
the 64bit allocation flag to see if the BAR is a 64bit one.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This makes diagnosing problems in address space allocation
much easier.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The settings in GPR8 are dependent upon the particular layout of the
hardware platform. As such, they should be configurable via the device
tree.
Look up PHY Tx driver settings from the device tree. Fall back to the
original hard-coded values if they are not specified in the device tree.
[Andrey Smirnov: port to Barebox codebase]
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Remove the remnants of the workaround for erratum ERR005184 which was never
completely implemented. The checks alone don't carry any value as we don't
act properly on the result.
A workaround should be added to the lane speed change in establish_link
later.
[Andrey Smirnov: port to Barebox codebase]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds the PHY reset into a common error path of
imx6_pcie_establish_link(), deduplicating some of the debug prints. Also
reduce the severity of the "no-link" message in the one place where it is
expected to be hit when no peripheral is attached.
[Andrey Smirnov: port to Barebox codebase]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move imx6_pcie_reset_phy() near the other PHY related functions in the
file. This is a cosmetic change, but also allows to do the following
changes without introducing needless forward declarations.
[Andrey Smirnov: port to Barebox codebase]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Simplify a trivial if-return sequence by combining it with a preceding
function call.
The semantic patch that makes this change is available in
scripts/coccinelle/misc/simple_return.cocci.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Rename imx6_pcie_start_link() to imx6_pcie_establish_link() to follow the
convention of other DesignWare-based host drivers. No functional change.
[Andrey Smirnov: port to BB codebase]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
I.MX6+ version of the silicon exposed PCIe core's reset signal as a bit
in one of the control registers. As a result using old, pre-i.MX6+,
reset sequence on i.MX6+ leads to Barebox hanging during startup. Using
exposed reset bit instead solves the problem.
This commit is based on portions of commit
c34068d48273e24d392d9a49a38be807954420ed
in http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of manualy flipping the bits call imx6_pcie_assert_core_reset()
to give the code, executing after BB, a clean slate. This also makes the
function match similar code in Linux kernel driver.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Our asprintf and vasprintf have different prototypes than the glibc
functions. This causes trouble when we want to share barebox code
with userspace code. Change the prototypes for (v)asprintf to match
the glibc prototypes. Since the current (v)asprintf are convenient
to use change the existing functions to b(v)asprintf.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As the i.MX6 PCIe core doesn't have a software reachable reset
wired up, it's hard for any driver to get the core into a known
good state.
To make it easier for whatever software follows barebox, bring
back the core into a safe state before leaving barebox.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When booting Barebox in the HW environment where PCIe core has been
used but not properly shut down, writing to PCIE_PL_PFLR in
imx6_pcie_assert_core_reset would cause data abort exception.
The problem can be easily reproduced on a i.MX6 based board with PCIe
slot populated with some device by doing:
> bootm -f -e 0x1050 <your board's>.img
Ignoring this exception seem to allow PCIe core to successfully
initialize and enumerate devices properly. This is also how Linux
Kernel version of the driver handles this situation -- it installs
dummy no-op abort handler at the beginning of device's probing.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reconcile imx6_pcie_start_link with almost identical
imx6_pcie_establish_link from analogous Linux kernel driver. This
change is purely cosmetical, but refactoring the code this way
simplifies implementation comparison.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Apparently this was here to fix issues with some QEMU version,
but hasn't worked in the intended way for a long time. The probe
code should be mature enough by now, so this workaround isn't
needed anymore.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The probe code now does a much better job at detecting bad BARs.
Also make sure to preserve any previous content of the BAR
registers if we don't relocate them.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The PCI core fills in the primary bus number, so there is no
need to walk up the PCI hierarchy in the driver manually.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This was erroneously left uninitialzed as nothing was using it.
The i.MX6 PCI driver needs this to be filled properly to decide
if a config space access is allowed for a specific devfn.
This fixes PCI enumeration on the Gateworks GW54xx board.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The bridge device needs to be registered and activated before
the scanning can proceed, as the bridge is the parent for other
devices.
This fixes a NULL ptr derefernce when scanning PCI hierarchies
with bridges behind bridges.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since 2011 barebox' of_device_id struct uses unsigned long type for data field:
struct of_device_id {
char *compatible;
unsigned long data;
};
Almost always struct of_device_id.data field are used as pointer
and need 'unsigned long' casting.
E.g. see 'git grep -A 4 of_device_id drivers/' output:
drivers/ata/sata-imx.c:static __maybe_unused struct of_device_id imx_sata_dt_ids[] = {
drivers/ata/sata-imx.c- {
drivers/ata/sata-imx.c- .compatible = "fsl,imx6q-ahci",
drivers/ata/sata-imx.c- .data = (unsigned long)&data_imx6,
drivers/ata/sata-imx.c- }, {
Here is of_device_id struct in linux kernel v4.0:
struct of_device_id {
char name[32];
char type[32];
char compatible[128];
const void *data;
};
Changing of_device_id.data type to 'const void *data' will increase
barebox' linux kernel compatibility and decrease number of 'unsigned
long' casts.
Part of the patch was done using the 'coccinelle' tool with the
following semantic patch:
@rule1@
identifier dev;
identifier type;
identifier func;
@@
func(...) {
<...
- dev_get_drvdata(dev, (unsigned long *)&type)
+ dev_get_drvdata(dev, (const void **)&type)
...>
}
@rule2@
identifier dev;
identifier type;
identifier func;
identifier data;
@@
func(...) {
<...
- dev_get_drvdata(dev, (unsigned long *)&type->data)
+ dev_get_drvdata(dev, (const void **)&type->data)
...>
}
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
dev->priv is for private use of the device driver, so do not
use it in the pci core. Instead, introduce a id field in struct
pci_device.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Commit b8a1bb1dd2 (pci: defer device registration until after bridge setup)
changed the activation order of devices, so that bridges above the devices could
be configured properly before activating the devices below. This commit failed
to acknowledge that there may be devices located directly on the root bus without
any bridge in between and so those devices would never get enabled.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The bus implementations currently call the drivers remove
hook unconditionally, but this hook is seldomly populated. Only call
it when it's actually populated.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the required brackets, so that we don't write unused registers
with potentially bogus values.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This file originates in Linux. Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.
This commit was generated by the following commands:
find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
git mv include/sizes.h include/linux/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some devices need a considerable amount of time
from reset deassertion until they are ready to
establish a link. Relaxing the link-up timeout
helps to detect them more reliable.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The bridge filtering logic needs a minimum
alignment of 1MB for mem and 4KB for io resources.
Take this into account while assigning resources
to devices in oredr to not produce overlapping
windows between different bridges.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The previous math would return negative sizes
for some BARs.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is the same fix that was applied to the Linux kernel in commit
56fab6e18944 (PCI: mvebu: Fix uninitialized variable in
mvebu_get_tgt_attr()).
Fixes: 5a9ba98 ("pci: mvebu: Add PCIe driver")
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
So that PCI devices hang down from bridges and root
bridges down from the PCI host controller when
calling devinfo.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Otherwise the drivers for a device may probe before the
devices parent bridge is fully configured, which leads
to errors when accessing the BARs.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some host controllers provide a prefetchable
memory area and devices will prefer this for
some of their BARs.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Lucas Stach
Sascha Hauer
Andrey Smirnov
Fabio Estevam
Lucas Stach
Antony Pavlov
Masahiro Yamada
Thomas Petazzoni