The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
This reduced M,N couple corresponds to the advised value from
TI HW team.
Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.
Signed-off-by: Sebastien Jan <s-jan@ti.com>
The PLL setup values currently assume a 24 Mhz input clock.
This patch uses V_OSCK from the board config file to support boards
with different input clock rates.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so
Micron memory will not be detected!
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Some rams (Micron for example) return duplicate mr data on all byte lanes.
Users of the get_mr function currently don't deal with this duplicated
data gracefully. This patch detects the duplicated data and returns only
the expected 8 bit mr data.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Errata ID:i727
Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.
Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.
This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.
This will be used to skip the module configurations
that are retained across a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.
Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.
A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).
Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
The macro mistakenly referred to 32bit struct instead of 8bit one.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.
Fix the mask for these bits.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Previously, only the low 5 bits (NCH) were being transfered
from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed.
VTP_RECAL should be bit 15, not 18.
The only mainline board affected by this change is davinci_sonata.
The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT.
However, if the program that loads u-boot on these boards
copied the code from u-boot, they will need fixed as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Please get tested by acks before applying, where tested by
means an overnight memory test.
Thanks
Troy
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.
So always ensure that the size of memory used for testing is
aligned to the power of 2.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.
This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.
Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.
So take care of the above scenarios while calculating the
size of the actual ram.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9. While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Remove unnecessary brackets.
Unwrap lines which are below 80 chars.
Single line comment as single line (as the rest).
Moved init values to the source code.
cc: s-paulraj@ti.com
cc: khasim@ti.com
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
The beagle board uses the background color to show an orange screen during
startup. This patch adds the ability to add a frame buffer, with the
intention not to break the beagle board use case (I don't have one).
videomodes.c is not used. Scrolling depends on this patch:
http://patchwork.ozlabs.org/patch/155662/
cc: trini@ti.com
cc: s-paulraj@ti.com
cc: khasim@ti.com
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
s6e8ax0 panel has many panel of types. This patch support another panel
on TIZEN lunchbox board(HWREVISION 2). This panel has reversed panel
display type. So, I had added necessary command.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
npe.c: In function 'npe_initialize':
npe.c:630:13: warning: assignment from incompatible pointer type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 'master' of git://git.denx.de/u-boot-usb:
USB: S5P: Add ehci support
usb:udc:samsung Add functions for storing private gadget data in UDC driver
usb:gadget:composite: Support for composite at gadget.h
usb:gadget:composite USB composite gadget support
usb:udc:samsung:cleanup Replace DEBUG_* macros with debug_cond() calls
usb:udc: Remove duplicated USB definitions from include/linux/usb/ch9.h file
USB: Document the QH and qTD antics in EHCI-HCD
USB: Drop cache flush bloat in EHCI-HCD
USB: Drop ehci_alloc/ehci_free in ehci-hcd
USB: Align buffers at cacheline
usb: use noinline define
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
omap4: do not enable auxiliary cores
omap4: do not enable fs-usb module
omap4: panda: disable uart2 pads during boot
igep00x0: change mpurate from 500 to auto
igep00x0: enable the use of a plain text file
tegra2: trivially enable 13 mhz crystal frequency
tegra: Enable keyboard for Seaboard
tegra: Switch on console mux and use environment for console
tegra: Add tegra keyboard driver
tegra: fdt: Add keyboard definitions for Seaboard
tegra: fdt: Add keyboard controller definition
tegra: Add keyboard support to funcmux
input: Add support for keyboard matrix decoding from an fdt
input: Add generic keyboard input handler
input: Add linux/input.h for key code support
fdt: Add fdtdec functions to read byte array
tegra: Enable LP0 on Seaboard
tegra: fdt: Add EMC data for Tegra2 Seaboard
tegra: i2c: Add function to find DVC bus
fdt: tegra: Add EMC node to device tree
tegra: Add EMC settings for Seaboard
tegra: Turn off power detect in board init
tegra: Set up warmboot code on Nvidia boards
tegra: Setup PMC scratch info from ap20 setup
tegra: Add warmboot implementation
tegra: Set up PMU for Nvidia boards
tegra: Add PMU to manage power supplies
tegra: Add EMC support for optimal memory timings
tegra: Add header file for APB_MISC register
tegra: Add tegra_get_chip_type() to detect SKU
tegra: Add flow, gp_padctl, fuse, sdram headers
tegra: Add crypto library for warmboot code
tegra: Add functions to access low-level Osc/PLL details
tegra: Move ap20.h header into arch location
Add AES crypto library
i2c: Add TPS6586X driver
Add abs() macro to return absolute value
fdt: Add function to return next compatible subnode
fdt: Add function to locate an array in the device tree
i.MX28: Avoid redefining serial_put[cs]()
i.MX28: Check if WP detection is implemented at all
i.MX28: Add battery boot components to SPL
i.MX28: Reorder battery status functions in SPL
i.MX28: Add LRADC init to i.MX28 SPL
i.MX28: Add LRADC register definitions
i.MX28: Shut down the LCD controller before reset
i.MX28: Add LCDIF register definitions
i.MX28: Implement boot pads sampling and reporting
i.MX28: Improve passing of data from SPL to U-Boot
M28EVK: Add SD update command
M28EVK: Implement support for new board V2.0
FEC: Abstract out register setup
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
i.MX28: Add delay after CPU bypass is cleared
spi: mxs: Allow other chip selects to work
spi: mxs: Introduce spi_cs_is_valid()
mx53loco: Remove unneeded gpio_set_value()
mx53loco: Add CONFIG_REVISION_TAG
mx53loco: Turn on VUSB regulator
mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
pmic: dialog: Avoid name conflicts
imx: Add u-boot.imx as target for ARM9 i.MX SOCs
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
imx: usb: There is no such register
i.MX25: usb: Set PORTSCx register
imx: nand: Support flash based BBT
i.MX25: This architecture has a GPIO4 too
i.MX25: esdhc: Add mxc_get_clock infrastructure
i.MX6: mx6q_sabrelite: add SATA bindings
i.MX6: add enable_sata_clock()
i.MX6: Add ANATOP regulator init
mx28evk: add NAND support
USB: ehci-mx6: Fix broken IO access
M28: Scan only first 512 MB of DRAM to avoid memory wraparound
Revert "i.MX28: Enable additional DRAM address bits"
M28: Enable FDT support
mx53loco: Add support for 1GHz operation for DA9053-based boards
mx53loco: Allow to print CPU information at a later stage
mx5: Add clock config interface
imx-common: Factor out get_ahb_clk()
i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
mx31pdk: Allow booting a zImage kernel
mx6qarm2: Allow booting a zImage kernel
mx6qsabrelite: Allow booting a zImage kernel
mx28evk: Allow booting a zImage kernel
m28evk: Allow to booting a dt kernel
mx28evk: Allow to booting a dt kernel
mx6qsabrelite: No need to set the direction for GPIO3_23 again
pmic: Add support for the Dialog DA9053 PMIC
MX53: mx53loco: Add SATA support
MX53: Add support to ESG ima3 board
SATA: add driver for MX5 / MX6 SOCs
MX53: add function to set SATA clock to internal
SATA: check for return value from sata functions
MX5: Add definitions for SATA controller
NET: fec_mxc.c: Add a way to disable auto negotiation
Define UART4 and UART5 base addresses
EXYNOS: Change bits per pixel value proper for u-boot.
EXYNOS: support TRATS board display function
LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
LCD: add data structure for EXYNOS display driver
EXYNOS: add LCD and MIPI DSI clock interface.
EXYNOS: definitions of system resgister and power management registers.
SMDK5250: fix compiler warning
misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
misc:pmic:max8997 MAX8997 support for PMIC driver
TRATS: modify the trats's configuration
ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
cm-t35: add I2C multi-bus support
include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
omap3: Introduce weak misc_init_r
omap730p2: Remove empty misc_init_r
omap5912osk: Remove empty misc_init_r
omap4+: Remove CONFIG_ARCH_CPU_INIT
omap4: Remove CONFIG_SYS_MMC_SET_DEV
OMAP3: pandora: drop console kernel argument
OMAP3: pandora: revise GPIO configuration
...
All arches init this the same way, so move the logic into the core
net code to avoid duplicating it everywhere else.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr"). After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.
This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.
Signed-off-by: Matt Porter <mporter@ti.com>
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: R Sricharan <r.sricharan@ti.com>
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra keyboard controller provides a simple interface to a matrix
keyboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus.
This allows us to talk to the PMU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a definition of the memory controller node according to the bindings
here:
http://patchwork.ozlabs.org/patch/132928/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a basic header file for this register, to be filled in as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These headers provide access to additional Tegra features.
flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to include this from board code, so move the header into
an easily-accessible location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This macro is generally useful to make it available in common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This code is part of battery boot support for i.MX28.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:
"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"
The values are currently negated in code - fixed.
Reported-by: David Jander <david.jander@protonic.nl>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: David Jander <david.jander@protonic.nl>
Acked-by: David Jander <david.jander@protonic.nl>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.
This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.
Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.
For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.
Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
types.h must be included in imx-regs.h if one wants to include
imx-regs.h in a board configuration file. That for one's part is
necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and
a proper thing is to define it with IMX_MMC_SDHCx_BASE in board
configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
implement get_clocks function. This is how it seems to be implemented
elsewhere.
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
This reverts commit 69d26d09de.
Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.
Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
where the chips are wired differently. The patch-to-be-reverted
caused the DRAM to behave like this:
[128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]
Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
mx5: Add clock config interface
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
get_ahb_clk() is a common function between mx5 and mx6.
Place it into imx-common directory.
Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.
As stated by Freescale's support:
Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
SATA_ALT_REF_CLK[1:0] (offset 0x180C)
'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
EXYNOS SoC platform has MIPI-DSI controller and MIPI-DSI
based LCD Panel could be used with it. This patch supports MIPI-DSI driver
based Samsung SoC chip.
LCD panel driver based MIPI-DSI should be registered to MIPI-DSI driver at
board file and LCD panel driver specific function registered to mipi_dsim_ddi
structure at lcd panel init function called system init.
In the MIPI-DSI driver, find lcd panel driver by using registered
lcd panel name, and then initialize lcd panel driver.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
This patch support EXYNOS FB and FIMD display drivers.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc
in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic
usase of tzpc.
Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This rule confirms that if we're on ARM and we have enabled THUMB builds
that we have a new enough toolchain to produce a working binary.
Changes in v2:
- Switch to ALL-$(CONFIG_SYS_THUMB_BUILD) in arch/arm/config.mk (Mike F)
- Simplfy checkthumb test after doing the above
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Avoid using __attribute__ ((__packed__)) unless it's
absolutely necessary. "packed" will remove alignment
requirements for the respective objects and may cause
alignment issues unless alignment is also enforced
using a pragma.
Here, these packed attributes were causing alignment
faults in Thumb build.
Signed-off-by: Aneesh V <aneesh@ti.com>
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.
Signed-off-by: Aneesh V <aneesh@ti.com>
Enable Thumb build and ARM-Thumb interworking based on the new
config flag CONFIG_SYS_THUMB_BUILD
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This will add ARM specific over-rides for the defines
from linux/linkage.h
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
PD_TIM bit field which specifies the power down timing is defined
to occupy bits 8-11, where as it is actually from 12-15 bits.
So correcting this.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The full internal SRAM of size 128kb is public in the case of OMAP5 soc.
So change the base address accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.
As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.
With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.
NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.
Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
This change adds initial support for NXP LPC32x0 SoC series.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
In driver mmc, generic s5p_sdhci code is implemented.
s5p_mmc file is dupulicated.
we are good that use the generic sdhci.
This patch supported the sdhci for Samsung-SoC.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lei Wen<leiwen@marvell.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* 'master' of git://git.denx.de/u-boot-i2c:
i2c:designware Turn off the ctrl when setting the speed
i2c: Add support for designware i2c controller
sh: i2c: Add support I2C controller of SH7734
* 'marex@denx.de' of git://git.denx.de/u-boot-staging:
CMD: CONFIG_CMD_SETECPR -> CONFIG_CMD_SETEXPR on omap3_logic
CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
CMD: Fix typo CMD_FSL -> CMD_MFSL in readme
HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM
CMD: Remove CMD_LOG, it's unused
CMD: Fix typo KGBD -> KGDB on debris board
CMD: Drop CONFIG_CMD_EMMC, it's not used
CMD: Drop CONFIG_CMD_DFL, it's not used
CMD: Drop CMD_DCR, it's not used
CMD: Drop CMD_CAN, it's not used
CMD: Remove CMD_AUTOSCRIPT, it's not used
AT91: Drop AT91_SPIMUX command from cmd_all
Earlier, a driver exists in the u-boot source for designware i2c interface. That
driver was specific to spear platforms. This patch implements the i2c controller
as a generic driver which can be used by multiple platforms
The driver files are now renamed to designware_i2c.c and designware_i2c.h and
these are moved into drivers/i2c folder for reusability by other
platforms
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux for ARM. During the re-organization, the call to
fdt_fixup_ethernet() was removed. I assume this was useful, so add it
back.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux() for ARM. During the re-organization, the code to pass
the device tree to the kernel was removed. Add it back. This restores
the ability to boot a kernel using device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Allen Martin <amartin@nvidia.com>
Tested-by: Allen Martin <amartin@nvidia.com>
We certainly don't want the compiler to reorganise the code for dcache flushing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Stefano Babic <sbabic@denx.de>
As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Freescale SOCs require an header to u-boot.bin
The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>
This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.
The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.
The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.
NOTE: This patch depends on:
http://patchwork.ozlabs.org/patch/150957/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of printf().
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Since commit 5c1ad3e6f8
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and invalidate_dcache_range()
functions. This driver is also configured for ARM1136 based
'flea3' and 'mx35pdk' boards which currently do not build
as there are no ARM1136 specific flush_dcache_range() and
invalidate_dcache_range() functions. Add various ARM1136
cache functions to fix building for 'flea3' and 'mx35pdk'.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
This command boots Linux zImage from where the zImage is loaded to. Passing
initrd and fdt is supported.
Tested on i.MX28 based DENX M28EVK
Tested on PXA270 based Voipac PXA270.
NOTE: This currently only supports ARM, but other architectures can be easily
added by defining bootz_setup().
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: albert.u.boot@aribaud.net
Cc: afleming@gmail.com,
Cc: Simon Glass <sjg@chromium.org>,
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.
Now that we can factor out this difference, we can move most cpus over
to the common .lds file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most ARM CPUs use a very similar link script. This adds a basic
script that can be used by most CPUs.
Two new symbols are introduced which are intended to eventually be
defined on all architectures to make things easier for generic relocation
and reduce special-case code for each architecture:
__image_copy_start is the start of the text area (equivalent to the
existing _start on ARM). It marks the start of the region which must be
copied to a new location during relocation. This symbol is called
__text_start on x86 and microblaze.
__image_copy_end is the end of the region which must be copied to a new
location during relocation. It is normally equal to the start of the BSS
region, but this can vary in some cases (SPL?). Making this an explicit
symbol on its own removes any ambiguity and permits common code to always
do the right thing.
This new script makes use of CPUDIR, now defined by both Makefile and
spl/Makefile, to find the directory containing the start.o object file,
which is always placed first in the image.
To permit MMU setup prior to relocation (as used by pxa) we add an area
to the link script which contains space for this. This is taken
from commit 7f4cfcf. CPUs can put the contents in there using their
start.S file. BTW, shouldn't that area be 16KB-aligned?
Signed-off-by: Simon Glass <sjg@chromium.org>
This is set by the top level Makefile anyway, so drop it. This does
have the effect of changing the order - now the board link script will
have preference over the CPU one. But this seems more correct anyway.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix:
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
Add basic i2c driver for Tegra2 with 8- and 16-bit address support.
The driver requires CONFIG_OF_CONTROL to obtain its configuration
from the device tree.
(Simon Glass: sjg@chromium.org modified for upstream)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add U-Boot's peripheral clock information to the Tegra20 device tree file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When using CONFIG_OF_CONTROL, add a check that we have a valid FDT
and panic() if not. This must be done after the console is ready.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds clock references to the USB part of the device tree for U-Boot,
and marks USB1 as supporting legacy mode (which we disable in the driver).
The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with T3x later and we first need to agree
on the format for this timing information in the fdt and may in fact
decide that it has no place there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds a basic binding for the oscillator and peripheral clocks. The
second cell is the clock number, defined as the bit number within the clock
enable register if the peripheral clock.
This uses the RFC clock bindings from Grant Likely so may change later:
https://lkml.org/lkml/2011/12/12/498
It is taken from Stephen Warren's patch here:
http://patchwork.ozlabs.org/patch/141359/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
config.mk is updated to provide this file to boards through the
built-in mechanism:
/include/ ARCH_CPU_DTS
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).
Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Implement reset for highbank platform. Reset is triggered via a wfi
instruction, so enabling armv7 for the compiler is necessary.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
udelay calls were off due to failing to convert us to ns. Fix this and drop
the unnecessary shifts since NS_PER_TICK is only 7ns.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The get_tbclk function was missing and the recent commit "common: add
possibility for readline_into_buffer timeout" makes it required.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC).
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch fixes the s3c24x0 timer code to work with the ARM
relocation feature.
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adds prep subcommand to bootm implementation of ARM. When bootm is called
with the subcommand prep the function stops right after ATAGS creation and
before announce_and_cleanup.
This is used in command "cmd_spl export"
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
Call i2c initialization in spl_board_init only if I2C
is configured for the board.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
This only outputs "Assuming u-boot.bin..." if debug is active.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
This adds Linux booting to the SPL
This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)
Related CONFIGs:
CONFIG_SPL_OS_BOOT
Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
defines the IO-pin number u-boot switch - if pressed u-boot is
booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normaly RAM-begin + 0x100
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Linux crashes if the GPMC isn't configured for the dm9000.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
This implements booting of Linux from NAND in SPL
Related config parameters:
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normally RAM-start + 0x100 (on ARM)
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.
FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.
Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
Instead of compiling the function and using the result as a constant, simply use
the constant.
NOTE: This patch works around bug:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be
enough according to the datasheet and bootlets.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
After booting mx6qsabrelite from POR the following is reported:
CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset
This is because both the POR and WDOG bits are set after reset.
Fix this by also checking both bits in the POR case.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Enables all fourteen address lines for DRAM
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7.
This is due to the fact that there are two registers for total of 16 lines.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
IxEthAcc.c: In function ‘ixEthAccInit’:
IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum <anonymous>’ [-Wenum-compare]
IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’:
IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable]
IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’:
IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Add -EB flag to LD to switch endianness of the linker. This should make armeb
targets buildable again. Also, make use of U-Boot's internal libgcc instead of
toolchain's one, this works around the use of libraries from GCC, which might be
little endian.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.
Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch introduces an 8-bit register, mx28_register_8, in order to
prepare for fixing erroneous 32-bit wide access of registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch replaces the use of magice numbers for scratch register
addresses with earlier defined register definitions.
Signed-off-by: Robert Delien <robert@delien.nl>
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func. This also fixes the build errors:
ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
Add calls to bootstage before and after relocation, and just
before jumping to the OS.
The idea here is you can call bootstage_report() to get a report.
Additionally, if you define CONFIG_BOOTSTAGE_REPORT then a report is
printed automatically by U-Boot just before jumping to the kernel.
Signed-off-by: Simon Glass <sjg@chromium.org>
These calls should not be made directly any more, since bootstage
will call the show_boot_...() functions as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
This changes the number 15 as used in boot_stage_progress() to use the
new name provided for it. This is a separate patch because it touches
so many files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
All boards are using the gen_atmel_mci driver now, so no need
to carry the old driver around.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Boards can select either the 'built-in' parser or the hush parser. We
should not call builtin_run_command() if we are using the hush parser.
We use run_command() instead, since it knows how to call the correct
parser.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The current run_command() is only one of the parsing options - the other
is hush. We should not call run_command() when the hush parser is being
used. So we rename this function to better explain its purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.
Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f408
However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.
As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V <aneesh@ti.com>
The video setup for the Epson display is provided. Addtionally
some extra info is displayed next to the Linux logo.
Make get_cpu_rev() publicly available (added to sys_proto.h).
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
In commit 2d575e4685 a separate header
file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h.
The substantial difference between the davinci_dm6467evm and the
davinci_dm6467Tevm configuration is a single bit in the hardware revision
that is passed to the Linux kernel and davinci_dm6467evm has
REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a
REFCLK_FREQ = 33000000.
This patch removes include/configs/davinci_dm6467Tevm.h. Instead the
include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and
renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined
in boards.cfg.
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tom Rini <trini@ti.com>
* For cold silicon the DDR timings need to be relaxed in order for
the device to boot with DDR at 266MHz
* Fix proposed by James Doublesin
Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
check for the return status for eth_getenv_enetaddr_by_index()
and eth_setenv_enetaddr() functions and print appropriate message
on failure.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
get_reset_cause() function is only used inside print_cpuinfo(), so let it be
defined only when CONFIG_DISPLAY_CPUINFO is selected.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.
GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.
Discussion on the mailing list at
http://lists.denx.de/pipermail/u-boot/2012-January/116927.html
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.
2) Save and restore c1 control register: the exception vector
location needs to be set back to bootrom space to make the USB
interrupts work again. The SPL code needs to change this
option for the ram size probing.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
The DC power STS shouldn't be checked if booting off 5V supply.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Marek Vasut <marek.vasut@gmail.com>
commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Before we can send a command we need both the DATI (command inhibit on
mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear.
The previous behavior of only checking on DATI was insufficient on some
cards and incorrect behavior in any case. This makes the code check
for both bits being clear and makes the error print more clear as
to what happened. DATI_CMDDIS is removed as it was unused elsewhere
in the code and stood for 'DATI is set, cmds are disabled still'.
Fix originally spotted by Peter Bigot.
Tested-by: Peter A. Bigot <bigotp@acm.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard
to reflect the same.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
The current implementation invalidates the data cache before turning it
off and causes problems on the hawkboard. See the discussion in
http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
According to the ARM926EJ-S Technical Reference Manual, the cache should
be flushed instead.
Also fix the comments to match code.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Rebased and corrected commit message.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This patch reverts commit ca4b55800e
"arm, arm926ejs: always do cpu critical inits" since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board configurations that need low level initialization.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
The low level initialization code in
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for
DM644X SoCs only. This patch makes the lowlevel_init function in this
file a dummy function for SoCs other than DM644X.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Sergey Kubushyn <ksi@koi8.net>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS()
instead of "c". To make usage more clear, replace all single-letter
macro parameters with more descriptive parameter names.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
We do not have thermal management or Smartreflex
enabled at U-Boot level. So, it's better to stick
to OPP100 for MPU instead of the OPP Turbo that is
used now. Adjust the VDD_MPU accordingly.
Tested-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'bdinfo' command and also remove support print_cpuinfo() as it will
no longer be called.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
AM3517: Changed default clock rate for AM3517
Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows
the AM3517 to boot up at 600MHz instead of 500 MHz
Signed-off-by: Schuyler Patton <spatton@ti.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
usb dpll configuration is done only part of non-essential
dppl configuration however if CONFIG_USB_EHCI_OMAP is defined
we may have to configure usb dpll's for proper functioning
of usb modules. So move the usb dppl configuration to a new func.
and utilise the same during essential dpll configuration.
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Adding ehci clock enabling mechanism part of clock framework.
When essential clocks are enabled during init phase usb host
clocks can also be enabled from clock framework.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Clean up added ehci-omap.c and make it generic for re-use across
omap-soc having same ehci ip block. Also pass the modes to be configured
from board file and configure the ports accordingly. All usb layers
are not cache aligned, till then keep cache off for usb ops as ehci will use
internally dma for all usb ops.
* Add a generic common header ehci-omap.h having common ip block
data and reg shifts.
* Rename and modify ehci-omap3 to ehci.h retain only conflicting
sysc reg shifts remove others and move to common header file.
* pass the board data for beagle/panda accordinly to use
ehci ports.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support the generic watchdog timer for s5pc1xx and exynos4
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: HeungJun, Kim <riverful.kim@samsung.com>
This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power.
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch add watchdog.h for Exynos4
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Earliar ARM clock frequency was calculated by:
MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
It is fixed by calculating it as follows:
ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1)
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add TCMPB3 field in pwm structure, earliar this was res1.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
after http://patchwork.ozlabs.org/patch/136415/ was applied. All Marvell
build fails with below error
common/libcommon.o: In function `cread_line':
/home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_ticks'
/home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_tbclk'
/home/uboot/src/u-boot-arm/common/main.c:720: undefined reference to `get_ticks'
The same is fixed for Kirkwood, ARMADA100, pantheon and orion5x SoCs
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Wolfgang Denk <wd@denx.de>
FEC does not work on the i.mx51/53evk board, it will hangup
In: serial
Out: serial
Err: serial
Net:
After bisect, it due to the following commit:
be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse
has change the imx_get_mac_from_fuse fucntion prototype, but fail
to update i.mx5, here it does it.
After apply this patch, u-boot works again on i.mx51/53 evk boards.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Showing CPU frequency during boot is useful information.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX27 imx_get_XXXclock functions are made static to
generic.c and a public mxc_get_clock() function
is provided. Pins, base address and prototypes for
an i.MX31 specific board_init_mmc() are provided.
Some of the i.MX27 clock getters are unused and marked
as such to avoid warnings (./MAKEALL -s mx27), but
the code was left in for future use.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
The uart txd pad can also provide the rxd function. But it does not stop its
tx role. This could be used for a half duplex serial port.
Change names to reduce confusion.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
The Buffer Logic of VPSS is Not Reset by System Reset Pin, see
http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory 1.2.1
on page 9. Add workaroundcode proposed in the errata.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix
boot on all OMAP4 boards.
Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com>
Tested-by: Robert P. J. Day <rpjday@crashcourse.ca>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC
to determine where CS1 is mapped to. make_cs1_contiguous() will set
CS1 to follow after CS0. The CS_CFG register has values in bits 9:8
and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in
incorrect offsets on platforms with less than 128MB as 3:0 describe
128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk.
Tested-by: Grant Erickson <marathon96@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Wrap the function save_boot_params with CONFIG_SPL_BUILD. This will
allow non-SPL boards to define their own save_boot_params functions
in U-Boot itself.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
The OMAP-L138 has a pre-divider available on PLL0.
Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
This enables the data cache on Tegra2 boards.
As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe turning on the cache for all
Tegra2 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there seems
to be nothing better.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A value of 0 in the odmdata RAM size field means default, which is 512MB
not 1GB. Fix this. For reference, see:
http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\
f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\
h=1ec7010911454f19a5018952fd245785a62c59ad;\
hb=0e52d7fe25b11a656c376a37890be219470661fb
v2: New patch
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra appears to boot with function UARTA pre-selected on mux
group SDB. If two mux groups are both set to the same function,
it's unclear which group's pins drive the RX signals into the
HW module. For UARTA, SDB certainly overrides group IRTX in
practice. To solve this, configure some alternative function on
SDB to avoid the conflict. Also, tri-state the group to avoid
driving any signal onto it until we know what's connected.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
* implementation based on ti beagleboard/omap3evm
* timing data and i2c workaround for revision 0 boards taken from x-loader
* run-tested with overo revision 0 and 1 / boot from NAND and SDcard
* run-tested with x-loader
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to update incorrect ddr and timer
register offset.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to replace CONFIG_AM335X symbol
with CONFIG_AM333XX for AM33XX platforms.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Thomas Weber <weber@corscience.de>
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this function
weak.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.
Commit 23e9f0723e
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Raúl Porcel <armin76@gentoo.org>
Now the values in the defines agree with those in the manuals.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear. Using the correct method to clear the IRQs fixes it.
Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
For the i.mx6q, the burned-in MAC address will be the following odering,
fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2]
fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1]
fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0]
This patch also fix the error caculation for the fuse bank[0] address
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Let imx_get_mac_from_fuse function be a common function, so that other
mx28 boards can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.
This feature is important on mx28 SoC for example that has two FEC ports.
Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Config options for OMAP are not used with i.MX28 so remove dead code.
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
ARM boards should use the generic GPIO API
This means changing gpio to unsigned type
Remove the unused gpio_toggle() function which is not part of the API
Comment that free should not modify pin state
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and
extended to the new mxs_gpio.c.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
We add a way of initialising the selected of UARTs prior to relocation.
Boards can use the board_init_uart_f() instead of repeating this code
themselves.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
funcmux permits selection of config options for particular peripherals,
such as the pins that are used for that peripheral, if there are several
options.
Add UART selection to start with.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The clock init is not board specific, so move it into
the cpu code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This call is more of an architecture requirement than a board
one, so move it there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The AVP on Tegra2 doesn't boot properly when U-Boot is linked against
the GCC provided libgcc. To work around this, always build and link
against a private libgcc for Tegra2-based boards.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra2 Seaboard has the unfortunate feature that SPI and the console
UART are multiplexed on the same pins. We need to switch between one
and the other during SPI and console activity.
This new file implements a switch and keeps track of which peripheral
owns the pins. It also flips over the controlling GPIO as needed
Since we are adding a second file to board/nvidia/common, we create
a proper Makefile there and remove the direct board.o include from
board/nvidia/seaboard/Makefile
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch fixes a build warning for the cam_enc_4xx board introduced by
commit d6ec0c0dfc70447cf615ae80a952da81f73f16b4:
spl.c:35:13: warning: 'gdata' defined but not used
spl.c:36:13: warning: 'bdata' defined but not used
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
This code adds an SPL for booting from SPI flash on DA850 SoCs.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't
execute on Tegra, due to the AVP (ARM7TDI) not having a CP15.
Result was an undefined instruction hang just after reset.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Gerald van Baren <gvb.uboot@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Hello
This patch adds support for "print_cpuinfo" on Samsung s3c24x0
based targets. If activated by "#define CONFIG_DISPLAY_CPUINFO", the
chip ID and the 3 main cpu frequencies will be displayed.
Dave
Signed-off-by: David Müller <d.mueller@elsoft.ch>
During misc_init_r, make sure to setup the clocks
properly for the USB hub on the pandaboard. With
this in place, the USB hub and the ethernet works
on the pandaboard.
Signed-off-by: Chris Lalancette <clalancette@gmail.com>
Acked-by: Aneesh V <aneesh@ti.com>
Commit 2f3427c added noop cache functions implementation for arm926ejs
to fix compilation of drivers depending on these functions (DaVinci
EMAC in particular).
Unfortunately, the bug was introduced: noop implementation calls
dcache_disable which calls flush_dcache_all which in turn calls
dcache_disable thus creating an infinite loop.
This patch removes noop implementation for flush_dcache_all, we already
have default one in arch/arm/lib/cache.c and it should be used instead.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Fix trailing white space, indentation by spaces instead of TABs,
excessive blank lines, trailing blank lines.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit enables support for USB Gadgets on the Exynos4210 (C210 Universal)
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
CC: Remy Bohmer <linux@bohmer.net>
* 'master' of git://git.denx.de/u-boot-usb:
USB: efikamx: Enable USB on EfikaMX and EfikaSB
USB: Add generic ULPI layer and a viewport
USB: EHCI: Allow EHCI post-powerup configuration in board files
USB: mx51evk: add end enable USB host support on port 1
USB: mx53loco: add end enable USB host support on port 1
USB: MX5: Add MX5 usb post-init callback
USB: MX5: Abstract out mx51 USB pixmux configuration
USB: MX5: add generic USB EHCI support for mx51 and mx53
USB: MX5: add helper functions to enable USB clocks
usb:gadget:s5p Enable the USB Gadget framework at GONI
usb:gadget:s5p USB Device Controller (UDC) implementation
ehci: speed up initialization
usb: add help for missing start subcommand
cosmetic: remove excess whitespace from usb command help
usb: align usb_endpoint_descriptor to 16-bit boundary
usbtty: init endpoints prior to startup events
pxa: convert pxa27x_udc to use read and write functions
pxa: activate the first usb host port on pxa27x by default
pxa: fix usb host register mismatch
ehci-fsl: correct size of ehci caplength
USB: Add usb_event_poll() to get keyboards working with EHCI
USB: gadaget: add Marvell controller support
USB: Fix complaints about strict aliasing in OHCI-HCD
USB: Drop dead code from usb_kbd.c
USB: Rework usb_kbd.c
USB: Add functionality to poll the USB keyboard via control EP
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
V2: Fix spacing in crm_regs.h
This commit enables support for USB Gadgets on the GONI
reference target.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
The pxa27x has 3 usb host ports. Activate all by default.
Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Remy Bohmer <linux@bohmer.net>
With the ELDK 5.1 (beta) "armv7a" toolchain I'm get the following
build failure:
$ ./MAKEALL mx51evk
...
/opt/eldk-5.1/armv7a/sysroots/arm-linux-gnueabi/usr/lib/arm-linux-
gnueabi/4.6.1/libgcc.a(bpabi.o):(.ARM.exidx+0x0): undefined
reference to `__aeabi_unwind_cpp_pr1'
make: *** [u-boot] Error 1
This patch fixes the issue similar to commit
d442b6e7ad6a86e2fd0e6297291fe8872ff26fc6 but I don't know if it's
general enough or if it does harm when using other toolchains.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
The current way memsize.c is built just made a symlink into the directory
with SPL and then compiled it like any other file there. This was bad as that
broke the out-of-tree build.
The new way introduced in this patch uses the standard spl/Makefile methods
(CONFIG_SPL_LIBCOMMON_SUPPORT / CONFIG_SPL_LIBGENERIC_SUPPORT) to let files in
common/ be built. Because common/Makefile says memsize.c is always built (SPL
and non-SPL build), this fixes our issue with memsize.c out-of-tree build.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This moves SPL to common location so it can be reused by multiple boards. Also,
this commit adjusts M28 SoM to avoid breakage due to the move.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.
This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
added but just fix the checkpatch errors in the old file and remove
the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In board_init_f() the gd->bd pointer is not valid when dram_init() is called.
This only avoids dying because DRAM is at zero on Tegra2. The common ARM
routine sets up the banks in the same way anyway, so we can just remove this
code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This message is not required, since it is followed by an 'official' U-Boot
message.
U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23)
TEGRA2
Board: NVIDIA Seaboard
dynamic ram_size = 1073741824
DRAM: 1 GiB
becomes:
TEGRA2
Board: NVIDIA Seaboard
DRAM: 1 GiB
This is a separate commit since it changes behavior.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Since we have cache support built in we can remove Tegra's existing cache
initialization code amd other related dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some SOCs have do not start up with their 'main' CPU. The first U-Boot
code may then be executed with a CPU which does not have a CP15, or not a
useful one.
Here we split the initialization of CP15 into a separate call, which can
be performed later if required.
Once the main CPU is running, you should call cpu_init_cp15() to perform
this init as early as possible.
Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not
need to change, this CP15 init is still skipped in that case. The only
impact for these boards is that the cpu_init_cp15() will be available
even if it is never used on these boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra2 boot path is more complicated than it needs to be. Since we want
to move to building most of U-Boot with ARMv7 and only a small part with
ARMv4T (for AVP) it should be as simple as possible.
This makes tegra2_start() into a simple function which either does AVP
init or A9 init depending on which core is running it. Both cores now
following the same init path, beginning at _start, and the special Tegra2
boot path code is no longer required.
Only two files need to be built for ARMv4T, and this is handled in the
Tegra2 CPU Makefile.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to move away from a special Tegra2 start-up, and just use
arch_cpu_init() instead. However, if we run board_init_f() from boot
we need to build it for ARMv4T, since the Tegra's AVP start-up CPU
does not support ARMv7.
The effect of this is to do the AVP init earlier, and in
arch_cpu_init(), rather that board_early_init_f().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Sorry if this is already fixed somewhere - I could not find it.
This fixes these warnings:
usb_ohci.c: In function 'submit_control_msg':
usb_ohci.c:1081: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1081: note: initialized from here
usb_ohci.c:1084: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1084: note: initialized from here
usb_ohci.c:1087: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1087: note: initialized from here
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fix:
clocks.c: In function 'setup_post_dividers':
clocks.c:175: warning: comparison is always true due to limited range of
data type
clocks.c:177: warning: comparison is always true due to limited range of
data type
clocks.c:179: warning: comparison is always true due to limited range of
data type
clocks.c:181: warning: comparison is always true due to limited range of
data type
clocks.c:183: warning: comparison is always true due to limited range of
data type
clocks.c:185: warning: comparison is always true due to limited range of
data type
clocks.c:187: warning: comparison is always true due to limited range of
data type
clocks.c:189: warning: comparison is always true due to limited range of
data type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Fix:
clocks-common.c: In function 'setup_dplls':
clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
Fix:
spl.c: In function 'jump_to_image_no_args':
spl.c:103: warning: assignment makes pointer from integer without a cast
spl.c:105: warning: dereferencing type-punned pointer will break
strict-aliasing rules
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
Some functions were internal to the apbh dma driver, so annotate them static.
Some of the functions weren't used at all so drop them. This makes the U-Boot
binary smaller by about 1500 bytes.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This corects the warning below, obtained with my gcc 4.6 compiler.
arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll':
arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod'
I am not able to test this on MX5x hardware, but it does improve the
MAKEALL output for me. You may already have a similar patch, but I cannot
see it on the list.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4
doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by: Tom Rini <trini@ti.com>
This introduces 200MHz Micron parts timing information based on x-loader
to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init
logic is also based on what x-loader does in these cases. Note that
while previously u-boot would be flashed in with SW ECC in this case it
now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to
0x80100000.
Cc: Dirk Behme <dirk.behme@gmail.com>
Beagleboard rev C5, xM rev A:
Tested-by: Tom Rini <trini@ti.com>
Beagleboard xM rev C:
Tested-by: Matt Ranostay <mranostay@gmail.com>
Beagleboard rev B7, C2, xM rev B:
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
A number of boards are populated with a PoP chip for both DDR and NAND
memory. Other boards may simply use this as an easy way to identify
board revs. So we provide a function that can be called early to reset
the NAND chip and return the result of NAND_CMD_READID. All of this
code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by: Tom Rini <trini@ti.com>
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this
to provide the default 165MHz value.
Signed-off-by: Tom Rini <trini@ti.com>
This adds an MCFG macro to calculate the correct value, similar to
the ACTIMA/ACTIMB macros and adds a comment that all of the potential
values here are documented in the TRM. Then we convert the Micron
value to use this macro.
Signed-off-by: Tom Rini <trini@ti.com>
It's possible to need to call this function on the same banks multiple
times so we want to be sure that 'pos A' is cleared out again at the
end.
Signed-off-by: Tom Rini <trini@ti.com>
Since we go through the sequence to setup the SDRC timings more than
once, break this logic out into its own function and have that function
call mem_ok() to make sure the memory is usable.
Signed-off-by: Tom Rini <trini@ti.com>
We update the comment in make_cs1_contiguous() to be a little bit
more clear (it's been copy/pasted from other silicons) and then
explain in dram_init() why we need to always try this.
Note that in the previous behavior we were always calling this on
boards that never had cs1 populated anyhow so making sure we do
this always is fine and will correct things like omap3evm detecting
an invalid amount of memory (384MB).
Signed-off-by: Tom Rini <trini@ti.com>
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.
Signed-off-by: Tom Rini <trini@ti.com>
This patch avoids build breakage for SPLs that do not support printf.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
move the board/davinci/common/misc.c file to
arch/arm/cpu/arm926ejs/davinci/misc.c, so all
davinci boards can use this functions.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Christian Riesch <christian.riesch@omicron.at>
move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h
and add RTC_KICK0R_WE, RTC_KICK1R_WE defines,
so they are global useable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This patch replaces the pinmux configuration code in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by the code from
arch/arm/cpu/arm926ejs/davinci/pinmux.c.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Up to now nearly every davinci board has separate code for the
definition of pinmux configurations. This patch adds pinmux
configurations for the DA850 SoCs to the arch tree which may later
be used for all DA850 based boards.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
always do the cpu critical inits in cpu_init_crit,
and only jump to lowlevel_init, if CONFIG_SKIP_LOWLEVEL_INIT
is not defined.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Added noop implementation for dcache operations that will buzz
about missing real implementation and disable the dcache.
This fixes compilation of DaVinci EMAC driver on arm926ejs.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h
DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
The value from TRIM is not working for some 4430 silicons.
So, override with hw team recommended value. However, for
4460 TRIM value shall be used as long as the part is trimmed
This fixes boot problem on some OMAP4430 ES2.0 Panda boards
out there.
Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.
Reported-by: Rockefeller <rockefeller.lin@innocomm.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
TPS power IC is controlled using a GPIO (gpio_wk7).
This GPIO should be maintained at logic 1 always. As
such an internal pull-up on this pin will do the job,
driving the GPIO outuput is not needed. This will avoid
the need of using GPIO library in SPL and also may
save some power.
Signed-off-by: Aneesh V <aneesh@ti.com>
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
This allows SPL to have default implementation of
save_boot_params(), useful for SoCs that do
not intend to override this default implementation
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
We were not disabling external caches before jumping
to kernel. We were flushing all caches including
external caches and disabling caches globally in
CP15 System Control register. Apparently this is not
enough.
The bootstrap loader in Linux kernel that does decompression
enables data-caches again, flush them after use and disable
them before jumping to kernel proper. However, it's not aware
of the external caches.
Since we have left external cache enabled, external cache will
get used once caches are enabled globally, but it's not flushed
because decompressor is not aware of external caches. When it
jumps to kernel with caches disabled globally, we have stale
data in the external cache and a coherency problem.
This was breaking the boot for OMAP4 with latest mainline
kernel. The solution is to disable external caches in
cleanup_before_linux(). With this fix kernel is booting again.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
This patch fixes the clear bss loop for bss sections that have
zero length, i.e., where __bss_start == __bss_end__.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
The start.S on PXA was very obscure. This reworks it back to be close to arm1136
start.S and others.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
V2: Don't compile in relocation support if building SPL
This patch replaces the HAWKBOARD_KICK{0,1}_UNLOCK defines by
DV_SYSCFG_KICK{0,1}_UNLOCK.
The kick register values are not hawkboard specific but may be used
for all davinci boards. In commit f3c149d6c6
new defines for these values wer introduced.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
There is no need to have such a function twice.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Change my old email address which is no longer valid.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
cpuinfo.c: In function 'print_cpuinfo':
cpuinfo.c:155:6: warning: variable 'system_serial_low' set but not used
[-Wunused-but-set-variable]
cpuinfo.c:154:6: warning: variable 'system_serial_high' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
No one uses this driver, and it isn't converted to the NET_MULTI
framework (which we dropped recently), so drop this driver too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Fix:
pwm.c: In function 'pwm_config':
pwm.c:85:16: warning: variable 'timer_rate_hz' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.
Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.
Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.
Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fixing them here so that when the files are reused in
subsequent patches for omap5, avoids new checkpatch
warnings.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Much of omap4 soc support code can be reused for omap5.
Move them to the omap-common directory to facilitate
this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Cleanup register definitions by introducing new regs-uart.h, compliant with
rest of U-Boot.
* Remove old register definitions from pxa-regs.h
* Convert serial_pxa to new regs-uart.h
* Cleanup serial_pxa
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
GPR register definition is already available at imx-regs.h, so remove the duplication.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch introduces proper ARM vector handling for i.MX28 CPU. This issue
wasn't addressed because the interrupts weren't enabled on any ARMv5 core,
therefore the issue wasn't noticed earlier.
In previous implementation, the vectoring code used by i.MX28 CPU when an
exception happened was that of the SPL. With this change, the branch target when
an exception happens can be reconfigured by U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Taken from Linux kernel with minor modifications:
commit bf985969e27b507f734435a99df8bf745a3dbb2b
Author: Shawn Guo <shawn.guo@freescale.com>
Date: Mon Dec 20 22:57:43 2010 +0800
ARM: mxs: Add iomux support
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Andy Fleming <afleming@gmail.com>
This allows the SPL to avoid compiling in the CPU support code.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
timer.c used static data and are called before relocation.
Move all static variables into global_data structure. Also cleanup
timer.c from unused stubs and make it truly use 64 bit tick values.
Remove reset_timer_masked() get_timer_masked()
reference: arch/arm/cpu/arm926ejs/at91/timer.c
Based on Reinhard Meyer <u-boot@emk-elektronik.de>'s patches
5dca710a3dcfff263f41
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
da850_ddr_setup() expects the BOOTUNLOCK bit to be set in
If BOOTUNLOCK is not set in this define, several configuration
bits will not be writeable and the code will not work.
Since the BOOTUNLOCK and TIMUNLOCK bits are not configuration options
but access control bits, this patch changes the code to work
irrespective of the value of these bits in CONFIG_SYS_DA850_DDR2_SDBCR.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The LPSC functions defined in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
are replaced by those already defined in
arch/arm/cpu/arm926ejs/davinci/psc.c.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and
arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c
and da850_lowlevel.h since they apply not only to the AM1808 SoC
but to all DA850 chips. The function names and #defines are changed
likewise.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch fixes following compile error for da8xx evm
da830evm.c: In function 'board_init':
da830evm.c:222: error: 'DAVINCI_SYSCFG_SUSPSRC_UART2' undeclared (first use in this function)
da830evm.c:222: error: (Each undeclared identifier is reported only once
da830evm.c:222: error: for each function it appears in.)
make[2]: *** [da830evm.o] Error 1
similarly for da850evm.
introduced through commit:
f9fc237f1f
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
In addition to ensuring that PERCLK remains at least 2.5 times slower
than the AHB clock, certain steps need to be followed to ensure robust
operation of PERCLK when reconfiguring the PERCLK clock source.
To properly configure the PERCLK clock source, the following steps are
required:
1.In the CCGR registers, gate the clocks to all PERCLK-dependent
modules.
2.Select the desired input clock for the PERCLK root clock (to be either
source from the peripherals main source clock or the
lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit.
3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers
to the desired setting. Refer to the CBCDR register for details.
4.In the CCGR registers, enable the desired clocks for the
PERCLK-dependent module clocks.
If these steps aren't followed, GPT timer may stop and the kernel stops
at "Calibrating delay loop".
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Calculations for ACTIM_CTRLA amd ACTIM_CTRLB values
are defined in 'header' style comments.
Moved them along with definitions. Should help maintain
consistency between comments and code if any of these
are tweaked in future.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Define common macros to arrive at the values of registers
SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB for different memory
types.
This doesn't make any real change in the execution but
helps readability.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch is a port from the framebuffer driver
of the Linux driver drivers/video/da8xx-fb.c, used
on davinci da8xx and OMAP-L138 boards.
As base for the port, the following commit (last changes
for this driver at the moment in the Linux kernel tree)
was taken:
commit 1db41e032d563eb47deab40dc5595be306b143ba
Author: axel lin <axel.lin@gmail.com>
Date: Tue Feb 22 01:52:42 2011 +0000
video: da8xx-fb: fix section mismatch warning
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The hardware base address for ther LCD configuration
registers is missing, as well as some syscfg registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
used for booting (for example) from NAND using spl code.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Currently OMAP SPL code does all the initialization but does not set the
gd->have_console value so no output is actually performed. This patch
sets gd->have_console to 1.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
By default, on Kirkwood SoC DCache Lnd ICache line
lengths are 32 bytes long
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This generated file does not belong in the tree -> punt.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This allows to initialize DDR memory in C code.
Currently all mx31 boards use assembler code (lowlevel_init.S)
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31.
This function can be useful for setting a group of pins into tied to some specific peripherals.
Reuse this function from the linux kernel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
