Refs #123.

- Upgraded the XMClib to 2.1.8 in the XMC4700 Relax Kit demo programs.

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@164 5dc33758-31d5-4daf-9ae8-b24bf3d40d73

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.srec

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 S3150800195018B93120FFF7CAFE08BD034BFF22DA701B
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 S31508001990054B00221A709A6483F84320A3F8442062
-S315080019A09A705A70704700BF44090020024B187895
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 S315080019D0FF2B02D1FFF708FF50E0334A1278012A9D
 S315080019E060D1C93B352B46D8DFE803F0334545427D
 S315080019F045453F363C3945454545454545454545B3
@@ -425,10 +425,10 @@ S31508001A60AFFE0BE0FFF76EFF08E0FFF77FFF05E02C
 S31508001A70FFF7A0FE02E02020FFF738FE0A4B93F896
 S31508001A804330012B02D11020FFF730FE064BB3F985
 S31508001A904410002906DD1846012380F84330033038
-S31508001AA0FFF770FF08BD00BF4409002008B5074BC3
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 S31508001AB0044613B10021AFF30080054B1868836A0A
 S31508001AC003B19847204600F033F800BF0000000035
-S31508001AD0B41C000870B50E4B0E4CE41AA410002571
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 S31508001AF000F020F8084C094BE41AA41000251E46ED
 S31508001B00A54204D056F8253098470135F8E770BD48
@@ -437,36 +437,34 @@ S31508001B2002440346934202D003F8011BFAE77047C2
 S31508001B30FEE70000F8B500BFF8BC08BC9E46704733
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-S31508001D300000000000000000000000000000000095
-S30908001D400000000091
 S70508000000F2

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.depend

@@ -1064,60 +1064,60 @@
 	"led.h"
 	"xmc_gpio.h"
 
-1477087008 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\system_xmc4700.c
+1477087956 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\system_xmc4700.c
 	<string.h>
 	<XMC4700.h>
 	"system_XMC4700.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmc4700.h
+1473064960 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmc4700.h
 	"core_cm4.h"
 	"system_XMC4700.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cm4.h
+1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cm4.h
 	<stdint.h>
 	"core_cmInstr.h"
 	"core_cmFunc.h"
 	"core_cmSimd.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cminstr.h
+1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cminstr.h
-	<cmsis_armcc.h>
+	"cmsis_armcc.h"
-	<cmsis_armcc_V6.h>
+	"cmsis_armcc_V6.h"
-	<cmsis_gcc.h>
+	"cmsis_gcc.h"
 	<cmsis_iar.h>
 	<cmsis_ccs.h>
 	<cmsis_csm.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\cmsis_gcc.h
+1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\cmsis_gcc.h
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cmfunc.h
+1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cmfunc.h
-	<cmsis_armcc.h>
+	"cmsis_armcc.h"
-	<cmsis_armcc_V6.h>
+	"cmsis_armcc_V6.h"
-	<cmsis_gcc.h>
+	"cmsis_gcc.h"
 	<cmsis_iar.h>
 	<cmsis_ccs.h>
 	<cmsis_csm.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cmsimd.h
+1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\cmsis\core_cmsimd.h
-	<cmsis_armcc.h>
+	"cmsis_armcc.h"
-	<cmsis_armcc_V6.h>
+	"cmsis_armcc_V6.h"
-	<cmsis_gcc.h>
+	"cmsis_gcc.h"
 	<cmsis_iar.h>
 	<cmsis_ccs.h>
 	<cmsis_csm.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\system_xmc4700.h
+1468487305 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\system_xmc4700.h
 	<stdint.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_eru.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_eru.c
 	"xmc_eru.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eru.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eru.h
 	"xmc_common.h"
 	"xmc1_eru_map.h"
 	"xmc4_eru_map.h"
 
-1476977853 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_common.h
+1477088188 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_common.h
 	<stddef.h>
 	<stdint.h>
 	<stdbool.h>
@@ -1126,9 +1126,10 @@
 	"boot.h"
 	<stdio.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_device.h
+1469781874 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_device.h
 	"XMC4500.h"
 	"XMC4400.h"
+	"XMC4300.h"
 	"XMC4200.h"
 	"XMC4100.h"
 	"XMC4700.h"
@@ -1138,251 +1139,251 @@
 	"XMC1300.h"
 	"XMC1400.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_eru_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_eru_map.h
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_scu.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_scu.h
 	<xmc_common.h>
 	<xmc1_scu.h>
 	<xmc4_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_scu.h
+1467383079 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_scu.h
 	"xmc_common.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_flash.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_flash.c
 	"xmc_flash.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_flash.h
+1471242129 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_flash.h
 	"xmc_common.h"
 	"xmc1_flash.h"
 	"xmc4_flash.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_flash.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_flash.h
 	"xmc_common.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_gpio.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_gpio.c
 	"xmc_gpio.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_gpio.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_gpio.h
 	"xmc_common.h"
 	"xmc1_gpio.h"
 	"xmc4_gpio.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_gpio.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_gpio.h
 	"xmc_common.h"
 	"xmc4_gpio_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_gpio_map.h
+1471903247 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_gpio_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_rtc.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_rtc.c
 	<xmc_rtc.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_rtc.h
+1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_rtc.h
 	<xmc_common.h>
 	<time.h>
 	"xmc1_rtc.h"
 	"xmc4_rtc.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_rtc.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_rtc.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_scu.c
+1467379907 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc4_scu.c
 	<xmc_scu.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_can.c
+1467378878 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_can.c
 	"xmc_can.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_can.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_can.h
 	"xmc_common.h"
 	"xmc_scu.h"
 	"xmc_can_map.h"
 	<string.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_can_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_can_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ccu4.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ccu4.c
 	"xmc_ccu4.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ccu4.h
+1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ccu4.h
 	"xmc_common.h"
 	"xmc1_ccu4_map.h"
 	"xmc4_ccu4_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_ccu4_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_ccu4_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ccu8.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ccu8.c
 	"xmc_ccu8.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ccu8.h
+1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ccu8.h
 	"xmc_common.h"
 	"xmc1_ccu8_map.h"
 	"xmc4_ccu8_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_ccu8_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_ccu8_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_common.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_common.c
 	"xmc_common.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dac.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dac.c
 	<xmc_dac.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dac.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dac.h
 	<xmc_common.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dma.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dma.c
 	"xmc_dma.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dma.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dma.h
 	"xmc_common.h"
 	"xmc_dma_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dma_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dma_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dsd.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_dsd.c
 	"xmc_dsd.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dsd.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_dsd.h
 	<xmc_common.h>
 	<xmc_scu.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ebu.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ebu.c
 	<xmc_ebu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ebu.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ebu.h
 	<xmc_common.h>
 	<xmc_scu.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_eru.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_eru.c
 	"xmc_eru.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_eth_mac.c
+1472543436 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_eth_mac.c
 	<xmc_eth_mac.h>
 	<stdlib.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eth_mac.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eth_mac.h
 	"xmc_common.h"
 	"xmc_eth_mac_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eth_mac_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_eth_mac_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_fce.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_fce.c
 	<xmc_fce.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_fce.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_fce.h
 	<xmc_common.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_gpio.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_gpio.c
 	<xmc_gpio.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_hrpwm.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_hrpwm.c
 	<xmc_hrpwm.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_hrpwm.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_hrpwm.h
 	<xmc_common.h>
 	<xmc_hrpwm_map.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_hrpwm_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_hrpwm_map.h
 	"xmc_hrpwm.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_i2c.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_i2c.c
 	<xmc_i2c.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_i2c.h
+1471939947 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_i2c.h
 	"xmc_usic.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usic.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usic.h
 	"xmc_common.h"
 	"xmc1_usic_map.h"
 	"xmc4_usic_map.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_usic_map.h
+1469014921 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc4_usic_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_i2s.c
+1469450032 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_i2s.c
 	<xmc_scu.h>
 	<xmc_i2s.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_i2s.h
+1468425037 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_i2s.h
 	"xmc_usic.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ledts.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ledts.c
 	<xmc_ledts.h>
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ledts.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ledts.h
 	<xmc_common.h>
 	"xmc_scu.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_posif.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_posif.c
 	<xmc_posif.h>
 	<xmc_scu.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_posif.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_posif.h
 	<xmc_common.h>
 	<xmc_scu.h>
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_rtc.c
+1467378878 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_rtc.c
 	"xmc_scu.h"
 	"xmc_rtc.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_sdmmc.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_sdmmc.c
 	"xmc_sdmmc.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_sdmmc.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_sdmmc.h
 	"xmc_common.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_spi.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_spi.c
 	<xmc_scu.h>
 	<xmc_spi.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_spi.h
+1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_spi.h
 	"xmc_usic.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_uart.c
+1469448524 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_uart.c
 	<xmc_scu.h>
 	<xmc_uart.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_uart.h
+1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_uart.h
 	"xmc_usic.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_usbd.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_usbd.c
 	<xmc_usbd.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usbd.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usbd.h
 	"xmc_common.h"
 	<stdlib.h>
 	<string.h>
 	"xmc_usbd_regs.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usbd_regs.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usbd_regs.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_usic.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_usic.c
 	"xmc_usic.h"
 	"xmc_scu.h"
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_vadc.c
+1470204802 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_vadc.c
 	<xmc_vadc.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_vadc.h
+1470205055 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_vadc.h
 	<xmc_common.h>
 	<xmc_scu.h>
 	<xmc_vadc_map.h>
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_vadc_map.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_vadc_map.h
 
-1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_wdt.c
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_wdt.c
 	"xmc_wdt.h"
 	"xmc_scu.h"
 
-1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_wdt.h
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_wdt.h
 	"xmc_common.h"
 	"xmc_scu.h"
 
@@ -1458,3 +1459,56 @@
 1476787063 source:c:\work\software\openblt\target\source\xcp.c
 	"boot.h"
 
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_acmp.c
+	<xmc_acmp.h>
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_acmp.h
+	<xmc_common.h>
+
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_bccu.c
+	<xmc_bccu.h>
+	<xmc_scu.h>
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_bccu.h
+	<xmc_common.h>
+
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_ecat.c
+	<xmc_ecat.h>
+	<xmc_scu.h>
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ecat.h
+	"xmc_common.h"
+	"xmc_ecat_map.h"
+
+1469014958 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_ecat_map.h
+
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_math.c
+	<xmc_math.h>
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_math.h
+	<xmc_common.h>
+	<xmc_scu.h>
+
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_pau.c
+	"xmc_pau.h"
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_pau.h
+	"xmc_common.h"
+
+1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_prng.c
+	"xmc_prng.h"
+
+1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_prng.h
+	"xmc_common.h"
+
+1473236602 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\src\xmc_usbh.c
+	<stdint.h>
+	<string.h>
+	"xmc_usbh.h"
+
+1473236602 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\lib\xmclib\inc\xmc_usbh.h
+	<stdint.h>
+	"xmc_common.h"
+	"xmc_scu.h"
+	"xmc_gpio.h"
+

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.ebp

@@ -123,6 +123,12 @@
 		<Unit filename="..\lib\xmclib\inc\xmc4_usic_map.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_acmp.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_bccu.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\inc\xmc_can.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
@@ -156,6 +162,12 @@
 		<Unit filename="..\lib\xmclib\inc\xmc_ebu.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_ecat.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_ecat_map.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\inc\xmc_eru.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
@@ -192,9 +204,18 @@
 		<Unit filename="..\lib\xmclib\inc\xmc_ledts.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_math.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_pau.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\inc\xmc_posif.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_prng.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\inc\xmc_rtc.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
@@ -216,6 +237,9 @@
 		<Unit filename="..\lib\xmclib\inc\xmc_usbd_regs.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\inc\xmc_usbh.h">
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\inc\xmc_usic.h">
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
@@ -248,6 +272,14 @@
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_acmp.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_bccu.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\src\xmc_can.c">
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
@@ -280,6 +312,10 @@
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_ecat.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\src\xmc_eru.c">
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
@@ -312,10 +348,22 @@
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_math.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_pau.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\src\xmc_posif.c">
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_prng.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\src\xmc_rtc.c">
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
@@ -336,6 +384,10 @@
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />
 		</Unit>
+		<Unit filename="..\lib\xmclib\src\xmc_usbh.c">
+			<Option compilerVar="CC" />
+			<Option virtualFolder="Libs\xmclib\" />
+		</Unit>
 		<Unit filename="..\lib\xmclib\src\xmc_usic.c">
 			<Option compilerVar="CC" />
 			<Option virtualFolder="Libs\xmclib\" />

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.elay

@@ -21,7 +21,7 @@
 			<Cursor1 position="98456" topLine="1476" />
 		</Cursor>
 	</File>
-	<File name="..\lib\system_XMC4700.c" open="1" top="0" tabpos="4" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\lib\system_XMC4700.c" open="0" top="0" tabpos="4" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="17807" topLine="523" />
 		</Cursor>
@@ -31,92 +31,22 @@
 			<Cursor1 position="1661" topLine="49" />
 		</Cursor>
 	</File>
-	<File name="..\lib\XMC4700.h" open="1" top="0" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\lib\XMC4700.h" open="0" top="0" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="66765" topLine="905" />
 		</Cursor>
 	</File>
-	<File name="..\lib\xmclib\inc\xmc4_flash.h" open="0" top="0" tabpos="5" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\main.c" open="1" top="1" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="9778" topLine="127" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc4_gpio.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="8382" topLine="5" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc4_gpio_map.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="263856" topLine="5203" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_common.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="3525" topLine="75" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_device.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="6177" topLine="189" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_eth_mac.h" open="0" top="0" tabpos="4" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="7685" topLine="154" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_flash.h" open="0" top="0" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="9994" topLine="216" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_gpio.h" open="0" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="12994" topLine="302" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_i2c.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="20823" topLine="400" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_uart.h" open="0" top="0" tabpos="9" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="30672" topLine="504" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\inc\xmc_usic.h" open="0" top="0" tabpos="6" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="74389" topLine="1577" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\src\xmc4_flash.c" open="0" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="8220" topLine="201" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\src\xmc_ccu4.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="10141" topLine="255" />
-		</Cursor>
-	</File>
-	<File name="..\lib\xmclib\src\xmc_uart.c" open="0" top="0" tabpos="8" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
-		<Cursor>
-			<Cursor1 position="6208" topLine="126" />
-		</Cursor>
-	</File>
-	<File name="..\main.c" open="1" top="0" tabpos="11" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="2813" topLine="44" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\ARMCM4_XMC4\cpu.c" open="1" top="0" tabpos="8" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\ARMCM4_XMC4\cpu.c" open="0" top="0" tabpos="8" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="1868" topLine="25" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\ARMCM4_XMC4\flash.c" open="1" top="0" tabpos="10" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\ARMCM4_XMC4\flash.c" open="0" top="0" tabpos="10" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="20187" topLine="363" />
 		</Cursor>
@@ -126,12 +56,12 @@
 			<Cursor1 position="1056" topLine="0" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\ARMCM4_XMC4\GCC\cstart.S" open="1" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\ARMCM4_XMC4\GCC\cstart.S" open="0" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="13894" topLine="243" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\ARMCM4_XMC4\nvm.c" open="1" top="0" tabpos="6" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\ARMCM4_XMC4\nvm.c" open="0" top="0" tabpos="6" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="6447" topLine="121" />
 		</Cursor>
@@ -141,7 +71,7 @@
 			<Cursor1 position="3938" topLine="66" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\ARMCM4_XMC4\uart.c" open="1" top="0" tabpos="9" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\ARMCM4_XMC4\uart.c" open="0" top="0" tabpos="9" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="5181" topLine="57" />
 		</Cursor>
@@ -156,7 +86,7 @@
 			<Cursor1 position="6335" topLine="102" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\boot.c" open="1" top="1" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\boot.c" open="0" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="3280" topLine="27" />
 		</Cursor>
@@ -166,14 +96,14 @@
 			<Cursor1 position="4620" topLine="85" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\cop.c" open="1" top="0" tabpos="7" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\cop.c" open="0" top="0" tabpos="7" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
 			<Cursor1 position="2879" topLine="10" />
 		</Cursor>
 	</File>
-	<File name="..\..\..\..\Source\xcp.c" open="1" top="0" tabpos="5" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
+	<File name="..\..\..\..\Source\xcp.c" open="0" top="0" tabpos="5" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
 		<Cursor>
-			<Cursor1 position="41076" topLine="1124" />
+			<Cursor1 position="10852" topLine="250" />
 		</Cursor>
 	</File>
 </EmBitz_layout_file>

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/XMC4700.h

@@ -1,21 +1,30 @@
-/****************************************************************************/
+/*********************************************************************************************************************
-/**
+ * Copyright (c) 2015-2016, Infineon Technologies AG
-Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
+ * All rights reserved.                        
-* 
+ *                                             
-*
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
-* @par
+ * following conditions are met:   
-* Infineon Technologies AG (Infineon) is supplying this software for use with 
+ *                                                                              
-* Infineon's microcontrollers.  This file can be freely distributed within
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
-* development tools that are supporting such microcontrollers.
+ * disclaimer.                        
-*
+ * 
-* @par
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
-* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
-* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * 
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
-* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * products derived from this software without specific prior written permission.                                           
-* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *                                                                              
-*
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
-******************************************************************************/
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************/
 
 
 /****************************************************************************************************//**
@@ -24,11 +33,11 @@ Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
  * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
  *           XMC4700 from Infineon.
  *
- * @version  V1.0.1 (Reference Manual v1.0)
+ * @version  V1.3.0 (Reference Manual v1.3)
- * @date     14. September 2015
+ * @date     30. August 2016
  *
- * @note     Generated with SVDConv V2.87g 
+ * @note     Generated with SVDConv V2.87l 
- *           from CMSIS SVD File 'XMC4700_Processed_SVD.xml' Version 1.0.1 (Reference Manual v1.0),
+ *           from CMSIS SVD File 'XMC4700_Processed_SVD.xml' Version 1.3.0 (Reference Manual v1.3),
  *******************************************************************************************************/
 
 
@@ -66,107 +75,107 @@ typedef enum {
   PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
   SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
 /* ---------------------  XMC4700 Specific Interrupt Numbers  --------------------- */
-  SCU_0_IRQn                    =   0,              /*!<   0  SCU_0                                                            */
+  SCU_0_IRQn                    =   0,              /*!<   0  System Control                                                   */
-  ERU0_0_IRQn                   =   1,              /*!<   1  ERU0_0                                                           */
+  ERU0_0_IRQn                   =   1,              /*!<   1  External Request Unit 0                                          */
-  ERU0_1_IRQn                   =   2,              /*!<   2  ERU0_1                                                           */
+  ERU0_1_IRQn                   =   2,              /*!<   2  External Request Unit 0                                          */
-  ERU0_2_IRQn                   =   3,              /*!<   3  ERU0_2                                                           */
+  ERU0_2_IRQn                   =   3,              /*!<   3  External Request Unit 0                                          */
-  ERU0_3_IRQn                   =   4,              /*!<   4  ERU0_3                                                           */
+  ERU0_3_IRQn                   =   4,              /*!<   4  External Request Unit 0                                          */
-  ERU1_0_IRQn                   =   5,              /*!<   5  ERU1_0                                                           */
+  ERU1_0_IRQn                   =   5,              /*!<   5  External Request Unit 1                                          */
-  ERU1_1_IRQn                   =   6,              /*!<   6  ERU1_1                                                           */
+  ERU1_1_IRQn                   =   6,              /*!<   6  External Request Unit 1                                          */
-  ERU1_2_IRQn                   =   7,              /*!<   7  ERU1_2                                                           */
+  ERU1_2_IRQn                   =   7,              /*!<   7  External Request Unit 1                                          */
-  ERU1_3_IRQn                   =   8,              /*!<   8  ERU1_3                                                           */
+  ERU1_3_IRQn                   =   8,              /*!<   8  External Request Unit 1                                          */
-  PMU0_0_IRQn                   =  12,              /*!<  12  PMU0_0                                                           */
+  PMU0_0_IRQn                   =  12,              /*!<  12  Program Management Unit                                          */
-  VADC0_C0_0_IRQn               =  14,              /*!<  14  VADC0_C0_0                                                       */
+  VADC0_C0_0_IRQn               =  14,              /*!<  14  Analog to Digital Converter Common Block 0                       */
-  VADC0_C0_1_IRQn               =  15,              /*!<  15  VADC0_C0_1                                                       */
+  VADC0_C0_1_IRQn               =  15,              /*!<  15  Analog to Digital Converter Common Block 0                       */
-  VADC0_C0_2_IRQn               =  16,              /*!<  16  VADC0_C0_2                                                       */
+  VADC0_C0_2_IRQn               =  16,              /*!<  16  Analog to Digital Converter Common Block 0                       */
-  VADC0_C0_3_IRQn               =  17,              /*!<  17  VADC0_C0_3                                                       */
+  VADC0_C0_3_IRQn               =  17,              /*!<  17  Analog to Digital Converter Common Block 0                       */
-  VADC0_G0_0_IRQn               =  18,              /*!<  18  VADC0_G0_0                                                       */
+  VADC0_G0_0_IRQn               =  18,              /*!<  18  Analog to Digital Converter Group 0                              */
-  VADC0_G0_1_IRQn               =  19,              /*!<  19  VADC0_G0_1                                                       */
+  VADC0_G0_1_IRQn               =  19,              /*!<  19  Analog to Digital Converter Group 0                              */
-  VADC0_G0_2_IRQn               =  20,              /*!<  20  VADC0_G0_2                                                       */
+  VADC0_G0_2_IRQn               =  20,              /*!<  20  Analog to Digital Converter Group 0                              */
-  VADC0_G0_3_IRQn               =  21,              /*!<  21  VADC0_G0_3                                                       */
+  VADC0_G0_3_IRQn               =  21,              /*!<  21  Analog to Digital Converter Group 0                              */
-  VADC0_G1_0_IRQn               =  22,              /*!<  22  VADC0_G1_0                                                       */
+  VADC0_G1_0_IRQn               =  22,              /*!<  22  Analog to Digital Converter Group 1                              */
-  VADC0_G1_1_IRQn               =  23,              /*!<  23  VADC0_G1_1                                                       */
+  VADC0_G1_1_IRQn               =  23,              /*!<  23  Analog to Digital Converter Group 1                              */
-  VADC0_G1_2_IRQn               =  24,              /*!<  24  VADC0_G1_2                                                       */
+  VADC0_G1_2_IRQn               =  24,              /*!<  24  Analog to Digital Converter Group 1                              */
-  VADC0_G1_3_IRQn               =  25,              /*!<  25  VADC0_G1_3                                                       */
+  VADC0_G1_3_IRQn               =  25,              /*!<  25  Analog to Digital Converter Group 1                              */
-  VADC0_G2_0_IRQn               =  26,              /*!<  26  VADC0_G2_0                                                       */
+  VADC0_G2_0_IRQn               =  26,              /*!<  26  Analog to Digital Converter Group 2                              */
-  VADC0_G2_1_IRQn               =  27,              /*!<  27  VADC0_G2_1                                                       */
+  VADC0_G2_1_IRQn               =  27,              /*!<  27  Analog to Digital Converter Group 2                              */
-  VADC0_G2_2_IRQn               =  28,              /*!<  28  VADC0_G2_2                                                       */
+  VADC0_G2_2_IRQn               =  28,              /*!<  28  Analog to Digital Converter Group 2                              */
-  VADC0_G2_3_IRQn               =  29,              /*!<  29  VADC0_G2_3                                                       */
+  VADC0_G2_3_IRQn               =  29,              /*!<  29  Analog to Digital Converter Group 2                              */
-  VADC0_G3_0_IRQn               =  30,              /*!<  30  VADC0_G3_0                                                       */
+  VADC0_G3_0_IRQn               =  30,              /*!<  30  Analog to Digital Converter Group 3                              */
-  VADC0_G3_1_IRQn               =  31,              /*!<  31  VADC0_G3_1                                                       */
+  VADC0_G3_1_IRQn               =  31,              /*!<  31  Analog to Digital Converter Group 3                              */
-  VADC0_G3_2_IRQn               =  32,              /*!<  32  VADC0_G3_2                                                       */
+  VADC0_G3_2_IRQn               =  32,              /*!<  32  Analog to Digital Converter Group 3                              */
-  VADC0_G3_3_IRQn               =  33,              /*!<  33  VADC0_G3_3                                                       */
+  VADC0_G3_3_IRQn               =  33,              /*!<  33  Analog to Digital Converter Group 3                              */
-  DSD0_M_0_IRQn                 =  34,              /*!<  34  DSD0_M_0                                                         */
+  DSD0_M_0_IRQn                 =  34,              /*!<  34  Delta Sigma Demodulator Main                                     */
-  DSD0_M_1_IRQn                 =  35,              /*!<  35  DSD0_M_1                                                         */
+  DSD0_M_1_IRQn                 =  35,              /*!<  35  Delta Sigma Demodulator Main                                     */
-  DSD0_M_2_IRQn                 =  36,              /*!<  36  DSD0_M_2                                                         */
+  DSD0_M_2_IRQn                 =  36,              /*!<  36  Delta Sigma Demodulator Main                                     */
-  DSD0_M_3_IRQn                 =  37,              /*!<  37  DSD0_M_3                                                         */
+  DSD0_M_3_IRQn                 =  37,              /*!<  37  Delta Sigma Demodulator Main                                     */
-  DSD0_A_4_IRQn                 =  38,              /*!<  38  DSD0_A_4                                                         */
+  DSD0_A_4_IRQn                 =  38,              /*!<  38  Delta Sigma Demodulator Auxiliary                                */
-  DSD0_A_5_IRQn                 =  39,              /*!<  39  DSD0_A_5                                                         */
+  DSD0_A_5_IRQn                 =  39,              /*!<  39  Delta Sigma Demodulator Auxiliary                                */
-  DSD0_A_6_IRQn                 =  40,              /*!<  40  DSD0_A_6                                                         */
+  DSD0_A_6_IRQn                 =  40,              /*!<  40  Delta Sigma Demodulator Auxiliary                                */
-  DSD0_A_7_IRQn                 =  41,              /*!<  41  DSD0_A_7                                                         */
+  DSD0_A_7_IRQn                 =  41,              /*!<  41  Delta Sigma Demodulator Auxiliary                                */
-  DAC0_0_IRQn                   =  42,              /*!<  42  DAC0_0                                                           */
+  DAC0_0_IRQn                   =  42,              /*!<  42  Digital to Analog Converter                                      */
-  DAC0_1_IRQn                   =  43,              /*!<  43  DAC0_1                                                           */
+  DAC0_1_IRQn                   =  43,              /*!<  43  Digital to Analog Converter                                      */
-  CCU40_0_IRQn                  =  44,              /*!<  44  CCU40_0                                                          */
+  CCU40_0_IRQn                  =  44,              /*!<  44  Capture Compare Unit 4 (Module 0)                                */
-  CCU40_1_IRQn                  =  45,              /*!<  45  CCU40_1                                                          */
+  CCU40_1_IRQn                  =  45,              /*!<  45  Capture Compare Unit 4 (Module 0)                                */
-  CCU40_2_IRQn                  =  46,              /*!<  46  CCU40_2                                                          */
+  CCU40_2_IRQn                  =  46,              /*!<  46  Capture Compare Unit 4 (Module 0)                                */
-  CCU40_3_IRQn                  =  47,              /*!<  47  CCU40_3                                                          */
+  CCU40_3_IRQn                  =  47,              /*!<  47  Capture Compare Unit 4 (Module 0)                                */
-  CCU41_0_IRQn                  =  48,              /*!<  48  CCU41_0                                                          */
+  CCU41_0_IRQn                  =  48,              /*!<  48  Capture Compare Unit 4 (Module 1)                                */
-  CCU41_1_IRQn                  =  49,              /*!<  49  CCU41_1                                                          */
+  CCU41_1_IRQn                  =  49,              /*!<  49  Capture Compare Unit 4 (Module 1)                                */
-  CCU41_2_IRQn                  =  50,              /*!<  50  CCU41_2                                                          */
+  CCU41_2_IRQn                  =  50,              /*!<  50  Capture Compare Unit 4 (Module 1)                                */
-  CCU41_3_IRQn                  =  51,              /*!<  51  CCU41_3                                                          */
+  CCU41_3_IRQn                  =  51,              /*!<  51  Capture Compare Unit 4 (Module 1)                                */
-  CCU42_0_IRQn                  =  52,              /*!<  52  CCU42_0                                                          */
+  CCU42_0_IRQn                  =  52,              /*!<  52  Capture Compare Unit 4 (Module 2)                                */
-  CCU42_1_IRQn                  =  53,              /*!<  53  CCU42_1                                                          */
+  CCU42_1_IRQn                  =  53,              /*!<  53  Capture Compare Unit 4 (Module 2)                                */
-  CCU42_2_IRQn                  =  54,              /*!<  54  CCU42_2                                                          */
+  CCU42_2_IRQn                  =  54,              /*!<  54  Capture Compare Unit 4 (Module 2)                                */
-  CCU42_3_IRQn                  =  55,              /*!<  55  CCU42_3                                                          */
+  CCU42_3_IRQn                  =  55,              /*!<  55  Capture Compare Unit 4 (Module 2)                                */
-  CCU43_0_IRQn                  =  56,              /*!<  56  CCU43_0                                                          */
+  CCU43_0_IRQn                  =  56,              /*!<  56  Capture Compare Unit 4 (Module 3)                                */
-  CCU43_1_IRQn                  =  57,              /*!<  57  CCU43_1                                                          */
+  CCU43_1_IRQn                  =  57,              /*!<  57  Capture Compare Unit 4 (Module 3)                                */
-  CCU43_2_IRQn                  =  58,              /*!<  58  CCU43_2                                                          */
+  CCU43_2_IRQn                  =  58,              /*!<  58  Capture Compare Unit 4 (Module 3)                                */
-  CCU43_3_IRQn                  =  59,              /*!<  59  CCU43_3                                                          */
+  CCU43_3_IRQn                  =  59,              /*!<  59  Capture Compare Unit 4 (Module 3)                                */
-  CCU80_0_IRQn                  =  60,              /*!<  60  CCU80_0                                                          */
+  CCU80_0_IRQn                  =  60,              /*!<  60  Capture Compare Unit 8 (Module 0)                                */
-  CCU80_1_IRQn                  =  61,              /*!<  61  CCU80_1                                                          */
+  CCU80_1_IRQn                  =  61,              /*!<  61  Capture Compare Unit 8 (Module 0)                                */
-  CCU80_2_IRQn                  =  62,              /*!<  62  CCU80_2                                                          */
+  CCU80_2_IRQn                  =  62,              /*!<  62  Capture Compare Unit 8 (Module 0)                                */
-  CCU80_3_IRQn                  =  63,              /*!<  63  CCU80_3                                                          */
+  CCU80_3_IRQn                  =  63,              /*!<  63  Capture Compare Unit 8 (Module 0)                                */
-  CCU81_0_IRQn                  =  64,              /*!<  64  CCU81_0                                                          */
+  CCU81_0_IRQn                  =  64,              /*!<  64  Capture Compare Unit 8 (Module 1)                                */
-  CCU81_1_IRQn                  =  65,              /*!<  65  CCU81_1                                                          */
+  CCU81_1_IRQn                  =  65,              /*!<  65  Capture Compare Unit 8 (Module 1)                                */
-  CCU81_2_IRQn                  =  66,              /*!<  66  CCU81_2                                                          */
+  CCU81_2_IRQn                  =  66,              /*!<  66  Capture Compare Unit 8 (Module 1)                                */
-  CCU81_3_IRQn                  =  67,              /*!<  67  CCU81_3                                                          */
+  CCU81_3_IRQn                  =  67,              /*!<  67  Capture Compare Unit 8 (Module 1)                                */
-  POSIF0_0_IRQn                 =  68,              /*!<  68  POSIF0_0                                                         */
+  POSIF0_0_IRQn                 =  68,              /*!<  68  Position Interface (Module 0)                                    */
-  POSIF0_1_IRQn                 =  69,              /*!<  69  POSIF0_1                                                         */
+  POSIF0_1_IRQn                 =  69,              /*!<  69  Position Interface (Module 0)                                    */
-  POSIF1_0_IRQn                 =  70,              /*!<  70  POSIF1_0                                                         */
+  POSIF1_0_IRQn                 =  70,              /*!<  70  Position Interface (Module 1)                                    */
-  POSIF1_1_IRQn                 =  71,              /*!<  71  POSIF1_1                                                         */
+  POSIF1_1_IRQn                 =  71,              /*!<  71  Position Interface (Module 1)                                    */
-  CAN0_0_IRQn                   =  76,              /*!<  76  CAN0_0                                                           */
+  CAN0_0_IRQn                   =  76,              /*!<  76  MultiCAN                                                         */
-  CAN0_1_IRQn                   =  77,              /*!<  77  CAN0_1                                                           */
+  CAN0_1_IRQn                   =  77,              /*!<  77  MultiCAN                                                         */
-  CAN0_2_IRQn                   =  78,              /*!<  78  CAN0_2                                                           */
+  CAN0_2_IRQn                   =  78,              /*!<  78  MultiCAN                                                         */
-  CAN0_3_IRQn                   =  79,              /*!<  79  CAN0_3                                                           */
+  CAN0_3_IRQn                   =  79,              /*!<  79  MultiCAN                                                         */
-  CAN0_4_IRQn                   =  80,              /*!<  80  CAN0_4                                                           */
+  CAN0_4_IRQn                   =  80,              /*!<  80  MultiCAN                                                         */
-  CAN0_5_IRQn                   =  81,              /*!<  81  CAN0_5                                                           */
+  CAN0_5_IRQn                   =  81,              /*!<  81  MultiCAN                                                         */
-  CAN0_6_IRQn                   =  82,              /*!<  82  CAN0_6                                                           */
+  CAN0_6_IRQn                   =  82,              /*!<  82  MultiCAN                                                         */
-  CAN0_7_IRQn                   =  83,              /*!<  83  CAN0_7                                                           */
+  CAN0_7_IRQn                   =  83,              /*!<  83  MultiCAN                                                         */
-  USIC0_0_IRQn                  =  84,              /*!<  84  USIC0_0                                                          */
+  USIC0_0_IRQn                  =  84,              /*!<  84  Universal Serial Interface Channel (Module 0)                    */
-  USIC0_1_IRQn                  =  85,              /*!<  85  USIC0_1                                                          */
+  USIC0_1_IRQn                  =  85,              /*!<  85  Universal Serial Interface Channel (Module 0)                    */
-  USIC0_2_IRQn                  =  86,              /*!<  86  USIC0_2                                                          */
+  USIC0_2_IRQn                  =  86,              /*!<  86  Universal Serial Interface Channel (Module 0)                    */
-  USIC0_3_IRQn                  =  87,              /*!<  87  USIC0_3                                                          */
+  USIC0_3_IRQn                  =  87,              /*!<  87  Universal Serial Interface Channel (Module 0)                    */
-  USIC0_4_IRQn                  =  88,              /*!<  88  USIC0_4                                                          */
+  USIC0_4_IRQn                  =  88,              /*!<  88  Universal Serial Interface Channel (Module 0)                    */
-  USIC0_5_IRQn                  =  89,              /*!<  89  USIC0_5                                                          */
+  USIC0_5_IRQn                  =  89,              /*!<  89  Universal Serial Interface Channel (Module 0)                    */
-  USIC1_0_IRQn                  =  90,              /*!<  90  USIC1_0                                                          */
+  USIC1_0_IRQn                  =  90,              /*!<  90  Universal Serial Interface Channel (Module 1)                    */
-  USIC1_1_IRQn                  =  91,              /*!<  91  USIC1_1                                                          */
+  USIC1_1_IRQn                  =  91,              /*!<  91  Universal Serial Interface Channel (Module 1)                    */
-  USIC1_2_IRQn                  =  92,              /*!<  92  USIC1_2                                                          */
+  USIC1_2_IRQn                  =  92,              /*!<  92  Universal Serial Interface Channel (Module 1)                    */
-  USIC1_3_IRQn                  =  93,              /*!<  93  USIC1_3                                                          */
+  USIC1_3_IRQn                  =  93,              /*!<  93  Universal Serial Interface Channel (Module 1)                    */
-  USIC1_4_IRQn                  =  94,              /*!<  94  USIC1_4                                                          */
+  USIC1_4_IRQn                  =  94,              /*!<  94  Universal Serial Interface Channel (Module 1)                    */
-  USIC1_5_IRQn                  =  95,              /*!<  95  USIC1_5                                                          */
+  USIC1_5_IRQn                  =  95,              /*!<  95  Universal Serial Interface Channel (Module 1)                    */
-  USIC2_0_IRQn                  =  96,              /*!<  96  USIC2_0                                                          */
+  USIC2_0_IRQn                  =  96,              /*!<  96  Universal Serial Interface Channel (Module 2)                    */
-  USIC2_1_IRQn                  =  97,              /*!<  97  USIC2_1                                                          */
+  USIC2_1_IRQn                  =  97,              /*!<  97  Universal Serial Interface Channel (Module 2)                    */
-  USIC2_2_IRQn                  =  98,              /*!<  98  USIC2_2                                                          */
+  USIC2_2_IRQn                  =  98,              /*!<  98  Universal Serial Interface Channel (Module 2)                    */
-  USIC2_3_IRQn                  =  99,              /*!<  99  USIC2_3                                                          */
+  USIC2_3_IRQn                  =  99,              /*!<  99  Universal Serial Interface Channel (Module 2)                    */
-  USIC2_4_IRQn                  = 100,              /*!< 100  USIC2_4                                                          */
+  USIC2_4_IRQn                  = 100,              /*!< 100  Universal Serial Interface Channel (Module 2)                    */
-  USIC2_5_IRQn                  = 101,              /*!< 101  USIC2_5                                                          */
+  USIC2_5_IRQn                  = 101,              /*!< 101  Universal Serial Interface Channel (Module 2)                    */
-  LEDTS0_0_IRQn                 = 102,              /*!< 102  LEDTS0_0                                                         */
+  LEDTS0_0_IRQn                 = 102,              /*!< 102  LED and Touch Sense Control Unit (Module 0)                      */
-  FCE0_0_IRQn                   = 104,              /*!< 104  FCE0_0                                                           */
+  FCE0_0_IRQn                   = 104,              /*!< 104  Flexible CRC Engine                                              */
-  GPDMA0_0_IRQn                 = 105,              /*!< 105  GPDMA0_0                                                         */
+  GPDMA0_0_IRQn                 = 105,              /*!< 105  General Purpose DMA Unit 0                                       */
-  SDMMC0_0_IRQn                 = 106,              /*!< 106  SDMMC0_0                                                         */
+  SDMMC0_0_IRQn                 = 106,              /*!< 106  Multi Media Card Interface                                       */
-  USB0_0_IRQn                   = 107,              /*!< 107  USB0_0                                                           */
+  USB0_0_IRQn                   = 107,              /*!< 107  Universal Serial Bus (Module 0)                                  */
-  ETH0_0_IRQn                   = 108,              /*!< 108  ETH0_0                                                           */
+  ETH0_0_IRQn                   = 108,              /*!< 108  Ethernet (Module 0)                                              */
-  GPDMA1_0_IRQn                 = 110               /*!< 110  GPDMA1_0                                                         */
+  GPDMA1_0_IRQn                 = 110               /*!< 110  General Purpose DMA Unit 1                                       */
 } IRQn_Type;
 
 
@@ -1217,9 +1226,7 @@ typedef struct {                                    /*!< (@ 0x4801C000) SDMMC St
   __O  uint16_t  FORCE_EVENT_ERR_STATUS;            /*!< (@ 0x4801C052) Force Event Register for Error Interrupt Status        */
   __I  uint32_t  RESERVED3[8];
   __O  uint32_t  DEBUG_SEL;                         /*!< (@ 0x4801C074) Debug Selection Register                               */
-  __I  uint32_t  RESERVED4[30];
+  __I  uint32_t  RESERVED4[33];
-  __IO uint32_t  SPI;                               /*!< (@ 0x4801C0F0) SPI Interrupt Support Register                         */
-  __I  uint32_t  RESERVED5[2];
   __I  uint16_t  SLOT_INT_STATUS;                   /*!< (@ 0x4801C0FC) Slot Interrupt Status Register                         */
 } SDMMC_GLOBAL_TypeDef;
 
@@ -2078,9 +2085,7 @@ typedef struct {                                    /*!< (@ 0x40020000) CCU8 Str
   __O  uint32_t  GCSC;                              /*!< (@ 0x40020014) Global Channel Clear                                   */
   __I  uint32_t  GCST;                              /*!< (@ 0x40020018) Global Channel status                                  */
   __IO uint32_t  GPCHK;                             /*!< (@ 0x4002001C) Parity Checker Configuration                           */
-  __I  uint32_t  RESERVED[12];
+  __I  uint32_t  RESERVED[24];
-  __I  uint32_t  ECRD;                              /*!< (@ 0x40020050) Extended Capture Mode Read                             */
-  __I  uint32_t  RESERVED1[11];
   __I  uint32_t  MIDR;                              /*!< (@ 0x40020080) Module Identification                                  */
 } CCU8_GLOBAL_TypeDef;
 
@@ -5763,8 +5768,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_GENERAL_MIRRSTS_HDCR_Msk          (0x8UL)                   /*!< SCU_GENERAL MIRRSTS: HDCR (Bitfield-Mask: 0x01)             */
 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos     (5UL)                     /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bit 5)                      */
 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk     (0x20UL)                  /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bitfield-Mask: 0x01)        */
-#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos     (6UL)                     /*!< SCU_GENERAL MIRRSTS: OSCULSTAT (Bit 6)                      */
-#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk     (0x40UL)                  /*!< SCU_GENERAL MIRRSTS: OSCULSTAT (Bitfield-Mask: 0x01)        */
 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos     (7UL)                     /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bit 7)                      */
 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk     (0x80UL)                  /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bitfield-Mask: 0x01)        */
 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos       (8UL)                     /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bit 8)                        */
@@ -5809,8 +5812,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRSTAT_AI_Msk           (0x4UL)                   /*!< SCU_INTERRUPT SRSTAT: AI (Bitfield-Mask: 0x01)              */
 #define SCU_INTERRUPT_SRSTAT_DLROVR_Pos       (3UL)                     /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bit 3)                        */
 #define SCU_INTERRUPT_SRSTAT_DLROVR_Msk       (0x8UL)                   /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bitfield-Mask: 0x01)          */
-#define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos       (16UL)                    /*!< SCU_INTERRUPT SRSTAT: HDSTAT (Bit 16)                       */
-#define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk       (0x10000UL)               /*!< SCU_INTERRUPT SRSTAT: HDSTAT (Bitfield-Mask: 0x01)          */
 #define SCU_INTERRUPT_SRSTAT_HDCLR_Pos        (17UL)                    /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bit 17)                        */
 #define SCU_INTERRUPT_SRSTAT_HDCLR_Msk        (0x20000UL)               /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bitfield-Mask: 0x01)           */
 #define SCU_INTERRUPT_SRSTAT_HDSET_Pos        (18UL)                    /*!< SCU_INTERRUPT SRSTAT: HDSET (Bit 18)                        */
@@ -5819,8 +5820,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRSTAT_HDCR_Msk         (0x80000UL)               /*!< SCU_INTERRUPT SRSTAT: HDCR (Bitfield-Mask: 0x01)            */
 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos    (21UL)                    /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bit 21)                    */
 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk    (0x200000UL)              /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bitfield-Mask: 0x01)       */
-#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos    (22UL)                    /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT (Bit 22)                    */
-#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk    (0x400000UL)              /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT (Bitfield-Mask: 0x01)       */
 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos    (23UL)                    /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bit 23)                    */
 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk    (0x800000UL)              /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bitfield-Mask: 0x01)       */
 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos      (24UL)                    /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bit 24)                      */
@@ -5845,8 +5844,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRRAW_AI_Msk            (0x4UL)                   /*!< SCU_INTERRUPT SRRAW: AI (Bitfield-Mask: 0x01)               */
 #define SCU_INTERRUPT_SRRAW_DLROVR_Pos        (3UL)                     /*!< SCU_INTERRUPT SRRAW: DLROVR (Bit 3)                         */
 #define SCU_INTERRUPT_SRRAW_DLROVR_Msk        (0x8UL)                   /*!< SCU_INTERRUPT SRRAW: DLROVR (Bitfield-Mask: 0x01)           */
-#define SCU_INTERRUPT_SRRAW_HDSTAT_Pos        (16UL)                    /*!< SCU_INTERRUPT SRRAW: HDSTAT (Bit 16)                        */
-#define SCU_INTERRUPT_SRRAW_HDSTAT_Msk        (0x10000UL)               /*!< SCU_INTERRUPT SRRAW: HDSTAT (Bitfield-Mask: 0x01)           */
 #define SCU_INTERRUPT_SRRAW_HDCLR_Pos         (17UL)                    /*!< SCU_INTERRUPT SRRAW: HDCLR (Bit 17)                         */
 #define SCU_INTERRUPT_SRRAW_HDCLR_Msk         (0x20000UL)               /*!< SCU_INTERRUPT SRRAW: HDCLR (Bitfield-Mask: 0x01)            */
 #define SCU_INTERRUPT_SRRAW_HDSET_Pos         (18UL)                    /*!< SCU_INTERRUPT SRRAW: HDSET (Bit 18)                         */
@@ -5855,8 +5852,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRRAW_HDCR_Msk          (0x80000UL)               /*!< SCU_INTERRUPT SRRAW: HDCR (Bitfield-Mask: 0x01)             */
 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos     (21UL)                    /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bit 21)                     */
 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk     (0x200000UL)              /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bitfield-Mask: 0x01)        */
-#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos     (22UL)                    /*!< SCU_INTERRUPT SRRAW: OSCULSTAT (Bit 22)                     */
-#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk     (0x400000UL)              /*!< SCU_INTERRUPT SRRAW: OSCULSTAT (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos     (23UL)                    /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bit 23)                     */
 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk     (0x800000UL)              /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos       (24UL)                    /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bit 24)                       */
@@ -5881,8 +5876,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRMSK_AI_Msk            (0x4UL)                   /*!< SCU_INTERRUPT SRMSK: AI (Bitfield-Mask: 0x01)               */
 #define SCU_INTERRUPT_SRMSK_DLROVR_Pos        (3UL)                     /*!< SCU_INTERRUPT SRMSK: DLROVR (Bit 3)                         */
 #define SCU_INTERRUPT_SRMSK_DLROVR_Msk        (0x8UL)                   /*!< SCU_INTERRUPT SRMSK: DLROVR (Bitfield-Mask: 0x01)           */
-#define SCU_INTERRUPT_SRMSK_HDSTAT_Pos        (16UL)                    /*!< SCU_INTERRUPT SRMSK: HDSTAT (Bit 16)                        */
-#define SCU_INTERRUPT_SRMSK_HDSTAT_Msk        (0x10000UL)               /*!< SCU_INTERRUPT SRMSK: HDSTAT (Bitfield-Mask: 0x01)           */
 #define SCU_INTERRUPT_SRMSK_HDCLR_Pos         (17UL)                    /*!< SCU_INTERRUPT SRMSK: HDCLR (Bit 17)                         */
 #define SCU_INTERRUPT_SRMSK_HDCLR_Msk         (0x20000UL)               /*!< SCU_INTERRUPT SRMSK: HDCLR (Bitfield-Mask: 0x01)            */
 #define SCU_INTERRUPT_SRMSK_HDSET_Pos         (18UL)                    /*!< SCU_INTERRUPT SRMSK: HDSET (Bit 18)                         */
@@ -5891,8 +5884,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRMSK_HDCR_Msk          (0x80000UL)               /*!< SCU_INTERRUPT SRMSK: HDCR (Bitfield-Mask: 0x01)             */
 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos     (21UL)                    /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bit 21)                     */
 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk     (0x200000UL)              /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bitfield-Mask: 0x01)        */
-#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos     (22UL)                    /*!< SCU_INTERRUPT SRMSK: OSCULSTAT (Bit 22)                     */
-#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk     (0x400000UL)              /*!< SCU_INTERRUPT SRMSK: OSCULSTAT (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos     (23UL)                    /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bit 23)                     */
 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk     (0x800000UL)              /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos       (24UL)                    /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bit 24)                       */
@@ -5917,8 +5908,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRCLR_AI_Msk            (0x4UL)                   /*!< SCU_INTERRUPT SRCLR: AI (Bitfield-Mask: 0x01)               */
 #define SCU_INTERRUPT_SRCLR_DLROVR_Pos        (3UL)                     /*!< SCU_INTERRUPT SRCLR: DLROVR (Bit 3)                         */
 #define SCU_INTERRUPT_SRCLR_DLROVR_Msk        (0x8UL)                   /*!< SCU_INTERRUPT SRCLR: DLROVR (Bitfield-Mask: 0x01)           */
-#define SCU_INTERRUPT_SRCLR_HDSTAT_Pos        (16UL)                    /*!< SCU_INTERRUPT SRCLR: HDSTAT (Bit 16)                        */
-#define SCU_INTERRUPT_SRCLR_HDSTAT_Msk        (0x10000UL)               /*!< SCU_INTERRUPT SRCLR: HDSTAT (Bitfield-Mask: 0x01)           */
 #define SCU_INTERRUPT_SRCLR_HDCLR_Pos         (17UL)                    /*!< SCU_INTERRUPT SRCLR: HDCLR (Bit 17)                         */
 #define SCU_INTERRUPT_SRCLR_HDCLR_Msk         (0x20000UL)               /*!< SCU_INTERRUPT SRCLR: HDCLR (Bitfield-Mask: 0x01)            */
 #define SCU_INTERRUPT_SRCLR_HDSET_Pos         (18UL)                    /*!< SCU_INTERRUPT SRCLR: HDSET (Bit 18)                         */
@@ -5927,8 +5916,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRCLR_HDCR_Msk          (0x80000UL)               /*!< SCU_INTERRUPT SRCLR: HDCR (Bitfield-Mask: 0x01)             */
 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos     (21UL)                    /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bit 21)                     */
 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk     (0x200000UL)              /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bitfield-Mask: 0x01)        */
-#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos     (22UL)                    /*!< SCU_INTERRUPT SRCLR: OSCULSTAT (Bit 22)                     */
-#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk     (0x400000UL)              /*!< SCU_INTERRUPT SRCLR: OSCULSTAT (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos     (23UL)                    /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bit 23)                     */
 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk     (0x800000UL)              /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos       (24UL)                    /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bit 24)                       */
@@ -5953,8 +5940,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRSET_AI_Msk            (0x4UL)                   /*!< SCU_INTERRUPT SRSET: AI (Bitfield-Mask: 0x01)               */
 #define SCU_INTERRUPT_SRSET_DLROVR_Pos        (3UL)                     /*!< SCU_INTERRUPT SRSET: DLROVR (Bit 3)                         */
 #define SCU_INTERRUPT_SRSET_DLROVR_Msk        (0x8UL)                   /*!< SCU_INTERRUPT SRSET: DLROVR (Bitfield-Mask: 0x01)           */
-#define SCU_INTERRUPT_SRSET_HDSTAT_Pos        (16UL)                    /*!< SCU_INTERRUPT SRSET: HDSTAT (Bit 16)                        */
-#define SCU_INTERRUPT_SRSET_HDSTAT_Msk        (0x10000UL)               /*!< SCU_INTERRUPT SRSET: HDSTAT (Bitfield-Mask: 0x01)           */
 #define SCU_INTERRUPT_SRSET_HDCRCLR_Pos       (17UL)                    /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bit 17)                       */
 #define SCU_INTERRUPT_SRSET_HDCRCLR_Msk       (0x20000UL)               /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bitfield-Mask: 0x01)          */
 #define SCU_INTERRUPT_SRSET_HDCRSET_Pos       (18UL)                    /*!< SCU_INTERRUPT SRSET: HDCRSET (Bit 18)                       */
@@ -5963,8 +5948,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SCU_INTERRUPT_SRSET_HDCR_Msk          (0x80000UL)               /*!< SCU_INTERRUPT SRSET: HDCR (Bitfield-Mask: 0x01)             */
 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos     (21UL)                    /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bit 21)                     */
 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk     (0x200000UL)              /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bitfield-Mask: 0x01)        */
-#define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos     (22UL)                    /*!< SCU_INTERRUPT SRSET: OSCULSTAT (Bit 22)                     */
-#define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk     (0x400000UL)              /*!< SCU_INTERRUPT SRSET: OSCULSTAT (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos     (23UL)                    /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bit 23)                     */
 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk     (0x800000UL)              /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bitfield-Mask: 0x01)        */
 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos       (24UL)                    /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bit 24)                       */
@@ -6877,8 +6860,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x4UL)                 /*!< SDMMC BLOCK_GAP_CTRL: READ_WAIT_CTRL (Bitfield-Mask: 0x01)  */
 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos (3UL)                 /*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP (Bit 3)              */
 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x8UL)               /*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP (Bitfield-Mask: 0x01) */
-#define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos     (4UL)                     /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE (Bit 4)                      */
-#define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Msk     (0x10UL)                  /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE (Bitfield-Mask: 0x01)        */
 
 /* ------------------------------  SDMMC_WAKEUP_CTRL  ----------------------------- */
 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos (0UL)                 /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INT (Bit 0)              */
@@ -7154,10 +7135,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Pos         (0UL)                     /*!< SDMMC DEBUG_SEL: DEBUG_SEL (Bit 0)                          */
 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Msk         (0x1UL)                   /*!< SDMMC DEBUG_SEL: DEBUG_SEL (Bitfield-Mask: 0x01)            */
 
-/* ----------------------------------  SDMMC_SPI  --------------------------------- */
-#define SDMMC_SPI_SPI_INT_SUPPORT_Pos         (0UL)                     /*!< SDMMC SPI: SPI_INT_SUPPORT (Bit 0)                          */
-#define SDMMC_SPI_SPI_INT_SUPPORT_Msk         (0xffUL)                  /*!< SDMMC SPI: SPI_INT_SUPPORT (Bitfield-Mask: 0xff)            */
-
 /* ----------------------------  SDMMC_SLOT_INT_STATUS  --------------------------- */
 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos (0UL)                 /*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS (Bit 0)              */
 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0xffUL)              /*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS (Bitfield-Mask: 0xff) */
@@ -13166,18 +13143,6 @@ typedef struct {                                    /*!< (@ 0x48028F00) PORT15 S
 #define CCU8_GPCHK_PCSEL3_Pos                 (28UL)                    /*!< CCU8 GPCHK: PCSEL3 (Bit 28)                                 */
 #define CCU8_GPCHK_PCSEL3_Msk                 (0xf0000000UL)            /*!< CCU8 GPCHK: PCSEL3 (Bitfield-Mask: 0x0f)                    */
 
-/* ----------------------------------  CCU8_ECRD  --------------------------------- */
-#define CCU8_ECRD_CAPV_Pos                    (0UL)                     /*!< CCU8 ECRD: CAPV (Bit 0)                                     */
-#define CCU8_ECRD_CAPV_Msk                    (0xffffUL)                /*!< CCU8 ECRD: CAPV (Bitfield-Mask: 0xffff)                     */
-#define CCU8_ECRD_FPCV_Pos                    (16UL)                    /*!< CCU8 ECRD: FPCV (Bit 16)                                    */
-#define CCU8_ECRD_FPCV_Msk                    (0xf0000UL)               /*!< CCU8 ECRD: FPCV (Bitfield-Mask: 0x0f)                       */
-#define CCU8_ECRD_SPTR_Pos                    (20UL)                    /*!< CCU8 ECRD: SPTR (Bit 20)                                    */
-#define CCU8_ECRD_SPTR_Msk                    (0x300000UL)              /*!< CCU8 ECRD: SPTR (Bitfield-Mask: 0x03)                       */
-#define CCU8_ECRD_VPTR_Pos                    (22UL)                    /*!< CCU8 ECRD: VPTR (Bit 22)                                    */
-#define CCU8_ECRD_VPTR_Msk                    (0xc00000UL)              /*!< CCU8 ECRD: VPTR (Bitfield-Mask: 0x03)                       */
-#define CCU8_ECRD_FFL_Pos                     (24UL)                    /*!< CCU8 ECRD: FFL (Bit 24)                                     */
-#define CCU8_ECRD_FFL_Msk                     (0x1000000UL)             /*!< CCU8 ECRD: FFL (Bitfield-Mask: 0x01)                        */
-
 /* ----------------------------------  CCU8_MIDR  --------------------------------- */
 #define CCU8_MIDR_MODR_Pos                    (0UL)                     /*!< CCU8 MIDR: MODR (Bit 0)                                     */
 #define CCU8_MIDR_MODR_Msk                    (0xffUL)                  /*!< CCU8 MIDR: MODR (Bitfield-Mask: 0xff)                       */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/cmsis/cmsis_gcc.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_gcc.h
  * @brief    CMSIS Cortex-M Core Function/Instruction Header File
- * @version  V4.20
+ * @version  V4.30
- * @date     18. August 2015
+ * @date     20. October 2015
  ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
@@ -35,6 +35,14 @@
 #ifndef __CMSIS_GCC_H
 #define __CMSIS_GCC_H
 
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
@@ -42,10 +50,10 @@
   @{
  */
 
-/** \brief  Enable IRQ Interrupts
+/**
-
+  \brief   Enable IRQ Interrupts
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
+           Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
 {
@@ -53,9 +61,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
 }
 
 
-/** \brief  Disable IRQ Interrupts
+/**
-
+  \brief   Disable IRQ Interrupts
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
@@ -64,11 +72,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
 }
 
 
-/** \brief  Get Control Register
+/**
-
+  \brief   Get Control Register
-    This function returns the content of the Control Register.
+  \details Returns the content of the Control Register.
-
+  \return               Control Register value
-    \return               Control Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
@@ -79,11 +86,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
 }
 
 
-/** \brief  Set Control Register
+/**
-
+  \brief   Set Control Register
-    This function writes the given value to the Control Register.
+  \details Writes the given value to the Control Register.
-
+  \param [in]    control  Control Register value to set
-    \param [in]    control  Control Register value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
@@ -91,11 +97,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t c
 }
 
 
-/** \brief  Get IPSR Register
+/**
-
+  \brief   Get IPSR Register
-    This function returns the content of the IPSR Register.
+  \details Returns the content of the IPSR Register.
-
+  \return               IPSR Register value
-    \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
 {
@@ -106,11 +111,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
 }
 
 
-/** \brief  Get APSR Register
+/**
-
+  \brief   Get APSR Register
-    This function returns the content of the APSR Register.
+  \details Returns the content of the APSR Register.
-
+  \return               APSR Register value
-    \return               APSR Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
 {
@@ -121,9 +125,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
 }
 
 
-/** \brief  Get xPSR Register
+/**
-
+  \brief   Get xPSR Register
-    This function returns the content of the xPSR Register.
+  \details Returns the content of the xPSR Register.
 
     \return               xPSR Register value
  */
@@ -136,11 +140,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
 }
 
 
-/** \brief  Get Process Stack Pointer
+/**
-
+  \brief   Get Process Stack Pointer
-    This function returns the current value of the Process Stack Pointer (PSP).
+  \details Returns the current value of the Process Stack Pointer (PSP).
-
+  \return               PSP Register value
-    \return               PSP Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
 {
@@ -151,11 +154,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
 }
 
 
-/** \brief  Set Process Stack Pointer
+/**
-
+  \brief   Set Process Stack Pointer
-    This function assigns the given value to the Process Stack Pointer (PSP).
+  \details Assigns the given value to the Process Stack Pointer (PSP).
-
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
@@ -163,11 +165,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOf
 }
 
 
-/** \brief  Get Main Stack Pointer
+/**
-
+  \brief   Get Main Stack Pointer
-    This function returns the current value of the Main Stack Pointer (MSP).
+  \details Returns the current value of the Main Stack Pointer (MSP).
-
+  \return               MSP Register value
-    \return               MSP Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
 {
@@ -178,9 +179,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
 }
 
 
-/** \brief  Set Main Stack Pointer
+/**
-
+  \brief   Set Main Stack Pointer
-    This function assigns the given value to the Main Stack Pointer (MSP).
+  \details Assigns the given value to the Main Stack Pointer (MSP).
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
@@ -190,11 +191,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOf
 }
 
 
-/** \brief  Get Priority Mask
+/**
-
+  \brief   Get Priority Mask
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-
+  \return               Priority Mask value
-    \return               Priority Mask value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
@@ -205,11 +205,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
 }
 
 
-/** \brief  Set Priority Mask
+/**
-
+  \brief   Set Priority Mask
-    This function assigns the given value to the Priority Mask Register.
+  \details Assigns the given value to the Priority Mask Register.
-
+  \param [in]    priMask  Priority Mask
-    \param [in]    priMask  Priority Mask
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
@@ -219,10 +218,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p
 
 #if       (__CORTEX_M >= 0x03U)
 
-/** \brief  Enable FIQ
+/**
-
+  \brief   Enable FIQ
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
+           Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
 {
@@ -230,10 +229,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
 }
 
 
-/** \brief  Disable FIQ
+/**
-
+  \brief   Disable FIQ
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
+           Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
 {
@@ -241,11 +240,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void
 }
 
 
-/** \brief  Get Base Priority
+/**
-
+  \brief   Get Base Priority
-    This function returns the current value of the Base Priority register.
+  \details Returns the current value of the Base Priority register.
-
+  \return               Base Priority register value
-    \return               Base Priority register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
 {
@@ -256,11 +254,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
 }
 
 
-/** \brief  Set Base Priority
+/**
-
+  \brief   Set Base Priority
-    This function assigns the given value to the Base Priority register.
+  \details Assigns the given value to the Base Priority register.
-
+  \param [in]    basePri  Base Priority value to set
-    \param [in]    basePri  Base Priority value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
 {
@@ -268,12 +265,11 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
 }
 
 
-/** \brief  Set Base Priority with condition
+/**
-
+  \brief   Set Base Priority with condition
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-	or the new value increases the BASEPRI priority level.
+           or the new value increases the BASEPRI priority level.
-
+  \param [in]    basePri  Base Priority value to set
-    \param [in]    basePri  Base Priority value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
 {
@@ -281,11 +277,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32
 }
 
 
-/** \brief  Get Fault Mask
+/**
-
+  \brief   Get Fault Mask
-    This function returns the current value of the Fault Mask register.
+  \details Returns the current value of the Fault Mask register.
-
+  \return               Fault Mask register value
-    \return               Fault Mask register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
@@ -296,11 +291,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void
 }
 
 
-/** \brief  Set Fault Mask
+/**
-
+  \brief   Set Fault Mask
-    This function assigns the given value to the Fault Mask register.
+  \details Assigns the given value to the Fault Mask register.
-
+  \param [in]    faultMask  Fault Mask value to set
-    \param [in]    faultMask  Fault Mask value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
@@ -312,11 +306,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
 
 #if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
 
-/** \brief  Get FPSCR
+/**
-
+  \brief   Get FPSCR
-    This function returns the current value of the Floating Point Status/Control register.
+  \details Returns the current value of the Floating Point Status/Control register.
-
+  \return               Floating Point Status/Control register value
-    \return               Floating Point Status/Control register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
@@ -334,18 +327,17 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
 }
 
 
-/** \brief  Set FPSCR
+/**
-
+  \brief   Set FPSCR
-    This function assigns the given value to the Floating Point Status/Control register.
+  \details Assigns the given value to the Floating Point Status/Control register.
-
+  \param [in]    fpscr  Floating Point Status/Control value to set
-    \param [in]    fpscr  Floating Point Status/Control value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
   /* Empty asm statement works as a scheduling barrier */
   __ASM volatile ("");
-//  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");          // ARMCC_V6: needs to be checked
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
   __ASM volatile ("");
 #endif
 }
@@ -364,8 +356,8 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
 */
 
 /* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constrant "r" */
+ * Otherwise, use general registers, specified by constraint "r" */
 #if defined (__thumb__) && !defined (__thumb2__)
 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 #define __CMSIS_GCC_USE_REG(r) "l" (r)
@@ -374,9 +366,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
 #define __CMSIS_GCC_USE_REG(r) "r" (r)
 #endif
 
-/** \brief  No Operation
+/**
-
+  \brief   No Operation
-    No Operation does nothing. This instruction can be used for code alignment purposes.
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
 {
@@ -384,10 +376,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
 }
 
 
-/** \brief  Wait For Interrupt
+/**
-
+  \brief   Wait For Interrupt
-    Wait For Interrupt is a hint instruction that suspends execution
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
-    until one of a number of events occurs.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
 {
@@ -395,9 +386,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
 }
 
 
-/** \brief  Wait For Event
+/**
-
+  \brief   Wait For Event
-    Wait For Event is a hint instruction that permits the processor to enter
+  \details Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
@@ -406,9 +397,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
 }
 
 
-/** \brief  Send Event
+/**
-
+  \brief   Send Event
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
 {
@@ -416,11 +407,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
 }
 
 
-/** \brief  Instruction Synchronization Barrier
+/**
-
+  \brief   Instruction Synchronization Barrier
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
+           so that all instructions following the ISB are fetched from cache or memory,
-    memory, after the instruction has been completed.
+           after the instruction has been completed.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
 {
@@ -428,10 +419,10 @@ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
 }
 
 
-/** \brief  Data Synchronization Barrier
+/**
-
+  \brief   Data Synchronization Barrier
-    This function acts as a special kind of Data Memory Barrier.
+  \details Acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
+           It completes when all explicit memory accesses before this instruction complete.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
 {
@@ -439,10 +430,10 @@ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
 }
 
 
-/** \brief  Data Memory Barrier
+/**
-
+  \brief   Data Memory Barrier
-    This function ensures the apparent order of the explicit memory operations before
+  \details Ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
+           and after the instruction, without ensuring their completion.
  */
 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
 {
@@ -450,12 +441,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
 }
 
 
-/** \brief  Reverse byte order (32 bit)
+/**
-
+  \brief   Reverse byte order (32 bit)
-    This function reverses the byte order in integer value.
+  \details Reverses the byte order in integer value.
-
+  \param [in]    value  Value to reverse
-    \param [in]    value  Value to reverse
+  \return               Reversed value
-    \return               Reversed value
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
 {
@@ -470,12 +460,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
 }
 
 
-/** \brief  Reverse byte order (16 bit)
+/**
-
+  \brief   Reverse byte order (16 bit)
-    This function reverses the byte order in two unsigned short values.
+  \details Reverses the byte order in two unsigned short values.
-
+  \param [in]    value  Value to reverse
-    \param [in]    value  Value to reverse
+  \return               Reversed value
-    \return               Reversed value
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
 {
@@ -486,12 +475,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
 }
 
 
-/** \brief  Reverse byte order in signed short value
+/**
-
+  \brief   Reverse byte order in signed short value
-    This function reverses the byte order in a signed short value with sign extension to integer.
+  \details Reverses the byte order in a signed short value with sign extension to integer.
-
+  \param [in]    value  Value to reverse
-    \param [in]    value  Value to reverse
+  \return               Reversed value
-    \return               Reversed value
  */
 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
 {
@@ -506,13 +494,12 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
 }
 
 
-/** \brief  Rotate Right in unsigned value (32 bit)
+/**
-
+  \brief   Rotate Right in unsigned value (32 bit)
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
+  \param [in]    value  Value to rotate
-    \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
-    \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
-    \return               Rotated value
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
@@ -520,23 +507,21 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
 }
 
 
-/** \brief  Breakpoint
+/**
-
+  \brief   Breakpoint
-    This function causes the processor to enter Debug state.
+  \details Causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
+  \param [in]    value  is ignored by the processor.
-    \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
-                   If required, a debugger can use it to store additional information about the breakpoint.
  */
 #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 
 
-/** \brief  Reverse bit order of value
+/**
-
+  \brief   Reverse bit order of value
-    This function reverses the bit order of the given value.
+  \details Reverses the bit order of the given value.
-
+  \param [in]    value  Value to reverse
-    \param [in]    value  Value to reverse
+  \return               Reversed value
-    \return               Reversed value
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
@@ -545,39 +530,37 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 #else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
 
-  result = value;                      // r will be reversed bits of v; first get LSB of v
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
   for (value >>= 1U; value; value >>= 1U)
   {
     result <<= 1U;
     result |= value & 1U;
     s--;
   }
-  result <<= s;                       // shift when v's highest bits are zero
+  result <<= s;                        /* shift when v's highest bits are zero */
 #endif
   return(result);
 }
 
 
-/** \brief  Count leading zeros
+/**
-
+  \brief   Count leading zeros
-    This function counts the number of leading zeros of a data value.
+  \details Counts the number of leading zeros of a data value.
-
+  \param [in]  value  Value to count the leading zeros
-    \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
-    \return             number of leading zeros in value
  */
 #define __CLZ             __builtin_clz
 
 
 #if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 
-/** \brief  LDR Exclusive (8 bit)
+/**
-
+  \brief   LDR Exclusive (8 bit)
-    This function executes a exclusive LDR instruction for 8 bit value.
+  \details Executes a exclusive LDR instruction for 8 bit value.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
-    \return             value of type uint8_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
 {
@@ -595,12 +578,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t
 }
 
 
-/** \brief  LDR Exclusive (16 bit)
+/**
-
+  \brief   LDR Exclusive (16 bit)
-    This function executes a exclusive LDR instruction for 16 bit values.
+  \details Executes a exclusive LDR instruction for 16 bit values.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
-    \return        value of type uint16_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
 {
@@ -618,12 +600,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16
 }
 
 
-/** \brief  LDR Exclusive (32 bit)
+/**
-
+  \brief   LDR Exclusive (32 bit)
-    This function executes a exclusive LDR instruction for 32 bit values.
+  \details Executes a exclusive LDR instruction for 32 bit values.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
-    \return        value of type uint32_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
 {
@@ -634,14 +615,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32
 }
 
 
-/** \brief  STR Exclusive (8 bit)
+/**
-
+  \brief   STR Exclusive (8 bit)
-    This function executes a exclusive STR instruction for 8 bit values.
+  \details Executes a exclusive STR instruction for 8 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
-    \return          0  Function succeeded
+  \return          1  Function failed
-    \return          1  Function failed
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 {
@@ -652,14 +632,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value,
 }
 
 
-/** \brief  STR Exclusive (16 bit)
+/**
-
+  \brief   STR Exclusive (16 bit)
-    This function executes a exclusive STR instruction for 16 bit values.
+  \details Executes a exclusive STR instruction for 16 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
-    \return          0  Function succeeded
+  \return          1  Function failed
-    \return          1  Function failed
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 {
@@ -670,14 +649,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value,
 }
 
 
-/** \brief  STR Exclusive (32 bit)
+/**
-
+  \brief   STR Exclusive (32 bit)
-    This function executes a exclusive STR instruction for 32 bit values.
+  \details Executes a exclusive STR instruction for 32 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
-    \return          0  Function succeeded
+  \return          1  Function failed
-    \return          1  Function failed
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 {
@@ -688,10 +666,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value,
 }
 
 
-/** \brief  Remove the exclusive lock
+/**
-
+  \brief   Remove the exclusive lock
-    This function removes the exclusive lock which is created by LDREX.
+  \details Removes the exclusive lock which is created by LDREX.
-
  */
 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
 {
@@ -699,13 +676,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
 }
 
 
-/** \brief  Signed Saturate
+/**
-
+  \brief   Signed Saturate
-    This function saturates a signed value.
+  \details Saturates a signed value.
-
+  \param [in]  value  Value to be saturated
-    \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
-    \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
-    \return             Saturated value
  */
 #define __SSAT(ARG1,ARG2) \
 ({                          \
@@ -715,13 +691,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
  })
 
 
-/** \brief  Unsigned Saturate
+/**
-
+  \brief   Unsigned Saturate
-    This function saturates an unsigned value.
+  \details Saturates an unsigned value.
-
+  \param [in]  value  Value to be saturated
-    \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
-    \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
-    \return             Saturated value
  */
 #define __USAT(ARG1,ARG2) \
 ({                          \
@@ -731,13 +706,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
  })
 
 
-/** \brief  Rotate Right with Extend (32 bit)
+/**
-
+  \brief   Rotate Right with Extend (32 bit)
-    This function moves each bit of a bitstring right by one bit.
+  \details Moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
+           The carry input is shifted in at the left end of the bitstring.
-
+  \param [in]    value  Value to rotate
-    \param [in]    value  Value to rotate
+  \return               Rotated value
-    \return               Rotated value
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
 {
@@ -748,12 +722,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
 }
 
 
-/** \brief  LDRT Unprivileged (8 bit)
+/**
-
+  \brief   LDRT Unprivileged (8 bit)
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
-    \return             value of type uint8_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
 {
@@ -771,12 +744,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t
 }
 
 
-/** \brief  LDRT Unprivileged (16 bit)
+/**
-
+  \brief   LDRT Unprivileged (16 bit)
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
-    \return        value of type uint16_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
 {
@@ -794,12 +766,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_
 }
 
 
-/** \brief  LDRT Unprivileged (32 bit)
+/**
-
+  \brief   LDRT Unprivileged (32 bit)
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-
+  \param [in]    ptr  Pointer to data
-    \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
-    \return        value of type uint32_t at (*ptr)
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
 {
@@ -810,12 +781,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t
 }
 
 
-/** \brief  STRT Unprivileged (8 bit)
+/**
-
+  \brief   STRT Unprivileged (8 bit)
-    This function executes a Unprivileged STRT instruction for 8 bit values.
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
  */
 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
 {
@@ -823,12 +793,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volat
 }
 
 
-/** \brief  STRT Unprivileged (16 bit)
+/**
-
+  \brief   STRT Unprivileged (16 bit)
-    This function executes a Unprivileged STRT instruction for 16 bit values.
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
  */
 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
 {
@@ -836,12 +805,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, vola
 }
 
 
-/** \brief  STRT Unprivileged (32 bit)
+/**
-
+  \brief   STRT Unprivileged (32 bit)
-    This function executes a Unprivileged STRT instruction for 32 bit values.
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
-
+  \param [in]  value  Value to store
-    \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
-    \param [in]    ptr  Pointer to location
  */
 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
 {
@@ -859,7 +827,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volat
   @{
 */
 
-#if (__CORTEX_M >= 0x04)  /* only for Cortex-M4 and above */
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
 
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
 {
@@ -1169,7 +1137,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op
 
 #define __SSAT16(ARG1,ARG2) \
 ({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
+  int32_t __RES, __ARG1 = (ARG1); \
   __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
   __RES; \
  })
@@ -1253,9 +1221,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t o
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian */
   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian */
   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -1270,9 +1238,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian */
   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian */
   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -1319,9 +1287,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t o
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian */
   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian */
   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -1336,9 +1304,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian */
   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian */
   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -1353,17 +1321,17 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1
   return(result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
 {
-  uint32_t result;
+  int32_t result;
 
   __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
 {
-  uint32_t result;
+  int32_t result;
 
   __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
@@ -1398,4 +1366,8 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1
 /*@} end of group CMSIS_SIMD_intrinsics */
 
 
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
 #endif /* __CMSIS_GCC_H */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/cmsis/core_cm4.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cm4.h
  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.20
+ * @version  V4.30
- * @date     20. August 2015
+ * @date     20. October 2015
  ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
@@ -34,7 +34,7 @@
 
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -47,7 +47,8 @@
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.<br>
@@ -64,13 +65,14 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex_M4
+/**
+  \ingroup Cortex_M4
   @{
  */
 
 /*  CMSIS CM4 definitions */
 #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (0x14U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
 
@@ -82,6 +84,11 @@
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
   #define __STATIC_INLINE  static __inline
 
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
@@ -107,11 +114,6 @@
   #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
   #define __STATIC_INLINE  static inline
 
-#elif (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
 #else
   #error Unknown compiler
 #endif
@@ -131,6 +133,18 @@
     #define __FPU_USED         0U
   #endif
 
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #if (__FPU_PRESENT == 1U)
@@ -191,18 +205,6 @@
     #define __FPU_USED         0U
   #endif
 
-#elif (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
 #endif
 
 #include "core_cmInstr.h"                /* Core Instruction Access */
@@ -288,17 +290,20 @@
   - Core MPU Register
   - Core FPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
+/**
-    \brief Type definitions and defines for Cortex-M processor based devices.
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
+/**
-    \defgroup   CMSIS_CORE  Status and Control Registers
+  \ingroup    CMSIS_core_register
-    \brief  Core Register type definitions.
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
@@ -336,7 +341,8 @@ typedef union
 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
@@ -353,7 +359,8 @@ typedef union
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
@@ -403,7 +410,8 @@ typedef union
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
@@ -430,13 +438,15 @@ typedef union
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
+/**
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \ingroup    CMSIS_core_register
-    \brief      Type definitions for the NVIC Registers
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
@@ -462,13 +472,15 @@ typedef struct
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_SCB     System Control Block (SCB)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the System Control Block Registers
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
@@ -640,7 +652,7 @@ typedef struct
 #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
 
-/* SCB Configurable Fault Status Registers Definitions */
+/* SCB Configurable Fault Status Register Definitions */
 #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 
@@ -650,7 +662,7 @@ typedef struct
 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
-/* SCB Hard Fault Status Registers Definitions */
+/* SCB Hard Fault Status Register Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 
@@ -679,13 +691,15 @@ typedef struct
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
@@ -717,13 +731,15 @@ typedef struct
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the System Timer Registers.
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
@@ -767,13 +783,15 @@ typedef struct
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
 {
@@ -868,13 +886,15 @@ typedef struct
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
 {
@@ -1013,13 +1033,15 @@ typedef struct
 /*@}*/ /* end of group CMSIS_DWT */
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Trace Port Interface (TPI)
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
   @{
  */
 
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
 {
@@ -1167,13 +1189,15 @@ typedef struct
 
 
 #if (__MPU_PRESENT == 1U)
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
@@ -1190,7 +1214,7 @@ typedef struct
   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
+/* MPU Type Register Definitions */
 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
@@ -1200,7 +1224,7 @@ typedef struct
 #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
+/* MPU Control Register Definitions */
 #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
@@ -1210,11 +1234,11 @@ typedef struct
 #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
+/* MPU Region Number Register Definitions */
 #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
+/* MPU Region Base Address Register Definitions */
 #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 
@@ -1224,7 +1248,7 @@ typedef struct
 #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
+/* MPU Region Attribute and Size Register Definitions */
 #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
@@ -1260,13 +1284,15 @@ typedef struct
 
 
 #if (__FPU_PRESENT == 1U)
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Floating Point Unit (FPU)
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
   @{
  */
 
-/** \brief  Structure type to access the Floating Point Unit (FPU).
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
  */
 typedef struct
 {
@@ -1278,7 +1304,7 @@ typedef struct
   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
 } FPU_Type;
 
-/* Floating-Point Context Control Register */
+/* Floating-Point Context Control Register Definitions */
 #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
 
@@ -1306,11 +1332,11 @@ typedef struct
 #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
 
-/* Floating-Point Context Address Register */
+/* Floating-Point Context Address Register Definitions */
 #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
 
-/* Floating-Point Default Status Control Register */
+/* Floating-Point Default Status Control Register Definitions */
 #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
 
@@ -1323,7 +1349,7 @@ typedef struct
 #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
 
-/* Media and FP Feature Register 0 */
+/* Media and FP Feature Register 0 Definitions */
 #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
 
@@ -1348,7 +1374,7 @@ typedef struct
 #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
 
-/* Media and FP Feature Register 1 */
+/* Media and FP Feature Register 1 Definitions */
 #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
 
@@ -1365,13 +1391,15 @@ typedef struct
 #endif
 
 
-/** \ingroup  CMSIS_core_register
+/**
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \ingroup  CMSIS_core_register
-    \brief      Type definitions for the Core Debug Registers
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
   @{
  */
 
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
 {
@@ -1381,7 +1409,7 @@ typedef struct
   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 
-/* Debug Halting Control and Status Register */
+/* Debug Halting Control and Status Register Definitions */
 #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 
@@ -1418,14 +1446,14 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register */
+/* Debug Core Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
 #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
 
-/* Debug Exception and Monitor Control Register */
+/* Debug Exception and Monitor Control Register Definitions */
 #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 
@@ -1468,66 +1496,66 @@ typedef struct
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
+/**
-    \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \ingroup    CMSIS_core_register
-    \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
   @{
  */
 
 /**
-* Mask and shift a bit field value for use in a register bit range.
+  \brief   Mask and shift a bit field value for use in a register bit range.
-*
+  \param[in] field  Name of the register bit field.
-* \param[in] field Name of the register bit field.
+  \param[in] value  Value of the bit field.
-* \param[in] value Value of the bit field.
+  \return           Masked and shifted value.
-* \return Masked and shifted value.
 */
 #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
 
 /**
-* Mask and shift a register value to extract a bit filed value.
+  \brief     Mask and shift a register value to extract a bit filed value.
-*
+  \param[in] field  Name of the register bit field.
-* \param[in] field Name of the register bit field.
+  \param[in] value  Value of register.
-* \param[in] value Value of register.
+  \return           Masked and shifted bit field value.
-* \return Masked and shifted bit field value.
 */
 #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
 
 /*@} end of group CMSIS_core_bitfield */
 
 
-/** \ingroup    CMSIS_core_register
+/**
-    \defgroup   CMSIS_core_base     Core Definitions
+  \ingroup    CMSIS_core_register
-    \brief      Definitions for base addresses, unions, and structures.
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
 /* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
 
 #if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 #if (__FPU_PRESENT == 1U)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
 #endif
 
 /*@} */
@@ -1542,27 +1570,28 @@ typedef struct
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
+/**
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \ingroup  CMSIS_Core_FunctionInterface
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    @{
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/** \brief  Set Priority Grouping
+/**
-
+  \brief   Set Priority Grouping
-  The function sets the priority grouping field using the required unlock sequence.
+  \details Sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
+           Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
+           In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
+  \param [in]      PriorityGroup  Priority grouping field.
-    \param [in]      PriorityGroup  Priority grouping field.
  */
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
@@ -1578,11 +1607,10 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 }
 
 
-/** \brief  Get Priority Grouping
+/**
-
+  \brief   Get Priority Grouping
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
@@ -1590,11 +1618,10 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
 }
 
 
-/** \brief  Enable External Interrupt
+/**
-
+  \brief   Enable External Interrupt
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
@@ -1602,11 +1629,10 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 }
 
 
-/** \brief  Disable External Interrupt
+/**
-
+  \brief   Disable External Interrupt
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
@@ -1614,15 +1640,12 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 }
 
 
-/** \brief  Get Pending Interrupt
+/**
-
+  \brief   Get Pending Interrupt
-    The function reads the pending register in the NVIC and returns the pending bit
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-    for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
-
+  \return             0  Interrupt status is not pending.
-    \param [in]      IRQn  Interrupt number.
+  \return             1  Interrupt status is pending.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
@@ -1630,11 +1653,10 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 }
 
 
-/** \brief  Set Pending Interrupt
+/**
-
+  \brief   Set Pending Interrupt
-    The function sets the pending bit of an external interrupt.
+  \details Sets the pending bit of an external interrupt.
-
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
@@ -1642,11 +1664,10 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 }
 
 
-/** \brief  Clear Pending Interrupt
+/**
-
+  \brief   Clear Pending Interrupt
-    The function clears the pending bit of an external interrupt.
+  \details Clears the pending bit of an external interrupt.
-
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
@@ -1654,14 +1675,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 }
 
 
-/** \brief  Get Active Interrupt
+/**
-
+  \brief   Get Active Interrupt
-    The function reads the active register in NVIC and returns the active bit.
+  \details Reads the active register in NVIC and returns the active bit.
-
+  \param [in]      IRQn  Interrupt number.
-    \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
-
+  \return             1  Interrupt status is active.
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
  */
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
@@ -1669,14 +1688,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 }
 
 
-/** \brief  Set Interrupt Priority
+/**
-
+  \brief   Set Interrupt Priority
-    The function sets the priority of an interrupt.
+  \details Sets the priority of an interrupt.
-
+  \note    The priority cannot be set for every core interrupt.
-    \note The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
-
+  \param [in]  priority  Priority to set.
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
@@ -1691,16 +1708,14 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 }
 
 
-/** \brief  Get Interrupt Priority
+/**
-
+  \brief   Get Interrupt Priority
-    The function reads the priority of an interrupt. The interrupt
+  \details Reads the priority of an interrupt.
-    number can be positive to specify an external (device specific)
+           The interrupt number can be positive to specify an external (device specific) interrupt,
-    interrupt, or negative to specify an internal (core) interrupt.
+           or negative to specify an internal (core) interrupt.
-
+  \param [in]   IRQn  Interrupt number.
-
+  \return             Interrupt Priority.
-    \param [in]   IRQn  Interrupt number.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
@@ -1716,17 +1731,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 }
 
 
-/** \brief  Encode Priority
+/**
-
+  \brief   Encode Priority
-    The function encodes the priority for an interrupt with the given priority group,
+  \details Encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
+           preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
+           In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
+  \param [in]     PriorityGroup  Used priority group.
-    \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1744,17 +1758,16 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
 }
 
 
-/** \brief  Decode Priority
+/**
-
+  \brief   Decode Priority
-    The function decodes an interrupt priority value with a given priority group to
+  \details Decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
+           preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
+           In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
-    \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
@@ -1770,9 +1783,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
-/** \brief  System Reset
+/**
-
+  \brief   System Reset
-    The function initiates a system reset request to reset the MCU.
+  \details Initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
 {
@@ -1794,28 +1807,25 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
+/**
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \ingroup  CMSIS_Core_FunctionInterface
-    \brief      Functions that configure the System.
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
   @{
  */
 
 #if (__Vendor_SysTickConfig == 0U)
 
-/** \brief  System Tick Configuration
+/**
-
+  \brief   System Tick Configuration
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
+           Counter is in free running mode to generate periodic interrupts.
-
+  \param [in]  ticks  Number of ticks between two interrupts.
-    \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
-
+  \return          1  Function failed.
-    \return          0  Function succeeded.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    \return          1  Function failed.
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-
+           must contain a vendor-specific implementation of this function.
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
@@ -1840,25 +1850,24 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
+/**
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \ingroup  CMSIS_Core_FunctionInterface
-    \brief   Functions that access the ITM debug interface.
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
 #define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
-/** \brief  ITM Send Character
+/**
-
+  \brief   ITM Send Character
-    The function transmits a character via the ITM channel 0, and
+  \details Transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
+           \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
+  \param [in]     ch  Character to transmit.
-    \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
-
-    \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
@@ -1875,12 +1884,11 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 }
 
 
-/** \brief  ITM Receive Character
+/**
-
+  \brief   ITM Receive Character
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-
+  \return             Received character.
-    \return             Received character.
+  \return         -1  No character pending.
-    \return         -1  No character pending.
  */
 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
 {
@@ -1896,14 +1904,14 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
 }
 
 
-/** \brief  ITM Check Character
+/**
-
+  \brief   ITM Check Character
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
+  \return          0  No character available.
-    \return          0  No character available.
+  \return          1  Character available.
-    \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
   {

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/cmsis/core_cmFunc.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.20
+ * @version  V4.30
- * @date     02. July 2015
+ * @date     20. October 2015
  ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
@@ -34,7 +34,7 @@
 
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -46,31 +46,38 @@
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
- */
+*/
 
-#if   defined ( __CC_ARM )         /*------------------ RealView Compiler -----------------*/
+/*------------------ RealView Compiler -----------------*/
-  #include <cmsis_armcc.h>
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
 
-#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+/*------------------ ARM Compiler V6 -------------------*/
-  #include <cmsis_armcc_V6.h>
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
 
-#elif defined ( __GNUC__ )         /*------------------ GNU Compiler ----------------------*/
+/*------------------ GNU Compiler ----------------------*/
-  #include <cmsis_gcc.h>
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
 
-#elif defined ( __ICCARM__ )       /*------------------ ICC Compiler ----------------------*/
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
   #include <cmsis_iar.h>
 
-#elif defined ( __TMS470__ )       /*------------------ TI CCS Compiler -------------------*/
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
   #include <cmsis_ccs.h>
 
-#elif defined ( __TASKING__ )      /*------------------ TASKING Compiler ------------------*/
+/*------------------ TASKING Compiler ------------------*/
-    /*
+#elif defined ( __TASKING__ )
-     * The CMSIS functions have been implemented as intrinsics in the compiler.
+  /*
-     * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
-     * Including the CMSIS ones.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
    */
 
-#elif defined ( __CSMC__ )         /*------------------ COSMIC Compiler -------------------*/
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
   #include <cmsis_csm.h>
 
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/cmsis/core_cmInstr.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.20
+ * @version  V4.30
- * @date     02. July 2015
+ * @date     20. October 2015
  ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
@@ -34,7 +34,7 @@
 
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -48,29 +48,36 @@
   @{
 */
 
-#if   defined ( __CC_ARM )         /*------------------ RealView Compiler -----------------*/
+/*------------------ RealView Compiler -----------------*/
-  #include <cmsis_armcc.h>
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
 
-#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+/*------------------ ARM Compiler V6 -------------------*/
-  #include <cmsis_armcc_V6.h>
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
 
-#elif defined ( __GNUC__ )         /*------------------ GNU Compiler ----------------------*/
+/*------------------ GNU Compiler ----------------------*/
-  #include <cmsis_gcc.h>
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
 
-#elif defined ( __ICCARM__ )       /*------------------ ICC Compiler ----------------------*/
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
   #include <cmsis_iar.h>
 
-#elif defined ( __TMS470__ )       /*------------------ TI CCS Compiler -------------------*/
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
   #include <cmsis_ccs.h>
 
-#elif defined ( __TASKING__ )      /*------------------ TASKING Compiler ------------------*/
+/*------------------ TASKING Compiler ------------------*/
-    /*
+#elif defined ( __TASKING__ )
-     * The CMSIS functions have been implemented as intrinsics in the compiler.
+  /*
-     * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
-     * Including the CMSIS ones.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
    */
 
-#elif defined ( __CSMC__ )         /*------------------ COSMIC Compiler -------------------*/
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
   #include <cmsis_csm.h>
 
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/cmsis/core_cmSimd.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cmSimd.h
  * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.20
+ * @version  V4.30
- * @date     02. July 2015
+ * @date     20. October 2015
  ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
@@ -34,7 +34,7 @@
 
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -46,40 +46,42 @@
 #endif
 
 
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
   @{
 */
 
-#if   defined ( __CC_ARM )         /*------------------ RealView Compiler -----------------*/
+/*------------------ RealView Compiler -----------------*/
-  #include <cmsis_armcc.h>
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
 
-#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+/*------------------ ARM Compiler V6 -------------------*/
-  #include <cmsis_armcc_V6.h>
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
 
-#elif defined ( __GNUC__ )         /*------------------ GNU Compiler ----------------------*/
+/*------------------ GNU Compiler ----------------------*/
-  #include <cmsis_gcc.h>
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
 
-#elif defined ( __ICCARM__ )       /*------------------ ICC Compiler ----------------------*/
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
   #include <cmsis_iar.h>
 
-#elif defined ( __TMS470__ )       /*------------------ TI CCS Compiler -------------------*/
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
   #include <cmsis_ccs.h>
 
-#elif defined ( __TASKING__ )      /*------------------ TASKING Compiler ------------------*/
+/*------------------ TASKING Compiler ------------------*/
-    /*
+#elif defined ( __TASKING__ )
-     * The CMSIS functions have been implemented as intrinsics in the compiler.
+  /*
-     * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
-     * Including the CMSIS ones.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
    */
 
-#elif defined ( __CSMC__ )         /*------------------ COSMIC Compiler -------------------*/
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
   #include <cmsis_csm.h>
 
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/system_XMC4700.c

@@ -1,34 +1,49 @@
-/******************************************************************************
+/*********************************************************************************************************************
  * @file     system_XMC4700.c
- * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4700 Device Series
- *           for the Infineon XMC4700 Device Series
+ * @version  V1.0.2
- * @version  V1.0.0
+ * @date     01. Jun 2016
- * @date     03. Sep 2015
  *
- * Copyright (C) 2015 Infineon Technologies AG. All rights reserved.
+ * @cond
+ *********************************************************************************************************************
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.
  *
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
+ * following conditions are met:
  *
- * @par
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
- * Infineon Technologies AG (Infineon) is supplying this software for use with
+ * disclaimer.
- * Infineon's microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such microcontrollers.
  *
- * @par
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
- * THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * disclaimer in the documentation and/or other materials provided with the distribution.
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  *
- ******************************************************************************/
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
-
+ * products derived from this software without specific prior written permission.
-/********************** Version History ***************************************
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
+ * Infineon Technologies AG dave@infineon.com).
+ *********************************************************************************************************************
+ *
+ ********************** Version History ***************************************
  * V1.0.0, 03. Sep 2015, Initial version
- ******************************************************************************/
+ * V1.0.1, 26. Jan 2016, Disable trap generation from clock unit
+ * V1.0.2, 01. Jun 2016, Fix masking of OSCHPCTRL value 
+ ******************************************************************************
+ * @endcond
+ */
 
 /*******************************************************************************
  * Default clock initialization
- * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
+ * fPLL = 288MHz => fSYS = 144MHz => fCPU = 144MHz
  *                                => fPB  = 144MHz
  *                                => fCCU = 144MHz
  *                                => fETH = 72MHz
@@ -299,13 +314,13 @@
 
 #define ENABLE_USBPLL \
      (((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
-
+                     
 #if ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)
 #define USB_DIV (3U)
 #else
 #define USB_DIV (5U)
 #endif
-
+    
 /*******************************************************************************
  * GLOBAL VARIABLES
  *******************************************************************************/
@@ -317,24 +332,24 @@ uint8_t g_chipid[16] __attribute__((at(0x2003FFC4)));
 uint32_t SystemCoreClock __attribute__((at(0x2002CFC0)));
 uint8_t g_chipid[16] __attribute__((at(0x2002CFC4)));
 #else
-#error "system_XMC4700.c: device not supported"
+#error "system_XMC4700.c: device not supported" 
-#endif
+#endif    
 #elif defined ( __ICCARM__ )
 #if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \
     defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
 __no_init uint32_t SystemCoreClock;
 __no_init uint8_t g_chipid[16];
 #else
-#error "system_XMC4700.c: device not supported"
+#error "system_XMC4700.c: device not supported" 
-#endif
+#endif    
 #elif defined ( __GNUC__ )
 #if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \
     defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
 uint32_t SystemCoreClock __attribute__((section(".no_init")));
 uint8_t g_chipid[16] __attribute__((section(".no_init")));
 #else
-#error "system_XMC4700.c: device not supported"
+#error "system_XMC4700.c: device not supported" 
-#endif
+#endif    
 #elif defined ( __TASKING__ )
 #if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048)
 uint32_t SystemCoreClock __at( 0x2003FFC0 );
@@ -343,11 +358,11 @@ uint8_t g_chipid[16] __at( 0x2003FFC4 );
 uint32_t SystemCoreClock __at( 0x2002CFC0 );
 uint8_t g_chipid[16] __at( 0x2002CFC4 );
 #else
-#error "system_XMC4700.c: device not supported"
+#error "system_XMC4700.c: device not supported" 
-#endif
+#endif    
 #else
-#error "system_XMC4700.c: compiler not supported"
+#error "system_XMC4700.c: compiler not supported" 
-#endif
+#endif    
 
 extern uint32_t __isr_vector;
 
@@ -371,21 +386,21 @@ static void delay(uint32_t cycles)
 __WEAK void SystemInit(void)
 {
   memcpy(g_chipid, CHIPID_LOC, 16);
-
+  
   SystemCoreSetup();
-  SystemCoreClockSetup();
+  SystemCoreClockSetup(); 
 }
 
 __WEAK void SystemCoreSetup(void)
 {
   uint32_t temp;
-
+	
   /* relocate vector table */
   __disable_irq();
   SCB->VTOR = (uint32_t)(&__isr_vector);
   __DSB();
   __enable_irq();
-
+    
 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
   SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
                  (3UL << 11*2)  );               /* set CP11 Full Access */
@@ -402,16 +417,6 @@ __WEAK void SystemCoreSetup(void)
 
 __WEAK void SystemCoreClockSetup(void)
 {
-    SCU_TRAP->TRAPDIS |= SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
-                         SCU_TRAP_TRAPCLR_ULPWDGT_Msk |
-                         SCU_TRAP_TRAPCLR_SVCOLCKT_Msk |
-                         SCU_TRAP_TRAPCLR_UVCOLCKT_Msk;
-
-    SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
-                        SCU_TRAP_TRAPCLR_ULPWDGT_Msk |
-                        SCU_TRAP_TRAPCLR_SVCOLCKT_Msk |
-                        SCU_TRAP_TRAPCLR_UVCOLCKT_Msk;
-
 #if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
   /* Enable factory calibration */
   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
@@ -436,7 +441,7 @@ __WEAK void SystemCoreClockSetup(void)
     SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
     delay(DELAY_CNT_150US_50MHZ);
   }
-
+  
 #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
   /* Enable OSC_ULP */
   if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
@@ -477,9 +482,6 @@ __WEAK void SystemCoreClockSetup(void)
     /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
   }
   SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
-
-  SCU_TRAP->TRAPDIS &= ~SCU_TRAP_TRAPDIS_ULPWDT_Msk;
-
 #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
 
   /* Enable automatic calibration of internal fast oscillator */
@@ -497,7 +499,7 @@ __WEAK void SystemCoreClockSetup(void)
   /* enable OSC_HP */
   if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
   {
-    SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
+    SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
 
     /* select OSC_HP clock as PLL input */
@@ -509,9 +511,7 @@ __WEAK void SystemCoreClockSetup(void)
     while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
     {
       /* wait till OSC_HP output frequency is usable */
-    }
+    }   
-
-    SCU_TRAP->TRAPDIS &= ~SCU_TRAP_TRAPDIS_SOSCWDGT_Msk;
   }
 #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
 
@@ -549,9 +549,7 @@ __WEAK void SystemCoreClockSetup(void)
   while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
   {
     /* wait for normal mode */
-  }
+  } 
-
-  SCU_TRAP->TRAPDIS &= ~SCU_TRAP_TRAPDIS_SVCOLCKT_Msk;
 #endif /* ENABLE_PLL */
 
   /* Before scaling to final frequency we need to setup the clock dividers */
@@ -568,7 +566,7 @@ __WEAK void SystemCoreClockSetup(void)
   /* PLL frequency stepping...*/
   /* Reset OSCDISCDIS */
   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
-
+  
   SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
 	                  (PLL_K2DIV_48MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
 	                  (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
@@ -598,7 +596,7 @@ __WEAK void SystemCoreClockSetup(void)
 	                  (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
 
   delay(DELAY_CNT_50US_144MHZ);
-
+  
 #endif /* ENABLE_PLL */
 
 #if ENABLE_USBPLL
@@ -616,7 +614,7 @@ __WEAK void SystemCoreClockSetup(void)
       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
     }
 
-    SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
+    SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
     SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
 
     /* restart OSC Watchdog */
@@ -652,9 +650,7 @@ __WEAK void SystemCoreClockSetup(void)
   while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
   {
     /* wait for PLL Lock */
-  }
+  }  
-
-  SCU_TRAP->TRAPDIS &= ~SCU_TRAP_TRAPDIS_UVCOLCKT_Msk;
 #endif
 
 
@@ -714,13 +710,13 @@ __WEAK void SystemCoreClockUpdate(void)
       /* PLL prescalar mode */
       /* read back divider settings */
       kdiv  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
-
+      
       temp = (temp / kdiv);
     }
   }
   else
   {
-    /* fOFI is clock source for fSYS */
+    /* fOFI is clock source for fSYS */    
     temp = OFI_FREQUENCY;
   }
 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/system_XMC4700.h

@@ -1,31 +1,46 @@
-/**************************************************************************//**
+/*********************************************************************************************************************
- * @file     system_XMC4800.h
+ * @file     system_XMC4700.h
- * @brief    Header file for the XMC4800-Series systeminit
+ * @brief    Device specific initialization for the XMC4700-Series according to CMSIS
- *           
  * @version  V1.0
- * @date     22. May 2015
+ * @date     22 May 2015
  *
- * @note
+ * @cond
- * Copyright (C) 2015 Infineon Technologies AG. All rights reserved.
+ *********************************************************************************************************************
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ **************************** Change history *********************************
+ * V1.0, 22 May 2015, JFT, Initial version
+ *****************************************************************************
+ * @endcond 
+ */
 
- *
+#ifndef SYSTEM_XMC4700_H
- * @par
+#define SYSTEM_XMC4700_H
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon<EFBFBD>s microcontrollers.  
- * This file can be freely distributed within development tools that are supporting such microcontrollers. 
-
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- *
- ******************************************************************************/
-
-#ifndef SYSTEM_XMC4800_H
-#define SYSTEM_XMC4800_H
 
 /*******************************************************************************
  * HEADER FILES

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_ccu4_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_ccu4_map.h
- * @date 2015-10-27
+ * @date 2015-12-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -39,6 +39,9 @@
  * 2015-08-25:
  *     - Initial version
  *
+ * 2015-12-07:
+ *     - Add XMC4300 support
+ *
  * @endcond
  */
 
@@ -937,6 +940,107 @@
 #define CCU41_IN3_VADC0_G1ARBCNT           	6
 #endif
 
+#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
+#define CCU40_IN0_CAN0_SR7                 	7
+#define CCU40_IN0_CCU40_ST0                	12
+#define CCU40_IN0_CCU40_ST1                	13
+#define CCU40_IN0_CCU40_ST2                	14
+#define CCU40_IN0_CCU40_ST3                	15
+#define CCU40_IN0_ERU1_PDOUT0              	9
+#define CCU40_IN0_ERU1_PDOUT1              	3
+#define CCU40_IN0_P1_3                     	0
+#define CCU40_IN0_P2_1                     	2
+#define CCU40_IN0_P2_8                     	1
+#define CCU40_IN0_SCU_ERU1_IOUT0           	10
+#define CCU40_IN0_SCU_GSC40                	8
+#define CCU40_IN0_U0C0_DX2INS              	11
+#define CCU40_IN1_CCU40_ST0                	12
+#define CCU40_IN1_CCU40_ST1                	13
+#define CCU40_IN1_CCU40_ST2                	14
+#define CCU40_IN1_CCU40_ST3                	15
+#define CCU40_IN1_ERU1_PDOUT0              	3
+#define CCU40_IN1_ERU1_PDOUT1              	9
+#define CCU40_IN1_P1_2                     	0
+#define CCU40_IN1_P2_0                     	2
+#define CCU40_IN1_P2_8                     	1
+#define CCU40_IN1_SCU_ERU1_IOUT1           	10
+#define CCU40_IN1_SCU_GSC40                	8
+#define CCU40_IN2_CCU40_ST0                	12
+#define CCU40_IN2_CCU40_ST1                	13
+#define CCU40_IN2_CCU40_ST2                	14
+#define CCU40_IN2_CCU40_ST3                	15
+#define CCU40_IN2_ERU1_PDOUT0              	3
+#define CCU40_IN2_ERU1_PDOUT2              	9
+#define CCU40_IN2_P1_1                     	0
+#define CCU40_IN2_P2_7                     	2
+#define CCU40_IN2_P2_8                     	1
+#define CCU40_IN2_SCU_ERU1_IOUT2           	10
+#define CCU40_IN2_SCU_GSC40                	8
+#define CCU40_IN2_U0C1_DX2INS              	11
+#define CCU40_IN3_CCU40_ST0                	12
+#define CCU40_IN3_CCU40_ST1                	13
+#define CCU40_IN3_CCU40_ST2                	14
+#define CCU40_IN3_CCU40_ST3                	15
+#define CCU40_IN3_CCU80_IGBTO              	7
+#define CCU40_IN3_ERU1_PDOUT0              	3
+#define CCU40_IN3_ERU1_PDOUT3              	9
+#define CCU40_IN3_P1_0                     	0
+#define CCU40_IN3_P2_6                     	2
+#define CCU40_IN3_P2_8                     	1
+#define CCU40_IN3_SCU_ERU1_IOUT3           	10
+#define CCU40_IN3_SCU_GSC40                	8
+#define CCU40_IN3_U1C0_DX2INS              	11
+#define CCU40_IN3_VADC0_G0ARBCNT           	6
+#define CCU41_IN0_CAN0_SR7                 	7
+#define CCU41_IN0_CCU41_ST0                	12
+#define CCU41_IN0_CCU41_ST1                	13
+#define CCU41_IN0_CCU41_ST2                	14
+#define CCU41_IN0_CCU41_ST3                	15
+#define CCU41_IN0_ERU1_PDOUT0              	9
+#define CCU41_IN0_ERU1_PDOUT1              	3
+#define CCU41_IN0_P1_4                     	2
+#define CCU41_IN0_P2_5                     	0
+#define CCU41_IN0_P2_9                     	1
+#define CCU41_IN0_SCU_ERU1_IOUT0           	10
+#define CCU41_IN0_SCU_GSC41                	8
+#define CCU41_IN0_VADC0_G0BFL0             	11
+#define CCU41_IN1_CCU41_ST0                	12
+#define CCU41_IN1_CCU41_ST1                	13
+#define CCU41_IN1_CCU41_ST2                	14
+#define CCU41_IN1_CCU41_ST3                	15
+#define CCU41_IN1_ERU1_PDOUT0              	3
+#define CCU41_IN1_ERU1_PDOUT1              	9
+#define CCU41_IN1_P1_5                     	2
+#define CCU41_IN1_P2_4                     	0
+#define CCU41_IN1_P2_9                     	1
+#define CCU41_IN1_SCU_ERU1_IOUT1           	10
+#define CCU41_IN1_SCU_GSC41                	8
+#define CCU41_IN2_CCU41_ST0                	12
+#define CCU41_IN2_CCU41_ST1                	13
+#define CCU41_IN2_CCU41_ST2                	14
+#define CCU41_IN2_CCU41_ST3                	15
+#define CCU41_IN2_ERU1_PDOUT0              	3
+#define CCU41_IN2_ERU1_PDOUT2              	9
+#define CCU41_IN2_P1_10                    	2
+#define CCU41_IN2_P2_3                     	0
+#define CCU41_IN2_P2_9                     	1
+#define CCU41_IN2_SCU_ERU1_IOUT2           	10
+#define CCU41_IN2_SCU_GSC41                	8
+#define CCU41_IN2_VADC0_G0BFL1             	11
+#define CCU41_IN3_CCU41_ST0                	12
+#define CCU41_IN3_CCU41_ST1                	13
+#define CCU41_IN3_CCU41_ST2                	14
+#define CCU41_IN3_CCU41_ST3                	15
+#define CCU41_IN3_ERU1_PDOUT0              	3
+#define CCU41_IN3_ERU1_PDOUT3              	9
+#define CCU41_IN3_P1_11                    	2
+#define CCU41_IN3_P2_2                     	0
+#define CCU41_IN3_P2_9                     	1
+#define CCU41_IN3_SCU_ERU1_IOUT3           	10
+#define CCU41_IN3_SCU_GSC41                	8
+#define CCU41_IN3_VADC0_G0BFL2             	11
+#define CCU41_IN3_VADC0_G1ARBCNT           	6
+#endif
 
 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
 #define CCU40_IN0_CAN0_SR7                 	7

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_ccu8_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_ccu8_map.h
- * @date 2015-10-27
+ * @date 2015-12-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -39,6 +39,9 @@
  * 2015-08-25:
  *     - Initial version
  *
+ * 2015-12-07:
+ *     - Add XMC4300 support
+ *
  * @endcond
  */
 
@@ -521,6 +524,57 @@
 #define CCU80_IN3_VADC0_G0BFL3             	8
 #endif
 
+#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
+#define CCU80_IN0_CCU40_SR3                	10
+#define CCU80_IN0_CCU80_ST0                	12
+#define CCU80_IN0_CCU80_ST1                	13
+#define CCU80_IN0_CCU80_ST2                	14
+#define CCU80_IN0_CCU80_ST3                	15
+#define CCU80_IN0_ERU1_PDOUT0              	9
+#define CCU80_IN0_P0_7                     	0
+#define CCU80_IN0_P3_2                     	2
+#define CCU80_IN0_P3_4                     	1
+#define CCU80_IN0_SCU_ERU1_IOUT0           	6
+#define CCU80_IN0_SCU_GSC80                	7
+#define CCU80_IN0_VADC0_G0BFL0             	8
+#define CCU80_IN0_VADC0_G0SR3              	5
+#define CCU80_IN1_CCU41_SR3                	10
+#define CCU80_IN1_CCU80_ST0                	12
+#define CCU80_IN1_CCU80_ST1                	13
+#define CCU80_IN1_CCU80_ST2                	14
+#define CCU80_IN1_CCU80_ST3                	15
+#define CCU80_IN1_ERU1_PDOUT0              	9
+#define CCU80_IN1_ERU1_PDOUT1              	5
+#define CCU80_IN1_P0_7                     	0
+#define CCU80_IN1_P0_8                     	1
+#define CCU80_IN1_P3_1                     	2
+#define CCU80_IN1_SCU_ERU1_IOUT1           	6
+#define CCU80_IN1_SCU_GSC80                	7
+#define CCU80_IN1_VADC0_G0BFL1             	8
+#define CCU80_IN2_CCU80_ST0                	12
+#define CCU80_IN2_CCU80_ST1                	13
+#define CCU80_IN2_CCU80_ST2                	14
+#define CCU80_IN2_CCU80_ST3                	15
+#define CCU80_IN2_ERU1_PDOUT0              	9
+#define CCU80_IN2_ERU1_PDOUT2              	5
+#define CCU80_IN2_P0_6                     	1
+#define CCU80_IN2_P0_7                     	0
+#define CCU80_IN2_P3_0                     	2
+#define CCU80_IN2_SCU_ERU1_IOUT2           	6
+#define CCU80_IN2_SCU_GSC80                	7
+#define CCU80_IN2_VADC0_G0BFL2             	8
+#define CCU80_IN3_CCU80_ST0                	12
+#define CCU80_IN3_CCU80_ST1                	13
+#define CCU80_IN3_CCU80_ST2                	14
+#define CCU80_IN3_CCU80_ST3                	15
+#define CCU80_IN3_ERU1_PDOUT0              	9
+#define CCU80_IN3_ERU1_PDOUT3              	5
+#define CCU80_IN3_P0_7                     	0
+#define CCU80_IN3_P3_3                     	1
+#define CCU80_IN3_SCU_ERU1_IOUT3           	6
+#define CCU80_IN3_SCU_GSC80                	7
+#define CCU80_IN3_VADC0_G0BFL3             	8
+#endif
 
 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
 #define CCU80_IN0_CCU40_SR3                	10

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_eru_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_eru_map.h
- * @date 2015-10-27
+ * @date 2015-12-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -39,6 +39,10 @@
  * 2015-02-20:
  *     - Initial version
  *
+ * 2015-12-07:
+ *     - Add XMC4300 support
+ *
+ *
  * @endcond
  */
 
@@ -670,6 +674,87 @@
 #endif
 
 
+#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
+#define ERU0_ETL0_INPUTA_P0_1              	XMC_ERU_ETL_INPUT_A0
+#define ERU0_ETL0_INPUTA_P2_5              	XMC_ERU_ETL_INPUT_A2
+#define ERU0_ETL0_INPUTA_P3_2              	XMC_ERU_ETL_INPUT_A1
+#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6     	XMC_ERU_ETL_INPUT_A3
+#define ERU0_ETL0_INPUTB_P0_0              	XMC_ERU_ETL_INPUT_B0
+#define ERU0_ETL0_INPUTB_P2_0              	XMC_ERU_ETL_INPUT_B3
+#define ERU0_ETL0_INPUTB_P2_4              	XMC_ERU_ETL_INPUT_B2
+#define ERU0_ETL0_INPUTB_P3_1              	XMC_ERU_ETL_INPUT_B1
+#define ERU0_ETL1_INPUTA_P0_10             	XMC_ERU_ETL_INPUT_A0
+#define ERU0_ETL1_INPUTA_P2_3              	XMC_ERU_ETL_INPUT_A2
+#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7     	XMC_ERU_ETL_INPUT_A3
+#define ERU0_ETL1_INPUTA_SCU_HIB_SR0       	XMC_ERU_ETL_INPUT_A1
+#define ERU0_ETL1_INPUTB_P0_1              	XMC_ERU_ETL_INPUT_B1
+#define ERU0_ETL1_INPUTB_P0_9              	XMC_ERU_ETL_INPUT_B0
+#define ERU0_ETL1_INPUTB_P2_2              	XMC_ERU_ETL_INPUT_B2
+#define ERU0_ETL1_INPUTB_P2_6              	XMC_ERU_ETL_INPUT_B3
+#define ERU0_ETL2_INPUTA_P0_8              	XMC_ERU_ETL_INPUT_A1
+#define ERU0_ETL2_INPUTA_P1_5              	XMC_ERU_ETL_INPUT_A0
+#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6     	XMC_ERU_ETL_INPUT_A3
+#define ERU0_ETL2_INPUTB_P0_12             	XMC_ERU_ETL_INPUT_B2
+#define ERU0_ETL2_INPUTB_P0_4              	XMC_ERU_ETL_INPUT_B3
+#define ERU0_ETL2_INPUTB_P0_7              	XMC_ERU_ETL_INPUT_B1
+#define ERU0_ETL2_INPUTB_P1_4              	XMC_ERU_ETL_INPUT_B0
+#define ERU0_ETL3_INPUTA_P0_11             	XMC_ERU_ETL_INPUT_A2
+#define ERU0_ETL3_INPUTA_P1_1              	XMC_ERU_ETL_INPUT_A0
+#define ERU0_ETL3_INPUTA_P3_6              	XMC_ERU_ETL_INPUT_A1
+#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7     	XMC_ERU_ETL_INPUT_A3
+#define ERU0_ETL3_INPUTB_P0_2              	XMC_ERU_ETL_INPUT_B3
+#define ERU0_ETL3_INPUTB_P0_6              	XMC_ERU_ETL_INPUT_B2
+#define ERU0_ETL3_INPUTB_P1_0              	XMC_ERU_ETL_INPUT_B0
+#define ERU0_ETL3_INPUTB_P3_5              	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL0_INPUTA_CCU40_ST0         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL0_INPUTA_DAC_SGN_0         	XMC_ERU_ETL_INPUT_A3
+#define ERU1_ETL0_INPUTA_P1_5              	XMC_ERU_ETL_INPUT_A0
+#define ERU1_ETL0_INPUTB_CCU80_ST0         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL0_INPUTB_ERU1_IOUT3        	XMC_ERU_ETL_INPUT_B3
+#define ERU1_ETL0_INPUTB_P2_1              	XMC_ERU_ETL_INPUT_B0
+#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3   	XMC_ERU_ETL_INPUT_B2
+#define ERU1_ETL1_INPUTA_CCU40_ST1         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL1_INPUTA_ERU1_IOUT2        	XMC_ERU_ETL_INPUT_A3
+#define ERU1_ETL1_INPUTA_P1_15             	XMC_ERU_ETL_INPUT_A0
+#define ERU1_ETL1_INPUTB_CCU80_ST1         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL1_INPUTB_ERU1_IOUT2        	XMC_ERU_ETL_INPUT_B3
+#define ERU1_ETL1_INPUTB_P2_7              	XMC_ERU_ETL_INPUT_B0
+#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3   	XMC_ERU_ETL_INPUT_B2
+#define ERU1_ETL2_INPUTA_CCU40_ST2         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL2_INPUTA_DAC_SGN_1         	XMC_ERU_ETL_INPUT_A3
+#define ERU1_ETL2_INPUTA_P1_3              	XMC_ERU_ETL_INPUT_A0
+#define ERU1_ETL2_INPUTB_CCU80_ST2         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL2_INPUTB_ECAT0_SYNC0    	XMC_ERU_ETL_INPUT_B3
+#define ERU1_ETL2_INPUTB_P1_2              	XMC_ERU_ETL_INPUT_B0
+#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3   	XMC_ERU_ETL_INPUT_B2
+#define ERU1_ETL3_INPUTA_CCU40_ST3         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL3_INPUTA_ECAT0_SYNC1    	XMC_ERU_ETL_INPUT_A3
+#define ERU1_ETL3_INPUTA_P0_5              	XMC_ERU_ETL_INPUT_A0
+#define ERU1_ETL3_INPUTB_CCU80_ST3         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL3_INPUTB_P0_3              	XMC_ERU_ETL_INPUT_B0
+#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3   	XMC_ERU_ETL_INPUT_B2
+
+#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH  	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH  	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH  	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH  	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0	XMC_ERU_OGU_PERIPHERAL_TRIGGER2
+#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0	XMC_ERU_OGU_PERIPHERAL_TRIGGER2
+#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL  	XMC_ERU_OGU_PERIPHERAL_TRIGGER3
+#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3	XMC_ERU_OGU_PERIPHERAL_TRIGGER1
+#endif
+
+
 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
 #define ERU0_ETL0_INPUTA_P0_1              	XMC_ERU_ETL_INPUT_A0
 #define ERU0_ETL0_INPUTA_P2_5              	XMC_ERU_ETL_INPUT_A2
@@ -1836,9 +1921,11 @@
 #define ERU1_ETL2_INPUTA_P1_3              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL2_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL2_INPUTB_CCU80_ST2         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL2_INPUTB_ECAT0_SYNC0    	XMC_ERU_ETL_INPUT_B3
 #define ERU1_ETL2_INPUTB_P1_2              	XMC_ERU_ETL_INPUT_B0
 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3   	XMC_ERU_ETL_INPUT_B2
 #define ERU1_ETL3_INPUTA_CCU40_ST3         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL3_INPUTA_ECAT0_SYNC1    	XMC_ERU_ETL_INPUT_A3
 #define ERU1_ETL3_INPUTA_P0_5              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL3_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL3_INPUTB_CCU80_ST3         	XMC_ERU_ETL_INPUT_B1
@@ -1921,9 +2008,11 @@
 #define ERU1_ETL2_INPUTA_P1_3              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL2_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL2_INPUTB_CCU80_ST2         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL2_INPUTB_ECAT0_SYNC0    	XMC_ERU_ETL_INPUT_B3
 #define ERU1_ETL2_INPUTB_P1_2              	XMC_ERU_ETL_INPUT_B0
 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3   	XMC_ERU_ETL_INPUT_B2
 #define ERU1_ETL3_INPUTA_CCU40_ST3         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL3_INPUTA_ECAT0_SYNC1    	XMC_ERU_ETL_INPUT_A3
 #define ERU1_ETL3_INPUTA_P0_5              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL3_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL3_INPUTB_CCU80_ST3         	XMC_ERU_ETL_INPUT_B1
@@ -2007,9 +2096,11 @@
 #define ERU1_ETL2_INPUTA_P1_3              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL2_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL2_INPUTB_CCU80_ST2         	XMC_ERU_ETL_INPUT_B1
+#define ERU1_ETL2_INPUTB_ECAT0_SYNC0    	XMC_ERU_ETL_INPUT_B3
 #define ERU1_ETL2_INPUTB_P1_2              	XMC_ERU_ETL_INPUT_B0
 #define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3   	XMC_ERU_ETL_INPUT_B2
 #define ERU1_ETL3_INPUTA_CCU40_ST3         	XMC_ERU_ETL_INPUT_A2
+#define ERU1_ETL3_INPUTA_ECAT0_SYNC1    	XMC_ERU_ETL_INPUT_A3
 #define ERU1_ETL3_INPUTA_P0_5              	XMC_ERU_ETL_INPUT_A0
 #define ERU1_ETL3_INPUTA_POSIF1_SR1        	XMC_ERU_ETL_INPUT_A1
 #define ERU1_ETL3_INPUTB_CCU80_ST3         	XMC_ERU_ETL_INPUT_B1

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_flash.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_flash.h
- * @date 2015-10-27
+ * @date 2016-03-22
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -50,6 +50,12 @@
  *       4. XMC_FLASH_ResumeProtection
  *       5. XMC_FLASH_RepairPhysicalSector 
  *     - Added support for XMC4800/4700 devices
+ * 2015-12-07:
+ *     - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices
+ * 2016-03-18:
+ *     - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer
+ * 2016-03-22:
+ *     - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer
  * @endcond 
  *
  */
@@ -133,7 +139,7 @@
 #define XMC_FLASH_PHY_SECTOR_15    (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C0000UL) /**<Starting address of non cached
                                                                                          physical sector15 */
 
-#if UC_SERIES == XMC45
+#if UC_SERIES == XMC45 || UC_SERIES == XMC43 || UC_SERIES == XMC47 || UC_SERIES == XMC48
 #define XMC_FLASH_READ_ACCESS_TIME (22E-9F) /* Flash read access time  */
 #else
 #define XMC_FLASH_READ_ACCESS_TIME (20E-9F)
@@ -448,7 +454,7 @@ __STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states)
  */
 __STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void)
 {
-	PREF->PCON |= PREF_PCON_IBYP_Msk;
+	PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk;
 }
 
 /**
@@ -465,7 +471,7 @@ __STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void)
  */
 __STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void)
 {
-	PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk;
+	PREF->PCON |= PREF_PCON_IBYP_Msk;
 }
 
 /**
@@ -487,6 +493,13 @@ __STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void)
 __STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void)
 {
   PREF->PCON |= PREF_PCON_IINV_Msk;
+  __DSB();
+  __ISB();
+
+  PREF->PCON &= ~PREF_PCON_IINV_Msk;
+  __DSB();
+  __ISB();
+
 }
 
 /**
@@ -548,10 +561,12 @@ void XMC_FLASH_ConfirmProtection(uint8_t user);
  * Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection
  * process, it clears the error status bits inside status register. It temporarily disables the protection with
  * passwords \a password0 and \a password1 respectively. It reads the FSR register and verifies the protection state.
+ * Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
  *
  * \par<b>Related APIs:</b><BR>
  * XMC_FLASH_InstallProtection()<BR> 
  * XMC_FLASH_VerifyWriteProtection()<BR>
+ * XMC_FLASH_ResumeProtection()<BR>
  */
 bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1);
 
@@ -571,10 +586,12 @@ bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1);
  * process, it clears the error status bits inside status register. It temporarily disables the protection with
  * passwords \a password0 and \a password1 respectively for the intended sectors specified in \a protection_mask.
  * It reads the FSR register and verifies the write protection state.
+ * Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
  *
  * \par<b>Related APIs:</b><BR>
  * XMC_FLASH_InstallProtection()<BR> 
  * XMC_FLASH_VerifyReadProtection()<BR>
+ * XMC_FLASH_ResumeProtection()<BR>
  */
 bool XMC_FLASH_VerifyWriteProtection(uint32_t user, 
                                      uint32_t protection_mask, 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_gpio.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_gpio.h
- * @date 2015-10-27
+ * @date 2015-10-09
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_rtc.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_rtc.h
- * @date 2015-10-27
+ * @date 2015-05-20
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc4_usic_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_usic_map.h
- * @date 2015-10-27
+ * @date 2016-07-20
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -42,6 +42,14 @@
  * 2015-08-25:
  *     - Added XMC4800
  *      
+ * 2015-12-07:
+ *     - Add XMC4300 support
+ *
+ * 2016-07-20:
+ *     - Add missing USIC2_C1_DX0_P4_6,USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5, USIC2_C0_DX0_P9_4, USIC2_C1_DX1_P9_9, USIC2_C1_DX2_P9_8  for XMC47/48 BGA196
+ *     - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14 for XMC47/48 LQFP100
+ *     - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5 for XMC47/48 LQFP144
+ *
  * @endcond 
  *
  */
@@ -479,6 +487,67 @@
 #endif
 
 
+#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
+#define USIC0_C0_DX0_DOUT0  	6
+#define USIC0_C0_DX0_P1_4   	1
+#define USIC0_C0_DX0_P1_5   	0
+#define USIC0_C0_DX0_P5_0   	3
+#define USIC0_C0_DX1_DX0INS 	5
+#define USIC0_C0_DX1_P0_8   	1
+#define USIC0_C0_DX1_P1_1   	0
+#define USIC0_C0_DX1_SCLKOUT	6
+#define USIC0_C0_DX2_CCU40_SR1	4
+#define USIC0_C0_DX2_CCU80_SR1	5
+#define USIC0_C0_DX2_P0_7   	1
+#define USIC0_C0_DX2_P1_0   	0
+#define USIC0_C0_DX2_SELO0  	6
+#define USIC0_C0_DX3_DOUT1  	6
+#define USIC0_C0_DX4_DOUT2  	6
+#define USIC0_C0_DX5_DOUT3  	6
+#define USIC0_C1_DX0_DOUT0  	6
+#define USIC0_C1_DX0_P2_2   	0
+#define USIC0_C1_DX0_P2_5   	1
+#define USIC0_C1_DX0_P4_0   	4
+#define USIC0_C1_DX1_DX0INS 	5
+#define USIC0_C1_DX1_P2_4   	0
+#define USIC0_C1_DX1_P3_0   	1
+#define USIC0_C1_DX1_SCLKOUT	6
+#define USIC0_C1_DX2_CCU80_SR1	5
+#define USIC0_C1_DX2_P2_3   	0
+#define USIC0_C1_DX2_P3_1   	1
+#define USIC0_C1_DX2_SELO0  	6
+#define USIC0_C1_DX3_DOUT1  	6
+#define USIC0_C1_DX4_DOUT2  	6
+#define USIC0_C1_DX5_DOUT3  	6
+#define USIC1_C0_DX0_DOUT0  	6
+#define USIC1_C0_DX0_P0_4   	0
+#define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P2_14  	3
+#define USIC1_C0_DX0_P2_15  	2
+#define USIC1_C0_DX1_DX0INS 	5
+#define USIC1_C0_DX1_P0_11  	0
+#define USIC1_C0_DX1_SCLKOUT	6
+#define USIC1_C0_DX2_CCU41_SR1	4
+#define USIC1_C0_DX2_P0_6   	0
+#define USIC1_C0_DX2_SELO0  	6
+#define USIC1_C0_DX3_DOUT1  	6
+#define USIC1_C0_DX4_DOUT2  	6
+#define USIC1_C0_DX5_DOUT3  	6
+#define USIC1_C1_DX0_DOUT0  	6
+#define USIC1_C1_DX0_P0_0   	3
+#define USIC1_C1_DX1_DX0INS 	5
+#define USIC1_C1_DX1_P0_10  	0
+#define USIC1_C1_DX1_P4_0   	2
+#define USIC1_C1_DX1_SCLKOUT	6
+#define USIC1_C1_DX2_P0_12  	1
+#define USIC1_C1_DX2_P0_9   	0
+#define USIC1_C1_DX2_SELO0  	6
+#define USIC1_C1_DX3_DOUT1  	6
+#define USIC1_C1_DX4_DOUT2  	6
+#define USIC1_C1_DX5_DOUT3  	6
+#endif
+
+
 #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
 #define USIC0_C0_DX0_DOUT0  	6
 #define USIC0_C0_DX0_P1_4   	1
@@ -1358,6 +1427,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1394,6 +1464,8 @@
 #define USIC2_C0_DX0_P3_7   	2
 #define USIC2_C0_DX0_P5_0   	1
 #define USIC2_C0_DX0_P5_1   	0
+#define USIC2_C0_DX0_P6_5   	3
+#define USIC2_C0_DX0_P9_4   	4
 #define USIC2_C0_DX1_DX0INS 	5
 #define USIC2_C0_DX1_P5_2   	0
 #define USIC2_C0_DX1_P9_1   	2
@@ -1411,13 +1483,16 @@
 #define USIC2_C1_DX0_P3_4   	1
 #define USIC2_C1_DX0_P3_5   	0
 #define USIC2_C1_DX0_P4_0   	2
+#define USIC2_C1_DX0_P4_6   	4
 #define USIC2_C1_DX1_DX0INS 	5
 #define USIC2_C1_DX1_P3_6   	1
 #define USIC2_C1_DX1_P4_2   	0
+#define USIC2_C1_DX1_P9_9   	2
 #define USIC2_C1_DX1_SCLKOUT	6
 #define USIC2_C1_DX2_CCU43_SR1	4
 #define USIC2_C1_DX2_CCU81_SR1	5
 #define USIC2_C1_DX2_P4_1   	0
+#define USIC2_C1_DX2_P9_8   	2
 #define USIC2_C1_DX2_SELO0  	6
 #define USIC2_C1_DX3_DOUT1  	6
 #define USIC2_C1_DX4_DOUT2  	6
@@ -1461,6 +1536,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1557,6 +1633,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1593,6 +1670,7 @@
 #define USIC2_C0_DX0_P3_7   	2
 #define USIC2_C0_DX0_P5_0   	1
 #define USIC2_C0_DX0_P5_1   	0
+#define USIC2_C0_DX0_P6_5   	3
 #define USIC2_C0_DX1_DX0INS 	5
 #define USIC2_C0_DX1_P5_2   	0
 #define USIC2_C0_DX1_SCLKOUT	6
@@ -1608,6 +1686,7 @@
 #define USIC2_C1_DX0_P3_4   	1
 #define USIC2_C1_DX0_P3_5   	0
 #define USIC2_C1_DX0_P4_0   	2
+#define USIC2_C1_DX0_P4_6   	4
 #define USIC2_C1_DX1_DX0INS 	5
 #define USIC2_C1_DX1_P3_6   	1
 #define USIC2_C1_DX1_P4_2   	0
@@ -1666,6 +1745,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1702,6 +1782,8 @@
 #define USIC2_C0_DX0_P3_7   	2
 #define USIC2_C0_DX0_P5_0   	1
 #define USIC2_C0_DX0_P5_1   	0
+#define USIC2_C0_DX0_P6_5   	3
+#define USIC2_C0_DX0_P9_4   	4
 #define USIC2_C0_DX1_DX0INS 	5
 #define USIC2_C0_DX1_P5_2   	0
 #define USIC2_C0_DX1_P9_1   	2
@@ -1719,13 +1801,16 @@
 #define USIC2_C1_DX0_P3_4   	1
 #define USIC2_C1_DX0_P3_5   	0
 #define USIC2_C1_DX0_P4_0   	2
+#define USIC2_C1_DX0_P4_6   	4
 #define USIC2_C1_DX1_DX0INS 	5
 #define USIC2_C1_DX1_P3_6   	1
 #define USIC2_C1_DX1_P4_2   	0
+#define USIC2_C1_DX1_P9_9   	2
 #define USIC2_C1_DX1_SCLKOUT	6
 #define USIC2_C1_DX2_CCU43_SR1	4
 #define USIC2_C1_DX2_CCU81_SR1	5
 #define USIC2_C1_DX2_P4_1   	0
+#define USIC2_C1_DX2_P9_8   	2
 #define USIC2_C1_DX2_SELO0  	6
 #define USIC2_C1_DX3_DOUT1  	6
 #define USIC2_C1_DX4_DOUT2  	6
@@ -1769,6 +1854,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1865,6 +1951,7 @@
 #define USIC1_C0_DX0_DOUT0  	6
 #define USIC1_C0_DX0_P0_4   	0
 #define USIC1_C0_DX0_P0_5   	1
+#define USIC1_C0_DX0_P1_14  	4
 #define USIC1_C0_DX0_P2_14  	3
 #define USIC1_C0_DX0_P2_15  	2
 #define USIC1_C0_DX1_DX0INS 	5
@@ -1901,6 +1988,7 @@
 #define USIC2_C0_DX0_P3_7   	2
 #define USIC2_C0_DX0_P5_0   	1
 #define USIC2_C0_DX0_P5_1   	0
+#define USIC2_C0_DX0_P6_5   	3
 #define USIC2_C0_DX1_DX0INS 	5
 #define USIC2_C0_DX1_P5_2   	0
 #define USIC2_C0_DX1_SCLKOUT	6
@@ -1916,6 +2004,7 @@
 #define USIC2_C1_DX0_P3_4   	1
 #define USIC2_C1_DX0_P3_5   	0
 #define USIC2_C1_DX0_P4_0   	2
+#define USIC2_C1_DX0_P4_6   	4
 #define USIC2_C1_DX1_DX0INS 	5
 #define USIC2_C1_DX1_P3_6   	1
 #define USIC2_C1_DX1_P4_2   	0

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_acmp.h

@@ -0,0 +1,424 @@
+/**
+ * @file xmc_acmp.h
+ * @date 2015-09-02
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2014-12-10:
+ *     - Initial version
+ * 2015-02-20:
+ *     - Removed unused declarations<br> 
+ * 2015-05-08:
+ *     - Fixed sequence problem of low power mode in XMC_ACMP_Init() API<br>
+ *     - Fixed wrong register setting in XMC_ACMP_SetInput() API<br> 
+ *     - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
+ *       Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.<br>
+ * 2015-06-04:
+ *     - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
+ *     - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below<br> 
+ *       (a)XMC_ACMP_EnableReferenceDivider <br>
+ *       (b)XMC_ACMP_DisableReferenceDivider <br> 
+ *       (c)XMC_ACMP_SetInput <br> 
+ *     - Optimized enable and disable API's and moved to header file as static inline APIs.
+ *     - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure.
+ * 2015-06-20: 
+ *     - Removed version macros and declaration of GetDriverVersion API 
+ * 2015-06-26: 
+ *     - API help documentation modified.
+ * 2015-09-02: 
+ *     - API help documentation modified for XMC1400 device support.   
+ * @endcond 
+ *
+ */
+ 
+#ifndef XMC_ACMP_H
+#define XMC_ACMP_H
+ 
+
+/**
+ * @addtogroup XMClib XMC Peripheral Library
+ * @{
+ */
+
+/**
+ * @addtogroup ACMP
+ * @brief Analog Comparator(ACMP) low level driver for XMC1 family of microcontrollers. <br>
+ *
+ * The ACMP module consists of minimum of 3 analog comparators. Each analog comparator has two inputs, INP and INN. 
+ * Input INP is compared with input INN in the pad voltage domain.
+ * It generates a digital comparator output signal. The digital comparator output signal is shifted down from VDDP 
+ * power supply voltage level to VDDC core voltage level. The ACMP module provides the following functionalities.\n
+ * -# Monitor external voltage level
+ * -# Operates in low power mode
+ * -# Provides Inverted ouput option\n
+
+ * \par The ACMP low level driver funtionalities
+ * <OL>
+ * <LI>Initializes an instance of analog comparator module with the @ref XMC_ACMP_CONFIG_t configuration structure 
+ * using the API XMC_ACMP_Init().</LI>
+ * <LI>Programs the source of input(INP) specified by @ref XMC_ACMP_INP_SOURCE_t parameter using the API 
+ * XMC_ACMP_SetInput(). </LI>
+ * <LI>Sets the low power mode of operation using XMC_ACMP_SetLowPowerMode() API.</LI>
+ * </OL>
+ * @{
+ */
+ 
+/*********************************************************************************************************************
+ * HEADER FILES
+ ********************************************************************************************************************/
+#include <xmc_common.h>
+
+/*********************************************************************************************************************
+ * MACROS
+ ********************************************************************************************************************/
+/* If ACMP is available*/
+#if defined (COMPARATOR)
+
+#define XMC_ACMP0 (XMC_ACMP_t*)COMPARATOR /**< Comparator module base address defined*/
+
+#if UC_SERIES == XMC14
+#define XMC_ACMP_MAX_INSTANCES     (4U) /* Maximum number of Analog Comparators available*/
+#else
+#define XMC_ACMP_MAX_INSTANCES     (3U) /* Maximum number of Analog Comparators available*/
+#endif
+
+/* Checks if the pointer being passed is valid*/
+#define XMC_ACMP_CHECK_MODULE_PTR(PTR)  (((PTR)== (XMC_ACMP_t*)COMPARATOR))
+
+/* Checks if the instance being addressed is valid*/
+#define XMC_ACMP_CHECK_INSTANCE(INST)   (((INST)< XMC_ACMP_MAX_INSTANCES))
+
+/*********************************************************************************************************************
+ * ENUMS
+ ********************************************************************************************************************/
+
+/**
+ * Defines the return value of an API.
+ */ 
+typedef enum XMC_ACMP_STATUS
+{
+  XMC_ACMP_STATUS_SUCCESS = 0U, /**< API completes the execution successfully */
+  XMC_ACMP_STATUS_ERROR       , /**< API cannot fulfill the request */
+} XMC_ACMP_STATUS_t;
+
+/**
+ * Defines the hysteresis voltage levels to reduce noise sensitivity.
+ */ 
+typedef enum XMC_ACMP_HYSTERESIS
+{
+  XMC_ACMP_HYSTERESIS_OFF = 0U, /**< No hysteresis */
+  XMC_ACMP_HYSTERESIS_10     ,  /**< Hysteresis = 10mv */
+  XMC_ACMP_HYSTERESIS_15     ,  /**< Hysteresis = 15mv */
+  XMC_ACMP_HYSTERESIS_20        /**< Hysteresis = 20mv */
+} XMC_ACMP_HYSTERESIS_t;
+
+/**
+ *  Defines the comparator output status options.
+ */ 
+typedef enum XMC_ACMP_COMP_OUT
+{
+  XMC_ACMP_COMP_OUT_NO_INVERSION = 0U, /**< ACMP output is HIGH when, Input Positive(INP) greater than Input
+                                            Negative(INN). Vplus > Vminus */
+  XMC_ACMP_COMP_OUT_INVERSION          /**< ACMP output is HIGH when, Input Negative(INN) greater than Input
+                                            Positive(INP). Vminus > Vplus*/
+} XMC_ACMP_COMP_OUT_t;
+
+/**
+ *  Defines the analog comparator input connection method.
+ */ 
+typedef enum XMC_ACMP_INP_SOURCE
+{
+  XMC_ACMP_INP_SOURCE_STANDARD_PORT  = 0U,                                          /**< Input is connected to port */
+  XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT = (uint16_t)(COMPARATOR_ANACMP0_ACMP0_SEL_Msk) /**< Input is connected to port
+                                                                                     and ACMP1 INP */
+} XMC_ACMP_INP_SOURCE_t;
+
+/*********************************************************************************************************************
+ * DATA STRUCTURES
+ ********************************************************************************************************************/
+
+
+/*Anonymous structure/union guard start*/
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__TASKING__)
+  #pragma warning 586
+#endif
+
+/**
+ * ACMP module
+ */
+typedef struct {
+  __IO uint32_t  ORCCTRL;
+  __I  uint32_t  RESERVED[726];
+  __IO uint32_t  ANACMP[XMC_ACMP_MAX_INSTANCES];
+} XMC_ACMP_t;
+
+/**
+ *  Structure for initializing the ACMP module. It configures the ANACMP register of the respective input.
+ */
+typedef struct XMC_ACMP_CONFIG
+{
+  union
+  {
+    struct
+    {
+      uint32_t                  : 1;
+      uint32_t filter_disable   : 1; /**< Comparator filter option for removing glitches. By default this option
+                                          is selected in ANACMP register. Setting this option disables the filter */
+      uint32_t                  : 1;
+      uint32_t output_invert    : 1; /**< Option to invert the comparator output. Use XMC_@ref XMC_ACMP_COMP_OUT_t type*/
+      uint32_t hysteresis       : 2; /**< Hysteresis voltage to reduce noise sensitivity. Select the voltage levels
+                                          from the values defined in @ref XMC_ACMP_HYSTERESIS_t. */
+      uint32_t                  : 26;
+    };
+    uint32_t anacmp;
+  };
+} XMC_ACMP_CONFIG_t;
+
+/*Anonymous structure/union guard end*/
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__TASKING__)
+  #pragma warning restore
+#endif
+
+#ifdef __cplusplus
+   extern "C" {
+#endif
+
+/*********************************************************************************************************************
+ * API Prototypes
+ ********************************************************************************************************************/
+
+/**
+ * @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
+ * @param instance ACMP instance number. <BR>
+ *                 Range:<BR> 0 - ACMP0<BR>
+ *                            1 - ACMP1<BR>
+ *                            2 - ACMP2<BR>
+ *                            3 - ACMP3 - Only applicable for XMC1400 devices <BR> 
+ *
+ * @param config Pointer to configuration data. Refer data structure @ref XMC_ACMP_CONFIG_t for settings.
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ *  Initializes an instance of analog comparator module.<BR>\n
+ *  Configures the ANACMP resister with hysteresis, comparator filter and inverted comparator output.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  None.
+ */
+void XMC_ACMP_Init(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_CONFIG_t *const config);
+
+/**
+ * @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
+ * @param instance ACMP instance number. <BR>
+ *                 Range:<BR> 0 - ACMP0<BR>
+ *                            1 - ACMP1<BR>
+ *                            2 - ACMP2<BR>
+ *                            3 - ACMP3 - Only applicable for XMC1400 devices <BR>
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Enables an instance of ACMP module.<BR>\n
+ * Starts the comparator by setting CMP_EN bit of respective ANACMP \a instance register. The \a instance number 
+ * determines which analog comparator to be switched on. Call this API after the successful completion of the comparator 
+ * initilization and input selection.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_ACMP_DisableComparator().<BR>
+ */
+__STATIC_INLINE void XMC_ACMP_EnableComparator(XMC_ACMP_t *const peripheral, uint32_t instance)
+{
+  XMC_ASSERT("XMC_ACMP_EnableComparator:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
+  XMC_ASSERT("XMC_ACMP_EnableComparator:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
+
+  peripheral->ANACMP[instance] |= (uint16_t)COMPARATOR_ANACMP0_CMP_EN_Msk;
+
+}
+
+
+/**
+ * @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
+ * @param instance ACMP instance number. <BR>
+ *                 Range:<BR> 0 - ACMP0<BR>
+ *                            1 - ACMP1<BR>
+ *                            2 - ACMP2<BR>
+ *                            3 - ACMP3 - Only applicable for XMC1400 devices <BR> 
+ * @return
+ *    None<BR>
+ * \par<b>Description:</b><br>
+ * Disables an instance of ACMP module.<BR>\n
+ * Stops the comparator by resetting CMP_EN bit of respective ANACMP \a instance register. The \a instance number 
+ * determines which analog comparator to be switched off.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_ACMP_EnableComparator().
+ */
+__STATIC_INLINE void XMC_ACMP_DisableComparator(XMC_ACMP_t *const peripheral, uint32_t instance)
+{
+  XMC_ASSERT("XMC_ACMP_DisableComparator:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
+  XMC_ASSERT("XMC_ACMP_DisableComparator:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
+
+  peripheral->ANACMP[instance] &= (uint16_t)(~((uint32_t)COMPARATOR_ANACMP0_CMP_EN_Msk));
+}
+
+/**
+ * @param None 
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Enables the reference divider for analog comparator instance 1.<BR>\n
+ * ACMP1 input INP is driven by an internal reference voltage by setting DIV_EN bit of ANACMP1 register.
+ * Other comparator instances can also share this reference divider option by calling the XMC_ACMP_SetInput() API.
+ * 
+ * \par<b>Related APIs:</b><br>
+ * XMC_ACMP_SetInput().
+ */
+__STATIC_INLINE void XMC_ACMP_EnableReferenceDivider(void)
+{
+  /* Enable the divider switch and connect the divided reference to ACMP1.INP */
+  COMPARATOR->ANACMP1 |= (uint16_t)(COMPARATOR_ANACMP1_REF_DIV_EN_Msk);
+}
+
+/**
+ * @param None 
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Disables the reference divider for analog comparator instance 1.<BR>\n
+ * ACMP1 input INP is disconnected from the reference divider. This is achieved by reseting DIV_EN bit of ANACMP1 
+ * register.
+ *
+ * \par<b>Related APIs:</b><br>
+ * None.
+ */
+__STATIC_INLINE void XMC_ACMP_DisableReferenceDivider(void)
+{
+  /* Disable the divider switch and use ACMP1.INP as standard port*/
+  COMPARATOR->ANACMP1 &= (uint16_t)(~(COMPARATOR_ANACMP1_REF_DIV_EN_Msk));
+}
+
+/**
+ * @param peripheral Constant pointer to analog comparator module, of @ref XMC_ACMP_t type. Use @ref XMC_ACMP0 macro.
+ * @param instance ACMP instance number. <BR>
+ *                 Range:<BR> 0 - ACMP0<BR>
+ *                            2 - ACMP2<BR>
+ *                            3 - ACMP3 - Only applicable for XMC1400 devices <BR> 
+ * @param source ACMP input source selection options.<BR>
+ *                 Range:<BR> XMC_ACMP_INP_SOURCE_STANDARD_PORT  - Input is connected to port<BR>
+ *                            XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT - Input is connected to port and ACMP1 INP <BR> 
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Sets the analog comparartor input selection for ACMP0, ACMP2 instances.<BR>\n
+ * Apart from ACMP1 instance, each ACMP instances can be connected to its own port and ACMP1 INP.
+ * Calling @ref XMC_ACMP_EnableReferenceDivider() API, after this API can share the reference divider to one of the 
+ * comparartor input as explained in the following options.<br>
+ * The hardware options to set input are listed below.<br>
+ * <OL>
+ * <LI>The comparator inputs aren't connected to other ACMP1 comparator inputs.</LI>
+ * <LI>Can program the comparator-0 to connect ACMP0.INP to ACMP1.INP in XMC1200 AA or XMC1300 AA</LI>
+ * <LI>Can program the comparator-0 to connect ACMP0.INN to ACMP1.INP in XMC1200 AB or XMC1300 AB or XMC1400 AA</LI>
+ * <LI>Can program the comparator-2 to connect ACMP2.INP to ACMP1.INP</LI>
+ * </OL><br>
+ * Directly accessed registers are ANACMP0, ANACMP2 according to the availability of instance in the devices.
+ *
+ * \par<b>Related APIs:</b><br>
+ * @ref XMC_ACMP_EnableReferenceDivider.<BR>
+ * @ref XMC_ACMP_DisableReferenceDivider. 
+ */
+void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_INP_SOURCE_t source);
+
+
+/**
+ * @param None
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Set the comparartors to operate in low power mode, by setting the LPWR bit of ANACMP0 register.<BR>\n
+ * The low power mode is controlled by ACMP0 instance. Low power mode is applicable for all instances of the
+ * comparator. In low power mode, blanking time will be introduced to ensure the stability of comparartor output. This 
+ * will slow down the comparator operation.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_ACMP_ClearLowPowerMode().
+ */
+__STATIC_INLINE void XMC_ACMP_SetLowPowerMode(void)
+{
+  COMPARATOR->ANACMP0 |= (uint16_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk;
+}
+
+/**
+ * @param None 
+ * @return
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Exits the low power mode by reseting LPWR bit of ANACMP0 register.<BR>\n
+ * The low power mode is controlled by ACMP0 module.  Low power mode is applicable for all instances of the
+ * comparator. To re-enable the low power mode, call the related API @ref XMC_ACMP_SetLowPowerMode().  
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_ACMP_SetLowPowerMode().
+ */
+__STATIC_INLINE void XMC_ACMP_ClearLowPowerMode(void)
+{
+  COMPARATOR->ANACMP0 &= (uint16_t)(~(uint16_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* If ACMP is available*/
+
+#endif /* XMC_ACMP_H */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_can.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_can.h
- * @date 2015-10-27
+ * @date 2016-06-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -57,6 +57,10 @@
  *
  * 2015-09-15:
  *     - Added "xmc_can_map.h" include <br>
+ *
+ * 2016-06-07:
+ *     - Added XMC_CAN_IsPanelControlReady()
+ *
  * <b>Details of use for node configuration related APIs</b><br>
  * Please use the XMC_CAN_NODE_SetInitBit() and XMC_CAN_NODE_EnableConfigurationChange() before calling node configuration
  * related APIs.
@@ -80,6 +84,8 @@
  * XMC_CAN_NODE_ResetInitBit(CAN_NODE0)
  * @endcode
  *
+ * 2016-06-20:
+ *     - Fixed bug in XMC_CAN_MO_Config() <br>  
  * @endcond
  *
  */
@@ -641,6 +647,25 @@ void XMC_CAN_Enable(XMC_CAN_t *const obj);
 
 void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num);
 
+/**
+ *
+ * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef
+ *       for details.
+ *
+ * @return Ready status of list controller
+ *
+ * \par<b>Description:</b><br>
+ *  Returns ready status of the list controller
+ *
+ * \par<b>Related APIs:</b><BR>
+ *  XMC_CAN_PanelControl()
+ *
+ */
+__STATIC_INLINE bool XMC_CAN_IsPanelControlReady(XMC_CAN_t *const obj)
+{
+  return (bool)((obj->PANCTR & (CAN_PANCTR_BUSY_Msk | CAN_PANCTR_RBUSY_Msk)) == 0);
+}
+
 /**
  *
  * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_can_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_can_map.h
- * @date 2015-10-27
+ * @date 2015-10-20
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
@@ -351,7 +351,17 @@
 #define CAN_NODE5_RXD_P8_0   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
 #endif
 
-#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC14)
+#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
+#define CAN_NODE0_RXD_P1_5   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
+#define CAN_NODE0_RXD_P14_3   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
+#define CAN_NODE0_RXD_P3_12   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
+#define CAN_NODE1_RXD_P2_6   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
+#define CAN_NODE1_RXD_P1_13   	XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
+#define CAN_NODE1_RXD_P1_4      XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
+#define CAN_NODE1_RXD_CAN0INS   XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
+#endif
+
+#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC43)|| (UC_SERIES == XMC14)
 #define CAN_MO0 ((CAN_MO_TypeDef *)&(CAN_MO->MO[0]))
 #define CAN_MO1 ((CAN_MO_TypeDef *)&(CAN_MO->MO[1]))
 #define CAN_MO2 ((CAN_MO_TypeDef *)&(CAN_MO->MO[2]))
@@ -387,7 +397,7 @@
 #endif
 
 
-#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)
+#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)|| (UC_SERIES == XMC43)
 #define CAN_MO32 ((CAN_MO_TypeDef *)&(CAN_MO->MO[32]))
 #define CAN_MO33 ((CAN_MO_TypeDef *)&(CAN_MO->MO[33]))
 #define CAN_MO34 ((CAN_MO_TypeDef *)&(CAN_MO->MO[34]))
@@ -420,6 +430,7 @@
 #define CAN_MO61 ((CAN_MO_TypeDef *)&(CAN_MO->MO[61]))
 #define CAN_MO62 ((CAN_MO_TypeDef *)&(CAN_MO->MO[62]))
 #define CAN_MO63 ((CAN_MO_TypeDef *)&(CAN_MO->MO[63]))
+#if (UC_SERIES != XMC43)
 #define CAN_MO64 ((CAN_MO_TypeDef *)&(CAN_MO->MO[64]))
 #define CAN_MO65 ((CAN_MO_TypeDef *)&(CAN_MO->MO[65]))
 #define CAN_MO66 ((CAN_MO_TypeDef *)&(CAN_MO->MO[66]))
@@ -613,5 +624,6 @@
 #define CAN_MO254 ((CAN_MO_TypeDef *)&(CAN_MO->MO[254]))
 #define CAN_MO255 ((CAN_MO_TypeDef *)&(CAN_MO->MO[255]))
 #endif
+#endif
 
 #endif /* XMC_CAN_MAP_H*/

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ccu4.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ccu4.h
- * @date 2015-10-27
+ * @date 2016-05-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -60,7 +60,14 @@
  *     - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and 
  *       XMC_CCU4_SLICE_DisableMultipleEvents() APIs.
  *     - DOC updates for the newly added APIs.
- * 
+ *
+ * 2016-03-09:
+ *     - Optimization of write only registers 
+ *
+ * 2016-05-20:
+ *     - Added XMC_CCU4_SLICE_StopClearTimer()
+ *     - Changed implementation of XMC_CCU4_SLICE_StopTimer() and XMC_CCU4_SLICE_ClearTimer() to avoid RMW access
+ *
  * @endcond
  */
 
@@ -1443,7 +1450,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t *const slice)
 __STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice)
 {
   XMC_ASSERT("XMC_CCU4_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
-  slice->TCCLR |= (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk;
+  slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk;
 }
 
 /**
@@ -1462,7 +1469,24 @@ __STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice)
 __STATIC_INLINE void XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t *const slice)
 {
   XMC_ASSERT("XMC_CCU4_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
-  slice->TCCLR |= (uint32_t) CCU4_CC4_TCCLR_TCC_Msk;
+  slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TCC_Msk;
+}
+
+/**
+ * @param slice Constant pointer to CC4 Slice
+ * @return <BR>
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Stops and resets the timer count to zero, by setting CC4yTCCLR.TCC and CC4yTCCLR.TRBC bit.\n\n
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_CCU4_SLICE_StartTimer().
+ */
+__STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice)
+{
+  XMC_ASSERT("XMC_CCU4_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
+  slice->TCCLR = CCU4_CC4_TCCLR_TRBC_Msk | CCU4_CC4_TCCLR_TCC_Msk;
 }
 
 /**
@@ -1682,7 +1706,7 @@ __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLIC
 __STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk)
 {
   XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module));
-  module->GCSS |= (uint32_t)shadow_transfer_msk;  
+  module->GCSS = (uint32_t)shadow_transfer_msk;  
 }
 
 /**

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ccu8.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ccu8.h
- * @date 2015-10-27
+ * @date 2016-05-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -75,6 +75,13 @@
  *       XMC_CCU8_SLICE_DisableMultipleEvents() APIs.
  *     - DOC updates for the newly added APIs.
  *
+ * 2016-03-09:
+ *     - Optimization of write only registers
+ *
+ * 2016-05-20:
+ *     - Added XMC_CCU8_SLICE_StopClearTimer()
+ *     - Changed XMC_CCU8_SLICE_StopTimer() and XMC_CCU8_SLICE_ClearTimer() 
+ *
  * @endcond
  */
 
@@ -1780,7 +1787,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_StartTimer(XMC_CCU8_SLICE_t *const slice)
 __STATIC_INLINE void XMC_CCU8_SLICE_StopTimer(XMC_CCU8_SLICE_t *const slice)
 {
   XMC_ASSERT("XMC_CCU8_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice));
-  slice->TCCLR |= (uint32_t) CCU8_CC8_TCCLR_TRBC_Msk;
+  slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TRBC_Msk;
 }
 
 /**
@@ -1799,7 +1806,24 @@ __STATIC_INLINE void XMC_CCU8_SLICE_StopTimer(XMC_CCU8_SLICE_t *const slice)
 __STATIC_INLINE void XMC_CCU8_SLICE_ClearTimer(XMC_CCU8_SLICE_t *const slice)
 {
   XMC_ASSERT("XMC_CCU8_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice));
-  slice->TCCLR |= (uint32_t) CCU8_CC8_TCCLR_TCC_Msk;
+  slice->TCCLR = (uint32_t) CCU8_CC8_TCCLR_TCC_Msk;
+}
+
+/**
+ * @param slice Constant pointer to CC8 Slice
+ * @return <BR>
+ *    None<BR>
+ *
+ * \par<b>Description:</b><br>
+ * Stops and resets the timer count to zero, by setting CC8yTCCLR.TCC and CC8yTCCLR.TRBC bit.\n\n
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_CCU8_SLICE_StartTimer().
+ */
+__STATIC_INLINE void XMC_CCU8_SLICE_StopClearTimer(XMC_CCU8_SLICE_t *const slice)
+{
+  XMC_ASSERT("XMC_CCU8_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice));
+  slice->TCCLR = CCU8_CC8_TCCLR_TRBC_Msk | CCU8_CC8_TCCLR_TCC_Msk;
 }
 
 /**
@@ -2056,7 +2080,7 @@ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice
 __STATIC_INLINE void XMC_CCU8_EnableShadowTransfer(XMC_CCU8_MODULE_t *const module, const uint32_t shadow_transfer_msk)
 {
   XMC_ASSERT("XMC_CCU8_EnableShadowTransfer:Invalid module Pointer", XMC_CCU8_IsValidModule(module));
-  module->GCSS |= (uint32_t)shadow_transfer_msk;  
+  module->GCSS = (uint32_t)shadow_transfer_msk;  
 }
 
 /**

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_common.h

@@ -1,36 +1,36 @@
 /**
  * @file xmc_common.h
- * @date 2015-10-27
+ * @date 2016-05-30
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
- * All rights reserved.
+ * All rights reserved.                        
- *
+ *                                             
- * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
- * following conditions are met:
+ * following conditions are met:   
- *
+ *                                                                              
- * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
- * disclaimer.
+ * disclaimer.                        
- *
+ * 
- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
- * disclaimer in the documentation and/or other materials provided with the distribution.
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
- *
+ * 
- * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
- * products derived from this software without specific prior written permission.
+ * products derived from this software without specific prior written permission.                                           
- *
+ *                                                                              
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
- * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
- *
+ *                                                                              
- * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
- * Infineon Technologies AG dave@infineon.com).
+ * Infineon Technologies AG dave@infineon.com).                                                          
  *********************************************************************************************************************
  *
  * Change History
@@ -41,7 +41,13 @@
  *     - Brief section updated
  *     - Added XMC_LIB_VERSION macro
  *
- * @endcond
+ * 2016-02-26:
+ *     - Updated XMC_LIB_VERSION macro to v2.1.6
+ *      
+ * 2016-05-30:
+ *     - Updated XMC_LIB_VERSION macro to v2.1.8
+ *
+ * @endcond 
  *
  */
 
@@ -62,7 +68,7 @@
 
 /**
  * @addtogroup COMMON
- * @brief Common APIs to all peripherals for XMC microcontroller family
+ * @brief Common APIs to all peripherals for XMC microcontroller family 
  * @{
  */
 
@@ -70,9 +76,9 @@
  * MACROS
  *********************************************************************************************************************/
 #define XMC_LIB_MAJOR_VERSION	(2U)
-#define XMC_LIB_MINOR_VERSION	(0U)
+#define XMC_LIB_MINOR_VERSION	(1U)
-#define XMC_LIB_PATCH_VERSION	(2U)
+#define XMC_LIB_PATCH_VERSION	(8U)
-
+ 
 #define XMC_LIB_VERSION         ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION)
 
 /* Define WEAK attribute */
@@ -124,7 +130,7 @@ XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)};
 /*
  *
  */
-typedef struct XMC_DRIVER_VERSION
+typedef struct XMC_DRIVER_VERSION 
 {
   uint8_t major;
   uint8_t minor;

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_dac.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_dac.h
- * @date 2015-10-27
+ * @date 2015-08-31
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_device.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_device.h
- * @date 2015-10-27
+ * @date 2016-07-21
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -42,6 +42,17 @@
  * 2015-09-23:
  *     - Added XMC14 and XMC48/47
  *
+ * 2015-11-19:
+ *     - Added XMC43
+ *
+ * 2016-02-26:
+ *     - Fixed CCU8 version for XMC43/47/48
+ *
+ * 2016-06-14:
+ *     - Added XMC1201_T028x0016, XMC1202_T016x0064, XMC1301_T016x0032, XMC1302_Q040x0200, 
+ *             XMC1302_T028x0016, XMC1402_T038x0032, XMC1402_T038x0064, XMC1402_T038x0128, 
+ *             XMC1403_Q040x0064, XMC1403_Q040x0128, XMC1403_Q040x0200, XMC1402_T038x0200
+ *             XMC1402_Q040x0200, XMC1402_Q048x0200, XMC1201_T028x0032
  * @endcond 
  *
  */
@@ -58,6 +69,7 @@
 #define    XMC47      (47)
 #define    XMC45      (45)
 #define    XMC44      (44)
+#define    XMC43      (43)
 #define    XMC42      (42)
 #define    XMC41      (41)
 #define    XMC14      (14)
@@ -73,6 +85,7 @@
 #define    XMC4504    (4504)
 #define    XMC4400    (4400)
 #define    XMC4402    (4402)
+#define    XMC4300    (4300)
 #define    XMC4200    (4200)
 #define    XMC4100    (4100)
 #define    XMC4104    (4104)
@@ -113,7 +126,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F144x2048)
 #define UC_FAMILY    XMC4
@@ -123,7 +136,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F100x2048)
 #define UC_FAMILY    XMC4
@@ -133,7 +146,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_E196x1536)
 #define UC_FAMILY    XMC4
@@ -143,7 +156,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F144x1536)
 #define UC_FAMILY    XMC4
@@ -153,7 +166,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F100x1536)
 #define UC_FAMILY    XMC4
@@ -163,7 +176,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_E196x1024)
 #define UC_FAMILY    XMC4
@@ -173,7 +186,7 @@
 #define UC_FLASH     (1024UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F144x1024)
 #define UC_FAMILY    XMC4
@@ -183,7 +196,7 @@
 #define UC_FLASH     (1024UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4800_F100x1024)
 #define UC_FAMILY    XMC4
@@ -193,7 +206,7 @@
 #define UC_FLASH     (1024UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_E196x2048)
 #define UC_FAMILY    XMC4
@@ -203,7 +216,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_F144x2048)
 #define UC_FAMILY    XMC4
@@ -213,7 +226,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_F100x2048)
 #define UC_FAMILY    XMC4
@@ -223,7 +236,7 @@
 #define UC_FLASH     (2048UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_E196x1536)
 #define UC_FAMILY    XMC4
@@ -233,7 +246,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_F144x1536)
 #define UC_FAMILY    XMC4
@@ -243,7 +256,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4700_F100x1536)
 #define UC_FAMILY    XMC4
@@ -253,7 +266,7 @@
 #define UC_FLASH     (1536UL)
 #define MULTICAN_PLUS
 #define CCU4V2
-#define CCU8V1
+#define CCU8V2
 
 #elif defined(XMC4500_E144x1024)
 #define UC_FAMILY    XMC4
@@ -381,6 +394,16 @@
 #define CCU4V1
 #define CCU8V1
 
+#elif defined(XMC4300_F100x256)	
+#define UC_FAMILY    XMC4
+#define UC_SERIES    XMC43
+#define UC_DEVICE    XMC4300
+#define UC_PACKAGE   LQFP100
+#define UC_FLASH     (256UL)
+#define MULTICAN_PLUS
+#define CCU4V2
+#define CCU8V2
+
 #elif defined(XMC4200_E64x256) 	
 #define UC_FAMILY    XMC4
 #define UC_SERIES    XMC42
@@ -699,6 +722,22 @@
 #define UC_FLASH     (200UL)
 #define CCU4V2
 
+#elif defined(XMC1201_T028x0032)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC12
+#define UC_DEVICE    XMC1201
+#define UC_PACKAGE   TSSOP28
+#define UC_FLASH     (32UL)
+#define CCU4V2
+
+#elif defined(XMC1201_T028x0016)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC12
+#define UC_DEVICE    XMC1201
+#define UC_PACKAGE   TSSOP28
+#define UC_FLASH     (16UL)
+#define CCU4V2
+
 #elif defined(XMC1202_Q024x0016)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC12
@@ -747,6 +786,14 @@
 #define UC_FLASH     (32UL)
 #define CCU4V2
 
+#elif defined(XMC1202_T016x0064)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC12
+#define UC_DEVICE    XMC1202
+#define UC_PACKAGE   TSSOP16
+#define UC_FLASH     (64UL)
+#define CCU4V2
+
 #elif defined(XMC1202_T028x0016)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC12
@@ -842,6 +889,15 @@
 #define CCU4V2
 #define CCU8V2
 
+#elif defined(XMC1301_T016x0032)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC13
+#define UC_DEVICE    XMC1301
+#define UC_PACKAGE   TSSOP16
+#define UC_FLASH     (32UL)
+#define CCU4V2
+#define CCU8V2
+
 #elif defined(XMC1301_T038x0008)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC13
@@ -939,6 +995,15 @@
 #define CCU4V2
 #define CCU8V2
 
+#elif defined(XMC1302_Q040x0200)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC13
+#define UC_DEVICE    XMC1302
+#define UC_PACKAGE   VQFN40
+#define UC_FLASH     (200UL)
+#define CCU4V2
+#define CCU8V2
+
 #elif defined(XMC1302_T038x0016)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC13
@@ -984,6 +1049,15 @@
 #define CCU4V2
 #define CCU8V2
 
+#elif defined(XMC1302_T028x0016)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC13
+#define UC_DEVICE    XMC1302
+#define UC_PACKAGE   TSSOP28
+#define UC_FLASH     (16UL)
+#define CCU4V2
+#define CCU8V2
+
 #elif defined(XMC1302_T016x0008)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC13
@@ -1043,6 +1117,42 @@
 #define UC_FLASH     (128UL)
 #define CCU4V3
 
+#elif defined(XMC1402_T038x0032)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   TSSOP38
+#define UC_FLASH     (32UL)
+#define CCU4V3
+#define CCU8V3
+
+#elif defined(XMC1402_T038x0064)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   TSSOP38
+#define UC_FLASH     (64UL)
+#define CCU4V3
+#define CCU8V3
+
+#elif defined(XMC1402_T038x0128)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   TSSOP38
+#define UC_FLASH     (128UL)
+#define CCU4V3
+#define CCU8V3
+
+#elif defined(XMC1402_T038x0200)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   TSSOP38
+#define UC_FLASH     (200UL)
+#define CCU4V3
+#define CCU8V3
+
 #elif defined(XMC1402_Q040x0032)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC14
@@ -1070,6 +1180,15 @@
 #define CCU4V3
 #define CCU8V3
 
+#elif defined(XMC1402_Q040x0200)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   VQFN40
+#define UC_FLASH     (200UL)
+#define CCU4V3
+#define CCU8V3
+
 #elif defined(XMC1402_Q048x0032)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC14
@@ -1097,6 +1216,15 @@
 #define CCU4V3
 #define CCU8V3
 
+#elif defined(XMC1402_Q048x0200)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1402
+#define UC_PACKAGE   VQFN48
+#define UC_FLASH     (200UL)
+#define CCU4V3
+#define CCU8V3
+
 #elif defined(XMC1402_Q064x0064)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC14
@@ -1179,6 +1307,33 @@
 #define MULTICAN_PLUS
 #define CCU4V3
 
+#elif defined(XMC1403_Q040x0064)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1403
+#define UC_PACKAGE   VQFN40
+#define UC_FLASH     (64UL)
+#define MULTICAN_PLUS
+#define CCU4V3
+
+#elif defined(XMC1403_Q040x0128)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1403
+#define UC_PACKAGE   VQFN40
+#define UC_FLASH     (128UL)
+#define MULTICAN_PLUS
+#define CCU4V3
+
+#elif defined(XMC1403_Q040x0200)
+#define UC_FAMILY    XMC1
+#define UC_SERIES    XMC14
+#define UC_DEVICE    XMC1403
+#define UC_PACKAGE   VQFN40
+#define UC_FLASH     (200UL)
+#define MULTICAN_PLUS
+#define CCU4V3
+
 #elif defined(XMC1403_Q064x0064)
 #define UC_FAMILY    XMC1
 #define UC_SERIES    XMC14
@@ -1303,11 +1458,19 @@
 #if UC_SERIES == XMC45
 #include "XMC4500.h"
 #define PERIPHERAL_RESET_SUPPORTED
+#define USB_OTG_SUPPORTED
 
 #elif UC_SERIES == XMC44
 #include "XMC4400.h"
 #define CLOCK_GATING_SUPPORTED
 #define PERIPHERAL_RESET_SUPPORTED
+#define USB_OTG_SUPPORTED
+
+#elif UC_SERIES == XMC43
+#include "XMC4300.h"
+#define CLOCK_GATING_SUPPORTED
+#define PERIPHERAL_RESET_SUPPORTED
+#define USB_OTG_SUPPORTED
 
 #elif UC_SERIES == XMC42
 #include "XMC4200.h"
@@ -1323,11 +1486,13 @@
 #include "XMC4700.h"
 #define CLOCK_GATING_SUPPORTED
 #define PERIPHERAL_RESET_SUPPORTED
+#define USB_OTG_SUPPORTED
 
 #elif UC_SERIES == XMC48
 #include "XMC4800.h"
 #define CLOCK_GATING_SUPPORTED
 #define PERIPHERAL_RESET_SUPPORTED
+#define USB_OTG_SUPPORTED
 
 #elif UC_SERIES == XMC11
 #include "XMC1100.h"

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_dma.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_dma.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_dma_map.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_dma_map.h
- * @date 2015-10-27
+ * @date 2015-05-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_dsd.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_dsd.h
- * @date 2015-10-27
+ * @date 2015-09-18
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ebu.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ebu.h
- * @date 2015-10-27
+ * @date 2016-03-30
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -38,7 +38,10 @@
  *
  * 2015-06-20:
  *     - Initial
- *     - Description of changes 2
+ *
+ * 2016-03-30:
+ *     - Added ebu_data_hold_cycles_for_read_accesses to XMC_EBU_BUS_READ_CONFIG_t
+ *     - Added ebu_device_addressing_mode and ebu_data_hold_cycles_for_write_accesses to XMC_EBU_BUS_WRITE_CONFIG_t
  *      
  * @endcond 
  *
@@ -625,7 +628,10 @@ typedef struct XMC_EBU_BUS_READ_CONFIG
   	   * 11111B:  31 wait states                   <br>
        */
   	  uint32_t ebu_programmed_wait_states_for_read_accesses  : 5;
-  	  uint32_t                                               : 4;
+  	  /**
+  	   *
+  	   */
+  	  uint32_t ebu_data_hold_cycles_for_read_accesses: 4;
   	  /**
        * Frequency of external clock at pin BFCLKO
        */
@@ -688,7 +694,7 @@ typedef struct XMC_EBU_BUS_WRITE_CONFIG
 	    uint32_t                                               : 1;
 	    uint32_t ebu_wait_signal_polarity                      : 1;  /**< Reversed polarity at WAIT */
 	    uint32_t ebu_byte_control                              : 2;  /**< Byte control signal control */
-	    uint32_t                                               : 2;
+      uint32_t ebu_device_addressing_mode                    : 2; /**< Device addressing mode */
 	    uint32_t ebu_wait_control                              : 2;  /**< External wait control */
 	    uint32_t ebu_asynchronous_address_phase                : 1;  /**< Asynchronous address phase */
 	    uint32_t ebu_lock_chip_select                          : 1;  /**< Lock chip select */
@@ -731,7 +737,11 @@ typedef struct XMC_EBU_BUS_WRITE_CONFIG
  	     * 11111B:  31 wait states                    <br>
       */
  	    uint32_t ebu_programmed_wait_states_for_write_accesses : 5;
- 	    uint32_t                                               : 4;
+
+ 	    /**
+ 	     *
+ 	     */
+ 	    uint32_t ebu_data_hold_cycles_for_write_accesses : 4;
  	    /**<
        * Frequency of external clock at pin BFCLKO
        */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ecat.h

@@ -0,0 +1,462 @@
+
+/**
+ * @file xmc_ecat.h
+ * @date 2015-12-27
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-12-27:
+ *     - Initial Version<br>
+ *
+ * @endcond
+ */
+
+/**
+ * @addtogroup XMClib XMC Peripheral Library
+ * @{
+ */
+
+/**
+ * @addtogroup ECAT
+ * @brief EtherCAT Low level driver for XMC4800/XMC4300 series.
+ *
+ * EtherCAT is an Ethernet-based fieldbus system.
+ * The EtherCAT Slave Controller (ECAT) read the data addressed to them while the telegram passes through the device.
+ * An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the EtherCAT
+ * fieldbus and the slave application. EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard network
+ * controller can be used and no special hardware is required on master side. EtherCAT has a reserved EtherType of
+ * 0x88A4 that distinguishes it from other Ethernet frames. Thus, EtherCAT can run in parallel to other Ethernet
+ * protocols. EtherCAT does not require the IP protocol, however it can be encapsulated in IP/UDP. The EtherCAT
+ * Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor
+ * power.
+ *
+ * The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral. 
+ * For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending
+ * upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and
+ * basic functionalities.
+ * @{
+ */
+
+#ifndef XMC_ECAT_H
+#define XMC_ECAT_H
+
+/**********************************************************************************************************************
+ * HEADER FILES
+ *********************************************************************************************************************/
+
+#include "xmc_common.h"
+
+#if defined (ECAT0)
+
+#include "xmc_ecat_map.h"
+
+/**********************************************************************************************************************
+ * MACROS
+ *********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * ENUMS
+ *********************************************************************************************************************/
+
+/**
+ * ECAT status return values
+ */
+typedef enum XMC_ECAT_STATUS
+{
+  XMC_ECAT_STATUS_OK    = 0U, /**< Driver accepted application request */
+  XMC_ECAT_STATUS_BUSY  = 1U, /**< Driver is busy and cannot handle request */
+  XMC_ECAT_STATUS_ERROR = 2U  /**< Driver could not fulfil application request */
+} XMC_ECAT_STATUS_t;
+
+/**
+ * EtherCAT event enumeration types
+ */
+typedef enum XMC_ECAT_EVENT
+{
+  XMC_ECAT_EVENT_AL_CONTROL = ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk, /**< Application control event mask */
+  XMC_ECAT_EVENT_DC_LATCH = ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk,  /**< Distributed Clock latch event mask */
+  XMC_ECAT_EVENT_DC_SYNC0 = ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk, /**< State of distributed clock sync-0 event mask */
+  XMC_ECAT_EVENT_DC_SYNC1 = ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk, /**< State of distributed clock sync-1 event mask */
+  XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER = ECAT_AL_EVENT_MASK_SM_A_MASK_Msk, /**< SyncManager activation register mask*/
+  XMC_ECAT_EVENT_EEPROM = ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk, /**< EEPROM Emulation event mask*/
+  XMC_ECAT_EVENT_WATCHDOG = ECAT_AL_EVENT_MASK_WP_D_MASK_Msk, /**< WATCHDOG process data event mask*/
+  XMC_ECAT_EVENT_SM0 = ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk, /**< Sync Manager 0 event mask*/
+  XMC_ECAT_EVENT_SM1 = ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk, /**< Sync Manager 1 event mask*/
+  XMC_ECAT_EVENT_SM2 = ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk, /**< Sync Manager 2 event mask*/
+  XMC_ECAT_EVENT_SM3 = ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk, /**< Sync Manager 3 event mask*/
+  XMC_ECAT_EVENT_SM4 = ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk, /**< Sync Manager 4 event mask*/
+  XMC_ECAT_EVENT_SM5 = ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk, /**< Sync Manager 5 event mask*/
+  XMC_ECAT_EVENT_SM6 = ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk, /**< Sync Manager 6 event mask*/
+  XMC_ECAT_EVENT_SM7 = ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk  /**< Sync Manager 7 event mask*/
+} XMC_ECAT_EVENT_t;
+
+/**********************************************************************************************************************
+ * DATA STRUCTURES
+ *********************************************************************************************************************/
+
+/* Anonymous structure/union guard start */
+#if defined (__CC_ARM)
+#pragma push
+#pragma anon_unions
+#elif defined (__TASKING__)
+#pragma warning 586
+#endif
+
+/**
+ * ECAT port control data structure
+ */
+typedef struct XMC_ECAT_PORT_CTRL
+{
+  union 
+  {
+    struct
+    {
+      uint32_t enable_rstreq: 1;     /**< Master can trigger a reset of the XMC4700 / XMC4800 (::bool) */
+      uint32_t: 7;                   /**< Reserved bits */
+      uint32_t latch_input0: 2;      /**< Latch input 0 selection (::XMC_ECAT_PORT_LATCHIN0_t) */
+      uint32_t: 2;                   /**< Reserved bits */
+      uint32_t latch_input1: 2;      /**< Latch input 1 selection (::XMC_ECAT_PORT_LATCHIN1_t) */
+      uint32_t: 2;                   /**< Reserved bits */
+      uint32_t phyaddr_offset: 5;    /**< Ethernet PHY address offset, address of port 0 */
+      uint32_t: 1;                   /**< Reserved bits */
+      uint32_t mdio: 2;              /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */
+      uint32_t: 8;                   /**< Reserved bits */
+    };
+
+    uint32_t raw;
+  } common;
+
+  union 
+  {  
+    struct
+    {
+      uint32_t rxd0: 2;     /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */
+      uint32_t rxd1: 2;     /**< Receive data bit 1 (::XMC_ECAT_PORT0_CTRL_RXD1_t) */
+      uint32_t rxd2: 2;     /**< Receive data bit 2 (::XMC_ECAT_PORT0_CTRL_RXD2_t) */
+      uint32_t rxd3: 2;     /**< Receive data bit 3 (::XMC_ECAT_PORT0_CTRL_RXD3_t) */
+      uint32_t rx_err: 2;   /**< RX Error (::XMC_ECAT_PORT0_CTRL_RX_ERR_t) */
+      uint32_t rx_dv: 2;    /**< RX Data valid (::XMC_ECAT_PORT0_CTRL_RX_DV_t) */
+      uint32_t rx_clk: 2;   /**< RX Clock (::XMC_ECAT_PORT0_CTRL_RX_CLK_t) */
+      uint32_t: 2;          /**< Reserved bits */
+      uint32_t link: 2;     /**< Link status (::XMC_ECAT_PORT0_CTRL_LINK_t) */
+      uint32_t: 10;         /**< Reserved bits */
+      uint32_t tx_clk: 2;   /**< TX Clock (::XMC_ECAT_PORT0_CTRL_TX_CLK_t) */
+      uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT0_CTRL_TX_SHIFT_t) */
+    };
+
+    uint32_t raw;
+  } port0;
+
+  union 
+  {      
+    struct
+    {
+      uint32_t rxd0: 2;     /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */
+      uint32_t rxd1: 2;     /**< Receive data bit 1 (::XMC_ECAT_PORT_CTRL_RXD1_t) */
+      uint32_t rxd2: 2;     /**< Receive data bit 2 (::XMC_ECAT_PORT_CTRL_RXD2_t) */
+      uint32_t rxd3: 2;     /**< Receive data bit 3 (::XMC_ECAT_PORT_CTRL_RXD3_t) */
+      uint32_t rx_err: 2;   /**< RX Error (::XMC_ECAT_PORT_CTRL_RX_ERR_t) */
+      uint32_t rx_dv: 2;    /**< RX Data valid (::XMC_ECAT_PORT_CTRL_RX_DV_t) */
+      uint32_t rx_clk: 2;   /**< RX Clock (::XMC_ECAT_PORT_CTRL_RX_CLK_t) */
+      uint32_t: 2;          /**< Reserved bits */
+      uint32_t link: 2;     /**< Link status (::XMC_ECAT_PORT_CTRL_LINK_t) */
+      uint32_t: 10;         /**< Reserved bits */
+      uint32_t tx_clk: 2;   /**< TX Clock (::XMC_ECAT_PORT_CTRL_TX_CLK_t) */
+      uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT1_CTRL_TX_SHIFT_t) */
+    };
+
+    uint32_t raw;
+  } port1;
+  
+} XMC_ECAT_PORT_CTRL_t;
+
+/**
+ * ECAT EEPROM configuration area data structure
+ */
+typedef union XMC_ECAT_CONFIG
+{
+  struct
+  {
+    uint32_t : 8;
+
+    uint32_t : 2;
+    uint32_t enable_dc_sync_out : 1;
+    uint32_t enable_dc_latch_in : 1;
+    uint32_t enable_enhanced_link_p0 : 1;
+    uint32_t enable_enhanced_link_p1 : 1;
+    uint32_t : 2;
+
+    uint32_t : 16;
+
+    uint16_t sync_pulse_length; /**< Initialization value for Pulse Length of SYNC Signals register*/
+
+    uint32_t : 16;
+
+    uint16_t station_alias; /**< Initialization value for Configured Station Alias Address register */
+
+    uint16_t : 16;
+
+    uint16_t : 16;
+
+    uint16_t checksum;
+  };
+
+  uint32_t dword[4]; /**< Four 32 bit double word equivalent to 8 16 bit configuration area word. */
+} XMC_ECAT_CONFIG_t;
+
+/* Anonymous structure/union guard end */
+#if defined (__CC_ARM)
+#pragma pop
+#elif defined (__TASKING__)
+#pragma warning restore
+#endif
+
+/**********************************************************************************************************************
+ * API PROTOTYPES
+ *********************************************************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @param config XMC_ECAT_CONFIG_t
+ * @return XMC_ECAT_STATUS_t ECAT Initialization status
+ *
+ * \par<b>Description: </b><br>
+ * Initialize the Ethernet MAC peripheral <br>
+ *
+ * \par
+ * The function sets the link speed, applies the duplex mode, sets auto-negotiation
+ * and loop-back settings.
+ */
+void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config);
+
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enable the EtherCAT peripheral <br>
+ *
+ * \par
+ * The function de-asserts the peripheral reset.
+ */
+void XMC_ECAT_Enable(void);
+
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Disable the EtherCAT peripheral <br>
+ *
+ * \par
+ * The function asserts the peripheral reset.
+ */
+void XMC_ECAT_Disable(void);
+
+/**
+ * @param phy_addr PHY address
+ * @param reg_addr Register address
+ * @param data The destination to which the read data needs to be copied to.
+ *
+ * @return XMC_ECAT_STATUS_t EtherCAT Read PHY API return status
+ *
+ * \par<b>Description: </b><br>
+ * Read a PHY register <br>
+ *
+ * \par
+ * The function reads a PHY register. It essentially polls busy bit during max
+ * PHY_TIMEOUT time and reads the information into 'data' when not busy.
+ */
+XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
+
+/**
+ * @param phy_addr PHY address
+ * @param reg_addr Register address
+ * @param data The data to write
+ * @return XMC_ECAT_STATUS_t EtherCAT Write PHY API return status
+ *
+ * \par<b>Description: </b><br>
+ * Write a PHY register <br>
+ *
+ * \par
+ * The function reads a PHY register. It essentially writes the data and polls
+ * the busy bit until it is no longer busy.
+ */
+XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
+
+/**
+ * @param port_ctrl Port control configuration
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Set port control configuration <br>
+ *
+ * \par
+ * The function sets the port control by writing the configuration into the ECAT CON register.
+ *
+ */
+__STATIC_INLINE void XMC_ECAT_SetPortControl(const XMC_ECAT_PORT_CTRL_t port_ctrl)
+{
+  ECAT0_CON->CON = (uint32_t)port_ctrl.common.raw;
+  ECAT0_CON->CONP0 = (uint32_t)port_ctrl.port0.raw;
+  ECAT0_CON->CONP1 = (uint32_t)port_ctrl.port1.raw;
+}
+
+/**
+ * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enable ECAT event(s) <br>
+ *
+ * \par
+ * The function can be used to enable ECAT event(s).
+ */
+void XMC_ECAT_EnableEvent(uint32_t event);
+
+/**
+ * @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Disable an ECAT event(s) <br>
+ *
+ * \par
+ * The function can be used to disable ECAT event(s).
+ */
+void XMC_ECAT_DisableEvent(uint32_t event);
+
+/**
+ * @param None
+ * @return uint32_t Event status
+ *
+ * \par<b>Description: </b><br>
+ * Get event status <br>
+ *
+ * \par
+ * The function returns the ECAT status and interrupt status as a single word. The user
+ * can then check the status of the events by using an appropriate mask.
+ */
+uint32_t XMC_ECAT_GetEventStatus(void);
+
+
+/**
+ * @param channel SyncManager channel number.
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Disables selected SyncManager channel <br>
+ *
+ * \par
+ * Sets bit 0 of the corresponding 0x807 register.
+ */
+void XMC_ECAT_DisableSyncManChannel(const uint8_t channel);
+
+/**
+ * @param channel SyncManager channel number.
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enables selected SyncManager channel <br>
+ *
+ * \par
+ * Resets bit 0 of the corresponding 0x807 register.
+ */
+void XMC_ECAT_EnableSyncManChannel(const uint8_t channel);
+
+/**
+ * @param None
+ * @return uint16_t Content of register 0x220-0x221
+ *
+ * \par<b>Description: </b><br>
+ * Get content of AL event register <br>
+ *
+ * \par
+ * Get the first two bytes of the AL Event register (0x220-0x221).
+ */
+__STATIC_INLINE uint16_t XMC_ECAT_GetALEventRegister(void)
+{
+  return ((uint16_t)ECAT0->AL_EVENT_REQ);
+}
+
+/**
+ * @param None
+ * @return uint16_t Content of register 0x220-0x221
+ *
+ * \par<b>Description: </b><br>
+ * Get content of AL event register <br>
+ *
+ * \par
+ * Get the first two bytes of the AL Event register (0x220-0x221).
+ */
+__STATIC_INLINE uint16_t XMC_ECAT_GetALEventMask(void)
+{
+  return ((uint16_t)ECAT0->AL_EVENT_MASK);
+}
+
+/**
+ * @param intMask Interrupt mask (disabled interrupt shall be zero)
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Sets application event mask register <br>
+ *
+ * \par
+ * Performs a logical OR with the AL Event Mask register (0x0204 : 0x0205).
+ */
+__STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask)
+{
+  ECAT0->AL_EVENT_MASK |= (uint32_t)(intMask);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+ 
+/**
+ * @}
+ */
+ 
+/**
+ * @}
+ */
+ 
+#endif /* defined (ECAT) */
+
+#endif /* XMC_ECAT_H */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ecat_map.h

@@ -0,0 +1,287 @@
+/**
+ * @file xmc_ecat_map.h
+ * @date 2016-07-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-09-09:
+ *     - Initial
+ *
+ * 2015-07-20:
+ *     - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1
+ *
+ * @endcond
+ */
+
+#ifndef XMC_ECAT_MAP_H
+#define XMC_ECAT_MAP_H
+
+/**
+ * ECAT PORT 0 receive data 0 line
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RXD0
+{
+  XMC_ECAT_PORT0_CTRL_RXD0_P1_4  = 0U, /**< RXD0A receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD0_P5_0  = 1U, /**< RXD0B receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD0_P7_4  = 2U, /**< RXD0C receive data line */
+} XMC_ECAT_PORT0_CTRL_RXD0_t;
+
+/**
+ * ECAT PORT 0 receive data 1 line
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RXD1
+{
+  XMC_ECAT_PORT0_CTRL_RXD1_P1_5  = 0U, /**< RXD1A receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD1_P5_1  = 1U, /**< RXD1B receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD1_P7_5  = 2U, /**< RXD1C receive data line */
+} XMC_ECAT_PORT0_CTRL_RXD1_t;
+
+/**
+ * ECAT PORT 0 receive data 2 line
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RXD2
+{
+  XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD2_P5_2  = 1U, /**< RXD2B receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD2_P7_6  = 2U  /**< RXD2C receive data line */
+} XMC_ECAT_PORT0_CTRL_RXD2_t;
+
+/**
+ * ECAT PORT 0 receive data 3 line
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RXD3
+{
+  XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD3_P5_7  = 1U, /**< RXD3B Receive data line */
+  XMC_ECAT_PORT0_CTRL_RXD3_P7_7  = 2U  /**< RXD3C Receive data line */
+} XMC_ECAT_PORT0_CTRL_RXD3_t;
+
+/**
+ * ECAT PORT 0 receive error line
+ */
+typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR
+{
+  XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0  = 0U, /**< RX_ERRA Receive error line */
+  XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6  = 1U, /**< RX_ERRB Receive error line */
+  XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9  = 2U  /**< RX_ERRC Receive error line */
+} XMC_ECAT_PORT0_CTRL_RX_ERR_t;
+
+/**
+ * ECAT PORT 0 receive clock line
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK
+{
+  XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1  = 0U, /**< RX_CLKA Recevive clock */
+  XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4  = 1U, /**< RX_CLKB Recevive clock */
+  XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */
+} XMC_ECAT_PORT0_CTRL_RX_CLK_t;
+
+/**
+ * ECAT PORT 0 data valid
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_RX_DV
+{
+  XMC_ECAT_PORT0_CTRL_RX_DV_P1_9  = 0U, /**< RX_DVA Receive data valid */
+  XMC_ECAT_PORT0_CTRL_RX_DV_P5_6  = 1U, /**< RX_DVB Receive data valid */
+  XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */
+} XMC_ECAT_PORT0_CTRL_RX_DV_t;
+
+/**
+ * ECAT PORT 0 link status
+ */
+typedef enum XMC_ECAT_PORT0_CTRL_LINK
+{
+  XMC_ECAT_PORT0_CTRL_LINK_P4_1  = 0U, /**< LINKA Link status */
+  XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */
+  XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */
+} XMC_ECAT_PORT0_CTRL_LINK_t;
+
+/**
+ * ECAT PORT 0 transmit clock
+ */ 
+typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK
+{
+  XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0  = 0U,  /**< TX_CLKA transmit clock */
+  XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5  = 1U,  /**< TX_CLKB transmit clock */
+  XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1  = 2U,  /**< TX_CLKC transmit clock */
+} XMC_ECAT_PORT0_CTRL_TX_CLK_t;
+
+/**
+ * ECAT PORT 1 receive data 0 line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RXD0
+{
+  XMC_ECAT_PORT1_CTRL_RXD0_P0_11  = 0U, /**< RXD0A receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD0_P14_7  = 1U, /**< RXD0B receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD0_P8_4   = 2U, /**< RXD0C receive data line */
+} XMC_ECAT_PORT1_CTRL_RXD0_t;
+
+/**
+ * ECAT PORT 1 receive data 1 line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RXD1
+{
+  XMC_ECAT_PORT1_CTRL_RXD1_P0_6   = 0U, /**< RXD1A receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD1_P8_5   = 2U, /**< RXD1C receive data line */
+} XMC_ECAT_PORT1_CTRL_RXD1_t;
+
+/**
+ * ECAT PORT 1 receive data 2 line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RXD2
+{
+  XMC_ECAT_PORT1_CTRL_RXD2_P0_5   = 0U, /**< RXD2A receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD2_P8_6   = 2U  /**< RXD2C receive data line */
+} XMC_ECAT_PORT1_CTRL_RXD2_t;
+
+/**
+ * ECAT PORT 1 receive data 3 line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RXD3
+{
+  XMC_ECAT_PORT1_CTRL_RXD3_P0_4   = 0U, /**< RXD3A Receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */
+  XMC_ECAT_PORT1_CTRL_RXD3_P8_7   = 2U  /**< RXD3C Receive data line */
+} XMC_ECAT_PORT1_CTRL_RXD3_t;
+
+/**
+ * ECAT PORT 1 receive error line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR
+{
+  XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5  = 0U, /**< RX_ERRA Receive error line */
+  XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */
+  XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9  = 2U  /**< RX_ERRC Receive error line */
+} XMC_ECAT_PORT1_CTRL_RX_ERR_t;
+
+/**
+ * ECAT PORT 1 receive clock line
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK
+{
+  XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1  = 0U, /**< RX_CLKA Recevive clock */
+  XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */
+  XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */
+} XMC_ECAT_PORT1_CTRL_RX_CLK_t;
+
+/**
+ * ECAT PORT 1 data valid
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_RX_DV
+{
+  XMC_ECAT_PORT1_CTRL_RX_DV_P0_9   = 0U, /**< RX_DVA Receive data valid */
+  XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */
+  XMC_ECAT_PORT1_CTRL_RX_DV_P8_11  = 2U, /**< RX_DVC Receive data valid */
+} XMC_ECAT_PORT1_CTRL_RX_DV_t;
+
+/**
+ * ECAT PORT 0 link status
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_LINK
+{
+  XMC_ECAT_PORT1_CTRL_LINK_P3_4  = 0U, /**< LINKA Link status */
+  XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */
+  XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */
+} XMC_ECAT_PORT1_CTRL_LINK_t;
+
+/**
+ * ECAT PORT 1 transmit clock
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK
+{
+  XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U,  /**< TX_CLKA transmit clock */
+  XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9  = 1U,  /**< TX_CLKB transmit clock */
+  XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0  = 2U,  /**< TX_CLKC transmit clock */
+} XMC_ECAT_PORT1_CTRL_TX_CLK_t;
+
+/**
+ * ECAT management data I/O
+ */ 
+typedef enum XMC_ECAT_PORT_CTRL_MDIO
+{
+  XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */
+  XMC_ECAT_PORT_CTRL_MDIO_P4_2  = 1U, /**< MDIOB management data I/O */
+  XMC_ECAT_PORT_CTRL_MDIO_P9_7  = 2U  /**< MDIOC management data I/O */
+} XMC_ECAT_PORT_CTRL_MDIO_t;
+
+/**
+ * ECAT latch 0
+ */
+typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0
+{
+  XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5 = 0U, /**< LATCH0A line */
+  XMC_ECAT_PORT_CTRL_LATCHIN0_9_0   = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */
+  XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0   = 1U, /**< LATCH0B line */
+  XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0   = 2U, /**< LATCH0C line */
+  XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0   = 3U, /**< LATCH0D line */  
+} XMC_ECAT_PORT_CTRL_LATCHIN0_t;
+
+/**
+ * ECAT latch 1
+ */
+typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1
+{
+  XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4 = 0U, /**< LATCH1 A line */
+  XMC_ECAT_PORT_CTRL_LATCHIN1_9_1   = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */
+  XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1   = 1U, /**< LATCH1 B line */
+  XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1   = 2U, /**< LATCH1C line */
+  XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1   = 3U, /**< LATCH1D line */  
+} XMC_ECAT_PORT_CTRL_LATCHIN1_t;
+
+/**
+ * ECAT Port 0 Manual TX Shift configuration
+ */
+typedef enum XMC_ECAT_PORT0_CTRL_TX_SHIFT
+{
+  XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS  = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */
+  XMC_ECAT_PORT0_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */
+  XMC_ECAT_PORT0_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */
+  XMC_ECAT_PORT0_CTRL_TX_SHIFT_30NS = 3U  /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */
+} XMC_ECAT_PORT0_CTRL_TX_SHIFT_t;
+
+/**
+ * ECAT Port 1 Manual TX Shift configuration
+ */
+typedef enum XMC_ECAT_PORT1_CTRL_TX_SHIFT
+{
+  XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS  = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */
+  XMC_ECAT_PORT1_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */
+  XMC_ECAT_PORT1_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */
+  XMC_ECAT_PORT1_CTRL_TX_SHIFT_30NS = 3U  /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */
+} XMC_ECAT_PORT1_CTRL_TX_SHIFT_t;
+
+#endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_eru.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_eru.h
- * @date 2015-10-27
+ * @date 2016-03-10
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -46,6 +46,9 @@
  * 2015-10-07:
  *     - Doc update for XMC_ERU_ETL_CONFIG_t field  <br>
  *
+ * 2016-03-10:
+ *     - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
+ *
  * @endcond
  */
 
@@ -564,6 +567,20 @@ void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
                                   const uint8_t channel,
                                   const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection);
 
+/**
+ * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
+ * @param channel ERU_ETLx(Event trigger logic unit) channel.
+ *                Range : [0 to 3]
+ *
+ * @return XMC_ERU_ETL_EDGE_DETECTION_t indicate which egde/s is configured for event generation
+ *
+ * \par<b>Description:</b><br>
+ * Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.<br>
+ * \par
+ * Rising edge, falling edge or either edges can be selected to generate the event.
+ * Call this to get the configured trigger edge. */								  
+XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru,
+                                                          const uint8_t channel);
 /**
  * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
  * @param channel ERU_ETLx(Event trigger logic unit) channel.

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_eth_mac.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_eth_mac.h
- * @date 2015-10-27
+ * @date 2016-06-08
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -38,8 +38,18 @@
  * --------------
  *
  * 2015-06-20:
- *     - Initial <br>
+ *     - Initial
  *
+ * 2016-04-25:
+ *     - Change XMC_ETH_MAC_BUF_SIZE to 1524 to allow for Tagged MAC frame format
+ *  
+ * 2016-05-19:
+ *      - Added XMC_ETH_MAC_GetTxBuffer() and XMC_ETH_MAC_GetRxBuffer()
+ *      - Added XMC_ETH_MAC_SetTxBufferSize()
+ *
+ * 2016-06-08:
+ *      - Added XMC_ETH_MAC_IsRxDescriptorOwnedByDma()
+ * 
  * @endcond
  */
 
@@ -80,10 +90,62 @@
  * MACROS
  *********************************************************************************************************************/
 
-#define XMC_ETH_MAC_BUF_SIZE           (1518)     /**< ETH MAC buffer size */
+#define XMC_ETH_MAC_BUF_SIZE           (1524)     /**< ETH MAC buffer size */
 #define XMC_ETH_MAC_PHY_MAX_RETRIES    (0xffffUL) /**< Maximum retries */
 #define XMC_ETH_WAKEUP_REGISTER_LENGTH (8U)       /**< Remote wakeup frame reg length */
 
+/**
+ * TDES0 Descriptor TX Packet Control/Status
+ */
+#define ETH_MAC_DMA_TDES0_OWN  (0x80000000U) /**< Own bit 1=DMA, 0=CPU */
+#define ETH_MAC_DMA_TDES0_IC   (0x40000000U) /**< Interrupt on competition */
+#define ETH_MAC_DMA_TDES0_LS   (0x20000000U) /**< Last segment */
+#define ETH_MAC_DMA_TDES0_FS   (0x10000000U) /**< First segment */
+#define ETH_MAC_DMA_TDES0_DC   (0x08000000U) /**< Disable CRC */
+#define ETH_MAC_DMA_TDES0_DP   (0x04000000U) /**< Disable pad */
+#define ETH_MAC_DMA_TDES0_TTSE (0x02000000U) /**< Transmit time stamp enable */
+#define ETH_MAC_DMA_TDES0_CIC  (0x00C00000U) /**< Checksum insertion control */
+#define ETH_MAC_DMA_TDES0_TER  (0x00200000U) /**< Transmit end of ring */
+#define ETH_MAC_DMA_TDES0_TCH  (0x00100000U) /**< Second address chained */
+#define ETH_MAC_DMA_TDES0_TTSS (0x00020000U) /**< Transmit time stamp status */
+#define ETH_MAC_DMA_TDES0_IHE  (0x00010000U) /**< IP header error */
+#define ETH_MAC_DMA_TDES0_ES   (0x00008000U) /**< Error summary */
+#define ETH_MAC_DMA_TDES0_JT   (0x00004000U) /**< Jabber timeout */
+#define ETH_MAC_DMA_TDES0_FF   (0x00002000U) /**< Frame flushed */
+#define ETH_MAC_DMA_TDES0_IPE  (0x00001000U) /**< IP payload error */
+#define ETH_MAC_DMA_TDES0_LOC  (0x00000800U) /**< Loss of carrier */
+#define ETH_MAC_DMA_TDES0_NC   (0x00000400U) /**< No carrier */
+#define ETH_MAC_DMA_TDES0_LC   (0x00000200U) /**< Late collision */
+#define ETH_MAC_DMA_TDES0_EC   (0x00000100U) /**< Excessive collision */
+#define ETH_MAC_DMA_TDES0_VF   (0x00000080U) /**< VLAN frame */
+#define ETH_MAC_DMA_TDES0_CC   (0x00000078U) /**< Collision count */
+#define ETH_MAC_DMA_TDES0_ED   (0x00000004U) /**< Excessive deferral */
+#define ETH_MAC_DMA_TDES0_UF   (0x00000002U) /**< Underflow error */
+#define ETH_MAC_DMA_TDES0_DB   (0x00000001U) /**< Deferred bit */
+
+/**
+ * RDES0 Descriptor RX Packet Status
+ */
+#define ETH_MAC_DMA_RDES0_OWN  (0x80000000U) /**< Own bit 1=DMA, 0=CPU */
+#define ETH_MAC_DMA_RDES0_AFM  (0x40000000U) /**< Destination address filter fail */
+#define ETH_MAC_DMA_RDES0_FL   (0x3FFF0000U) /**< Frame length mask */
+#define ETH_MAC_DMA_RDES0_ES   (0x00008000U) /**< Error summary */
+#define ETH_MAC_DMA_RDES0_DE   (0x00004000U) /**< Descriptor error */
+#define ETH_MAC_DMA_RDES0_SAF  (0x00002000U) /**< Source address filter fail */
+#define ETH_MAC_DMA_RDES0_LE   (0x00001000U) /**< Length error */
+#define ETH_MAC_DMA_RDES0_OE   (0x00000800U) /**< Overflow error */
+#define ETH_MAC_DMA_RDES0_VLAN (0x00000400U) /**< VLAN tag */
+#define ETH_MAC_DMA_RDES0_FS   (0x00000200U) /**< First descriptor */
+#define ETH_MAC_DMA_RDES0_LS   (0x00000100U) /**< Last descriptor */
+#define ETH_MAC_DMA_RDES0_TSA  (0x00000080U) /**< Timestamp available */
+#define ETH_MAC_DMA_RDES0_LC   (0x00000040U) /**< Late collision */
+#define ETH_MAC_DMA_RDES0_FT   (0x00000020U) /**< Frame type */
+#define ETH_MAC_DMA_RDES0_RWT  (0x00000010U) /**< Receive watchdog timeout */
+#define ETH_MAC_DMA_RDES0_RE   (0x00000008U) /**< Receive error */
+#define ETH_MAC_DMA_RDES0_DBE  (0x00000004U) /**< Dribble bit error */
+#define ETH_MAC_DMA_RDES0_CE   (0x00000002U) /**< CRC error */
+#define ETH_MAC_DMA_RDES0_ESA  (0x00000001U) /**< Extended Status/Rx MAC address */
+
 /**********************************************************************************************************************
  * ENUMS
  *********************************************************************************************************************/
@@ -1132,6 +1194,21 @@ __STATIC_INLINE void XMC_ETH_MAC_SetLink(XMC_ETH_MAC_t *const eth_mac,
  */
 void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac);
 
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @return bool true if RX descriptor is owned by DMA, false otherwise
+ *
+ * \par<b>Description: </b><br>
+ * Is RX descriptor owned by DMA? <br>
+ *
+ * \par
+ * The function checks if the RX descriptor is owned by the DMA.
+ */
+__STATIC_INLINE bool XMC_ETH_MAC_IsRxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac)
+{
+  return ((eth_mac->rx_desc[eth_mac->rx_index].status & ETH_MAC_DMA_RDES0_OWN) != 0U);
+}
+
 /**
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
  * @return None
@@ -1154,7 +1231,10 @@ void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac);
  * \par
  * The function checks if the TX descriptor is owned by the DMA.
  */
-bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac);
+__STATIC_INLINE bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac)
+{
+  return ((eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) != 0U);
+}
 
 /**
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
@@ -1286,6 +1366,43 @@ __STATIC_INLINE void XMC_ETH_MAC_ResumeRx(XMC_ETH_MAC_t *const eth_mac)
   eth_mac->regs->RECEIVE_POLL_DEMAND = 0U;
 }
 
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @return Pointer to current TX buffer
+ *
+ * \par<b>Description: </b><br>
+ * Returns the current TX buffer.
+ */
+__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBuffer(XMC_ETH_MAC_t *const eth_mac)
+{
+  return (uint8_t *)(eth_mac->tx_desc[eth_mac->tx_index].buffer1);
+}
+
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @return Pointer to current RX buffer
+ *
+ * \par<b>Description: </b><br>
+ * Returns the current RX buffer.
+ */
+__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetRxBuffer(XMC_ETH_MAC_t *const eth_mac)
+{
+  return (uint8_t *)(eth_mac->rx_desc[eth_mac->rx_index].buffer1); 
+}
+
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @param size Size of buffer
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Sets the current TX buffer size.
+ */
+__STATIC_INLINE void XMC_ETH_MAC_SetTxBufferSize(XMC_ETH_MAC_t *const eth_mac, uint32_t size)
+{
+  eth_mac->tx_desc[eth_mac->tx_index].length = size;
+}
+
 /**
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
  * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_eth_mac_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_eth_mac_map.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_eth_phy.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_eth_phy.h
- * @date 2015-10-27
+ * @date 2015-12-15
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -37,7 +37,10 @@
  * --------------
  *
  * 2015-06-20:
- *     - Initial <br>
+ *     - Initial
+ *
+ * 2015-12-15:
+ *     - Added XMC_ETH_PHY_ExitPowerDown and XMC_ETH_PHY_Reset
  *
  * @endcond
  */
@@ -95,7 +98,7 @@ extern "C" {
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
  * @param phy_addr Physical address
  * @param config A constant pointer to XMC_ETH_PHY_CONFIG_t, pointing to a physical layer config
- * @return int32_t ETH physical layer initialization status
+ * @return int32_t return status XMC_ETH_PHY_STATUS_t
  *
  * \par<b>Description: </b><br>
  * Initialize the ETH physical layer interface <br>
@@ -109,17 +112,36 @@ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const X
 /**
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
  * @param phy_addr Physical address
- * @return int32_t ETH MAC return status
+ * @return int32_t return status XMC_ETH_PHY_STATUS_t
  *
  * \par<b>Description: </b><br>
- * Enable power down mode <br>
+ * Enter power down mode <br>
  *
- * \par
- * Power-down mode is used to power down the KSZ8021/31RNL device (on the XMC4500 relax kit)
- * when it is not in use after power-up. It is enabled by writing a 1 to register 0h, bit [11].  
  */
 int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
 
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @param phy_addr Physical address
+ * @return int32_t return status XMC_ETH_PHY_STATUS_t
+ *
+ * \par<b>Description: </b><br>
+ * Exit power down mode <br>
+ *
+ */
+int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
+
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @param phy_addr Physical address
+ * @return int32_t return status XMC_ETH_PHY_STATUS_t
+ *
+ * \par<b>Description: </b><br>
+ * Reset transciver <br>
+ *
+ */
+int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
+
 /**
  * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
  * @param phy_addr Physical address
@@ -162,6 +184,16 @@ XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint
  */
 XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
 
+/**
+ * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
+ * @param phy_addr Physical address
+ * @return bool True if autonegotiation process is finished otherwise false
+ *
+ * \par<b>Description: </b><br>
+ * Get status of autonegotiation <br>
+ */
+bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_fce.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_fce.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_flash.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_flash.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -191,7 +191,7 @@ void XMC_FLASH_DisableEvent(const uint32_t event_msk);
  * Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one
  * page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr)
  * to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines
- * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.
+ * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation.
  * \endif
  * \if XMC4
  * Programs a single flash page associated with the specified \a address.\n\n  XMC4000 flash can be programmed with a
@@ -199,7 +199,7 @@ void XMC_FLASH_DisableEvent(const uint32_t event_msk);
  * bits inside status register. It starts the write process by issuing the page mode command followed by the load page
  * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page
  * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the
- * erase operation.\n
+ * programming operation.\n
  * \endif
  *
  * \par<b>Note:</b><br>

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_gpio.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_gpio.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_hrpwm.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_hrpwm.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_hrpwm_map.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_hrpwm_map.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_i2c.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_i2c.h
- * @date 2015-10-27
+ * @date 2016-05-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -64,6 +64,12 @@
  *     - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to  XMC_I2C_CH_EnableAcknowledgeAddress0()
  *       and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0().
  *
+ * 2016-05-20:
+ *     - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission()
+ *
+ * 2016-08-17:
+ *     - Improved documentation of slave address passing
+ *
  * @endcond 
  *
  */
@@ -359,8 +365,8 @@ __STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const cha
  * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
  * 				  \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
  * @param  interrupt_node Interrupt node pointer to be configured. \n
- * 						  \b Range: @ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
+ * 						  \b Range: @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
- * 						  			@ref XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
+ * 						  			@ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
  * @param service_request Service request number.\n
  * 						  \b Range: 0 to 5.
  * @return None
@@ -434,7 +440,10 @@ __STATIC_INLINE void XMC_I2C_CH_SetInputSource(XMC_USIC_CH_t *const channel, con
  *
  * \par
  * Address is set in PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.
- * (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)
+ * (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)\n
+ * @note A 7-bit address should include an additional bit at the LSB for read/write indication. For example, address 0x05 should
+ * be provided as 0x0a. A 10-bit address should be provided with the identifier 0b11110xx at the most significant bits. For example,
+ * address 0x305 should be provided as 0x7b05(bitwise OR with 0x7800).
  *
  * \par<b>Related APIs:</b><br>
  * XMC_I2C_CH_GetSlaveAddress()\n\n
@@ -450,7 +459,9 @@ void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t add
  *
  * \par
  * Returns the address using PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.<br>
- * (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)
+ * (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)\n
+ * @note A 7-bit address will include an additional bit at the LSB. For example, address 0x05 will be returned as 0x0a.
+ * 10-bit address will not include the 10-bit address identifier 0b11110xx at the most signifcant bits.
  *
  * \par<b>Related APIs:</b><br>
  * XMC_I2C_CH_SetSlaveAddress()\n\n
@@ -467,7 +478,11 @@ uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel);
  * Starts the I2C master \a channel.<br>
  *
  * \par
- * Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.
+ * Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
+ * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
+ * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
+ * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
+ * followed by 1-bit field for read/write).
  *
  * \par<b>Related APIs:</b><br>
  * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
@@ -484,7 +499,11 @@ void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, c
  * Sends the repeated start condition from I2C master \a channel.<br>
  *
  * \par
- * Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.
+ * Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
+ * @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
+ * be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
+ * For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
+ * followed by 1-bit field for read/write).
  *
  * \par<b>Related APIs:</b><br>
  * XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
@@ -711,6 +730,43 @@ __STATIC_INLINE void XMC_I2C_CH_DisableAcknowledgeAddress0(XMC_USIC_CH_t *const
   channel->PCR_IICMode &= ~USIC_CH_PCR_IICMode_ACK00_Msk;
 }
 
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Enable data transmission.\n\n
+ * Use this function in combination with XMC_I2C_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_I2C_CH_DisableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
+}
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Disable data transmission.\n\n
+ * Use this function in combination with XMC_I2C_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_I2C_CH_EnableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); 
+}
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_i2s.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_i2s.h
- * @date 2015-10-27
+ * @date 2016-06-30
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
@@ -51,6 +51,12 @@
  * 2015-09-14:
  *     - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length<br>
  *
+ * 2016-05-20:
+ *     - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission()
+ *
+ * 2016-06-30:
+ *     - Documentation updates.
+ *
  * @endcond
  *
  */
@@ -222,13 +228,15 @@ typedef enum XMC_I2S_CH_BUS_MODE
  */
 typedef struct XMC_I2S_CH_CONFIG
 {
-  uint32_t baudrate;					   /**< Module baud rate for communication */
+  uint32_t baudrate;					             /**< Module baud rate for communication */
-  uint8_t data_bits;                       /**< Number of bits for the data field. Value configured as USIC channel word length. \n
+  uint8_t data_bits;                       /**< Data word length. A data frame can consists of several data words. \n
+                                                Value configured as USIC channel word length. \n
                                                   \b Range: minimum= 1, maximum= 16*/
-  uint8_t frame_length;                    /**< Indicates number of bits in a frame. Configured as USIC channel frame length. \n
+  uint8_t frame_length;                    /**< Number of data bits transferred after a change of signal WA (data frame). \n
+                                                Configured as USIC channel frame length. \n
                                                   \b Range: minimum= 1, maximum= 63*/
-  uint8_t data_delayed_sclk_periods;       /**< Data delay defined in sclk periods*/
+  uint8_t data_delayed_sclk_periods;       /**< Data delay defined in sclk periods */
-  XMC_I2S_CH_WA_POLARITY_t wa_inversion;   /**< Enable inversion of Slave select signal relative to the internal WA*/
+  XMC_I2S_CH_WA_POLARITY_t wa_inversion;   /**< Enable inversion of Slave select signal relative to the internal WA */
   XMC_I2S_CH_BUS_MODE_t	bus_mode;          /**< Bus mode MASTER/SLAVE */
 } XMC_I2S_CH_CONFIG_t;
 
@@ -239,6 +247,29 @@ typedef struct XMC_I2S_CH_CONFIG
 #ifdef __cplusplus
 extern "C" {
 #endif
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
+ * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t.
+ * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n
+ *          \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n
+ *                    @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed.
+ *
+ * \par<b>Description</b><br>
+ * Initializes the USIC channel for I2S protocol.\n\n
+ * During the initialization, USIC channel is enabled and baudrate is configured.
+ * After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length).
+ * The number of data bits transferred after a change of signal WA is defined by config->frame_length.
+ * A data frame can consist of several data words with a data word length defined by config->data_bits.
+ * The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA.
+ * The system word length is set by default to the frame length defined by config->frame_length.
+ *
+ * XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel.
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n
+ */
 void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config);
 
 /**
@@ -755,6 +786,43 @@ __STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const ch
   XMC_USIC_CH_DisableDelayCompensation(channel);
 }
 
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Enable data transmission.\n\n
+ * Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_I2S_CH_DisableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
+}
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Disable data transmission.\n\n
+ * Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_I2S_CH_EnableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); 
+}
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_ledts.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ledts.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_pau.h

@@ -0,0 +1,396 @@
+/**
+ * @file xmc_pau.h
+ * @date 2015-06-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-02-20:
+ *     - Initial version
+ *      
+ * 2015-05-20:
+ *     - Documentation updated
+ *
+ * 2015-06-20:
+ *     - Removed version macros and declaration of GetDriverVersion API
+ * @endcond 
+ *
+ */
+
+#ifndef XMC_PAU_H
+#define XMC_PAU_H
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ *********************************************************************************************************************/
+
+#include "xmc_common.h"
+
+#if defined(PAU)
+  
+/**
+ * @addtogroup XMClib XMC Peripheral Library
+ * @{
+ */
+
+/**
+ * @addtogroup PAU
+ * @brief Peripheral Access Unit (PAU) driver for the XMC1000 microcontroller family
+ *
+ * The Peripheral Access Unit (PAU) supports access control of memories and peripherals. 
+ * It allows user application to enable/disable the access to the registers of a peripheral.
+ * It generates a HardFault exception when there is an access to a disabled or unassigned
+ * address location. It also provides information on the availability of peripherals and
+ * sizes of memories.
+ *
+ * The PAU low level driver provides functions to check the availability of peripherals
+ * and to enable/disable peripheral access.
+ * @{
+ */  
+ 
+/*********************************************************************************************************************
+ * MACROS
+ *********************************************************************************************************************/
+
+/**
+ * A convenient symbol for the PAU peripheral base address
+ */
+#define XMC_PAU ((XMC_PAU_t *) PAU_BASE)
+
+/*
+ * This macro is used in the LLD for assertion checks (XMC_ASSERT)
+ */
+#define XMC_PAU_CHECK_MODULE_PTR(p) ((p) == XMC_PAU)
+
+/*********************************************************************************************************************
+ * ENUMS
+ *********************************************************************************************************************/
+
+/**
+ * Status return values for PAU low level driver
+ */ 
+typedef enum XMC_PAU_STATUS
+{
+  XMC_PAU_STATUS_OK    = 0U, /**< Operation successful */
+  XMC_PAU_STATUS_BUSY  = 1U, /**< Busy with a previous request */
+  XMC_PAU_STATUS_ERROR = 2U  /**< Operation unsuccessful */
+} XMC_PAU_STATUS_t;
+ 
+/**
+ * PAU peripheral select
+ */
+typedef enum XMC_PAU_PERIPHERAL
+{
+  XMC_PAU_PERIPHERAL_FLASH                = PAU_PRIVDIS0_PDIS2_Msk, /**< Flash SFRs Privilege Disable Flag */
+  XMC_PAU_PERIPHERAL_RAM_BLOCK1           = PAU_PRIVDIS0_PDIS5_Msk, /**< RAM Block 1 Privilege Disable Flag */
+  XMC_PAU_PERIPHERAL_RAM_BLOCK2           = PAU_PRIVDIS0_PDIS6_Msk, /**< RAM Block 2 Privilege Disable Flag */
+  XMC_PAU_PERIPHERAL_RAM_BLOCK3           = PAU_PRIVDIS0_PDIS7_Msk, /**< RAM Block 3 Privilege Disable Flag */
+  #if defined(WDT)
+   XMC_PAU_PERIPHERAL_WDT                 = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */
+  #endif
+  #if defined(MATH)
+   XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */
+  #endif
+  #if defined(MATH)
+   XMC_PAU_PERIPHERAL_MATH_CORDIC         = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag  */
+  #endif
+  #if defined(PORT0)
+   XMC_PAU_PERIPHERAL_PORT0               = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */
+  #endif
+  #if defined(PORT1)
+   XMC_PAU_PERIPHERAL_PORT1               = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */
+  #endif
+  #if defined(PORT2)
+   XMC_PAU_PERIPHERAL_PORT2               = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */
+#endif
+#if defined(PORT3)
+   XMC_PAU_PERIPHERAL_PORT3               = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */
+#endif
+#if defined(PORT4)
+   XMC_PAU_PERIPHERAL_PORT4               = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */
+#endif
+#if defined(USIC0)
+   XMC_PAU_PERIPHERAL_USIC0_CH0           = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */
+   XMC_PAU_PERIPHERAL_USIC0_CH1           = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */
+#endif
+#if defined(USIC1)
+   XMC_PAU_PERIPHERAL_USIC1_CH0           = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */
+   XMC_PAU_PERIPHERAL_USIC1_CH1           = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */
+#endif
+#if defined(PRNG)
+   XMC_PAU_PERIPHERAL_PRNG                = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/
+#endif
+#if defined(VADC)
+   XMC_PAU_PERIPHERAL_VADC_GLOBAL         = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */
+#if defined(VADC_G0)
+   XMC_PAU_PERIPHERAL_VADC_GROUP0         = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */
+#endif
+#if defined(VADC_G1)
+   XMC_PAU_PERIPHERAL_VADC_GROUP1         = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */
+#endif
+#endif
+#if defined(SHS0)
+   XMC_PAU_PERIPHERAL_VADC_SHS0           = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */
+#endif
+#if defined(CCU40)
+   XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL     = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */
+#if defined(CCU40_CC41)
+   XMC_PAU_PERIPHERAL_CCU40_CC41                = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */
+#endif
+#if defined(CCU40_CC42)
+   XMC_PAU_PERIPHERAL_CCU40_CC42                = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */
+#endif
+#if defined(CCU40_CC43)
+   XMC_PAU_PERIPHERAL_CCU40_CC43                = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */
+#endif
+#endif
+#if defined(CCU41)
+   XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL     = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */
+#if defined(CCU41_CC41)
+   XMC_PAU_PERIPHERAL_CCU41_CC41                = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */
+#endif
+#if defined(CCU41_CC42)
+   XMC_PAU_PERIPHERAL_CCU41_CC42                = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */
+#endif
+#if defined(CCU41_CC43)
+   XMC_PAU_PERIPHERAL_CCU41_CC43                = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */
+#endif
+#endif
+#if defined(CCU80) 
+   XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL     = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */
+#if defined(CCU80_CC81)
+   XMC_PAU_PERIPHERAL_CCU80_CC81                = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */
+#endif
+#if defined(CCU80_CC82)
+   XMC_PAU_PERIPHERAL_CCU80_CC82                = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */
+#endif
+#if defined(CCU80_CC83)
+   XMC_PAU_PERIPHERAL_CCU80_CC83                = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */
+#endif
+#endif
+#if defined(CCU81) 
+   XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL     = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */
+#if defined(CCU81_CC81)
+   XMC_PAU_PERIPHERAL_CCU81_CC81                = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */
+#endif
+#if defined(CCU81_CC82)
+   XMC_PAU_PERIPHERAL_CCU81_CC82                = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */
+#endif
+#if defined(CCU81_CC83)
+   XMC_PAU_PERIPHERAL_CCU81_CC83                = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */
+#endif
+#endif
+#if defined(POSIF0)
+   XMC_PAU_PERIPHERAL_POSIF0              = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */
+#endif
+#if defined(POSIF1)
+   XMC_PAU_PERIPHERAL_POSIF1              = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */
+#endif
+#if defined(LEDTS0)  
+   XMC_PAU_PERIPHERAL_LEDTS0              = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */
+#endif
+#if defined(LEDTS1)  
+   XMC_PAU_PERIPHERAL_LEDTS1              = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */
+#endif
+#if defined(LEDTS2)  
+   XMC_PAU_PERIPHERAL_LEDTS2              = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */
+#endif
+#if defined(BCCU0)   
+   XMC_PAU_PERIPHERAL_BCCU0               = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */
+#endif
+#if defined(CAN)   
+#if defined(CAN_NODE0)   
+   XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */
+#endif   
+#if defined(CAN_NODE1)   
+   XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */
+#endif
+   XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */
+#endif
+} XMC_PAU_PERIPHERAL_t;
+
+
+/*********************************************************************************************************************
+ * DATA STRUCTURES
+ *********************************************************************************************************************/
+ 
+ 
+/**
+ * External Peripheral Access Unit (PAU) device structure <br>
+ *
+ * The structure represents a collection of all hardware registers
+ * used to configure the PAU peripheral on the XMC microcontroller.
+ * The registers can be accessed with ::XMC_PAU.
+ */
+typedef struct 
+{
+  __I  uint32_t  RESERVED0[16];
+  __I  uint32_t  AVAIL[3];
+  __I  uint32_t  RESERVED1[13];
+  __IO uint32_t  PRIVDIS[3];
+  __I  uint32_t  RESERVED2[221];
+  __I  uint32_t  ROMSIZE;
+  __I  uint32_t  FLSIZE; 
+  __I  uint32_t  RESERVED3[2];
+  __I  uint32_t  RAM0SIZE;
+} XMC_PAU_t;
+
+/*********************************************************************************************************************
+ * API PROTOTYPES
+ *********************************************************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be enabled
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enable the peripheral access <br>
+ *
+ * \par
+ * The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral 
+ * during run time.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PAU_DisablePeripheralAccess() 
+ */
+void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
+
+/**
+ * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Disable the peripheral access <br>
+ *
+ * \par
+ * The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral 
+ * during run time. An access to a disabled or unassigned address location generates a hardfault 
+ * exception.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PAU_EnablePeripheralAccess() 
+ */
+void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
+
+/**
+ * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access enabled status to be checked
+ * @return bool "false" if peripheral access is enabled, "true" otherwise
+ *
+ * \par<b>Description: </b><br>
+ * Checks if the peripheral access is enabled or not <br>
+ *
+ * \par
+ * The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral 
+ * during run time is enabled or not.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess() 
+ */
+bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral);
+
+/**
+ * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
+ * @return bool Returns "true" if peripheral is available, "false" otherwise
+ *
+ * \par<b>Description: </b><br>
+ * Checks if a peripheral is available or not <br>
+ *
+ * \par
+ * The function checks the AVAILx.AVAILy bit to know whether the peripheral 
+ * is available or not for the particular device variant.
+ */
+bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral);
+
+/**
+ * @return uint32_t Returns ROM size
+ *
+ * \par<b>Description: </b><br>
+ * Gets the ROM size <br>
+ *
+ * \par
+ * The function checks the ROMSIZE.ADDR bitfield to indicate the available size of ROM in the device in bytes.
+ */
+__STATIC_INLINE uint32_t XMC_PAU_GetROMSize(void)
+{
+  return (uint32_t)(((XMC_PAU->ROMSIZE & PAU_ROMSIZE_ADDR_Msk) >> PAU_ROMSIZE_ADDR_Pos) * 256U);
+}
+
+/**
+ * @return uint32_t Returns flash size
+ *
+ * \par<b>Description: </b><br>
+ * Gets the flash size <br>
+ *
+ * \par
+ * The function checks the FLSIZE.ADDR bitfield to indicate the available size of FLASH in the device in Kbytes.
+ */
+__STATIC_INLINE uint32_t XMC_PAU_GetFlashSize(void)
+{
+  return (uint32_t)((((XMC_PAU->FLSIZE & PAU_FLSIZE_ADDR_Msk) >> PAU_FLSIZE_ADDR_Pos) - 1U) * 4U);
+}
+
+/**
+ * @return uint32_t Returns RAM size
+ *
+ * \par<b>Description: </b><br>
+ * Gets RAM size <br>
+ *
+ * \par
+ * The function checks the RAM0SIZE.ADDR bitfield to indicate the available size of RAM in the device in bytes.
+ */
+__STATIC_INLINE uint32_t XMC_PAU_GetRAMSize(void)
+{
+  return (uint32_t)(((XMC_PAU->RAM0SIZE & PAU_RAM0SIZE_ADDR_Msk) >> PAU_RAM0SIZE_ADDR_Pos) * 256U);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PAU) */
+
+#endif /* XMC_PAU_H */
+

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_posif.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_posif.h
- * @date 2015-10-27
+ * @date 2016-03-09
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           
@@ -54,6 +54,10 @@
  *
  * 2015-07-02:
  *     - Updated XMC_POSIF_QD_GetDirection API
+ *
+ * 2016-03-09:
+ *     - Optimization of write only registers
+ *
  * @endcond 
  *
  */
@@ -558,7 +562,7 @@ void XMC_POSIF_SelectInputSource(XMC_POSIF_t *const peripheral, const XMC_POSIF_
  */
 __STATIC_INLINE void XMC_POSIF_Start(XMC_POSIF_t *const peripheral)
 {
-  peripheral->PRUNS |= (uint32_t)POSIF_PRUNS_SRB_Msk;
+  peripheral->PRUNS = (uint32_t)POSIF_PRUNS_SRB_Msk;
 }
 
 /**
@@ -575,7 +579,7 @@ __STATIC_INLINE void XMC_POSIF_Start(XMC_POSIF_t *const peripheral)
  */
 __STATIC_INLINE void XMC_POSIF_Stop(XMC_POSIF_t *const peripheral)
 {
-  peripheral->PRUNC |= (uint32_t)(POSIF_PRUNC_CRB_Msk | POSIF_PRUNC_CSM_Msk);
+  peripheral->PRUNC = (uint32_t)(POSIF_PRUNC_CRB_Msk | POSIF_PRUNC_CSM_Msk);
 }
 
 /**
@@ -744,7 +748,7 @@ __STATIC_INLINE void XMC_POSIF_HSC_SetHallPatterns(XMC_POSIF_t *const peripheral
  */
 __STATIC_INLINE void XMC_POSIF_HSC_UpdateHallPattern(XMC_POSIF_t *const peripheral)
 {
-  peripheral->MCMS |= (uint32_t)POSIF_MCMS_STHR_Msk;
+  peripheral->MCMS = (uint32_t)POSIF_MCMS_STHR_Msk;
 }
 
 /**
@@ -976,7 +980,7 @@ __STATIC_INLINE void XMC_POSIF_DisableEvent(XMC_POSIF_t *const peripheral, const
  */
 __STATIC_INLINE void XMC_POSIF_SetEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event)
 {
-  peripheral->SPFLG |= (uint32_t)1 << (uint8_t)event;
+  peripheral->SPFLG = (uint32_t)1 << (uint8_t)event;
 }
 
 /**
@@ -993,7 +997,7 @@ __STATIC_INLINE void XMC_POSIF_SetEvent(XMC_POSIF_t *const peripheral, const XMC
  */
 __STATIC_INLINE void XMC_POSIF_ClearEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event)
 {
-  peripheral->RPFLG |= (uint32_t)1 << (uint8_t)event;
+  peripheral->RPFLG = (uint32_t)1 << (uint8_t)event;
 }
 
 /**

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_prng.h

@@ -0,0 +1,285 @@
+
+/**
+ * @file xmc_prng.h
+ * @date 2015-06-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-02-20:
+ *     - Initial <br>
+ *     - Documentation updates <br>
+ *
+ * 2015-06-20:
+ *     - Removed version macros and declaration of GetDriverVersion API <br>
+ *
+ * @endcond
+ */
+ 
+#ifndef XMC_PRNG_H
+#define XMC_PRNG_H
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ *********************************************************************************************************************/
+
+#include "xmc_common.h"
+
+#if defined (PRNG) 
+
+/**
+ * @addtogroup XMClib XMC Peripheral Library
+ * @{
+ */
+
+/**
+ * @addtogroup PRNG
+ * @brief Pseudo Random Number Generator (PRNG) driver for XMC1000 microcontroller family
+ *
+ * The pseudo random bit generator (PRNG) provides random data with fast generation times.
+ * PRNG has to be initialized by the user software before use. The initialization consists
+ * of two basic phases: key-loading and warm-up.
+ *  
+ * The PRNG low level driver provides functions to configure and initialize the PRNG hardware
+ * peripheral.
+ * @{
+ */  
+
+/*********************************************************************************************************************
+ * MACROS
+ *********************************************************************************************************************/
+ 
+/**
+ * Byte mask value for random data block size
+ */ 
+#define XMC_PRNG_RDBS_BYTE_READ_MASK (0x00FFU)
+
+/*********************************************************************************************************************
+ * ENUMS
+ *********************************************************************************************************************/
+
+/**
+ * PRNG key load operation modes
+ */
+typedef enum XMC_PRNG_KEY_LOAD_OP_MODE {
+  XMC_PRNG_STRM_MODE = 0U, /**< Streaming mode (default) */
+  XMC_PRNG_KLD_MODE  = 1U  /**< Loading mode */
+} XMC_PRNG_KEY_LOAD_OP_MODE_t;
+
+/**
+ * PRNG data block size
+ */
+typedef enum XMC_PRNG_DATA_BLOCK_SIZE {
+  XMC_PRNG_RDBS_RESET = 0U, /**< Reset state (no random data block size defined) */
+  XMC_PRNG_RDBS_BYTE  = 1U, /**< BYTE (8-bit) */
+  XMC_PRNG_RDBS_WORD  = 2U  /**< WORD (16-bit) */
+} XMC_PRNG_DATA_BLOCK_SIZE_t;
+
+/**
+ * PRNG driver initialization status
+ */
+typedef enum XMC_PRNG_INIT_STATUS {
+  XMC_PRNG_NOT_INITIALIZED = 0U, /**< Reset state or Non-initialized state (Same as XMC_PRNG_RDBS_RESET) */
+  XMC_PRNG_INITIALIZED     = 1U  /**< Initialized state */
+} XMC_PRNG_INIT_STATUS_t;
+
+/*********************************************************************************************************************
+ * DATA STRUCTURES
+ *********************************************************************************************************************/
+
+/**
+ * Key words and data block size configuration values of PRNG <br>
+ *
+ * The structure presents a convenient way to set/obtain the key word and data block configuration
+ * values of PRNG.
+ * The XMC_PRNG_Init() can be used to populate the structure with the key word and data block
+ * configuration values of the PRNG module.
+ */ 
+typedef struct XMC_PRNG_INIT
+{
+  uint16_t key_words[5];                 /**< Keywords */
+  XMC_PRNG_DATA_BLOCK_SIZE_t block_size; /**< Block size */
+} XMC_PRNG_INIT_t;
+
+/*********************************************************************************************************************
+ * API PROTOTYPES
+ *********************************************************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @param prng Pointer to a constant instance of ::XMC_PRNG_INIT_t, pointing to
+ *             the initialization configuration.
+ * @return XMC_PRNG_INIT_STATUS_t XMC_PRNG_INITIALIZED if initialized,
+ *                                XMC_PRNG_NOT_INITIALIZED otherwise.
+ *
+ * \par<b>Description: </b><br>
+ * Initialize the PRNG peripheral with the configured key words and block size <br>
+ *
+ * \par
+ * The function configures block size for key loading mode, enables key loading mode,
+ * loads key words (80 bits) and wait till RDV is set, enables the streaming mode and
+ * waits for warmup phase. This function programmes the CTRL and WORD registers. 
+ */
+XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng);
+
+
+
+/**
+ * @param block_size Block size of type ::XMC_PRNG_DATA_BLOCK_SIZE_t for read access
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Programming Random Block Size <br>
+ *
+ * \par
+ * The function sets the random data block size as byte or word by programming CTRL.RDBS bitfield.
+ * block_size = 0 for Reset state, block_size = 1 for 'byte' and block_size = 2 for 'word'.
+ */
+__STATIC_INLINE void XMC_PRNG_SetRandomDataBlockSize(XMC_PRNG_DATA_BLOCK_SIZE_t block_size)
+{
+  PRNG->CTRL = (uint16_t)((PRNG->CTRL & (uint32_t)~PRNG_CTRL_RDBS_Msk) |
+                          ((uint32_t)block_size << (uint32_t)PRNG_CTRL_RDBS_Pos));
+}
+
+/**
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Checks the validity (CHK.RDV bit) of the generated random data <br>
+ *
+ * \par
+ * The function checks the validity (CHK.RDV bit) of the generated random data.
+ * In key loading mode, this value indicates if the next partial key word can be written
+ * to PRNG_WORD or not.
+ */
+__STATIC_INLINE uint16_t XMC_PRNG_CheckValidStatus(void)
+{
+  return (PRNG->CHK & PRNG_CHK_RDV_Msk);
+}
+
+/**
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enables the PRNG key loading mode <br>
+ *
+ * \par
+ * The function initializes the key loading by setting the bit CTRL.KLD. In this mode, Register WORD
+ * acts as always as a 16 bit destination register. After the complete key has been loaded, the CTRL.KLD
+ * must be set to '0' to prepare the following warmup phase.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PRNG_EnableStreamingMode()
+ */
+__STATIC_INLINE void XMC_PRNG_EnableKeyLoadingMode(void)
+{
+  PRNG->CTRL |= (uint16_t)PRNG_CTRL_KLD_Msk;
+}
+
+/**
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enables the Streaming mode <br>
+ *
+ * \par
+ * The function enables the streaming mode and disables the PRNG key loading mode by resetting the
+ * CTRL.KLD bit. 
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PRNG_EnableKeyLoadingMode()
+ */
+__STATIC_INLINE void XMC_PRNG_EnableStreamingMode(void)
+{
+  PRNG->CTRL &= (uint16_t)~PRNG_CTRL_KLD_Msk;
+}
+
+/**
+ * @param key Key word to load into PRNG WORD register
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Loads a partial key word to the PRNG WORD register <br>
+ *
+ * \par
+ * The function loads partial key word to WORD registr. These partial
+ * words are sequentially written and loading a key word will take 16 clock
+ * cycles. The CHK.RDV bit is set to '0' while loading is in progress. '1' indicates
+ * that the next partial key word can be written to WORD register. 
+ */
+__STATIC_INLINE void XMC_PRNG_LoadKeyWords(uint16_t key)
+{
+  PRNG->WORD = key;
+}
+
+/**
+ * @param None
+ * @return uint16_t Generated random number
+ *
+ * \par<b>Description: </b><br>
+ * Gets the generated random number <br>
+ *
+ * \par
+ * The function gives the generated random number by returning the content of WORD
+ * register. Before reading the WORD register to get the generated random number it is
+ * required to check the bit CHK.RDV is set which indicates that the next random data block
+ * can be read from WORD register. After a word has been read the bit CHK.RDV is reset
+ * by the hardware and generation of new random bits starts.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_PRNG_CheckValidStatus()
+ */
+__STATIC_INLINE uint16_t XMC_PRNG_GetPseudoRandomNumber(void)
+{
+  return PRNG->WORD;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* #if defined (PRNG) */
+
+#endif /* XMC_PRNG_H */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_rtc.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_rtc.h
- * @date 2015-10-27
+ * @date 2016-05-19
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -46,6 +46,10 @@
  *   
  * 2015-06-20:
  *     - Removed version macros and declaration of GetDriverVersion API
+ *
+ * 2016-05-19:
+ *     - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
+ *
  * @endcond 
  *
  */
@@ -463,6 +467,23 @@ void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval);
  */    
 void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time);
 
+/**
+ * @param stdtime Pointer to a ::tm structure containing the time parameters seconds,
+ *                minutes, hours, days, daysofweek, month, year(since 1900) and days in a   
+ *                year in standard format.           
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Sets the RTC module time value in standard format <br>
+ *
+ * \par
+ * The function sets the time values from TIM0, TIM1 registers. 
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_RTC_SetTime(), XMC_RTC_GetTime()
+ */     
+void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime);
+
 /**
  * @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds,
  *                minutes, hours, days, daysofweek, month, year(since 1900) and days in a   
@@ -519,6 +540,23 @@ void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm);
  */    
 void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm);
 
+/**
+ * @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds,
+ *                alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,  
+ *                alarm year(since 1900) and alarm days in a year in standard format.           
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Sets the RTC module alarm time value in standard format <br>
+ *
+ * \par
+ * The function sets the alarm time values from ATIM0, ATIM1 registers. 
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm()
+ */     
+void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime);
+
 /**
  * @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds,
  *                alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,  

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_scu.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_scu.h
- * @date 2015-10-27
+ * @date 2016-03-09
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -49,6 +49,12 @@
  *       XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,
  *       XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,
  *       XMC_SCU_INTERUPT_ClearEventStatus
+ *
+ * 2015-11-30:
+ *     - Documentation improved <br>
+ *      
+ * 2016-03-09:
+ *     - Optimization of write only registers
  *      
  * @endcond 
  *
@@ -176,7 +182,7 @@ typedef enum XMC_SCU_STATUS
  ********************************************************************************************************************/
 
 /**
- * Function pointer type used for registering callback functions on SCU event occurence.
+ * Function pointer type used for registering callback functions on SCU event occurrence.
  */
 typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);
 
@@ -309,7 +315,7 @@ void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
  * @return None
  *
  * \par<b>Description</b><br>
- * Disables generation of interrupt on occurence of the input event.\n\n
+ * Disables generation of interrupt on occurrence of the input event.\n\n
  * The events are disabled by resetting the respective bit fields in the SRMSK register. \n
  * \par<b>Related APIs:</b><BR>
  * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n
@@ -400,7 +406,7 @@ __STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void)
 __STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void)
 {
   /* Clear RSTSTAT.RSTSTAT bitfield */
-  SCU_RESET->RSTCLR |= (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
+  SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
 }
  
 /**
@@ -548,7 +554,7 @@ __STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void)
  *          \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n
  *            \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n
  * \par<b>Description</b><br>
- * Assigns the event handler function to be executed on occurence of the selected event.\n\n
+ * Assigns the event handler function to be executed on occurrence of the selected event.\n\n
  * If the input event is valid, the handler function will be assigned to a table to be executed
  * when the interrupt is generated and the event status is set in the event status register. By using this API,
  * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_sdmmc.h

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_sdmmc.h
- * @date 2015-10-27
+ * @date 2016-07-11
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -44,6 +44,23 @@
  * 2015-06-20:
  *     - Removed version macros and declaration of GetDriverVersion API <br>
  *
+ * 2016-01-16:
+ *     - Added the following APIs to the XMC_SDMMC low level driver <br>
+ *         1) XMC_SDMMC_EnableDelayCmdDatLines <br>
+ *         2) XMC_SDMMC_DisableDelayCmdDatLines <br>
+ *         3) XMC_SDMMC_SetDelay <br>
+ *         4) XMC_SDMMC_EnableHighSpeed <br>
+ *         5) XMC_SDMMC_DisableHighSpeed <br>
+ *
+ * 2016-04-07:
+ *     - Added XMC_SDMMC_COMMAND_RESPONSE_t <br>
+ *
+ * 2016-07-11:
+ *     - Adjust masks for the following functions: <br>
+ *       1) XMC_SDMMC_SetBusVoltage <br>
+ *       2) XMC_SDMMC_SetDataLineTimeout <br>
+ *       3) XMC_SDMMC_SDClockFreqSelect <br>
+ *
  * @endcond
  */
 
@@ -178,6 +195,14 @@
   ((d == XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD)   ||\
    (d == XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST))
 
+/*
+ * Min and max number of delay elements <br>
+ *
+ * This macro is used in the LLD for assertion checks (XMC_ASSERT).
+ */
+#define XMC_SDMMC_MIN_DELAY_ELEMENTS (0U)
+#define XMC_SDMMC_MAX_DELAY_ELEMENTS (15U)
+
 /*******************************************************************************
  * ENUMS
  *******************************************************************************/
@@ -291,6 +316,17 @@ typedef enum
   XMC_SDMMC_RESPONSE_TYPE_R7                /**< Response type: R7 */
 } XMC_SDMMC_RESPONSE_TYPE_t;
 
+/**
+* Command response selection
+*/
+typedef enum XMC_SDMMC_COMMAND_RESPONSE
+{
+  XMC_SDMMC_COMMAND_RESPONSE_NONE = 0, /**< No Response */
+  XMC_SDMMC_COMMAND_RESPONSE_LONG = 1, /**< Response length 136 */
+  XMC_SDMMC_COMMAND_RESPONSE_SHORT = 2, /**< Response length 48 */
+  XMC_SDMMC_COMMAND_RESPONSE_SHORT_BUSY = 3, /**< Response length 48 check Busy after response */
+} XMC_SDMMC_COMMAND_RESPONSE_t;
+
 /**
  * Types of SDMMC commands
  */
@@ -474,14 +510,14 @@ typedef union
 {
   struct
   {
-    uint16_t response_type_sel : 2; /**< Response type select */
+    uint16_t response_type_sel : 2; /**< Response type select ::XMC_SDMMC_COMMAND_RESPONSE_t */
-    uint16_t                   : 1; /**< Reserved bit */
+    uint16_t                   : 1;
     uint16_t crc_check_en      : 1; /**< Command CRC check enable */
     uint16_t index_check_en    : 1; /**< Command index check enable */
     uint16_t dat_present_sel   : 1; /**< Data present select */
-    uint16_t cmd_type          : 2; /**< Command type */
+    uint16_t cmd_type          : 2; /**< Command type ::XMC_SDMMC_COMMAND_TYPE_t */
     uint16_t cmd_index         : 6; /**< Command index */
-    uint16_t                   : 2; /**< Reserved bits */
+    uint16_t                   : 2;
   };
   uint16_t cmd;
 } XMC_SDMMC_COMMAND_t;
@@ -1366,8 +1402,8 @@ __STATIC_INLINE void XMC_SDMMC_SDClockFreqSelect(XMC_SDMMC_t *const sdmmc, XMC_S
   XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
   XMC_ASSERT("XMC_SDMMC_SDClockFreqSelect: Invalid clock frequency selection", XMC_SDMMC_CHECK_SDCLK_FREQ(clk));
 
-  sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk &
+  sdmmc->CLOCK_CTRL = (uint16_t)((sdmmc->CLOCK_CTRL & (uint32_t)~SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk) |
-                                  (uint32_t)((uint32_t)clk << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos));
+                                 (uint32_t)(clk << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos));
 }
 
 /**
@@ -1388,7 +1424,8 @@ __STATIC_INLINE void XMC_SDMMC_SetBusVoltage(XMC_SDMMC_t *const sdmmc, XMC_SDMMC
   XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
   XMC_ASSERT("XMC_SDMMC_SetBusVoltage: Invalid bus voltage", XMC_SDMMC_CHECK_BUS_VOLTAGE(bus_voltage));
 
-  sdmmc->POWER_CTRL |= (uint8_t)((uint32_t)bus_voltage << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos);
+  sdmmc->POWER_CTRL = (uint8_t)((sdmmc->POWER_CTRL & (uint32_t)~SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk) |
+                                (uint32_t)(bus_voltage << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos));
 }
 
 /**
@@ -1409,8 +1446,8 @@ __STATIC_INLINE void XMC_SDMMC_SetDataLineTimeout(XMC_SDMMC_t *const sdmmc, XMC_
   XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
   XMC_ASSERT("XMC_SDMMC_SetDataLineTimeout: Invalid timeout", XMC_SDMMC_CHECK_DAT_TIMEOUT_COUNTER(timeout));
 
-  sdmmc->TIMEOUT_CTRL |= (uint8_t)(((uint32_t)timeout << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos) &
+  sdmmc->TIMEOUT_CTRL = (uint8_t)((sdmmc->TIMEOUT_CTRL & (uint32_t)~SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk) |
-                                   (uint32_t)SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk);
+                                  (uint32_t)(timeout << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos));
 }
 
 /**
@@ -1457,6 +1494,94 @@ __STATIC_INLINE void XMC_SDMMC_SetDataTransferDirection(XMC_SDMMC_t *const sdmmc
 	                                (uint16_t)((uint16_t)dir << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos));
 }
 
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Enable delay on the command/data out lines <br>
+ *
+ * \par
+ * Use the function to enable delay on the command/data out lines. Invoke this function
+ * before selecting the number of delay elements.
+ */
+__STATIC_INLINE void XMC_SDMMC_EnableDelayCmdDatLines(void)
+{
+  SCU_GENERAL->SDMMCDEL |= (uint32_t)SCU_GENERAL_SDMMCDEL_TAPEN_Msk;
+}
+
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Disable delay on the command/data out lines <br>
+ *
+ * \par
+ * Use the function to disable delay on the command/data out lines.
+ */
+__STATIC_INLINE void XMC_SDMMC_DisableDelayCmdDatLines(void)
+{
+  SCU_GENERAL->SDMMCDEL &= (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPEN_Msk;
+}
+
+/**
+ * @param tapdel Number of delay elements to select
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * Set number of delay elements on the command/data out lines <br>
+ *
+ * \par
+ * Use the function to set the number of delay elements on the command/data out lines.
+ * The function writes the delay value to the SDMMC delay control register (SDMMCDEL)
+ * within the realm of the SCU peripheral. A delay of tapdel + 1 is considered as the
+ * final selected number of delay elements.
+ */
+__STATIC_INLINE void XMC_SDMMC_SetDelay(uint8_t tapdel)
+{
+  SCU_GENERAL->SDMMCDEL = (uint32_t)((SCU_GENERAL->SDMMCDEL & (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPDEL_Msk) |
+	                                (uint32_t)(tapdel << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos));
+}
+
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * High speed enable <br>
+ *
+ * \par
+ * Use the function to enable high speed operation. The default is a normal speed operation.
+ * Once enabled, the host controller outputs command and data lines at the rising edge of the
+ * SD clock (up to 50 MHz for SD).
+ */
+__STATIC_INLINE void XMC_SDMMC_EnableHighSpeed(XMC_SDMMC_t *const sdmmc)
+{
+  XMC_ASSERT("XMC_SDMMC_EnableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
+
+  sdmmc->HOST_CTRL |= (uint8_t)SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk;
+}
+
+/**
+ * @param None
+ * @return None
+ *
+ * \par<b>Description: </b><br>
+ * High speed disable <br>
+ *
+ * \par
+ * Use the function to disable high speed operation. The host controller will switch back
+ * to a normal speed mode. In this mode, the host controller outputs command and data lines
+ * at 25 MHz for SD.
+ */
+__STATIC_INLINE void XMC_SDMMC_DisableHighSpeed(XMC_SDMMC_t *const sdmmc)
+{
+  XMC_ASSERT("XMC_SDMMC_DisableHighSpeed: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
+
+  sdmmc->HOST_CTRL &= (uint8_t)~SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk;
+}
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_spi.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_spi.h
- * @date 2015-10-27
+ * @date 2016-05-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -62,6 +62,13 @@
  *
  * 2015-09-08:
  *     - Adding API for configuring the receiving clock phase in the slave:XMC_SPI_CH_DataLatchedInTrailingEdge() and XMC_SPI_CH_DataLatchedInLeadingEdge() <br>
+ *
+ * 2016-04-10:
+ *     - Added an API for configuring the transmit mode:XMC_SPI_CH_SetTransmitMode() <br>
+ *
+ * 2016-05-20:
+ *     - Added XMC_SPI_CH_EnableDataTransmission() and XMC_SPI_CH_DisableDataTransmission()
+ * 
  * @endcond 
  *
  */
@@ -438,6 +445,27 @@ void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH
  */
 void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel);
 
+/**
+ * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
+ * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n
+ *             Refer @ref XMC_SPI_CH_MODE_t for valid values.
+ *
+ * @return None
+ *
+ * \par<b>Description:</b><br>
+ * In Dual and Quad modes,  hardware port control(CCR.HPCEN) mode is enabled. \n\n
+ * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the 
+ * mode to ensure the proper communication.
+ * 
+ * \par<b>Related APIs:</b><BR>
+ * XMC_SPI_CH_Transmit()
+ */
+__STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode)
+{
+  channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) |
+                  (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk);
+}
+
 /**
  * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
  * @param data Data to be transmitted
@@ -1170,6 +1198,72 @@ __STATIC_INLINE void XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *co
   XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,2U,combination_mode);
 }
 
+/**
+ * @param  channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
+ *
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * The SELOx lines (with x = 1-7) can be used as addresses for an external address
+ * decoder to increase the number of external slave devices.
+ */
+__STATIC_INLINE void XMC_SPI_CH_EnableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel)
+{
+  /* Configuration of Protocol Control Register */
+  channel->PCR_SSCMode = (uint32_t)(channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELCTR_Msk));
+}
+
+/**
+ * @param  channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
+ *
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Each SELOx line (with x = 0-7) can be directly connected to an external slave device.
+ */
+__STATIC_INLINE void XMC_SPI_CH_DisableSlaveSelectCodedMode(XMC_USIC_CH_t *const channel)
+{
+  /* Configuration of Protocol Control Register */
+  channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_SELCTR_Msk;
+}
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Enable data transmission.\n\n
+ * Use this function in combination with XMC_SPI_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_SPI_CH_DisableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
+}
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_SPI0_CH0, @ref XMC_SPI0_CH1,@ref XMC_SPI1_CH0,@ref XMC_SPI1_CH1,@ref XMC_SPI2_CH0,@ref XMC_SPI2_CH1 @note Availability of SPI1 and SPI2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Disable data transmission.\n\n
+ * Use this function in combination with XMC_SPI_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_SPI_CH_EnableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); 
+}
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_uart.h

@@ -1,12 +1,12 @@
  /**
  * @file xmc_uart.h
- * @date 2015-10-27
+ * @date 2016-05-20
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -50,6 +50,10 @@
  *     - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
  *     - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent()
  *       for supporting multiple events configuration <br>
+ * 
+ * 2016-05-20:
+ *     - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission()
+ *
  * @endcond 
  *
  */
@@ -754,6 +758,43 @@ __STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const chann
   XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq);
 }
 
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Enable data transmission.\n\n
+ * Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_UART_CH_DisableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
+}
+
+/**
+ * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
+ *          \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Disable data transmission.\n\n
+ * Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
+ * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_UART_CH_EnableDataTransmission()\n\n\n
+ */
+__STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
+{
+  XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); 
+}
+
 #ifdef __cplusplus
 }
 #endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_usbd.h

@@ -1,11 +1,11 @@
 /**
  * @file xmc_usbd.h
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_usbd_regs.h

@@ -33,13 +33,13 @@
 
 /*
  * @file xmc_usbd_regs.h
- * @date 2015-10-27
+ * @date 2015-02-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_usbh.h

@@ -0,0 +1,416 @@
+/**
+ * @file xmc_usbh.h
+ * @date 2016-06-30
+ *
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2016-06-30:
+ *     - Initial Version.<br>
+ * 2016-09-01:
+ *     - Removed Keil specific inclusions and macros<br>
+ *
+ * @endcond
+ *
+ */
+
+#ifndef XMC_USBH_H
+#define XMC_USBH_H
+
+#include <stdint.h>
+#include "xmc_common.h"
+#include "xmc_scu.h"
+#include "xmc_gpio.h"
+
+#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || defined(DOXYGEN))
+/**
+ * @addtogroup XMClib XMC Peripheral Library
+ * @{
+ */
+
+/**
+ * @addtogroup USBH
+ * @brief Universal Serial Bus Host (USBH) driver for the XMC4000 microcontroller family.
+ *
+ * The USBH is the host mode device driver for the USB0 hardware module on XMC4000 family of microcontrollers.
+ * The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers.
+ * The USB module includes the following features in host mode:
+ * -# Complies with the USB 2.0 Specification.
+ * -# Supports up to 14 bidirectional pipes, including control pipe 0.
+ * -# Supports SOFs in Full-Speed modes.
+ * -# Supports clock gating for power saving.
+ * -# Supports FIFO mode data transaction.
+ *
+ * The below figure shows the overview of USB0 module in XMC4 microntroller.
+ * @image html USB_module_overview.png
+ * @image latex ../images/USB_module_overview.png
+ *
+ *
+ * The USBH device driver supports the following features:\n
+ * -# Initialize/Uninitialize the USB0 module on XMC4000 device.
+ * -# Control VBUS state.
+ * -# Reset USB port.
+ * -# Set the USB device address.
+ * -# Allocate pipe for new endpoint communication.
+ * -# Modify an existing pipe.
+ * -# Transfer data on selected pipe.
+ * -# Abort ongoing data transaction.
+ * -# Handle multi packet data transaction by updating toggle information.
+ *
+ * The USBH device driver expects registration of callback functions ::XMC_USBH_SignalPortEvent_t and ::XMC_USBH_SignalPipeEvent_t to be executed
+ * when there is port event interrupt and pipe event interrupt respectively.\n
+ * The USBH driver is CMSIS API compatible. Please use Driver_USBH0 to access the USBH API.\n
+ * For example, to initialize the USB host controller, use Driver_USBH0.Initialize().\n
+ *
+ * @{
+ */
+
+/**********************************************************************************************************************
+ * MACROS
+ *********************************************************************************************************************/
+/*Drive VBUS*/
+#define XMC_USB_DRIVE_PORT1                         P3_2  /**< Default port(PORT3, pin 2) used to enable VBUS voltage regulator on the board */
+#define XMC_USB_DRIVE_PORT2                         P0_1  /**< Alternate port that can be used to enable VBUS voltage regulator(PORT0, pin 1) */
+
+#ifndef USBH0_MAX_PIPE_NUM
+#define USBH0_MAX_PIPE_NUM                          (14U) /**< Representation of number of pipes available */
+#endif
+#if (USBH0_MAX_PIPE_NUM > 14U)
+#error  Too many Pipes, maximum Pipes that this driver supports is 14 !!!
+#endif
+
+#define XMC_USBH_CLOCK_GATING_ENABLE               1  /**< Used to enable clock gating when the driver is powered down*/
+#define XMC_USBH_CLOCK_GATING_DISABLE              0  /**< Used to disable clock gating when the driver is fully powered*/
+
+#define  USB_CH_HCCHARx_MPS(x)                      (((uint32_t)    x   ) & (uint32_t)USB_CH_HCCHAR_MPS_Msk)  /**< Masks maximum packet size information from the HCCHAR register value provided as input */
+#define  USB_CH_HCCHARx_EPNUM(x)                    (((uint32_t)    x   << USB_CH_HCCHAR_EPNum_Pos) & (uint32_t)USB_CH_HCCHAR_EPNum_Msk)  /**< Shifts the value to the position of endpoint number(EPNum) in the HCCHAR register*/
+#define  USB_CH_HCCHARx_EPTYPE(x)                   (((uint32_t)    x   << USB_CH_HCCHAR_EPType_Pos) & (uint32_t)USB_CH_HCCHAR_EPType_Msk)  /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/
+#define  USB_CH_HCCHARx_MCEC(x)                     (((uint32_t)    x   << USB_CH_HCCHAR_MC_EC_Pos) & (uint32_t)USB_CH_HCCHAR_MC_EC_Msk)  /**< Shifts the value to the position of multi-count(MC_EC) field in the HCCHAR register*/
+#define  USB_CH_HCCHARx_DEVADDR(x)                  (((uint32_t)    x   << USB_CH_HCCHAR_DevAddr_Pos) & (uint32_t)USB_CH_HCCHAR_DevAddr_Msk)  /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/
+#define  USB_CH_HCCHARx_EPDIR(x)                    (((uint32_t)    x   << USB_CH_HCCHAR_EPDir_Pos) & (uint32_t)USB_CH_HCCHAR_EPDir_Msk)  /**< Shifts the value to the position of endpoint direction(EPDir) in the HCCHAR register*/
+#define  USB_CH_HCCHAR_LSDEV_Msk                    (((uint32_t)    0x1   << 15U) & 0x1U)
+#define  USB_CH_HCTSIZx_DPID(x)                     (((uint32_t)    x   << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos) & (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk)  /**< Shifts the value to the position of packet ID (PID) in the HCTSIZ register*/
+#define  USB_CH_HCTSIZx_DPID_DATA0                  (USB_CH_HCTSIZx_DPID(0U)) /**< Represents DATA toggle DATA0 as in HCTSIZ register*/
+#define  USB_CH_HCTSIZx_DPID_DATA2                  (USB_CH_HCTSIZx_DPID(1U)) /**< Represents DATA toggle DATA2 as in HCTSIZ register*/
+#define  USB_CH_HCTSIZx_DPID_DATA1                  (USB_CH_HCTSIZx_DPID(2U)) /**< Represents DATA toggle DATA1 as in HCTSIZ register*/
+#define  USB_CH_HCTSIZx_DPID_MDATA                  (USB_CH_HCTSIZx_DPID(3U)) /**< Represents DATA toggle MDATA as in HCTSIZ register*/
+#define  USB_CH_HCTSIZx_DPID_SETUP                  (USB_CH_HCTSIZx_DPID(3U)) /**< Represents SETUP token as in HCTSIZ register*/
+#define  USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT    0x2 /**< Represents IN data token as in receive status pop register(GRXSTSP)*/
+#define  USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL    0x3 /**< Represents paket status information as in receive status pop register(GRXSTSP)*/
+
+
+#define  USB_CH_HCFG_FSLSSUP(x)                     (((uint32_t)    x  <<  USB_HCFG_FSLSSupp_Pos) & USB_HCFG_FSLSSupp_Msk)  /**< Provides register value to update USB full speed related mask FLSSupp of register HCFG*/
+#define  USB_CH_HCFG_FSLSPCS(x)                     (((uint32_t)    x        ) & USB_HCFG_FSLSPclkSel_Msk)  /**< Provides register value to update PHY clock selection in register HCFG*/
+
+#define  USB_CH_HCINTx_ALL                          (USB_CH_HCINTMSK_XferComplMsk_Msk | \
+                                                      USB_CH_HCINTMSK_ChHltdMsk_Msk | \
+                                                      USB_CH_HCINTMSK_StallMsk_Msk | \
+                                                      USB_CH_HCINTMSK_NakMsk_Msk | \
+                                                      USB_CH_HCINTMSK_AckMsk_Msk | \
+                                                      USB_CH_HCINTMSK_XactErrMsk_Msk | \
+                                                      USB_CH_HCINTMSK_BblErrMsk_Msk | \
+                                                      USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \
+                                                      USB_CH_HCINTMSK_DataTglErrMsk_Msk)  /**< Mask for selecting all channel related events*/
+
+#define  USB_CH_HCINTx_ERRORS                       (USB_CH_HCINTMSK_XactErrMsk_Msk | \
+                                                      USB_CH_HCINTMSK_BblErrMsk_Msk | \
+                                                      USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \
+                                                      USB_CH_HCINTMSK_DataTglErrMsk_Msk)  /**< Mask for selecting all channel error related events*/
+/*Macro to find pipe index using handle*/
+#define USBH_PIPE_GET_INDEX(handle)                 (((uint32_t)handle - (uint32_t)USB0_CH0_BASE)/(0x20U))  /**< Macro provides index of the USB channel based on its base address*/
+
+#define XMC_USBH_API_VERSION                        ((uint16_t)((uint16_t)XMC_LIB_MAJOR_VERSION << 8U) |XMC_LIB_MINOR_VERSION)  /**<  USBH low level driver API version */
+
+/* General return codes */
+#define XMC_USBH_DRIVER_OK                           0 /**< Operation succeeded */
+#define XMC_USBH_DRIVER_ERROR                       -1 /**< Unspecified error */
+#define XMC_USBH_DRIVER_ERROR_BUSY                  -2 /**< Driver is busy*/
+#define XMC_USBH_DRIVER_ERROR_TIMEOUT               -3 /**< Timeout occurred */
+#define XMC_USBH_DRIVER_ERROR_UNSUPPORTED           -4 /**< Operation not supported*/
+#define XMC_USBH_DRIVER_ERROR_PARAMETER             -5 /**< Parameter error*/
+#define XMC_USBH_DRIVER_ERROR_SPECIFIC              -6 /**< Start of driver specific errors*/
+
+/* USB Speed */
+#define XMC_USBH_SPEED_LOW                          0U       /**< Low-speed USB*/
+#define XMC_USBH_SPEED_FULL                         1U       /**< Full-speed USB*/
+#define XMC_USBH_SPEED_HIGH                         2U       /**< High-speed USB*/
+
+/* USB Endpoint Type */
+#define XMC_USBH_ENDPOINT_CONTROL                   0       /**< Control Endpoint*/
+#define XMC_USBH_ENDPOINT_ISOCHRONOUS               1       /**< Isochronous Endpoint*/
+#define XMC_USBH_ENDPOINT_BULK                      2       /**< Bulk Endpoint*/
+#define XMC_USBH_ENDPOINT_INTERRUPT                 3       /**< Interrupt Endpoint*/
+
+#define XMC_USBH_SignalEndpointEvent_t              XMC_USBH_SignalPipeEvent_t  /**< Legacy name for the pipe event handler*/
+
+/****** USB Host Packet Information *****/
+#define XMC_USBH_PACKET_TOKEN_Pos                    0 /**< Packet token position*/
+#define XMC_USBH_PACKET_TOKEN_Msk                   (0x0FUL << XMC_USBH_PACKET_TOKEN_Pos)  /**< Packet token mask*/
+#define XMC_USBH_PACKET_SETUP                       (0x01UL << XMC_USBH_PACKET_TOKEN_Pos)  /**< SETUP Packet*/
+#define XMC_USBH_PACKET_OUT                         (0x02UL << XMC_USBH_PACKET_TOKEN_Pos)  /**< OUT Packet*/
+#define XMC_USBH_PACKET_IN                          (0x03UL << XMC_USBH_PACKET_TOKEN_Pos)  /**< IN Packet*/
+#define XMC_USBH_PACKET_PING                        (0x04UL << XMC_USBH_PACKET_TOKEN_Pos)  /**< PING Packet*/
+
+#define XMC_USBH_PACKET_DATA_Pos                     4  /**< Packet data PID position*/
+#define XMC_USBH_PACKET_DATA_Msk                    (0x0FUL << XMC_USBH_PACKET_DATA_Pos)   /**< Packet data PID mask*/
+#define XMC_USBH_PACKET_DATA0                       (0x01UL << XMC_USBH_PACKET_DATA_Pos)   /**< DATA0 PID */
+#define XMC_USBH_PACKET_DATA1                       (0x02UL << XMC_USBH_PACKET_DATA_Pos)   /**< DATA1 PID */
+
+#define XMC_USBH_PACKET_SPLIT_Pos                    8
+#define XMC_USBH_PACKET_SPLIT_Msk                   (0x0FUL << XMC_USBH_PACKET_SPLIT_Pos)
+#define XMC_USBH_PACKET_SSPLIT                      (0x08UL << XMC_USBH_PACKET_SPLIT_Pos)  /**< SSPLIT Packet */
+#define XMC_USBH_PACKET_SSPLIT_S                    (0x09UL << XMC_USBH_PACKET_SPLIT_Pos)  /**< SSPLIT Packet: Data Start */
+#define XMC_USBH_PACKET_SSPLIT_E                    (0x0AUL << XMC_USBH_PACKET_SPLIT_Pos)  /**< SSPLIT Packet: Data End */
+#define XMC_USBH_PACKET_SSPLIT_S_E                  (0x0BUL << XMC_USBH_PACKET_SPLIT_Pos)  /**< SSPLIT Packet: Data All */
+#define XMC_USBH_PACKET_CSPLIT                      (0x0CUL << XMC_USBH_PACKET_SPLIT_Pos)  /**< CSPLIT Packet */
+
+#define XMC_USBH_PACKET_PRE                         (1UL << 12)                            /**< PRE Token */
+
+
+/****** USB Host Port Event *****/
+#define XMC_USBH_EVENT_CONNECT                      (1UL << 0)     /**< USB Device Connected to Port */
+#define XMC_USBH_EVENT_DISCONNECT                   (1UL << 1)     /**< USB Device Disconnected from Port */
+#define XMC_USBH_EVENT_OVERCURRENT                  (1UL << 2)     /**< USB Device caused Overcurrent */
+#define XMC_USBH_EVENT_RESET                        (1UL << 3)     /**< USB Reset completed */
+#define XMC_USBH_EVENT_SUSPEND                      (1UL << 4)     /**< USB Suspend occurred */
+#define XMC_USBH_EVENT_RESUME                       (1UL << 5)     /**< USB Resume occurred */
+#define XMC_USBH_EVENT_REMOTE_WAKEUP                (1UL << 6)     /**< USB Device activated Remote Wakeup */
+
+/****** USB Host Pipe Event *****/
+#define XMC_USBH_EVENT_TRANSFER_COMPLETE            (1UL << 0)     /**< Transfer completed */
+#define XMC_USBH_EVENT_HANDSHAKE_NAK                (1UL << 1)     /**< NAK Handshake received */
+#define XMC_USBH_EVENT_HANDSHAKE_NYET               (1UL << 2)     /**< NYET Handshake received */
+#define XMC_USBH_EVENT_HANDSHAKE_MDATA              (1UL << 3)     /**< MDATA Handshake received */
+#define XMC_USBH_EVENT_HANDSHAKE_STALL              (1UL << 4)     /**< STALL Handshake received */
+#define XMC_USBH_EVENT_HANDSHAKE_ERR                (1UL << 5)     /**< ERR Handshake received */
+#define XMC_USBH_EVENT_BUS_ERROR                    (1UL << 6)     /**< Bus Error detected */
+/*******************************************************************************
+ * ENUMS
+ *******************************************************************************/
+/**
+ * @brief General power states of USB peripheral driver
+*/
+typedef enum XMC_USBH_POWER_STATE {
+  XMC_USBH_POWER_OFF,                        /**< Power off: no operation possible */
+  XMC_USBH_POWER_LOW,                        /**< Low Power mode: retain state, detect and signal wake-up events */
+  XMC_USBH_POWER_FULL                        /**< Power on: full operation at maximum performance */
+} XMC_USBH_POWER_STATE_t;
+/*******************************************************************************
+ * DATA STRUCTURES
+ *******************************************************************************/
+/**
+ * @brief USB host Driver Version
+*/
+typedef struct XMC_USBH_DRIVER_VERSION {
+  uint16_t api;                         /**< API version */
+  uint16_t drv;                         /**< Driver version */
+} XMC_USBH_DRIVER_VERSION_t;
+
+
+/**
+ * @brief USB Host Port State
+*/
+typedef struct XMC_USBH_PORT_STATE {
+  uint32_t connected   : 1;             /**< USB Host Port connected flag */
+  uint32_t overcurrent : 1;             /**< USB Host Port overcurrent flag */
+  uint32_t speed       : 2;             /**< USB Host Port speed setting (ARM_USB_SPEED_xxx) */
+} XMC_USBH_PORT_STATE_t;
+
+/**
+ * @brief USB Host Pipe Handle. It represents the physical address of a USB channel
+*/
+typedef uint32_t XMC_USBH_PIPE_HANDLE;
+#define XMC_USBH_EP_HANDLE XMC_USBH_PIPE_HANDLE  /**< Legacy name for pipe handle used by CMSIS*/
+
+/**
+ * @brief USB Host Driver Capabilities.
+*/
+typedef struct XMC_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     /**< Root HUB available Ports Mask */
+  uint32_t auto_split         :  1;     /**< Automatic SPLIT packet handling */
+  uint32_t event_connect      :  1;     /**< Signal Connect event */
+  uint32_t event_disconnect   :  1;     /**< Signal Disconnect event */
+  uint32_t event_overcurrent  :  1;     /**< Signal Overcurrent event */
+} XMC_USBH_CAPABILITIES_t;
+
+
+typedef void (*XMC_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    /**< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. */
+typedef void (*XMC_USBH_SignalPipeEvent_t) (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  /**< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. */
+
+/**
+ * @brief Access structure of USB Host Driver.
+*/
+typedef struct XMC_USBH_DRIVER {
+  XMC_USBH_DRIVER_VERSION_t    (*GetVersion)            (void);                                /**< Pointer to \ref ARM_USBH_GetVersion : Get driver version. */
+  XMC_USBH_CAPABILITIES_t (*GetCapabilities)       (void);                                     /**< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. */
+  int32_t               (*Initialize)            (XMC_USBH_SignalPortEvent_t cb_port_event,
+                                                  XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */
+  int32_t               (*Uninitialize)          (void);                                     /**< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. */
+  int32_t               (*PowerControl)          (XMC_USBH_POWER_STATE_t state);                    /**< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. */
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  /**< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. */
+  int32_t               (*PortReset)             (uint8_t port);                             /**< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. */
+  int32_t               (*PortSuspend)           (uint8_t port);                             /**< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). */
+  int32_t               (*PortResume)            (uint8_t port);                             /**< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). */
+  XMC_USBH_PORT_STATE_t   (*PortGetState)          (uint8_t port);                           /**< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. */
+  XMC_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */
+  int32_t               (*PipeModify)            (XMC_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */
+  int32_t               (*PipeDelete)            (XMC_USBH_PIPE_HANDLE pipe_hndl);           /**< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. */
+  int32_t               (*PipeReset)             (XMC_USBH_PIPE_HANDLE pipe_hndl);           /**< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. */
+  int32_t               (*PipeTransfer)          (XMC_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */
+  uint32_t              (*PipeTransferGetResult) (XMC_USBH_PIPE_HANDLE pipe_hndl);           /**< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. */
+  int32_t               (*PipeTransferAbort)     (XMC_USBH_PIPE_HANDLE pipe_hndl);           /**< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. */
+  uint16_t              (*GetFrameNumber)        (void);                                     /**< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. */
+} const XMC_USBH_DRIVER_t;
+
+
+/**
+ * @brief Structure to handle various states of USB host driver. An instance exists for each USB channel
+ */
+typedef struct XMC_USBH0_pipe {
+  uint32_t  packet;                 /**< Holds packet token and PID information of ongoing data packet transaction*/
+  uint8_t  *data;                   /**< Holds address of data buffer. It represents source buffer for OUT or SETUP transfer and
+                                          destination address for IN transfer*/
+  uint32_t  num;                    /**< Number of bytes of data to be transmitted*/
+  uint32_t  num_transferred_total;  /**< Number of bytes transmitted or received at the moment*/
+  uint32_t  num_transferring;       /**< Number of bytes being transmitted currently*/
+  uint16_t  ep_max_packet_size;     /**< Maximum packet size for the selected pipe*/
+  uint16_t  interval_reload;        /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the period for repeated transfer*/
+  uint16_t  interval;               /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the decrementing count to reach 0 for initiating retransmission*/
+  uint8_t   ep_type;                /**< Endpoint type for selected pipe*/
+  uint8_t   in_use;                 /**< Set to true when transfer is in progress and reset only after the /ref num of bytes is transferred*/
+  uint8_t   transfer_active;        /**< Set to true when a transfer has been initiated and reset when event for transfer complete occurs*/
+	uint8_t   interrupt_triggered;    /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/
+  uint8_t   event;                  /**< Holds pipe specific event flags*/
+} XMC_USBH0_pipe_t;
+
+
+typedef struct xmc_usb_host_device {
+	USB0_GLOBAL_TypeDef *global_register;           /**< Global register interface            */
+	USB0_CH_TypeDef *host_channel_registers;        /**< Host channel interface               */
+	XMC_USBH_SignalPortEvent_t SignalPortEvent_cb;  /**< Port event callback; set during init */
+  XMC_USBH_SignalPipeEvent_t SignalPipeEvent_cb;  /**< Pipe event callback; set during init */
+	bool init_done;                                 /**< init status */
+	XMC_USBH_POWER_STATE_t power_state;             /**< USB Power status */
+	bool port_reset_active;                         /**< Port reset state */
+} XMC_USBH0_DEVICE_t;
+
+/*******************************************************************************
+ * API PROTOTYPES
+ *******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @param gintsts USB global interrupt status.
+ * @return None.
+ *
+ * \par<b>Description:</b><br>
+ * Updates logical state of the USB host driver based on the input status value. It handles port interrupt
+ * and channel interrupt. It responsible for updating data toggle information for multi-packet data transmission.
+ * It executes the callback function on transfer completion and reception of data. It also does error management and
+ * calls the relevant callback functions to indicate it to the application.
+ */
+void XMC_USBH_HandleIrq (uint32_t gintsts);
+/**
+ * @param ms Delay in milliseconds.
+ * @return uint8_t Value has no significance for the low level driver.
+ *
+ * \par<b>Description:</b><br>
+ * Function implements time delay logic. The USB host low level driver provides a weak definition
+ * for delay which has to re-implemented with time delay logic. The low level driver expects blocking
+ * implementation of the delay.
+ */
+ uint8_t XMC_USBH_osDelay(uint32_t ms);
+ 
+/**
+ * @param port Address of the port which has the pin used to enable VBUS charge pump.
+ * @param pin Pin number in the port selected in previous argument using which the VBUS charge pump has to be enabled.
+ * @return None
+ *
+ * \par<b>Description:</b><br>
+ * Configures the port pin with alternate output function 1. VBUS enabling pins work with alternate output function 1. \n
+ * <i>Note:</i>The input port pin should support USB VBUS as an alternate function. \n
+ * Typical ports that support VBUS enable are: P3_2 and P0_1.
+ *
+ */
+void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin);
+
+/**
+ * @return USB host mode interrupt status. Bit field USB0_BASE->GINTSTS_HOSTMODE
+ *
+ * \par<b>Description:</b><br>
+ * Provides USB host global interrupt status. \n
+ * This value can be used to provide interrupt status to the IRQ handler function XMC_USBH_HandleIrq().
+ *
+ */
+uint32_t XMC_USBH_GetInterruptStatus(void);
+
+/**
+ * @return None
+ *
+ * \par<b>Description:</b><br>
+ * De-asserts resume bit. \n
+ * The function shall be called 20ms after detecting port remote wakeup event. \n
+ *
+ */
+void XMC_USBH_TurnOffResumeBit(void);
+#ifdef __cplusplus
+}
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif
+#endif /* XMC_USBH_H */
+
+

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_usic.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_usic.h
- * @date 2015-10-27
+ * @date 2016-04-10
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -67,6 +67,12 @@
  *     - Added API for enabling the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active. Feature used for RS-232
  *       Clear to Send (CTS) signal: XMC_USIC_CH_EnableTBUFDataValidTrigger() and XMC_USIC_CH_DisableTBUFDataValidTrigger().
  *
+ * 2016-03-09:
+ *     - Optimization of write only registers
+ *
+ * 2016-04-10:
+ *     - Added an API to put the data into FIFO when hardware port control is enabled: XMC_USIC_CH_TXFIFO_PutDataHPCMode() <br>
+ *
  * @endcond
  *
  */
@@ -1269,7 +1275,7 @@ __STATIC_INLINE void XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t *cons
  */
 __STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
 {
-  channel->FMR |= (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line);
+  channel->FMR = (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line);
 }
 
 /**
@@ -1480,6 +1486,30 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const chan
   channel->IN[frame_length] = data;
 }
 
+/**
+ * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
+ * 				   \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
+ * @param data Data to be transmitted.
+ * @param frame_length Frame length to be configured while transmitting the data. \n
+ * 			\b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15.
+ * @return None
+ *
+ * \par<b>Description</b><br>
+ * Writes data to the transmit FIFO in hardware port control mode. \n\n
+ * When hardware port control is enabled for dynamic update of frame length, this API can be used.
+ * \a frame_length represents the frame length to be updated by the peripheral. 
+ * \a frame_length is used as index for the IN[] register array.
+ * 
+ * \par<b>Related APIs:</b><BR>
+ * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
+ */
+__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const channel,
+                                                       const uint16_t data,
+                                                       const uint32_t frame_length)
+{
+  channel->IN[frame_length] = data;
+}
+
 /**
  * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
  * 				   \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
@@ -1494,7 +1524,7 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const chan
  */
 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel)
 {
-  channel->TRBSCR |= (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk;
+  channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk;
 }
 
 /**
@@ -1599,7 +1629,7 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channe
 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
                                                    const uint32_t event)
 {
-  channel->TRBSCR |= event;
+  channel->TRBSCR = event;
 }
 
 /**
@@ -1760,7 +1790,7 @@ __STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel
  */
 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel)
 {
-  channel->TRBSCR |= (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk;
+  channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk;
 }
 
 /**
@@ -1870,7 +1900,7 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channe
 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
                                                    const uint32_t event)
 {
-  channel->TRBSCR |= event;
+  channel->TRBSCR = event;
 }
 
 /**

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_vadc.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_vadc.h
- * @date 2015-10-27
+ * @date 2016-06-17
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -66,6 +66,42 @@
  *           - XMC_VADC_GROUP_ChannelGetResultAlignment
  *           - XMC_VADC_GROUP_ChannelGetInputClass
  *           - XMC_VADC_GROUP_SetResultSubtractionValue
+ *
+ * 2015-12-01:
+ *     - Added:
+ *     - XMC4300 device supported
+ *
+ *     - Fixed:
+ *     - XMC_VADC_GLOBAL_TriggerEvent API updated. OR operation removed. 
+ *     - XMC_VADC_GLOBAL_ClearEvent API updated. Multiple events triggering on clearing the event is fixed.   
+ *     - Wrong MACRO name defined in xmc_vadc_map.h file corrected for XMC4200/4100 devices.
+ *       XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE
+ *
+ * 2015-12-01:
+ *     - New APIs Created.
+ *           - XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled
+ *           - XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled
+ *     - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range.
+ *     - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100.
+ *
+ * 2016-03-09:
+ *     - Optimization of write only registers
+ *
+ * 2016-03-18:
+ *     - Fixed XMC_VADC_GLOBAL_SHS_IsConverterReady(): API checks the STEPCFG register for the ready bit instead of 
+ *       SHSCFG SFR. 
+ *
+ * 2016-06-17:
+ *     - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE
+ *     - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t
+ *     - New APIs added are:
+ *           - XMC_VADC_GROUP_SetSyncSlaveReadySignal
+ *           - XMC_VADC_GROUP_ChannelGetAssertedEvents
+ *           - XMC_VADC_GROUP_GetAssertedResultEvents
+ *           - XMC_VADC_GROUP_SetResultRegPriority
+ *           - XMC_VADC_GROUP_SetSyncReadySignal
+ *           - XMC_VADC_GROUP_GetSyncReadySignal
+ *           - XMC_VADC_GROUP_GetResultRegPriority
  * @endcond 
  *
  */
@@ -145,20 +181,22 @@
  * MACROS
  ********************************************************************************************************************/
 
-#if ((UC_SERIES == XMC42)||(UC_SERIES == XMC41))
+#if ((UC_SERIES == XMC42)||(UC_SERIES == XMC41) || (UC_SERIES == XMC43))
-#define XMC_VADC_GROUP_AVAILABLE         (1U) /*  Defines the availability of group resource in a device*/
+#define XMC_VADC_GROUP_AVAILABLE           (1U) /*  Defines the availability of group resource in a device*/
-#define XMC_VADC_GSCAN_AVAILABLE         (1U) /*  Defines the availability of scan request resource in a device*/
+#define XMC_VADC_GSCAN_AVAILABLE           (1U) /*  Defines the availability of scan request resource in a device*/
-#define XMC_VADC_QUEUE_AVAILABLE         (1U) /*  Defines the availability of queue request resource in a device*/
+#define XMC_VADC_QUEUE_AVAILABLE           (1U) /*  Defines the availability of queue request resource in a device*/
-#define XMC_VADC_EMUX_AVAILABLE          (1U) /*  Defines the availability of external multiplexer support in a
+#define XMC_VADC_EMUX_AVAILABLE            (1U) /*  Defines the availability of external multiplexer support in a
                                                     device*/
-#define XMC_VADC_BOUNDARY_AVAILABLE      (1U) /*  Defines the availability of boundary check support in a device*/
+#define XMC_VADC_BOUNDARY_AVAILABLE        (1U) /*  Defines the availability of boundary check support in a device*/
-#define XMC_VADC_MULTIPLE_SLAVEGROUPS    (1U) /*  Defines the availability of synchronous request source in device*/
+#define XMC_VADC_MULTIPLE_SLAVEGROUPS      (1U) /*  Defines the availability of synchronous request source in device*/
-#define XMC_VADC_MAXIMUM_NUM_GROUPS      (2U) /*  Defines the maximum number of groups available in a device*/
+#define XMC_VADC_MAXIMUM_NUM_GROUPS        (2U) /*  Defines the maximum number of groups available in a device*/
-#define XMC_VADC_BOUNDARY_FLAG_SELECT    (1U) /*  Defines the availability of boundary flags in a device*/
+#define XMC_VADC_BOUNDARY_FLAG_SELECT      (1U) /*  Defines the availability of boundary flags in a device*/
-#define XMC_VADC_EMUX_CH_SEL_STYLE       (1U) /*  Defines the external multiplexer channel selection mode of
+#define XMC_VADC_EMUX_CH_SEL_STYLE         (1U) /*  Defines the external multiplexer channel selection mode of
                                                     operation for a particular device*/
-#define XMC_VADC_SHS_AVAILABLE           (0U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_AVAILABLE             (0U) /* Defines the availability of sample and hold module*/
-#define XMC_VADC_GROUP_SRCREG_AVAILABLE  (1U) /* Define the availability of a source specific result register */
+#define XMC_VADC_SHS_FULL_SET_REG          (0U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_GROUP_SRCREG_AVAILABLE    (1U) /* Define the availability of a source specific result register */
+#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */
 #endif
 
 #if (UC_SERIES == XMC44 || UC_SERIES == XMC47 || UC_SERIES == XMC48)
@@ -174,7 +212,9 @@
 #define XMC_VADC_EMUX_CH_SEL_STYLE       (1U) /*  Defines the external multiplexer channel selection mode of
                                                     operation for a particular device*/
 #define XMC_VADC_SHS_AVAILABLE           (0U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_FULL_SET_REG        (0U) /* Defines the availability of sample and hold module*/
 #define XMC_VADC_GROUP_SRCREG_AVAILABLE  (1U) /* Define the availability of a source specific result register */
+#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */
 #endif
 
 #if (UC_SERIES == XMC45)
@@ -190,7 +230,9 @@
 #define XMC_VADC_EMUX_CH_SEL_STYLE       (0U) /*  Defines the external multiplexer channel selection mode of
                                                     operation for a particular device*/
 #define XMC_VADC_SHS_AVAILABLE           (0U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_FULL_SET_REG        (0U) /* Defines the availability of sample and hold module*/
 #define XMC_VADC_GROUP_SRCREG_AVAILABLE  (0U) /* Define the availability of a source specific result register */
+#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */
 #endif
 
 #if (UC_SERIES == XMC14 || UC_SERIES == XMC13 || UC_SERIES == XMC12)
@@ -206,7 +248,9 @@
 #define XMC_VADC_EMUX_CH_SEL_STYLE       (1U) /*  Defines the external multiplexer channel selection mode of
                                                     operation for a particular device*/
 #define XMC_VADC_SHS_AVAILABLE           (1U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_FULL_SET_REG        (1U) /* Defines the availability of sample and hold module*/
 #define XMC_VADC_GROUP_SRCREG_AVAILABLE  (1U) /* Define the availability of a source specific result register */
+#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (1U) /* Define the availability of a priority for result register */
 #endif
 
 #if (UC_SERIES == XMC11)
@@ -225,8 +269,10 @@
                                                     XMC1100 device for effective working*/ 
 #define XMC_VADC_EMUX_CH_SEL_STYLE       (0U) /*  Defines the external multiplexer channel selection mode of
                                                     operation for a particular device*/
-#define XMC_VADC_SHS_AVAILABLE           (0U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_AVAILABLE           (1U) /* Defines the availability of sample and hold module*/
+#define XMC_VADC_SHS_FULL_SET_REG        (0U) /* Defines the availability of sample and hold module*/
 #define XMC_VADC_GROUP_SRCREG_AVAILABLE  (0U) /* Define the availability of a source specific result register */
+#define XMC_VADC_RESULT_PRIORITY_AVAILABLE (0U) /* Define the availability of a priority for result register */
 #endif
 
 #define XMC_VADC_NUM_PORTS               (16U) /* Defines the number of hardware ports that can be configured
@@ -652,6 +698,8 @@ typedef enum XMC_VADC_CHANNEL_ALIAS
 } XMC_VADC_CHANNEL_ALIAS_t;
 
 #if(XMC_VADC_SHS_AVAILABLE == 1U)
+
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
 /**
  * Defines the gain calibration selection.
  */
@@ -662,6 +710,7 @@ typedef enum XMC_VADC_SHS_GAIN_LEVEL
   XMC_VADC_SHS_GAIN_LEVEL_2 = SHS_CALOC0_CALOFFVAL2_Pos, /**< Select the calibration value for gain level 2 */
   XMC_VADC_SHS_GAIN_LEVEL_3 = SHS_CALOC0_CALOFFVAL3_Pos  /**< Select the calibration value for gain level 3 */
 }XMC_VADC_SHS_GAIN_LEVEL_t;
+#endif
 
 /**
  * Defines the Delta sigma loop.
@@ -698,6 +747,20 @@ typedef enum XMC_VADC_BOUNDARY_NODE
   XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_3   /**<Route the Group boundary flag to Common Service Request line 3 */
 }XMC_VADC_BOUNDARY_NODE_t;
 #endif
+
+#if (XMC_VADC_GROUP_AVAILABLE == 1U)
+/**
+ * Defines the ready signal selection
+ */
+typedef enum XMC_VADC_SYNCTR_EVAL
+{
+  XMC_VADC_SYNCTR_EVAL_1 = VADC_G_SYNCTR_EVALR1_Msk, /**<Mask to set the EVAL1 bits of SYNCTR */
+#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U)
+  XMC_VADC_SYNCTR_EVAL_2 = VADC_G_SYNCTR_EVALR2_Msk, /**<Mask to set the EVAL2 bits of SYNCTR */
+  XMC_VADC_SYNCTR_EVAL_3 = VADC_G_SYNCTR_EVALR3_Msk  /**<Mask to set the EVAL3 bits of SYNCTR */
+#endif
+}XMC_VADC_SYNCTR_EVAL_t;
+#endif
 /*********************************************************************************************************************
  * DATA STRUCTURES
  ********************************************************************************************************************/
@@ -1156,6 +1219,7 @@ typedef struct XMC_VADC_RESULT_CONFIG
 } XMC_VADC_RESULT_CONFIG_t;
 
 #if(XMC_VADC_SHS_AVAILABLE == 1U)
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
 /**
  * Structure to initialize the Stepper configurations
  */
@@ -1194,7 +1258,7 @@ typedef struct XMC_VADC_GLOBAL_SHS_STEP_CONFIG
     uint32_t stepcfg;
   };
 }XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t;
-
+#endif
 /**
  * Sample and hold Initialization structure
  */
@@ -1212,9 +1276,9 @@ typedef struct XMC_VADC_GLOBAL_SHS_CONFIG
     };
     uint32_t shscfg;
   };
-
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
   XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t calibration_order; /**< order in which the calibration should be taken up*/
-
+#endif
 }XMC_VADC_GLOBAL_SHS_CONFIG_t;
 
 #endif
@@ -1736,7 +1800,7 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const globa
   XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Global Event", 
             ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type)))
 
-  global_ptr->GLOBEFLAG |= event_type;
+  global_ptr->GLOBEFLAG = event_type;
 }
 
 /**
@@ -1760,7 +1824,7 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_ClearEvent(XMC_VADC_GLOBAL_t *const global_
   XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Global Event", 
             ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type)))
 
-  global_ptr->GLOBEFLAG |= ((uint32_t)(event_type << (uint32_t)16));
+  global_ptr->GLOBEFLAG = ((uint32_t)(event_type << (uint32_t)16));
 }
 
 /**
@@ -1813,6 +1877,7 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co
  */
  void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config);
 
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
  /**
   * @param shs_ptr Constant pointer to the VADC Sample and hold module
   * @param  config Struct consisting of various step configurations.
@@ -1837,7 +1902,7 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co
 
   shs_ptr->STEPCFG = (uint32_t) config->stepcfg;
  }
-
+#endif
 
  /**
   * @param shs_ptr Constant pointer to the VADC Sample and hold module
@@ -1856,10 +1921,10 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co
  {
   XMC_ASSERT("XMC_VADC_GLOBAL_SHS_IsConverterReady:Wrong SHS Pointer",(shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0))
 
-  return((bool)((shs_ptr->STEPCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1));
+  return((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1));
  }
 
-
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
 /**
  * @param shs_ptr Constant pointer to the VADC Sample and hold module
  * @param group_num group number for which the accelerated mode needs to be enabled.<BR>Range: [0x0 to 0x1]
@@ -1914,7 +1979,7 @@ void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr
                                             XMC_VADC_GROUP_INDEX_t group_num,
                                             uint8_t sst_value);
 
-
+#endif
 /**
  * @param shs_ptr Constant pointer to the VADC Sample and hold module
  * @param  divs_value The clock divider value that is possible
@@ -1960,7 +2025,7 @@ void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,
                                        XMC_VADC_GROUP_INDEX_t group_num,
                                        uint8_t ch_num);
 
-
+#if(XMC_VADC_SHS_FULL_SET_REG == 1U)
 /**
  * @param shs_ptr Constant pointer to the VADC Sample and hold module
  * @param  max_calibration_time calibration time
@@ -2053,6 +2118,7 @@ void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const
                                                    XMC_VADC_GROUP_INDEX_t group_num,
                                                    XMC_VADC_SHS_GAIN_LEVEL_t gain_level,
                                                    uint8_t offset_calibration_value);
+#endif
 
 /**
  * @param shs_ptr Constant pointer to the VADC Sample and hold module
@@ -2269,6 +2335,81 @@ void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint3
  */
 void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group);
 
+/**
+ *
+ * @param group_ptr  Constant Pointer to the VADC Group waiting for ready signal
+ * @param eval_waiting_group  The VADC Group which expects a ready signal to start it's conversion.
+ * @param eval_origin_group  The VADC Group from which the eval_waiting_group will expect a ready signal
+ * @return None
+ *
+ * \par<b>Description:</b><br>
+ * Sets the ready signal in the eval_waiting_group .<BR>\n
+ * For Synchronized conversion all the slaves participating need to configure the ready signal.
+ * A slave group will also need to configure the ready signals coming from the other slave groups.
+ * A call to this API would configure the Sync.slave's EVAL Bits (GxSYNCTR.EVALy).
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_VADC_GROUP_CheckSlaveReadiness()<BR> XMC_VADC_GROUP_IgnoreSlaveReadiness()<BR>
+ */
+void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr,
+                                            uint32_t eval_waiting_group,
+                                            uint32_t eval_origin_group);
+
+/**
+ *
+ * @param group_ptr  Constant Pointer to the VADC Group
+ * @return
+ *         uint32_t EVAL bits for the group
+ *
+ * \par<b>Description:</b><br>
+ * Get the Eval bits of the group.<BR>\n
+ * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves.
+ * A call to this API would return the Sync EVAL Bits (GxSYNCTR.EVALy) which can be used to set in the slaves.
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_VADC_GROUP_CheckSlaveReadiness()<BR> XMC_VADC_GROUP_IgnoreSlaveReadiness()<BR>
+ */
+__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr)
+{
+  uint32_t eval_mask;
+  XMC_ASSERT("XMC_VADC_GROUP_GetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U)
+  eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk;
+#else
+  eval_mask = VADC_G_SYNCTR_EVALR1_Msk;
+#endif
+  return( group_ptr->SYNCTR & eval_mask);
+}
+
+/**
+ * @param group_ptr  Constant Pointer to the VADC Group
+ * @param eval_mask  mask to configure the eval bits
+ *                   Use XMC_VADC_SYNCTR_EVAL_t to create the mask.
+ * @return None
+ *
+ * \par<b>Description:</b><br>
+ * Set the Eval bits of the group.<BR>\n
+ * For Synchronized conversion the master's ready signal configuration must be copied onto the slaves.
+ * A call to this API would configure the Sync EVAL Bits (GxSYNCTR.EVALy).
+ *
+ * \par<b>Related APIs:</b><BR>
+ * XMC_VADC_GROUP_CheckSlaveReadiness()<BR> XMC_VADC_GROUP_IgnoreSlaveReadiness()<BR>
+ */
+__STATIC_INLINE void XMC_VADC_GROUP_SetSyncReadySignal(XMC_VADC_GROUP_t *const group_ptr, uint32_t mask)
+{
+  uint32_t eval_mask;
+  XMC_ASSERT("XMC_VADC_GROUP_SetSyncReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+#if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U)
+  eval_mask = VADC_G_SYNCTR_EVALR1_Msk | VADC_G_SYNCTR_EVALR2_Msk | VADC_G_SYNCTR_EVALR3_Msk;
+#else
+  eval_mask = VADC_G_SYNCTR_EVALR1_Msk;
+#endif
+  group_ptr->SYNCTR &= ~(eval_mask);
+  group_ptr->SYNCTR |= mask;
+}
+
 /**
  *
  * @param group_ptr   Constant pointer to the master VADC Group
@@ -2439,7 +2580,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_ExternalMuxControlInit(XMC_VADC_GROUP_t *con
 void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr,
                                                   const uint8_t boundary_flag_num,
                                                   const XMC_VADC_BOUNDARY_NODE_t node);
-#endif /* XMC_VADC_BOUNDARY_FLAG_SELECT */
+#endif
 
 /**
  * @param group_ptr Constant pointer to the VADC group
@@ -2488,7 +2629,7 @@ __STATIC_INLINE XMC_VADC_GROUP_CLASS_t XMC_VADC_GROUP_GetInputClass(XMC_VADC_GRO
 
   return (input_value);
 }
-#endif /* XMC_VADC_GROUP_AVAILABLE */
+#endif
 
 #if (XMC_VADC_GSCAN_AVAILABLE == 1U)
 /**
@@ -2553,6 +2694,28 @@ __STATIC_INLINE void XMC_VADC_GROUP_ScanDisableArbitrationSlot(XMC_VADC_GROUP_t
   group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN1_Msk);
 }
 
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *    bool  returns true if the arbitration is enabled else returns false.
+ *
+ * \par<b>Description:</b><br>
+ * Returns the arbitration status of the scan request source.<BR>\n
+ * If the scan request source must have its conversion request considered by the arbiter, it must participate in
+ * the arbitration rounds. Even if a load event occurs the scan channel can only be converted when the arbiter comes
+ * to the scan slot. A call to this API would return the status of the arbitration slot of scan.
+ * A call to this API would read the register bit field GxARBPR.ASEN1.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GROUP_ScanEnableArbitrationSlot(),<BR>  XMC_VADC_GROUP_ScanDisableArbitrationSlot()<BR>
+ */
+__STATIC_INLINE bool XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+  return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN1_Msk) >> VADC_G_ARBPR_ASEN1_Pos);
+}
+
 /**
  * @param group_ptr     Constant pointer to the VADC group
  * @param trigger_input  Choice of the input earmarked as a trigger line
@@ -2946,6 +3109,48 @@ __STATIC_INLINE void XMC_VADC_GROUP_ScanDisableExternalTrigger(XMC_VADC_GROUP_t
  *  None.
  */
 void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const uint32_t channel_num);
+
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Enables the scan request source event .<BR>
+ * By using this API the request source event will be activated for the scan request source.
+ * Other configurations w.r.t service node pointer are not done in this API.
+ * A call to this API would configure the register bit field GxASMR.ENSI.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GROUP_ScanDisableEvent(),<BR> XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()<BR>
+ */
+__STATIC_INLINE void XMC_VADC_GROUP_ScanEnableEvent(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_ScanEnableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+  group_ptr->ASMR |= ((uint32_t)VADC_G_ASMR_ENSI_Msk);
+}
+
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Disables the scan request source event .<BR>
+ * By using this API the request source event will be deactivated for the scan request source.
+ * Other configurations w.r.t service node pointer are not done in this API.
+ * A call to this API would configure the register bit field GxASMR.ENSI.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GROUP_ScanEnableEvent(),<BR> XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode()<BR>
+ */
+__STATIC_INLINE void XMC_VADC_GROUP_ScanDisableEvent(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_ScanDisableEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+  group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENSI_Msk);
+}
 #endif
 
 /**
@@ -3366,7 +3571,7 @@ __STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus(XMC_VADC_GLO
  */
 __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr)
 {
-  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger:Wrong Group Pointer", (global_ptr == VADC))
+  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC))
 
   global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_ENTR_Msk;
 }
@@ -3388,11 +3593,53 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger(XMC_VADC_GL
  */
 __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger(XMC_VADC_GLOBAL_t *const global_ptr)
 {
-  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger:Wrong Group Pointer", (global_ptr == VADC))
+  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger:Wrong Module Pointer", (global_ptr == VADC))
 
   global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENTR_Msk);
 }
 
+/**
+ * @param global_ptr       Pointer to the VADC module
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Enables the background scan request source event .<BR>
+ * By using this API the request source event will be activated for the background scan request source.
+ * Other configurations w.r.t service node pointer are not done in this API.
+ * A call to this API would configure the register bit field BRSMR.ENSI.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GLOBAL_BackgroundEnableEvent(),<BR> XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()<BR>
+ */
+__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundEnableEvent(XMC_VADC_GLOBAL_t *const global_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundEnableEvent:Wrong Module Pointer", (global_ptr == VADC))
+
+  global_ptr->BRSMR |= ((uint32_t)VADC_BRSMR_ENSI_Msk);
+}
+
+/**
+ * @param global_ptr     Pointer to the VADC module
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Disables the background scan request source event .<BR>
+ * By using this API the request source event will be deactivated for the background scan request source.
+ * Other configurations w.r.t service node pointer are not done in this API.
+ * A call to this API would configure the register bit field BRSMR.ENSI.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GROUP_BackgroundEnableEvent(),<BR> XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode()<BR>
+ */
+__STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundDisableEvent(XMC_VADC_GLOBAL_t *const global_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundDisableEvent:Wrong Module Pointer", (global_ptr == VADC))
+
+  global_ptr->BRSMR &= ~((uint32_t)VADC_BRSMR_ENSI_Msk);
+}
+
 #if (XMC_VADC_QUEUE_AVAILABLE == 1U)
 /**
  * @param group_ptr Pointer to the VADC group
@@ -3458,6 +3705,29 @@ __STATIC_INLINE void XMC_VADC_GROUP_QueueDisableArbitrationSlot(XMC_VADC_GROUP_t
   group_ptr->ARBPR &= ~((uint32_t)VADC_G_ARBPR_ASEN0_Msk);
 }
 
+
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *    bool  returns true if the arbitration is enabled else returns false.
+ *
+ * \par<b>Description:</b><br>
+ * Returns the arbitration status of the queue request source.<BR>\n
+ * If the queue request source must have its conversion request considered by the arbiter, it must participate in
+ * the arbitration rounds. Even if a load event occurs the queue channel can only be converted when the arbiter comes
+ * to the queue slot. A call to this API would return the status of the arbitration slot of queue.
+ * A call to this API would read the register bit field GxARBPR.ASEN1.
+ *
+ * \par<b>Related APIs:</b><br>
+ *  XMC_VADC_GROUP_QueueEnableArbitrationSlot(),<BR>  XMC_VADC_GROUP_QueueDisableArbitrationSlot()<BR>
+ */
+__STATIC_INLINE bool XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+
+  return ((group_ptr->ARBPR & (uint32_t)VADC_G_ARBPR_ASEN0_Msk) >> VADC_G_ARBPR_ASEN0_Pos);
+}
+
 /**
  * @param group_ptr     Constant pointer to the VADC group
  * @param input_num  Choice of the input earmarked as a trigger line
@@ -3756,7 +4026,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_QueueTriggerReqSrcEvent(XMC_VADC_GROUP_t *co
 __STATIC_INLINE void XMC_VADC_GROUP_QueueClearReqSrcEvent(XMC_VADC_GROUP_t *const group_ptr)
 {
   XMC_ASSERT("XMC_VADC_GROUP_QueueClearReqSrcEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
-  group_ptr->SEFCLR |= (uint32_t)VADC_G_SEFCLR_SEV0_Msk;
+  group_ptr->SEFCLR = (uint32_t)VADC_G_SEFCLR_SEV0_Msk;
 }
 
 /**
@@ -4072,6 +4342,25 @@ uint8_t XMC_VADC_GROUP_ChannelGetResultRegister(XMC_VADC_GROUP_t *const group_pt
  */
 void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num);
 
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *      uint32_t returns the asserted channel events
+ *
+ * \par<b>Description:</b><br>
+ * Returns the Channel event flag register.<BR>\n
+ * The return is merely the channel events which are asserted.
+ * A call to this API would read the register bit fields of GxCEFLAG.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_VADC_GROUP_ChannelClearEvent().
+ */
+__STATIC_INLINE uint32_t XMC_VADC_GROUP_ChannelGetAssertedEvents(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_ChannelGetAssertedEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+  return(group_ptr->CEFLAG);
+}
+
 /**
  * @param group_ptr     Constant pointer to the VADC group
  * @param ch_num   Channel whose channel event is to be acknowledged
@@ -4093,7 +4382,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_ChannelClearEvent(XMC_VADC_GROUP_t *const gr
 
   XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
   XMC_ASSERT("XMC_VADC_GROUP_ChannelClearEvent:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP))
-  group_ptr->CEFCLR |= (uint32_t)((uint32_t)1 << ch_num);
+  group_ptr->CEFCLR = (uint32_t)((uint32_t)1 << ch_num);
 }
 
 /**
@@ -4404,6 +4693,25 @@ __STATIC_INLINE void XMC_VADC_GROUP_TriggerResultEvent(XMC_VADC_GROUP_t *const g
   group_ptr->REFLAG = (uint32_t)((uint32_t)1 << res_reg);
 }
 
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *      uint32_t returns the asserted result events
+ *
+ * \par<b>Description:</b><br>
+ * Returns the Result event flag register.<BR>\n
+ * The return is merely the result events which are asserted.
+ * A call to this API would read the register bit fields of GxREFLAG.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_VADC_GROUP_TriggerResultEvent().
+ */
+__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAssertedResultEvents(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_GetAssertedResultEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+  return(group_ptr->REFLAG);
+}
+
 /**
  * @param group_ptr     Constant pointer to the VADC group
  * @param res_reg  Result Register for which the result event is being acknowledged
@@ -4529,6 +4837,50 @@ __STATIC_INLINE bool XMC_VADC_GROUP_IsResultRegisterInFifo(XMC_VADC_GROUP_t *con
              ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS))
   return( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk));
 }
+
+#if XMC_VADC_RESULT_PRIORITY_AVAILABLE == 1U
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @param res_reg  Result Registers which need to be set for priority conversions
+ *                 Bit location 0..15 represents Result Register-0..15 respectively.
+ *                 To add the result register as priority.
+ *                 Passing a 0x0 will clear all the selected channels
+ *                 <BR>Range: [0x0 to 0xFFFF]
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Prioritize a Result register for group conversions.<BR>\n
+ * Applications that need to reserve certain result registers only for Queue and scan request sources should
+ * use this API. A call to this API would access the register bit fields of GxRRASS.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_VADC_GROUP_GetResultRegPriority().
+ */
+__STATIC_INLINE void XMC_VADC_GROUP_SetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_mask)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_SetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+  group_ptr->RRASS = (uint32_t)res_mask;
+}
+
+/**
+ * @param group_ptr     Constant pointer to the VADC group
+ * @return
+ *    None
+ *
+ * \par<b>Description:</b><br>
+ * Get the priority of all Result register.<BR>\n
+ * A call to this API would access the register bit fields of GxRRASS.
+ *
+ * \par<b>Related APIs:</b><br>
+ * XMC_VADC_GROUP_SetResultRegPriority().
+ */
+__STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr)
+{
+  XMC_ASSERT("XMC_VADC_GROUP_GetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr))
+  return(group_ptr->RRASS);
+}
+#endif
 #endif
 
 #ifdef __cplusplus
@@ -4544,4 +4896,4 @@ __STATIC_INLINE bool XMC_VADC_GROUP_IsResultRegisterInFifo(XMC_VADC_GROUP_t *con
  */
 
  
-#endif /* XMC_VADC_H */
+#endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_vadc_map.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_vadc_map.h
- * @date 2015-10-27
+ * @date 2015-12-01
  *
  * @cond
 *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -39,6 +39,13 @@
  * 2015-02-15:
  *     - Initial version
  *
+ * 2015-12-01:
+ *     - Added:
+ *     - XMC4300 device supported
+ *
+ *     - Fixed: 
+ *     - Wrong MACRO name corrected for XMC4200/4100 devices.
+ *       XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE
  * @endcond 
  *
  */
@@ -56,23 +63,23 @@ extern "C" {
  * MACROS
  *********************************************************************************************************************/
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3         XMC_VADC_REQ_GT_A
-#define XMC_CCU_40_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_40_ST2         XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_ST1  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_ST1         XMC_VADC_REQ_GT_C
-#define XMC_CCU_40_ST0  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_40_ST0         XMC_VADC_REQ_GT_D
-#define XMC_ERU_0_PDOUT2  	    XMC_VADC_REQ_GT_K
+#define XMC_ERU_0_PDOUT2       XMC_VADC_REQ_GT_K
-#define XMC_ERU_0_PDOUT3	    XMC_VADC_REQ_GT_L
+#define XMC_ERU_0_PDOUT3       XMC_VADC_REQ_GT_L
-#define XMC_ERU_0_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_0_PDOUT0       XMC_VADC_REQ_GT_O
-#define XMC_ERU_0_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_0_PDOUT1       XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2         XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3         XMC_VADC_REQ_TR_B
-#define XMC_ERU_0_IOUT2         XMC_VADC_REQ_TR_G
+#define XMC_ERU_0_IOUT2        XMC_VADC_REQ_TR_G
-#define XMC_ERU_0_IOUT3         XMC_VADC_REQ_TR_H
+#define XMC_ERU_0_IOUT3        XMC_VADC_REQ_TR_H
-#define XMC_ERU_0_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_0_IOUT0        XMC_VADC_REQ_TR_M
-#define XMC_ERU_0_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_0_IOUT1        XMC_VADC_REQ_TR_N
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL         XMC_VADC_REQ_TR_P
 
 #endif
 
@@ -80,57 +87,57 @@ extern "C" {
 #if (UC_SERIES == XMC12)
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_40_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_40_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_ST1  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_ST1          XMC_VADC_REQ_GT_C
-#define XMC_CCU_40_ST0  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_40_ST0          XMC_VADC_REQ_GT_D
-#define XMC_LEDTS_0_FN         	XMC_VADC_REQ_GT_I
+#define XMC_LEDTS_0_FN          XMC_VADC_REQ_GT_I
-#define XMC_LEDTS_1_FN  	    XMC_VADC_REQ_GT_J
+#define XMC_LEDTS_1_FN          XMC_VADC_REQ_GT_J
-#define XMC_ERU_0_PDOUT2  	    XMC_VADC_REQ_GT_K
+#define XMC_ERU_0_PDOUT2        XMC_VADC_REQ_GT_K
-#define XMC_ERU_0_PDOUT3	    XMC_VADC_REQ_GT_L
+#define XMC_ERU_0_PDOUT3        XMC_VADC_REQ_GT_L
-#define XMC_ERU_0_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_0_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_0_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_0_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
 #define XMC_BCCU0_TRIGOUT       XMC_VADC_REQ_TR_F
 #define XMC_ERU_0_IOUT2         XMC_VADC_REQ_TR_G
 #define XMC_ERU_0_IOUT3         XMC_VADC_REQ_TR_H
-#define XMC_ERU_0_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_0_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_0_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_0_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 
 #if (UC_SERIES == XMC13)
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_40_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_40_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_ST1  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_ST1          XMC_VADC_REQ_GT_C
-#define XMC_CCU_40_ST0  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_40_ST0          XMC_VADC_REQ_GT_D
-#define XMC_CCU_80_ST3_A  	    XMC_VADC_REQ_GT_E
+#define XMC_CCU_80_ST3_A        XMC_VADC_REQ_GT_E
-#define XMC_CCU_81_ST3  	    XMC_VADC_REQ_GT_F
+#define XMC_CCU_81_ST3          XMC_VADC_REQ_GT_F
-#define XMC_ERU_0_PDOUT2  	    XMC_VADC_REQ_GT_K
+#define XMC_ERU_0_PDOUT2        XMC_VADC_REQ_GT_K
-#define XMC_ERU_0_PDOUT3  	    XMC_VADC_REQ_GT_L
+#define XMC_ERU_0_PDOUT3        XMC_VADC_REQ_GT_L
-#define XMC_CCU_80_ST0	        XMC_VADC_REQ_GT_M
+#define XMC_CCU_80_ST0          XMC_VADC_REQ_GT_M
-#define XMC_CCU_80_ST1  	    XMC_VADC_REQ_GT_N
+#define XMC_CCU_80_ST1          XMC_VADC_REQ_GT_N
-#define XMC_ERU_0_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_0_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_0_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_0_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
 #define XMC_BCCU0_TRIGOUT       XMC_VADC_REQ_TR_F
 #define XMC_ERU_0_IOUT2         XMC_VADC_REQ_TR_G
 #define XMC_ERU_0_IOUT3         XMC_VADC_REQ_TR_H
-#define XMC_CCU_80_SR2         	XMC_VADC_REQ_TR_I
+#define XMC_CCU_80_SR2          XMC_VADC_REQ_TR_I
-#define XMC_CCU_80_SR3  	    XMC_VADC_REQ_TR_J
+#define XMC_CCU_80_SR3          XMC_VADC_REQ_TR_J
-#define XMC_ERU_0_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_0_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_0_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_0_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_POSIF_0_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_0_SR1         XMC_VADC_REQ_TR_O
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 
@@ -138,163 +145,168 @@ extern "C" {
 #if (UC_SERIES == XMC14)
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_40_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_40_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_ST1  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_ST1          XMC_VADC_REQ_GT_C
-#define XMC_CCU_40_ST0  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_40_ST0          XMC_VADC_REQ_GT_D
-#define XMC_CCU_80_ST3_A  	    XMC_VADC_REQ_GT_E
+#define XMC_CCU_80_ST3_A        XMC_VADC_REQ_GT_E
-#define XMC_CCU_81_ST3  	    XMC_VADC_REQ_GT_F
+#define XMC_CCU_81_ST3          XMC_VADC_REQ_GT_F
-#define XMC_LEDTS0_FN    	    XMC_VADC_REQ_GT_I
+#define XMC_LEDTS0_FN           XMC_VADC_REQ_GT_I
-#define XMC_LEDTS1_FN  	        XMC_VADC_REQ_GT_J
+#define XMC_LEDTS1_FN           XMC_VADC_REQ_GT_J
-#define XMC_ERU_0_PDOUT2  	    XMC_VADC_REQ_GT_K
+#define XMC_ERU_0_PDOUT2        XMC_VADC_REQ_GT_K
-#define XMC_ERU_0_PDOUT3  	    XMC_VADC_REQ_GT_L
+#define XMC_ERU_0_PDOUT3        XMC_VADC_REQ_GT_L
-#define XMC_CCU_80_ST0	        XMC_VADC_REQ_GT_M
+#define XMC_CCU_80_ST0          XMC_VADC_REQ_GT_M
-#define XMC_CCU_80_ST1  	    XMC_VADC_REQ_GT_N
+#define XMC_CCU_80_ST1          XMC_VADC_REQ_GT_N
-#define XMC_ERU_0_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_0_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_0_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_0_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
 #define XMC_BCCU0_TRIGOUT       XMC_VADC_REQ_TR_F
 #define XMC_ERU_0_IOUT2         XMC_VADC_REQ_TR_G
 #define XMC_ERU_0_IOUT3         XMC_VADC_REQ_TR_H
-#define XMC_CCU_80_SR2         	XMC_VADC_REQ_TR_I
+#define XMC_CCU_80_SR2          XMC_VADC_REQ_TR_I
-#define XMC_CCU_80_SR3  	    XMC_VADC_REQ_TR_J
+#define XMC_CCU_80_SR3          XMC_VADC_REQ_TR_J
-#define XMC_ERU_0_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_0_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_0_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_0_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_POSIF_0_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_0_SR1         XMC_VADC_REQ_TR_O
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 
 
-#if ( (UC_SERIES == XMC42)||(UC_SERIES == XMC41) )
+#if ( (UC_SERIES == XMC42)||(UC_SERIES == XMC41) || (UC_SERIES == XMC43) )
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_41_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_41_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_SR0  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_SR0          XMC_VADC_REQ_GT_C
-#define XMC_CCU_41_SR1  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_41_SR1          XMC_VADC_REQ_GT_D
-#define XMC_CCU_80_ST3_A  	    XMC_VADC_REQ_GT_E
+#define XMC_CCU_80_ST3_A        XMC_VADC_REQ_GT_E
-#define XMC_CCU_80_ST3_B  	    XMC_VADC_REQ_GT_F
+#define XMC_CCU_80_ST3_B        XMC_VADC_REQ_GT_F
-#define XMC_DAC_0_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_0_SGN           XMC_VADC_REQ_GT_I
-#define XMC_DAC_1_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_1_SGN           XMC_VADC_REQ_GT_I
-#define XMC_LEDTS_FN         	XMC_VADC_REQ_GT_J
+#define XMC_LEDTS_FN            XMC_VADC_REQ_GT_J
-#define XMC_VADC_G0_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G0_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G1_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G1_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G0_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G0_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G3_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G1_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_CCU_80_SR0	        XMC_VADC_REQ_GT_M
+#define XMC_CCU_80_SR0          XMC_VADC_REQ_GT_M
-#define XMC_CCU_80_SR1  	    XMC_VADC_REQ_GT_N
+#define XMC_CCU_80_SR1          XMC_VADC_REQ_GT_N
-#define XMC_ERU_1_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_1_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_1_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_1_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
-#define XMC_CCU_41_SR2  	    XMC_VADC_REQ_TR_C
+#define XMC_CCU_41_SR2          XMC_VADC_REQ_TR_C
-#define XMC_CCU_41_SR3  	    XMC_VADC_REQ_TR_D
+#define XMC_CCU_41_SR3          XMC_VADC_REQ_TR_D
-#define XMC_CCU_80_SR2         	XMC_VADC_REQ_TR_I
+#define XMC_CCU_80_SR2          XMC_VADC_REQ_TR_I
-#define XMC_CCU_80_SR3  	    XMC_VADC_REQ_TR_J
+#define XMC_CCU_80_SR3          XMC_VADC_REQ_TR_J
-#define XMC_ERU_1_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_1_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_1_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_1_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_POSIF_0_SR1  	    XMC_VADC_REQ_TR_O
+#if (UC_SERIES == XMC43)
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_ERU_1_IOUT2         XMC_VADC_REQ_TR_N
+#endif
+#if (UC_SERIES != XMC43)
+#define XMC_POSIF_0_SR1         XMC_VADC_REQ_TR_O
+#endif
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 
 #if ( UC_SERIES == XMC44 ) || ( UC_SERIES == XMC48)
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_41_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_41_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_SR0  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_SR0          XMC_VADC_REQ_GT_C
-#define XMC_CCU_41_SR1  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_41_SR1          XMC_VADC_REQ_GT_D
-#define XMC_CCU_80_ST3_A  	    XMC_VADC_REQ_GT_E
+#define XMC_CCU_80_ST3_A        XMC_VADC_REQ_GT_E
-#define XMC_CCU_80_ST3_B  	    XMC_VADC_REQ_GT_F
+#define XMC_CCU_80_ST3_B        XMC_VADC_REQ_GT_F
-#define XMC_CCU_81_ST3_A       	XMC_VADC_REQ_GT_G
+#define XMC_CCU_81_ST3_A        XMC_VADC_REQ_GT_G
-#define XMC_CCU_81_ST3_B       	XMC_VADC_REQ_GT_H
+#define XMC_CCU_81_ST3_B        XMC_VADC_REQ_GT_H
-#define XMC_DAC_0_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_0_SGN           XMC_VADC_REQ_GT_I
-#define XMC_DAC_1_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_1_SGN           XMC_VADC_REQ_GT_I
-#define XMC_LEDTS_FN         	XMC_VADC_REQ_GT_J
+#define XMC_LEDTS_FN            XMC_VADC_REQ_GT_J
-#define XMC_VADC_G0_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G0_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G1_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G1_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G2_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G2_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G3_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G3_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G0_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G0_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G1_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G1_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G2_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G2_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G3_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G3_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_CCU_80_SR0	        XMC_VADC_REQ_GT_M
+#define XMC_CCU_80_SR0          XMC_VADC_REQ_GT_M
-#define XMC_CCU_80_SR1  	    XMC_VADC_REQ_GT_N
+#define XMC_CCU_80_SR1          XMC_VADC_REQ_GT_N
-#define XMC_ERU_1_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_1_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_1_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_1_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
-#define XMC_CCU_41_SR2  	    XMC_VADC_REQ_TR_C
+#define XMC_CCU_41_SR2          XMC_VADC_REQ_TR_C
-#define XMC_CCU_41_SR3  	    XMC_VADC_REQ_TR_D
+#define XMC_CCU_41_SR3          XMC_VADC_REQ_TR_D
-#define XMC_CCU_42_SR3  	    XMC_VADC_REQ_TR_E
+#define XMC_CCU_42_SR3          XMC_VADC_REQ_TR_E
 #define XMC_CCU_43_SR3          XMC_VADC_REQ_TR_F
-#define XMC_CCU_80_SR2         	XMC_VADC_REQ_TR_I
+#define XMC_CCU_80_SR2          XMC_VADC_REQ_TR_I
-#define XMC_CCU_80_SR3  	    XMC_VADC_REQ_TR_J
+#define XMC_CCU_80_SR3          XMC_VADC_REQ_TR_J
-#define XMC_CCU_81_SR2  	    XMC_VADC_REQ_TR_K
+#define XMC_CCU_81_SR2          XMC_VADC_REQ_TR_K
-#define XMC_CCU_81_SR3	        XMC_VADC_REQ_TR_L
+#define XMC_CCU_81_SR3          XMC_VADC_REQ_TR_L
-#define XMC_ERU_1_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_1_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_1_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_1_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_ERU_1_IOUT2  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_1_IOUT2         XMC_VADC_REQ_TR_N
-#define XMC_POSIF_0_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_0_SR1         XMC_VADC_REQ_TR_O
-#define XMC_POSIF_1_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_1_SR1         XMC_VADC_REQ_TR_O
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 
 #if ( UC_SERIES == XMC45 )
 
 /*  Group request source Gating input connection mappings */
-#define XMC_CCU_40_ST3 	        XMC_VADC_REQ_GT_A
+#define XMC_CCU_40_ST3          XMC_VADC_REQ_GT_A
-#define XMC_CCU_41_ST2  	    XMC_VADC_REQ_GT_B
+#define XMC_CCU_41_ST2          XMC_VADC_REQ_GT_B
-#define XMC_CCU_40_SR0  	    XMC_VADC_REQ_GT_C
+#define XMC_CCU_40_SR0          XMC_VADC_REQ_GT_C
-#define XMC_CCU_41_SR1  	    XMC_VADC_REQ_GT_D
+#define XMC_CCU_41_SR1          XMC_VADC_REQ_GT_D
-#define XMC_CCU_80_ST3_A  	    XMC_VADC_REQ_GT_E
+#define XMC_CCU_80_ST3_A        XMC_VADC_REQ_GT_E
-#define XMC_CCU_80_ST3_B  	    XMC_VADC_REQ_GT_F
+#define XMC_CCU_80_ST3_B        XMC_VADC_REQ_GT_F
-#define XMC_CCU_81_ST3_A       	XMC_VADC_REQ_GT_G
+#define XMC_CCU_81_ST3_A        XMC_VADC_REQ_GT_G
-#define XMC_CCU_81_ST3_B       	XMC_VADC_REQ_GT_H
+#define XMC_CCU_81_ST3_B        XMC_VADC_REQ_GT_H
-#define XMC_DAC_0_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_0_SGN           XMC_VADC_REQ_GT_I
-#define XMC_DAC_1_SGN         	XMC_VADC_REQ_GT_I
+#define XMC_DAC_1_SGN           XMC_VADC_REQ_GT_I
-#define XMC_LEDTS_FN         	XMC_VADC_REQ_GT_J
+#define XMC_LEDTS_FN            XMC_VADC_REQ_GT_J
-#define XMC_VADC_G0_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G0_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G1_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G1_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G2_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G2_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G3_BLOUT0  	XMC_VADC_REQ_GT_K
+#define XMC_VADC_G3_BLOUT0      XMC_VADC_REQ_GT_K
-#define XMC_VADC_G0_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G0_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G1_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G1_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G2_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G2_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_VADC_G3_SAMPLE  	XMC_VADC_REQ_GT_L
+#define XMC_VADC_G3_SAMPLE      XMC_VADC_REQ_GT_L
-#define XMC_CCU_80_SR0	        XMC_VADC_REQ_GT_M
+#define XMC_CCU_80_SR0          XMC_VADC_REQ_GT_M
-#define XMC_CCU_80_SR1  	    XMC_VADC_REQ_GT_N
+#define XMC_CCU_80_SR1          XMC_VADC_REQ_GT_N
-#define XMC_ERU_1_PDOUT0  	    XMC_VADC_REQ_GT_O
+#define XMC_ERU_1_PDOUT0        XMC_VADC_REQ_GT_O
-#define XMC_ERU_1_PDOUT1	    XMC_VADC_REQ_GT_P
+#define XMC_ERU_1_PDOUT1        XMC_VADC_REQ_GT_P
 
 /* Group request source Trigger input connection mappings */
-#define XMC_CCU_40_SR2 	        XMC_VADC_REQ_TR_A
+#define XMC_CCU_40_SR2          XMC_VADC_REQ_TR_A
-#define XMC_CCU_40_SR3  	    XMC_VADC_REQ_TR_B
+#define XMC_CCU_40_SR3          XMC_VADC_REQ_TR_B
-#define XMC_CCU_41_SR2  	    XMC_VADC_REQ_TR_C
+#define XMC_CCU_41_SR2          XMC_VADC_REQ_TR_C
-#define XMC_CCU_41_SR3  	    XMC_VADC_REQ_TR_D
+#define XMC_CCU_41_SR3          XMC_VADC_REQ_TR_D
-#define XMC_CCU_42_SR3  	    XMC_VADC_REQ_TR_E
+#define XMC_CCU_42_SR3          XMC_VADC_REQ_TR_E
 #define XMC_CCU_43_SR3          XMC_VADC_REQ_TR_F
-#define XMC_CCU_80_SR2         	XMC_VADC_REQ_TR_I
+#define XMC_CCU_80_SR2          XMC_VADC_REQ_TR_I
-#define XMC_CCU_80_SR3  	    XMC_VADC_REQ_TR_J
+#define XMC_CCU_80_SR3          XMC_VADC_REQ_TR_J
-#define XMC_CCU_81_SR2  	    XMC_VADC_REQ_TR_K
+#define XMC_CCU_81_SR2          XMC_VADC_REQ_TR_K
-#define XMC_CCU_81_SR3	        XMC_VADC_REQ_TR_L
+#define XMC_CCU_81_SR3          XMC_VADC_REQ_TR_L
-#define XMC_ERU_1_IOUT0  	    XMC_VADC_REQ_TR_M
+#define XMC_ERU_1_IOUT0         XMC_VADC_REQ_TR_M
-#define XMC_ERU_1_IOUT1  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_1_IOUT1         XMC_VADC_REQ_TR_N
-#define XMC_ERU_1_IOUT2  	    XMC_VADC_REQ_TR_N
+#define XMC_ERU_1_IOUT2         XMC_VADC_REQ_TR_N
-#define XMC_POSIF_0_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_0_SR1         XMC_VADC_REQ_TR_O
-#define XMC_POSIF_1_SR1  	    XMC_VADC_REQ_TR_O
+#define XMC_POSIF_1_SR1         XMC_VADC_REQ_TR_O
-#define XMC_REQ_GT_SEL	        XMC_VADC_REQ_TR_P
+#define XMC_REQ_GT_SEL          XMC_VADC_REQ_TR_P
 
 #endif
 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/inc/xmc_wdt.h

@@ -1,12 +1,12 @@
 /**
  * @file xmc_wdt.h
- * @date 2015-10-27
+ * @date 2015-08-06
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc4_eru.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_eru.c
- * @date 2015-10-27
+ * @date 2015-02-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc4_flash.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_flash.c
- * @date 2015-10-27
+ * @date 2016-01-08
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -49,6 +49,17 @@
  *       3. XMC_FLASH_EraseUCB
  *       4. XMC_FLASH_ResumeProtection
  *       5. XMC_FLASH_RepairPhysicalSector
+ *
+ * 2016-01-08: 
+ *     - Wait until operation is finished for the next functions:
+ *       1. XMC_FLASH_InstallProtection
+ *       2. XMC_FLASH_ConfirmProtection
+ *       3. XMC_FLASH_ProgramPage
+ *       4. XMC_FLASH_EraseSector
+ *       5. XMC_FLASH_ErasePhysicalSector
+ *       6. XMC_FLASH_EraseUCB
+ *     - Fix XMC_FLASH_VerifyReadProtection and XMC_FLASH_VerifyWriteProtection
+ *
  * @endcond 
  *
  */
@@ -63,13 +74,23 @@
 
 #define XMC_FLASH_PROTECTION_CONFIGURATION_WORDS (8UL) /* Used to upadte the assembly buffer during protection 
                                                           configuration */
-#define XMC_FLASH_PROTECTION_CONFIRMATION_OFFSET (512UL) /* Offset address for UCB page */
+#define XMC_FLASH_PROT_CONFIRM_OFFSET (512UL) /* Offset address for UCB page */
-#define XMC_FLASH_PROTECTION_CONFIRMATION_WORDS  (4UL)
+#define XMC_FLASH_PROT_CONFIRM_WORDS  (4UL)
-#define XMC_FLASH_PROTECTION_CONFIRMATION_CODE   (0x8AFE15C3UL)
+#define XMC_FLASH_PROT_CONFIRM_CODE   (0x8AFE15C3UL)
 
 /*********************************************************************************************************************
  * LOCAL FUNCTIONS
  ********************************************************************************************************************/
+void XMC_FLASH_lEnterPageModeCommand(void);
+void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word);
+void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address);
+void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address);
+void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address);
+void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1);
+void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1);
+void XMC_FLASH_lRepairPhysicalSectorCommand(void);
+void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address);
+void XMC_FLASH_lClearStatusCommand(void);
 
 /*
  * Command to program the PFLASH in to page mode, so that assembly buffer is used 
@@ -79,7 +100,7 @@ void XMC_FLASH_lEnterPageModeCommand(void)
   volatile uint32_t *address;
 
   address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
-  *address = 0x50;
+  *address = (uint32_t)0x50U;
 }
 
 /*
@@ -247,17 +268,20 @@ void XMC_FLASH_DisableEvent(const uint32_t event_msk)
  */
 void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data)
 {
-  uint32_t index;
+  uint32_t idx;
 
   XMC_FLASH_lClearStatusCommand();  
   XMC_FLASH_lEnterPageModeCommand();
 
-  for (index = 0; index < XMC_FLASH_WORDS_PER_PAGE; index += 2)
+  for (idx = 0U; idx < XMC_FLASH_WORDS_PER_PAGE; idx += 2U)
   {
-    XMC_FLASH_lLoadPageCommand(data[index], data[index + 1]);
+    XMC_FLASH_lLoadPageCommand(data[idx], data[idx + 1U]);
   }
 
   XMC_FLASH_lWritePageCommand(address);    
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -267,6 +291,9 @@ void XMC_FLASH_EraseSector(uint32_t *address)
 {
   XMC_FLASH_lClearStatusCommand();
   XMC_FLASH_lEraseSectorCommand(address);
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -319,6 +346,9 @@ void XMC_FLASH_ErasePhysicalSector(uint32_t *address)
 {
   XMC_FLASH_lClearStatusCommand();
   XMC_FLASH_lErasePhysicalSectorCommand(address);
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -349,6 +379,9 @@ void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address)
   *address = 0x55U;
   address = ucb_sector_start_address;
   *address = 0xc0U;
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -370,9 +403,9 @@ void XMC_FLASH_InstallProtection(uint8_t user,
 	                             uint32_t password_0,
                                  uint32_t password_1)
 {
-  uint32_t index; 
+  uint32_t idx;
   
-  XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U));
+  XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U))
 
   XMC_FLASH_lEnterPageModeCommand();
 
@@ -381,12 +414,15 @@ void XMC_FLASH_InstallProtection(uint8_t user,
   XMC_FLASH_lLoadPageCommand(password_0, password_1);
   XMC_FLASH_lLoadPageCommand(password_0, password_1);
   
-  for (index = 0; index < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); index += 2)
+  for (idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); idx += 2U)
   {
     XMC_FLASH_lLoadPageCommand(0UL, 0UL);
   }
 
   XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB)));
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -394,23 +430,26 @@ void XMC_FLASH_InstallProtection(uint8_t user,
  */
 void XMC_FLASH_ConfirmProtection(uint8_t user)
 {
-  uint32_t index;
+  uint32_t idx;
 
-  XMC_ASSERT(" XMC_FLASH_ConfirmProtection: User level out of range", (user < 3U));
+  XMC_ASSERT(" XMC_FLASH_ConfirmProtection: User level out of range", (user < 3U))
 
   XMC_FLASH_lEnterPageModeCommand();
 
-  XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROTECTION_CONFIRMATION_CODE, 0U);
+  XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U);
-  XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROTECTION_CONFIRMATION_CODE, 0U);
+  XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U);
 
   /* Fill the rest of page buffer with zeros*/
-  for (index = 0UL; index < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIRMATION_WORDS); index += 2)
+  for (idx = 0UL; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROT_CONFIRM_WORDS); idx += 2U)
   {
     XMC_FLASH_lLoadPageCommand(0UL, 0UL);
   }
 
   XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + 
-                                 (user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROTECTION_CONFIRMATION_OFFSET));
+                                 (user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROT_CONFIRM_OFFSET));
+
+  /* wait until the operation is completed */
+  while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
 }
 
 /*
@@ -418,11 +457,18 @@ void XMC_FLASH_ConfirmProtection(uint8_t user)
  */
 bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1)
 {
-  XMC_FLASH_lClearStatusCommand();
+  bool status = false;
-  XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1);
+  
+  /* Check if read protection is installed */
+  if ((XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) != 0U)
+  {  
+    XMC_FLASH_lClearStatusCommand();
+    XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1);
 
-  return (bool)((XMC_FLASH_GetStatus() & XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) && 
+    status = (bool)(XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE);
-                (FLASH0->PROCON0 & XMC_FLASH_PROTECTION_READ_GLOBAL));
+  }
+
+  return status;
 }
 
 /*
@@ -434,17 +480,22 @@ bool XMC_FLASH_VerifyWriteProtection(uint32_t user,
                                      uint32_t password_0, 
                                      uint32_t password_1)
 {
-  uint32_t *flash_procon_ptr;
+  bool status = false;
+  uint32_t *flash_procon_ptr = (uint32_t *)(void*)(&(FLASH0->PROCON0) + user);
 
-  XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 3U));
+  XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 2U))
 
-  flash_procon_ptr = (uint32_t *)(&(FLASH0->PROCON0) + user);
+  /* Check if write protection for selected user is installed */
+  if ((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPROIN0_Pos + user))) != 0U)
+  {  
+    XMC_FLASH_lClearStatusCommand();
+    XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1);
+    
+    status = (bool)((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPRODIS0_Pos + user)))) &&
+             (*flash_procon_ptr == (protection_mask & (uint32_t)(~(uint32_t)XMC_FLASH_PROTECTION_READ_GLOBAL)));
+  }
 
-  XMC_FLASH_lClearStatusCommand();
+  return status;
-  XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1);
-
-  return (bool)((XMC_FLASH_GetStatus() & (1U << (FLASH_FSR_WPRODIS0_Pos + user))) && 
-                 (*flash_procon_ptr == (protection_mask & ~XMC_FLASH_PROTECTION_READ_GLOBAL)));
 }
 
 /*

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc4_gpio.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_gpio.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc4_rtc.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc4_rtc.c
- * @date 2015-10-27
+ * @date 2016-03-09
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -39,6 +39,9 @@
  * 2015-02-20:
  *     - Initial <br>
  *      
+ * 2016-03-09:
+ *     - Optimize write only registers
+ *      
  * @endcond 
  *
  */
@@ -161,7 +164,7 @@ void XMC_RTC_ClearEvent(const uint32_t event)
   {
     /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
   }
-  RTC->CLRSR |= event;
+  RTC->CLRSR = event;
 }
 
 #endif /* UC_FAMILY == XMC4 */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_acmp.c

@@ -0,0 +1,119 @@
+/**
+ * @file xmc_acmp.c
+ * @date 2015-06-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2014-12-10:
+ *     - Initial <br>
+ * 2015-02-20:
+ *     - Removed unused declarations<br> 
+ * 2015-05-08:
+ *     - Fixed sequence problem of low power mode in XMC_ACMP_Init() API<br>
+ *     - Fixed wrong register setting in XMC_ACMP_SetInput() API<br> 
+ *     - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
+ *       Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.<br>
+ * 2015-06-04:
+ *     - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API. <br>
+ *     - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below<br> 
+ *       (a)XMC_ACMP_EnableReferenceDivider <br>
+ *       (b)XMC_ACMP_DisableReferenceDivider <br> 
+ *       (c)XMC_ACMP_SetInput <br> 
+ *     - Optimized enable and disable API's and moved to header file as static inline APIs.
+ *     - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure.
+ * 2015-06-20: 
+ *     - Removed definition of GetDriverVersion API 
+ * @endcond 
+ *
+ */
+
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ ********************************************************************************************************************/
+#include <xmc_acmp.h>
+
+/* If ACMP is available*/
+#if defined (COMPARATOR)
+
+/*********************************************************************************************************************
+ * MACROS
+ ********************************************************************************************************************/
+
+#define XMC_ACMP_INSTANCE_1    (1U) /* Instance number for Slice-1 */
+
+/*********************************************************************************************************************
+ * API IMPLEMENTATION
+ ********************************************************************************************************************/
+
+/* API to initialize an instance of ACMP module */
+void XMC_ACMP_Init(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_CONFIG_t *const config)
+{
+
+  XMC_ASSERT("XMC_ACMP_Init:NULL Configuration", (config != (XMC_ACMP_CONFIG_t *)NULL))
+  XMC_ASSERT("XMC_ACMP_Init:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
+  XMC_ASSERT("XMC_ACMP_Init:Wrong instance number", XMC_ACMP_CHECK_INSTANCE(instance) )
+
+  /*
+   * Initializes the comparator with configuration supplied. Low power node setting is retained during initialization.
+   * All the instances passed are handled with low power setting, to avoid conditional check for ACMP0 instance.
+   * This reduces the code size. No side effects, because this register bit field is empty for other instances.
+   */
+  peripheral->ANACMP[instance] = ((peripheral->ANACMP[instance] & (uint32_t)COMPARATOR_ANACMP0_CMP_LPWR_Msk)) |
+                                 (uint32_t)config->anacmp;
+}
+
+/* API to select INP source */
+void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, XMC_ACMP_INP_SOURCE_t source)
+{
+  XMC_ASSERT("XMC_ACMP_SetInput:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral))
+  XMC_ASSERT("XMC_ACMP_SetInput:Wrong instance number", ((instance != XMC_ACMP_INSTANCE_1) &&
+                                                          XMC_ACMP_CHECK_INSTANCE(instance)) )
+  XMC_ASSERT("XMC_ACMP_SetInput:Wrong input source", ((source == XMC_ACMP_INP_SOURCE_STANDARD_PORT) ||
+                                                      (source == XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT)) )
+
+  /*
+   * Three options of Input Setting are listed below
+   * 1. The comparator inputs aren't connected to other comparator inputs
+   * 2. Can program the comparators to connect ACMP0.INP to ACMP1.INP in XMC1200 AA or XMC1300 AA
+   *    Can program the comparators to connect ACMP0.INN to ACMP1.INP in XMC1200 AB or XMC1300 AB or XMC1400 AA
+   * 3. Can program the comparators to connect ACMP2.INP to ACMP1.INP
+   * 4. Can program the comparators to connect ACMP3.INP to ACMP1.INP in XMC1400
+   */
+  peripheral->ANACMP[instance] = ((peripheral->ANACMP[instance] & (uint32_t)(~COMPARATOR_ANACMP0_ACMP0_SEL_Msk))) |
+                                 (uint32_t)source;
+}
+
+#endif /* #ifdef ACMP_AVAILABLE */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_bccu.c

@@ -0,0 +1,577 @@
+/**
+ * @file xmc_bccu.c
+ * @date 2015-06-20
+ *
+ * @cond
+  *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-02-19:
+ *     - Initial draft <br>
+ *
+ * 2015-05-08:
+ *     - Minor bug fixes in following APIs: XMC_BCCU_ConcurrentStartDimming(), XMC_BCCU_ConcurrentAbortDimming(),
+ *               XMC_BCCU_SetGlobalDimmingLevel() <br>
+ *     
+ * 2015-06-20:
+ *     - Removed version macros and declaration of GetDriverVersion API
+ *
+ * <b>Detailed description of file:</b><br>
+ * APIs for the functional blocks of BCCU have been defined:<br>
+ * -- GLOBAL configuration <br>
+ * -- Clock configuration, Function/Event configuration, Interrupt configuration <br>
+ *
+ * @endcond
+ *
+ */
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ ********************************************************************************************************************/
+#include <xmc_bccu.h>
+
+#if defined(BCCU0)
+#include <xmc_scu.h>
+
+/*********************************************************************************************************************
+ * MACROS
+ ********************************************************************************************************************/
+#define XMC_BCCU_NO_OF_CHANNELS    (9U)
+#define XMC_BCCU_CHANNEL_MASK      ((0x1 << XMC_BCCU_NO_OF_CHANNELS)-1)
+#define XMC_BCCU_NO_OF_DIM_ENGINE  (3U)
+#define XMC_BCCU_DIM_ENGINE_MASK   (((0x1 << XMC_BCCU_NO_OF_DIM_ENGINE)-1))
+
+/*********************************************************************************************************************
+ * ENUMS
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * DATA STRUCTURES
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * GLOBAL DATA
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * LOCAL/UTILITY ROUTINES
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * API IMPLEMENTATION
+ ********************************************************************************************************************/
+
+/*
+ * API to initialise the global resources of a BCCU module
+ */
+void XMC_BCCU_GlobalInit(XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t *const config)
+{
+  XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_BCCU0);
+
+  bccu->GLOBCON = config->globcon;
+  
+  bccu->GLOBCLK = config->globclk;
+  bccu->GLOBDIM = config->global_dimlevel;  
+
+}
+
+/*
+ * API to configure the global trigger mode & delay of a BCCU module
+ */
+void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay)
+{
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);
+  bccu->GLOBCON |= ((uint32_t)mode | ((uint32_t)delay << BCCU_GLOBCON_TRDEL_Pos));
+}
+
+/*
+ * API to configure the trap input selection of a BCCU module
+ */
+void XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t input)
+{
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPIS_Msk);
+  bccu->GLOBCON |= ((uint32_t)input << BCCU_GLOBCON_TRAPIS_Pos);
+}
+
+/*
+ * API to configure the trap edge selection of a BCCU module
+ */
+void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge)
+{
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TRAPED_Msk);
+  bccu->GLOBCON |= ((uint32_t)edge << BCCU_GLOBCON_TRAPED_Pos);
+}
+
+/*
+ * API to configure the suspend mode of a BCCU module
+ */
+void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t mode)
+{
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_SUSCFG_Msk);
+  bccu->GLOBCON |= ((uint32_t)mode << BCCU_GLOBCON_SUSCFG_Pos);
+}
+
+/*
+ * API to configure number of consecutive zeroes allowed at modulator output (flicker watch-dog number)
+ */
+void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no)
+{
+  XMC_ASSERT("XMC_BCCU_SetFlickerWDThreshold: Invalid threshold no", (threshold_no <= BCCU_GLOBCON_WDMBN_Msk));
+  
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_WDMBN_Msk);
+  bccu->GLOBCON |= (uint32_t)(threshold_no << BCCU_GLOBCON_WDMBN_Pos);
+}
+
+/*
+ * API to configure the fast clock prescaler factor of a BCCU module
+ */
+void XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div)
+{
+  XMC_ASSERT("XMC_BCCU_SetFastClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_FCLK_PS_Msk));
+  
+  bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_FCLK_PS_Msk);
+  bccu->GLOBCLK |= div;
+  
+}
+
+/*
+ * API to configure the dimmer clock prescaler factor of a BCCU module
+ */
+void XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div)
+{
+  XMC_ASSERT("XMC_BCCU_SetDimClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_DCLK_PS_Msk));
+
+  bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_DCLK_PS_Msk);
+  bccu->GLOBCLK |= (uint32_t)(div << BCCU_GLOBCLK_DCLK_PS_Pos);
+  
+}
+
+/*
+ * API to configure the modulator output (bit-time) clock prescaler factor of a BCCU module
+ */
+void XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div)
+{
+  bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_BCS_Msk);
+  bccu->GLOBCLK |= ((uint32_t)div << BCCU_GLOBCLK_BCS_Pos);
+}
+
+/*
+ * API to enable the channels at the same time
+ */
+void XMC_BCCU_ConcurrentEnableChannels (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentEnableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->CHEN |= mask;
+}
+
+/*
+ * API to disable the channels at the same time
+ */
+void XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentDisableChannels: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+  bccu->CHEN &= ~(uint32_t)(mask);
+}
+
+/*
+ * API to set the channel's output passive levels at the same time
+ */
+void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentSetOutputPassiveLevel: Invalid channel mask", (chan_mask <= XMC_BCCU_CHANNEL_MASK));
+  
+  bccu->CHOCON &= ~(uint32_t)(chan_mask);
+  bccu->CHOCON |= (chan_mask * (uint32_t)level);
+}
+
+/*
+ * API to enable the various types of traps at the same time
+ */
+void XMC_BCCU_ConcurrentEnableTrap (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentEnableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->CHOCON |= (uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);
+}
+
+/*
+ * API to disable the various types of traps at the same time
+ */
+void XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentDisableTrap: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->CHOCON &= ~(uint32_t)(mask << BCCU_CHOCON_CH0TPE_Pos);
+}
+
+/*
+ * API to configure trigger mode and trigger delay at the same time, and also configure the channel enable
+ */
+void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig)
+{
+  uint32_t reg;
+  
+  XMC_ASSERT("XMC_BCCU_ConcurrentConfigTrigger: Invalid channel mask", (trig->mask_chans <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk);
+  bccu->GLOBCON |= ((uint32_t)trig->mode | ((uint32_t)trig->delay << BCCU_GLOBCON_TRDEL_Pos));
+  reg = 0U;
+  reg |= trig->mask_chans;
+  reg |= ((uint32_t)trig->mask_trig_lines << BCCU_CHTRIG_TOS0_Pos);
+  bccu->CHTRIG = reg;
+}
+
+/*
+ * API to start the linear walk of the channels to change towards target intensity at the same time
+ */
+void XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentStartLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->CHSTRCON |= (uint32_t)(mask);
+}
+
+/*
+ * API to abort the linear walk of the channels at the same time
+ */
+void XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentAbortLinearWalk: Invalid channel mask", (mask <= XMC_BCCU_CHANNEL_MASK));
+
+  bccu->CHSTRCON |= (uint32_t)(mask << BCCU_CHSTRCON_CH0A_Pos);
+}
+
+/*
+ * API to enable the dimming engines at the same time
+ */
+void XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentEnableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
+
+  bccu->DEEN = (uint32_t)(mask);
+}
+
+/*
+ * API to enable the dimming engines at the same time
+ */
+void XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentDisableDimmingEngine: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
+
+  bccu->DEEN &= ~(uint32_t)(mask);
+}
+
+/*
+ * API to start the dimming engines at the same time to change towards target dim level
+ */
+void XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentStartDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
+
+  bccu->DESTRCON = (uint32_t)(mask);
+}
+
+/*
+ * API to abort the dimming engines at the same time
+ */
+void XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask)
+{
+  XMC_ASSERT("XMC_BCCU_ConcurrentAbortDimming: Invalid dimming engine mask", (mask <= XMC_BCCU_DIM_ENGINE_MASK));
+
+  bccu->DESTRCON = (uint32_t)(mask << BCCU_DESTRCON_DE0A_Pos);
+}
+
+/*
+ * API to configure the dim level of a dimming engine
+ */
+void  XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level)
+{
+  XMC_ASSERT("XMC_BCCU_SetGlobalDimmingLevel: Invalid global dimming level", (level <= BCCU_GLOBDIM_GLOBDIM_Msk));
+
+  bccu->GLOBDIM = level;
+}
+
+/*
+ * API to enable a specific channel
+ */
+void XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no)
+{
+  XMC_ASSERT("XMC_BCCU_EnableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHEN |= (uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);
+}
+
+/*
+ * API to disable a specific channel
+ */
+void XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no)
+{
+  XMC_ASSERT("XMC_BCCU_DisableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHEN &= ~(uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no);
+}
+
+/*
+ * API to set the specific channel's passive level
+ */
+void XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level)
+{
+  XMC_ASSERT("XMC_BCCU_SetOutputPassiveLevel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHOCON |= ((uint32_t)level << chan_no);
+}
+
+/*
+ * API to enable the specific channel trap
+ */
+void XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no)
+{
+  XMC_ASSERT("XMC_BCCU_EnableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHOCON |= (uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);
+}
+
+/*
+ * API to disable the specific channel trap
+ */
+void XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no)
+{
+  XMC_ASSERT("XMC_BCCU_DisableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHOCON &= ~(uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no);
+}
+
+/*
+ * API to configure specific channel trigger enable and trigger line.
+ */
+void XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line)
+{
+  uint32_t reg;
+  XMC_ASSERT("XMC_BCCU_EnableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_TOS0_Msk << chan_no);
+  reg = (uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);
+  reg |= ((uint32_t)trig_line << (BCCU_CHTRIG_TOS0_Pos + chan_no));
+  bccu->CHTRIG |= reg;
+}
+
+/*
+ * API to disable specific channel
+ */
+void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no)
+{
+  XMC_ASSERT("XMC_BCCU_DisableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1)));
+
+  bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no);
+}
+
+/*
+ * API to initialise the channel of a BCCU module
+ */
+void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config)
+{
+  channel->CHCONFIG = config->chconfig;
+ 
+  channel->PKCMP = config->pkcmp;
+ 
+  channel->PKCNTR = config->pkcntr;
+}
+
+/*
+ * API to configure channel trigger edge and force trigger edge
+ */
+void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en)
+{
+  uint32_t reg; 
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_TRED_Msk | BCCU_CH_CHCONFIG_ENFT_Msk);
+  
+  reg = ((uint32_t)edge << BCCU_CH_CHCONFIG_TRED_Pos);
+  reg |= (uint32_t)(force_trig_en << BCCU_CH_CHCONFIG_ENFT_Pos);
+  channel->CHCONFIG |= reg;
+}
+
+/*
+ * API to configure the linear walker clock prescaler factor of a BCCU channel
+ */
+void XMC_BCCU_CH_SetLinearWalkPrescaler (XMC_BCCU_CH_t *const channel, uint32_t clk_div)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_LINPRES_Msk);
+  channel->CHCONFIG |= (uint32_t)(clk_div << BCCU_CH_CHCONFIG_LINPRES_Pos);
+}
+
+/*
+ * API to set channel target intensity
+ */
+void XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_int)
+{
+  channel->INTS = ch_int;
+}
+
+/*
+ * API to retrieve the channel actual intensity
+ */
+uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel)
+{
+  return (uint32_t)(channel->INT & BCCU_CH_INT_CHINT_Msk);
+}
+
+/*
+ * API to enable packer. Also configures packer threshold, off-time and on-time compare levels
+ */
+void XMC_BCCU_CH_EnablePacker (XMC_BCCU_CH_t *const channel, uint32_t thresh, uint32_t off_comp, uint32_t on_comp)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk | BCCU_CH_CHCONFIG_PKTH_Msk);
+  channel->CHCONFIG |= thresh;
+  channel->PKCMP = (off_comp | (uint32_t)(on_comp << BCCU_CH_PKCMP_ONCMP_Pos));
+  channel->CHCONFIG |= (uint32_t)BCCU_CH_CHCONFIG_PEN_Msk;
+}
+
+/*
+ * API to configure packer threshold
+ */
+void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PKTH_Msk);
+  channel->CHCONFIG |= val;
+}
+
+/*
+ * API to configure packer off-time compare level
+ */
+void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level)
+{
+  channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_OFFCMP_Msk);
+  channel->PKCMP |= level;
+}
+
+/*
+ * API to configure packer on-time compare level.
+ */
+void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level)
+{
+  channel->PKCMP &= ~(uint32_t)(BCCU_CH_PKCMP_ONCMP_Msk);
+  channel->PKCMP |= (level << BCCU_CH_PKCMP_ONCMP_Pos);
+}
+
+/*
+ * API to disable a packer.
+ */
+void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_PEN_Msk);
+}
+
+/*
+ * API to set packer off-time counter value
+ */
+void XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val)
+{
+  channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_OFFCNTVAL_Msk);
+  channel->PKCNTR |= cnt_val;
+}
+
+/*
+ * API to set packer on-time counter value
+ */
+void XMC_BCCU_CH_SetPackerOnCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt_val)
+{
+  channel->PKCNTR &= ~(uint32_t)(BCCU_CH_PKCNTR_ONCNTVAL_Msk);
+  channel->PKCNTR |= (uint32_t)(cnt_val << BCCU_CH_PKCNTR_ONCNTVAL_Pos);
+}
+
+/*
+ * API to select the dimming engine of a channel
+ */
+void XMC_BCCU_CH_SelectDimEngine (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_DIMMING_SOURCE_t sel)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DSEL_Msk);
+  channel->CHCONFIG |= ((uint32_t)sel << BCCU_CH_CHCONFIG_DSEL_Pos);
+}
+
+/*
+ * API to bypass the dimming engine. And the brightness of channel is depending only on
+ * intensity of the channel.
+ */
+void XMC_BCCU_CH_EnableDimmingBypass (XMC_BCCU_CH_t *const channel)
+{
+  channel->CHCONFIG |= (uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);
+}
+
+/*
+ * API to disable the bypass of dimming engine. And the brightness of channel is depending
+ * on intensity of channel and dimming level of dimming engine.
+ */
+void XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel)
+{
+  channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_DBP_Msk);
+}
+
+/*
+ * API to initialise a specific dimming engine of a BCCU module
+ */
+void XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CONFIG_t *const config)
+{
+  dim_engine->DTT = config->dtt;
+}
+
+/*
+ * API to set dimming engine target dim level
+ */
+void XMC_BCCU_DIM_SetTargetDimmingLevel (XMC_BCCU_DIM_t *const dim_engine, uint32_t level)
+{
+  dim_engine->DLS = level;
+}
+
+/*
+ * API to configure the dimming clock prescaler factor of a dimming engine
+ */
+void XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div)
+{
+  dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DIMDIV_Msk);
+  dim_engine->DTT |= div;
+}
+
+/*
+ * API to configure the dimming curve
+ */
+void XMC_BCCU_DIM_ConfigDimCurve (XMC_BCCU_DIM_t *const dim_engine, uint32_t dither_en, XMC_BCCU_DIM_CURVE_t sel)
+{
+  uint32_t reg;
+  dim_engine->DTT &= ~(uint32_t)(BCCU_DE_DTT_DTEN_Msk | BCCU_DE_DTT_CSEL_Msk);
+  reg = (uint32_t)(dither_en << BCCU_DE_DTT_DTEN_Pos);
+  reg |= ((uint32_t)sel << BCCU_DE_DTT_CSEL_Pos);
+  dim_engine->DTT |= reg;
+}
+
+#endif /* BCCU0 */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_can.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_can.c
- * @date 2015-10-27
+ * @date 2016-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -53,6 +53,11 @@
  * 2015-09-08:
  *     - Fixed bug in XMC_CAN_Init() <br>
  *
+ * 2016-06-07:
+ *     - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller
+ *
+ * 2015-06-20:
+ *     - Fixed bug in XMC_CAN_MO_Config() <br> 
  * @endcond
  *
  */ 
@@ -205,13 +210,14 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node,
 /* Function to allocate message object from free list to node list */
 void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num)
 {
-  /* Panel Command for  allocation of MO to node list */
+  /* wait while panel operation is in progress. */
-  XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U));
+  while (XMC_CAN_IsPanelControlReady(obj) == false)
-  /* wait until panel as done the command */
-  while (obj->PANCTR & CAN_PANCTR_BUSY_Msk)
   {
     /*Do nothing*/
   };
+
+  /* Panel Command for  allocation of MO to node list */
+  XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U));
 }
 
 /* Disable XMC_CAN Peripheral */
@@ -433,10 +439,13 @@ void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_
 void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo)
 {
   uint32_t reg;
+  
   /* Configure MPN */
   uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U;
-  can_mo->can_mo_ptr->MOIPR = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos));
+  uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos));
-
+  can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk);
+  can_mo->can_mo_ptr->MOIPR |= set;
+  
   if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) &&
        (can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) ||
       ((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) &&

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_ccu4.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ccu4.c
- * @date 2015-10-27
+ * @date 2015-10-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_ccu8.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ccu8.c
- * @date 2015-10-27
+ * @date 2015-10-07
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_common.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_common.c
- * @date 2015-10-27
+ * @date 2015-02-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -58,7 +58,7 @@ struct list
  *******************************************************************************/
 #if defined(XMC_ASSERT_ENABLE) && !defined(XMC_USER_ASSERT_FUNCTION)
 
-void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line)
+__WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line)
 {
   while(1)
   {

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_dac.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_dac.c
- * @date 2015-10-27
+ * @date 2015-06-19
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_dma.c

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_dma.c
- * @date 2015-10-27
+ * @date 2016-04-08
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -54,6 +54,15 @@
  *       on advanced DMA channels) <br>
  *     - Updated XMC_DMA_CH_Disable() <br>
  *
+ * 2016-03-09:
+ *     - Optimize write only registers
+ *
+ * 2016-04-08:
+ *     - Update XMC_DMA_CH_EnableEvent and XMC_DMA_CH_DisableEvent.
+ *       Write optimization of MASKCHEV 
+ *     - Fix XMC_DMA_IRQHandler, clear channel event status before processing the event handler.
+ *       It corrects event losses if the DMA triggered in the event handler finished before returning from handler.
+ *
  * @endcond
  */
 
@@ -269,12 +278,12 @@ void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line)
   if (dma == XMC_DMA0)
   {
 #endif
-    DLR->OVRCLR |= (uint32_t)(0x1UL << line);
+    DLR->OVRCLR = (uint32_t)(0x1UL << line);
 #if defined(GPDMA1)
   }
   else
   {
-    DLR->OVRCLR |= (uint32_t)(0x100UL << line);
+    DLR->OVRCLR = (uint32_t)(0x100UL << line);
   }
 #endif
 }
@@ -469,7 +478,7 @@ void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const u
   {
     if (event & ((uint32_t)0x1UL << event_idx))
     {
-      dma->MASKCHEV[event_idx * 2UL] |= ((uint32_t)0x101UL << channel);
+      dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x101UL << channel);
     }
   }
 }
@@ -483,7 +492,7 @@ void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const
   {
     if (event & ((uint32_t)0x1UL << event_idx))
     {
-      dma->MASKCHEV[event_idx * 2UL] |= ((uint32_t)0x100UL << channel);
+      dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x100UL << channel);
     }
   }
 }
@@ -672,16 +681,15 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
       mask = (uint32_t)1U << channel;
       if ((event & mask) != 0)
       {
-        event_handler = dma_event_handlers[channel];
+        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_ERROR);
 
         /* Call user callback to handle event */
+        event_handler = dma_event_handlers[channel];
         if (event_handler != NULL)
         {
           event_handler(XMC_DMA_CH_EVENT_ERROR);
         }
-
+       
-        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_ERROR);
-        
         break;
       }
       ++channel;
@@ -695,18 +703,17 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
       mask = (uint32_t)1U << channel;
       if (event & mask)
       {
-        event_handler = dma_event_handlers[channel];
-
-        /* Call user callback to handle event */
-        if (event_handler != NULL)
-        {
-          event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
-        }
-
         XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | 
                                                                       (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | 
                                                                       (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | 
                                                                       (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE));
+
+        /* Call user callback to handle event */
+        event_handler = dma_event_handlers[channel];
+        if (event_handler != NULL)
+        {
+          event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
+        }
 																	  
         break;
       }
@@ -721,17 +728,17 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
       mask = (uint32_t)1U << channel;
       if (event & mask)
       {
-        event_handler = dma_event_handlers[channel];
+        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
+                                                                      (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | 
+                                                                      (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE));
 
         /* Call user callback to handle event */
+        event_handler = dma_event_handlers[channel];
         if (event_handler != NULL)
         {
           event_handler(XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
         }
 
-        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
-                                                                      (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | 
-                                                                      (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE));
         break;
       }
       ++channel;
@@ -745,15 +752,14 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
       mask = (uint32_t)1U << channel;
       if (event & mask)
       {
-        event_handler = dma_event_handlers[channel];
+        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE);
 
         /* Call user callback to handle event */
+        event_handler = dma_event_handlers[channel];
         if (event_handler != NULL)
         {
           event_handler(XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE);
         }
-
-        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE);
         
         break;
       }
@@ -768,15 +774,14 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
       mask = (uint32_t)1U << channel;
       if (event & mask)
       {
-        event_handler = dma_event_handlers[channel];
+        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE);
 
         /* Call user callback to handle event */
+        event_handler = dma_event_handlers[channel];
         if (event_handler != NULL)
         {
           event_handler(XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE);
-        }
+        }      
-        
-        XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE);
 
         break;
       }

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_dsd.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_dsd.c
- * @date 2015-10-27
+ * @date 2015-09-18
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_ebu.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ebu.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_ecat.c

@@ -0,0 +1,198 @@
+
+/**
+ * @file xmc_ecat.c
+ * @date 2015-10-21
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-12-27:
+ *     - Add clock gating control in enable/disable APIs
+ *
+ * 2015-10-21:
+ *     - Initial Version
+ *
+ * @endcond
+ */
+
+/*******************************************************************************
+ * HEADER FILES
+ *******************************************************************************/
+
+#include <xmc_ecat.h>
+
+#if defined (ECAT0)
+
+#include <xmc_scu.h>
+
+/*******************************************************************************
+ * MACROS
+ *******************************************************************************/
+
+/*******************************************************************************
+ * API IMPLEMENTATION
+ *******************************************************************************/
+/* The function defines the access state to the MII management for the PDI interface*/
+__STATIC_INLINE void XMC_ECAT_lRequestPhyAccessToMII(void)
+{
+  ECAT0->MII_PDI_ACS_STATE |= 0x01;
+}
+
+/* EtherCAT module clock ungating and deassert reset API (Enables ECAT) */
+void XMC_ECAT_Enable(void)
+{
+  XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
+  XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
+
+  while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){}
+}
+
+/* EtherCAT module clock gating and assert reset API (Disables ECAT)*/
+void XMC_ECAT_Disable(void)
+{
+  XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
+  while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){}
+
+  XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
+}
+
+/* EtherCAT initialization function */
+void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config)
+{
+  XMC_ECAT_Enable();
+
+  /* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */
+  
+  /* words 0x0-0x3 */
+  ECAT0->EEP_DATA[0U] = config->dword[0U];
+  ECAT0->EEP_DATA[1U] = config->dword[1U];
+  ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
+
+  /* words 0x4-0x7 */
+  ECAT0->EEP_DATA[0U] = config->dword[2U];
+  ECAT0->EEP_DATA[1U] = config->dword[3U];
+  ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
+
+  while (ECAT0->EEP_CONT_STAT & ECAT_EEP_CONT_STAT_L_STAT_Msk)
+  {
+    /* Wait until the EEPROM_Loaded signal is active */
+  }
+
+}
+
+/* EtherCAT application event enable API */
+void XMC_ECAT_EnableEvent(uint32_t event)
+{
+  ECAT0->AL_EVENT_MASK |= event;
+}
+/* EtherCAT application event disable API */
+void XMC_ECAT_DisableEvent(uint32_t event)
+{
+  ECAT0->AL_EVENT_MASK &= ~event;
+}
+
+/* EtherCAT application event status reading API */
+uint32_t XMC_ECAT_GetEventStatus(void)
+{
+  return (ECAT0->AL_EVENT_REQ);
+}
+
+/* EtherCAT SyncManager channel disable function*/
+void XMC_ECAT_DisableSyncManChannel(const uint8_t channel)
+{
+  ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U;
+}
+
+/* EtherCAT SyncManager channel enable function*/
+void XMC_ECAT_EnableSyncManChannel(const uint8_t channel)
+{
+  ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U);
+}
+
+
+/* EtherCAT PHY register read function*/
+XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+{
+  XMC_ECAT_STATUS_t status;
+
+  XMC_ECAT_lRequestPhyAccessToMII();
+
+  ECAT0->MII_PHY_ADR = phy_addr;
+  ECAT0->MII_PHY_REG_ADR = reg_addr;
+
+  ECAT0->MII_CONT_STAT |= 0x0100U;  /* read instruction */
+  while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
+  
+  if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
+  {
+    ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
+    status = XMC_ECAT_STATUS_ERROR;
+  }
+  else
+  {
+    *data = (uint16_t)ECAT0->MII_PHY_DATA;
+    status = XMC_ECAT_STATUS_OK;
+  }
+
+  return status;
+}
+
+/* EtherCAT PHY register write function*/
+XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+{
+  XMC_ECAT_STATUS_t status;
+
+  XMC_ECAT_lRequestPhyAccessToMII();
+
+  ECAT0->MII_PHY_ADR = phy_addr;
+  ECAT0->MII_PHY_REG_ADR = reg_addr;
+  ECAT0->MII_PHY_DATA = data;
+
+  ECAT0->MII_CONT_STAT |= 0x0200U;  /* write instruction */
+  while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
+
+  if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
+  {
+    ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
+    status = XMC_ECAT_STATUS_ERROR;
+  }
+  else
+  {
+    status = XMC_ECAT_STATUS_OK;
+  }
+
+  return status;
+}
+
+#endif

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_eru.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_eru.c
- * @date 2015-10-27
+ * @date 2016-03-10
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -42,6 +42,9 @@
  * 2015-06-20:
  *     - Removed definition of GetDriverVersion API <br>
  *
+ * 2016-03-10:
+ *     - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
+ *
  * @endcond
  */
 
@@ -190,6 +193,14 @@ void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
   eru->EXICON_b[channel].ED = (uint8_t)edge_detection;
 }
 
+/* Returns the configured event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register. */
+XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, const uint8_t channel)
+{
+  XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
+  XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Channel Number", (channel < 4U));
+  return ((XMC_ERU_ETL_EDGE_DETECTION_t)(eru->EXICON_b[channel].ED));
+}
+
 /* Set the status flag bit(FL) in EXICONx(x = [0 to 3]). */
 void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru,
                                    const uint8_t channel,

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_eth_mac.c

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_eth_mac.c
- * @date 2015-10-27
+ * @date 2016-08-30
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -37,12 +37,24 @@
  * Change History
  * --------------
  *
+ * 2015-06-20:
+ *     - Initial
+ *
  * 2015-09-01:
  *     - Add clock gating control in enable/disable APIs
  *     - Add transmit polling if run out of buffers
  *
- * 2015-06-20:
+ * 2015-11-30:
- *     - Initial
+ *     - Fix XMC_ETH_MAC_GetRxFrameSize return value in case of errors
+ *
+ * 2016-03-16:
+ *     - Fix XMC_ETH_MAC_DisableEvent
+ *
+ * 2016-05-19:
+ *     - Changed XMC_ETH_MAC_ReturnTxDescriptor and XMC_ETH_MAC_ReturnRxDescriptor
+ *
+ * 2016-08-30:
+ *     - Changed XMC_ETH_MAC_Init() to disable MMC interrupt events
  *
  * @endcond
  */
@@ -82,57 +94,6 @@
 #define XMC_ETH_MAC_MDC_DIVIDER_102 (4U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/102 */
 #define XMC_ETH_MAC_MDC_DIVIDER_124 (5U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/124 */
 
-/**
- * TDES0 Descriptor TX Packet Control/Status
- */
-#define ETH_MAC_DMA_TDES0_OWN  (0x80000000U) /**< Own bit 1=DMA, 0=CPU */
-#define ETH_MAC_DMA_TDES0_IC   (0x40000000U) /**< Interrupt on competition */
-#define ETH_MAC_DMA_TDES0_LS   (0x20000000U) /**< Last segment */
-#define ETH_MAC_DMA_TDES0_FS   (0x10000000U) /**< First segment */
-#define ETH_MAC_DMA_TDES0_DC   (0x08000000U) /**< Disable CRC */
-#define ETH_MAC_DMA_TDES0_DP   (0x04000000U) /**< Disable pad */
-#define ETH_MAC_DMA_TDES0_TTSE (0x02000000U) /**< Transmit time stamp enable */
-#define ETH_MAC_DMA_TDES0_CIC  (0x00C00000U) /**< Checksum insertion control */
-#define ETH_MAC_DMA_TDES0_TER  (0x00200000U) /**< Transmit end of ring */
-#define ETH_MAC_DMA_TDES0_TCH  (0x00100000U) /**< Second address chained */
-#define ETH_MAC_DMA_TDES0_TTSS (0x00020000U) /**< Transmit time stamp status */
-#define ETH_MAC_DMA_TDES0_IHE  (0x00010000U) /**< IP header error */
-#define ETH_MAC_DMA_TDES0_ES   (0x00008000U) /**< Error summary */
-#define ETH_MAC_DMA_TDES0_JT   (0x00004000U) /**< Jabber timeout */
-#define ETH_MAC_DMA_TDES0_FF   (0x00002000U) /**< Frame flushed */
-#define ETH_MAC_DMA_TDES0_IPE  (0x00001000U) /**< IP payload error */
-#define ETH_MAC_DMA_TDES0_LOC  (0x00000800U) /**< Loss of carrier */
-#define ETH_MAC_DMA_TDES0_NC   (0x00000400U) /**< No carrier */
-#define ETH_MAC_DMA_TDES0_LC   (0x00000200U) /**< Late collision */
-#define ETH_MAC_DMA_TDES0_EC   (0x00000100U) /**< Excessive collision */
-#define ETH_MAC_DMA_TDES0_VF   (0x00000080U) /**< VLAN frame */
-#define ETH_MAC_DMA_TDES0_CC   (0x00000078U) /**< Collision count */
-#define ETH_MAC_DMA_TDES0_ED   (0x00000004U) /**< Excessive deferral */
-#define ETH_MAC_DMA_TDES0_UF   (0x00000002U) /**< Underflow error */
-#define ETH_MAC_DMA_TDES0_DB   (0x00000001U) /**< Deferred bit */
-
-/**
- * RDES0 Descriptor RX Packet Status
- */
-#define ETH_MAC_DMA_RDES0_OWN  (0x80000000U) /**< Own bit 1=DMA, 0=CPU */
-#define ETH_MAC_DMA_RDES0_AFM  (0x40000000U) /**< Destination address filter fail */
-#define ETH_MAC_DMA_RDES0_FL   (0x3FFF0000U) /**< Frame length mask */
-#define ETH_MAC_DMA_RDES0_ES   (0x00008000U) /**< Error summary */
-#define ETH_MAC_DMA_RDES0_DE   (0x00004000U) /**< Descriptor error */
-#define ETH_MAC_DMA_RDES0_SAF  (0x00002000U) /**< Source address filter fail */
-#define ETH_MAC_DMA_RDES0_LE   (0x00001000U) /**< Length error */
-#define ETH_MAC_DMA_RDES0_OE   (0x00000800U) /**< Overflow error */
-#define ETH_MAC_DMA_RDES0_VLAN (0x00000400U) /**< VLAN tag */
-#define ETH_MAC_DMA_RDES0_FS   (0x00000200U) /**< First descriptor */
-#define ETH_MAC_DMA_RDES0_LS   (0x00000100U) /**< Last descriptor */
-#define ETH_MAC_DMA_RDES0_TSA  (0x00000080U) /**< Timestamp available */
-#define ETH_MAC_DMA_RDES0_LC   (0x00000040U) /**< Late collision */
-#define ETH_MAC_DMA_RDES0_FT   (0x00000020U) /**< Frame type */
-#define ETH_MAC_DMA_RDES0_RWT  (0x00000010U) /**< Receive watchdog timeout */
-#define ETH_MAC_DMA_RDES0_RE   (0x00000008U) /**< Receive error */
-#define ETH_MAC_DMA_RDES0_DBE  (0x00000004U) /**< Dribble bit error */
-#define ETH_MAC_DMA_RDES0_CE   (0x00000002U) /**< CRC error */
-#define ETH_MAC_DMA_RDES0_ESA  (0x00000001U) /**< Extended Status/Rx MAC address */
 
 /**
  * RDES1 Descriptor RX Packet Control
@@ -141,6 +102,7 @@
 #define ETH_MAC_DMA_RDES1_RER  (0x00008000U) /**< Receive end of ring */
 #define ETH_MAC_DMA_RDES1_RCH  (0x00004000U) /**< Second address chained */
 #define ETH_MAC_DMA_RDES1_RBS1 (0x00001FFFU) /**< Receive buffer 1 size */
+#define ETH_MAC_MMC_INTERRUPT_MSK  (0x03ffffffU) /**< Bit mask to disable MMMC transmit and receive interrupts*/
 
 /**
  * Normal MAC events
@@ -237,6 +199,10 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac)
   /* Clear interrupts */
   eth_mac->regs->STATUS = 0xFFFFFFFFUL;
 
+  /* Disable MMC interrupt events */
+  eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_MMC_INTERRUPT_MSK;
+  eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_MMC_INTERRUPT_MSK;
+
   eth_mac->frame_end = NULL;
 
   return status;
@@ -325,7 +291,7 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const u
   uint32_t ctrl;
 
   XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac != NULL);
-  XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac->regs != ETH0);
+  XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac->regs == ETH0);
   XMC_ASSERT("XMC_ETH_MAC_SendFrame:", (frame != NULL) && (len > 0));
 
   dst = eth_mac->frame_end;
@@ -405,7 +371,7 @@ uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *frame, uin
   uint8_t const *src;
 
   XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac != NULL);
-  XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac->regs != ETH0);
+  XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac->regs == ETH0);
   XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", (frame != NULL) && (len > 0));
 
   /* Fast-copy data to packet buffer */
@@ -445,16 +411,18 @@ uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac)
     /* Owned by DMA */
     len = 0U;
   }
-
+  else if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) ||
-  if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) ||
+           ((status & ETH_MAC_DMA_RDES0_FS) == 0U) ||
-      ((status & ETH_MAC_DMA_RDES0_FS) == 0U) ||
+           ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) 
-      ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) {
+  {
     /* Error, this block is invalid */
     len = 0xFFFFFFFFU;
   }
-
+  else 
-  /* Subtract CRC */
+  {
-  len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U;
+    /* Subtract CRC */
+    len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U;
+  }
 
   return len;
 }
@@ -633,7 +601,7 @@ void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event)
 
   eth_mac->regs->INTERRUPT_MASK |= event >> 16U;
 
-  event &= (uint16_t)~0xffffU;
+  event &= 0x7fffU;
   eth_mac->regs->INTERRUPT_ENABLE &= ~event;
 }
 
@@ -671,18 +639,26 @@ uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac)
 void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac)
 {
   eth_mac->rx_desc[eth_mac->rx_index].status |= ETH_MAC_DMA_RDES0_OWN;
+  eth_mac->rx_index++;
+  if (eth_mac->rx_index == eth_mac->num_rx_buf)
+  {
+    eth_mac->rx_index = 0U;
+  } 
 }
 
 /* Return TX descriptor */
 void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac)
 {
-  eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_OWN;
+  eth_mac->tx_ts_index = eth_mac->tx_index;
-}
 
-/* Is TX descriptor owned by DMA? */
+  eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC |ETH_MAC_DMA_TDES0_OWN;
-bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const eth_mac)
+  eth_mac->tx_index++;
-{
+  if (eth_mac->tx_index == eth_mac->num_tx_buf)
-  return ((eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) != 0U);
+  {
+    eth_mac->tx_index = 0U;
+  } 
+
+  eth_mac->frame_end = NULL;
 }
 
 /* Set VLAN tag */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_fce.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_fce.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_gpio.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_gpio.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_hrpwm.c

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_hrpwm.c
- * @date 2015-10-27
+ * @date 2015-07-14
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_i2c.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_i2c.c
- * @date 2015-10-27
+ * @date 2015-10-02
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_i2s.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_i2s.c
- * @date 2015-10-27
+ * @date 2015-06-30
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
@@ -49,6 +49,16 @@
  * 2015-09-28:
  *     - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs <br>
  *
+ * 2015-11-04: 
+ *     - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API <br>
+ *
+ * 2016-06-30:
+ *     - Modified XMC_I2S_CH_Init:
+ *       + change default passive level to 0
+ *       + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length.
+ *     - Modified XMC_I2S_CH_SetBaudrate:
+ *       + Optional Master clock output signal generated with a fixed phase relation to SCLK.
+ *
  * @endcond
  *
  */
@@ -67,7 +77,8 @@
 /*********************************************************************************************************************
  * MACROS
  ********************************************************************************************************************/
-#define XMC_I2S_CH_OVERSAMPLING (2UL)
+/* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */
+#define XMC_I2S_CH_OVERSAMPLING (4UL)
 
 /*********************************************************************************************************************
  * API IMPLEMENTATION
@@ -87,12 +98,10 @@ void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *co
   }
   /* Configuration of USIC Shift Control */
   /* Transmission Mode (TRM) = 1  */
-  /* Passive Data Level (PDL) = 1 */
+  channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) |
-  channel->SCTR = (uint32_t)(((uint32_t)(USIC_CH_SCTR_PDL_Msk | 
+                  (uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) |
-                  (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos)) |
+                  (uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) |
-                  (uint32_t)((uint32_t)((uint32_t)config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos)) |
+                  USIC_CH_SCTR_SDIR_Msk;
-                  (uint32_t)((uint32_t)((uint32_t)((uint32_t)config->data_bits -1U) << USIC_CH_SCTR_WLE_Pos) |
-                  (uint32_t)USIC_CH_SCTR_SDIR_Msk));
 
   /* Configuration of USIC Transmit Control/Status Register */
   /* TBUF Data Enable (TDEN) = 1 */
@@ -111,10 +120,14 @@ void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *co
     /* Configuration of Protocol Control Register */
     channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk;
   }
+
   /* Configuration of Protocol Control Register */
   channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk |
                           (uint32_t)config->wa_inversion) |
                           ((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos);
+
+  XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length);
+
   /* Clear protocol status */
   channel->PSCR = 0xFFFFFFFFUL;
 }
@@ -131,7 +144,8 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const u
     if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
     {
       channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) |
-                     (0x2UL << USIC_CH_BRG_CTQSEL_Pos));
+                     (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) |
+                     USIC_CH_BRG_PPPEN_Msk;
 
       status = XMC_I2S_CH_STATUS_OK;
     }
@@ -192,7 +206,7 @@ void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons
   /* Check FIFO size */
   if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
   {
-    while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
+    while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
     {
     }
 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_ledts.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_ledts.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
   *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_math.c

@@ -0,0 +1,463 @@
+
+/**
+ * @file xmc_math.c
+ * @date 2015-10-08
+ *
+ * @cond
+ **********************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without           
+ * modification,are permitted provided that the following conditions are met:   
+ *                                                                              
+ *   Redistributions of source code must retain the above copyright notice,      
+ *   this list of conditions and the following disclaimer.                        
+ * 
+ *   Redistributions in binary form must reproduce the above copyright notice,   
+ *   this list of conditions and the following disclaimer in the documentation    
+ *   and/or other materials provided with the distribution.                       
+ * 
+ *   Neither the name of the copyright holders nor the names of its contributors 
+ *   may be used to endorse or promote products derived from this software without
+ *   specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"  
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE    
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE   
+ * ARE  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE   
+ * LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR         
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF         
+ * SUBSTITUTE GOODS OR  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS    
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN      
+ * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)       
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE   
+ * POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share        
+ * modifications, enhancements or bug fixes with Infineon Technologies AG       
+ * dave@infineon.com).                                                          
+ **********************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-06-20: 
+ *     - Removed version macros and declaration of GetDriverVersion API <br>
+ *     - Updated copyright and change history section.
+ *
+ * 2015-09-23: 
+ *     - Added SQRT functions
+ *
+ * 2015-10-08:
+ *     - Return values for sin(), cos(), sinh(), cosh(), arctan() are corrected.
+ *
+ * @endcond
+ *
+ */
+
+/**
+ *
+ * @brief MATH driver - API implementation for XMC13 family MATH libraries. <br>
+ * 
+ * <b>Detailed description of file</b> <br>
+ * APIs provided in this file cover the following functional blocks of MATH: <br>
+ *
+ */
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ ********************************************************************************************************************/
+#include <xmc_math.h>
+
+#if defined (MATH)
+/*********************************************************************************************************************
+ * MACROS
+ ********************************************************************************************************************/
+/* Reciprocal of Circular gain in XMC_MATH_Q0_23_t format ((2^23)/1.646760258121) */
+#define XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023       (0x4DBA76U)
+/* Reciprocal of Hyperbolic gain in XMC_MATH_Q1_22_t format ((2^22)/0.828159360960) */
+#define XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22    (0x4D47A1U)
+/* Signed division is selected */
+#define XMC_MATH_SIGNED_DIVISION                      ((uint32_t) 0 << MATH_DIVCON_USIGN_Pos)
+/* Unsigned division is selected */
+#define XMC_MATH_UNSIGNED_DIVISION                    ((uint32_t) 1 << MATH_DIVCON_USIGN_Pos)
+
+/*********************************************************************************************************************
+ * ENUMS
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * GLOBAL DATA
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * DATA STRUCTURES
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * LOCAL ROUTINES
+ ********************************************************************************************************************/
+
+/*********************************************************************************************************************
+ * API IMPLEMENTATION - Utility functions
+ ********************************************************************************************************************/
+
+/* Utility function to check if the DIV unit is busy */
+bool XMC_MATH_DIV_IsBusy(void)
+{
+  bool status;
+  if (MATH->DIVST & MATH_DIVST_BSY_Msk)
+  {
+    status = true;  /* DIV unit is busy running a division operation */ 
+  }
+  else
+  {
+    status = false; /* DIV unit is idle */ 
+  }
+
+  return (status);
+}
+
+/* Utility function to check if the CORDIC unit is busy */
+bool XMC_MATH_CORDIC_IsBusy(void)
+{
+  bool status;
+  if (MATH->STATC & MATH_STATC_BSY_Msk)
+  {
+    status = true;  /* CORDIC unit is busy running an operation */  
+  }
+  else
+  {
+    status = false; /* CORDIC unit is idle */   
+  }
+
+  return (status);
+}
+
+/* This functions returns the status of a requested event */
+bool XMC_MATH_GetEventStatus(const XMC_MATH_EVENT_t event)
+{
+  bool status;
+  if (MATH->EVFR & (uint32_t) event)
+  {
+    status = true; /* Requested event has been detected */
+  }
+  else
+  {
+    status = false; /* Requested event has not been detected */
+  }
+  return (status);
+}
+
+#ifndef XMC_MATH_DISABLE_DIV_ABI
+/***********************************************************************************************************************
+ * API IMPLEMENTATION - aeabi routines
+ **********************************************************************************************************************/
+/* This function performs unsigned integer division */
+uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor)
+{
+  MATH->DIVCON  = XMC_MATH_UNSIGNED_DIVISION;
+  MATH->DVD     = dividend;
+  MATH->DVS     = divisor;
+
+  return ((uint32_t) MATH->QUOT);
+}
+
+/* This function performs signed integer division */
+int32_t __aeabi_idiv(int32_t dividend, int32_t divisor)
+{
+  MATH->DIVCON  = XMC_MATH_SIGNED_DIVISION;
+  MATH->DVD     = dividend;
+  MATH->DVS     = divisor;
+
+  return ((int32_t) MATH->QUOT);
+}
+
+/* This function performs unsigned integer division modulo */
+uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor)
+{
+  uint64_t remainder;
+
+  MATH->DIVCON  = XMC_MATH_UNSIGNED_DIVISION;
+  MATH->DVD     = dividend;
+  MATH->DVS     = divisor;
+
+  remainder = ((uint64_t) MATH->RMD) << 32U;
+  return (remainder | MATH->QUOT);
+}
+
+/* This function performs signed integer division modulo */
+int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor)
+{
+  uint64_t remainder;
+  uint64_t result;
+
+  MATH->DIVCON  = XMC_MATH_SIGNED_DIVISION;
+  MATH->DVD     = dividend;
+  MATH->DVS     = divisor;
+
+  remainder = ((uint64_t) MATH->RMD) << 32U;
+  result    = (remainder | MATH->QUOT);
+  return ((int64_t) result);
+}
+#endif
+
+/***********************************************************************************************************************
+ * API IMPLEMENTATION - Blocking functions
+ **********************************************************************************************************************/
+/* This function computes the cosine of a given angle in radians */
+XMC_MATH_Q0_23_t XMC_MATH_CORDIC_Cos(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  int32_t result;
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U;  /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+  result      = ((int32_t)MATH->CORRX) >> MATH_CORRX_RESULT_Pos;
+  return ((XMC_MATH_Q0_23_t) result);
+}
+
+/* This function computes the sine of a given angle in radians */
+XMC_MATH_Q0_23_t XMC_MATH_CORDIC_Sin(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  int32_t result;
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+  result      = ((int32_t)MATH->CORRY) >> MATH_CORRY_RESULT_Pos;
+  return ((XMC_MATH_Q0_23_t) result);
+}
+
+/* This function computes the tangent of a given angle in radians */
+XMC_MATH_Q0_11_t XMC_MATH_CORDIC_Tan(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  uint32_t result;
+  MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
+                 (uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE;      /* Chain the results of CORDIC operation to DIV unit */
+  MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos;            /* Right Shifts Divisor by 11 places prior to division */
+  MATH->STATC  = 0U; /* Clear register */
+  MATH->CON    = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                 (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ  = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY  = 0U; /* Clear register */
+  MATH->CORDX  = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+  result       = MATH->QUOT;
+  return ((XMC_MATH_Q0_11_t) result);
+}
+
+/* This function computes the arc tangent of a given angle in radians */
+XMC_MATH_Q0_23_t XMC_MATH_CORDIC_ArcTan(XMC_MATH_Q8_15_t x, XMC_MATH_Q8_15_t y)
+{
+  uint32_t result;
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR;
+  MATH->CORDZ = 0U; /* Clear register */
+  MATH->CORDY = ((uint32_t) y) << MATH_CORDY_DATA_Pos;
+  MATH->CORDX = ((uint32_t) x) << MATH_CORDX_DATA_Pos;
+  result      = ((int32_t)MATH->CORRZ) >> MATH_CORRZ_RESULT_Pos;
+  return ((XMC_MATH_Q0_23_t) result);
+}
+
+/* This function computes the hyperbolic cosine of a given angle in radians */
+XMC_MATH_Q1_22_t XMC_MATH_CORDIC_Cosh(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  int32_t result;
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+  result      = ((int32_t)MATH->CORRX) >> MATH_CORRX_RESULT_Pos;
+  return ((XMC_MATH_Q1_22_t) result);
+}
+
+/* This function computes the hyperbolic sine of a given angle in radians */
+XMC_MATH_Q1_22_t XMC_MATH_CORDIC_Sinh(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  int32_t result;
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+  result      = ((int32_t)MATH->CORRY) >> MATH_CORRY_RESULT_Pos;
+  return ((XMC_MATH_Q1_22_t) result);
+}
+
+/* This function computes the hyperbolic tangent of a given angle in radians */
+XMC_MATH_Q0_11_t XMC_MATH_CORDIC_Tanh(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  uint32_t result;
+  MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
+                 (uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE;      /* Chain the results of CORDIC operation to DIV unit */
+  MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos;            /* Right Shifts Divisor by 11 places prior to division */
+  MATH->STATC  = 0U; /* Clear register */
+  MATH->CON    = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                 (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ  = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY  = 0U; /* Clear register */
+  MATH->CORDX  = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+  result       = MATH->QUOT;
+  return ((XMC_MATH_Q0_11_t) result);
+}
+
+/***********************************************************************************************************************
+ * API IMPLEMENTATION - Non blocking functions
+ **********************************************************************************************************************/
+/* This function computes the cosine of a given angle in radians */
+void XMC_MATH_CORDIC_CosNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U;  /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the sine of a given angle in radians */
+void XMC_MATH_CORDIC_SinNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the tangent of a given angle in radians */
+void XMC_MATH_CORDIC_TanNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
+                 (uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE;      /* Chain the results of CORDIC operation to DIV unit */
+  MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos;            /* Right Shifts Divisor by 11 places prior to division */
+
+  MATH->STATC  = 0U; /* Clear register */
+  MATH->CON    = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR + \
+                 (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ  = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY  = 0U; /* Clear register */
+  MATH->CORDX  = XMC_MATH_RECIPROC_CIRCULAR_GAIN_IN_Q023 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the arc tangent of a given value */
+void XMC_MATH_CORDIC_ArcTanNB(XMC_MATH_Q8_15_t x, XMC_MATH_Q8_15_t y)
+{
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_CIRCULAR;
+  MATH->CORDZ = 0U; /* Clear register */
+  MATH->CORDY = ((uint32_t) y) << MATH_CORDY_DATA_Pos;
+  MATH->CORDX = ((uint32_t) x) << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the hyperbolic cosine of a given angle in radians */
+void XMC_MATH_CORDIC_CoshNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the hyperbolic sine of a given angle in radians */
+void XMC_MATH_CORDIC_SinhNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->STATC = 0U; /* Clear register */
+  MATH->CON   = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ = ((uint32_t)angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY = 0U; /* Clear register */
+  MATH->CORDX = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function computes the hyperbolic tangent of a given angle in radians */
+void XMC_MATH_CORDIC_TanhNB(XMC_MATH_Q0_23_t angle_in_radians)
+{
+  MATH->GLBCON = (uint32_t) XMC_MATH_DIV_DVDRC_CORRY_IS_SOURCE + \
+                 (uint32_t) XMC_MATH_DIV_DVSRC_CORRX_IS_SOURCE;      /* Chain the results of CORDIC operation to DIV unit */
+  MATH->DIVCON = (uint32_t) 11 << MATH_DIVCON_DVSSRC_Pos;            /* Right Shifts Divisor by 11 places prior to division */
+  MATH->STATC  = 0U; /* Clear register */
+  MATH->CON    = (uint32_t) XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC + \
+                 (uint32_t) XMC_MATH_CORDIC_ROTVEC_MODE_ROTATION;
+  MATH->CORDZ  = ((uint32_t) angle_in_radians) << MATH_CORDZ_DATA_Pos;
+  MATH->CORDY  = 0U; /* Clear register */
+  MATH->CORDX  = XMC_MATH_RECIPROC_HYPERBOLIC_GAIN_IN_Q1_22 << MATH_CORDX_DATA_Pos;
+}
+
+/* This function performs division for given two unsigned arguments */
+void XMC_MATH_DIV_UnsignedDivNB(uint32_t dividend, uint32_t divisor)
+{
+  MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
+  MATH->DVD    = dividend;
+  MATH->DVS    = divisor;
+}
+
+/* This function performs division for given two signed arguments */
+void XMC_MATH_DIV_SignedDivNB(int32_t dividend, int32_t divisor)
+{
+  MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
+  MATH->DVD    = dividend;
+  MATH->DVS    = divisor;
+}
+
+/* This function performs modulo operation for given two unsigned arguments */
+void XMC_MATH_DIV_UnsignedModNB(uint32_t dividend, uint32_t divisor)
+{
+  MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION;
+  MATH->DVD    = dividend;
+  MATH->DVS    = divisor;
+}
+
+/* This function performs modulo operation for given two signed arguments */
+void XMC_MATH_DIV_SignedModNB(int32_t dividend, int32_t divisor)
+{
+  MATH->DIVCON = XMC_MATH_SIGNED_DIVISION;
+  MATH->DVD    = dividend;
+  MATH->DVS    = divisor;
+}
+
+int16_t XMC_MATH_CORDIC_Q15_Sqrt(int16_t x)
+{
+  int32_t temp;
+  MATH->STATC = 0U; /* Clear register */
+
+  MATH->CON   = (uint32_t)XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC |
+                (uint32_t)XMC_MATH_CORDIC_ROTVEC_MODE_VECTORING;
+
+  temp = (int32_t)x << 15; /* Q30 to handle numbers > 1.0 */
+
+  MATH->CORDY = (temp - 0x10000000U); /* x - 0.25 */
+  MATH->CORDX = (temp + 0x10000000U); /* x + 0.25 */
+
+  return (int16_t)(((MATH->CORRX >> 14) * 39568) >> 16); /* Q16 * Q15 */
+}
+
+int32_t XMC_MATH_CORDIC_Q31_Sqrt(int32_t x)
+{
+  MATH->STATC = 0U; /* Clear register */
+
+  MATH->CON   = (uint32_t)XMC_MATH_CORDIC_OPERATING_MODE_HYPERBOLIC |
+                (uint32_t)XMC_MATH_CORDIC_ROTVEC_MODE_VECTORING;
+
+  x >>= 1;  /* Q30 to handle numbers > 1.0 */
+
+  MATH->CORDY = (x - 0x10000000U); /* x - 0.25 */
+  MATH->CORDX = (x + 0x10000000U); /* x + 0.25 */
+
+  return ((MATH->CORRX >> 14) * 39568); /* Q16 * Q15 */
+}
+
+#endif /* end of #if defined (MATH) */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_pau.c

@@ -0,0 +1,109 @@
+/**
+ * @file xmc_pau.c
+ * @date 2015-06-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-02-20:
+ *     - Initial <br>
+ *      
+ * 2015-06-20:
+ *     - Removed GetDriverVersion API
+ * @endcond 
+ *
+ */
+
+/**
+ *
+ * @brief PAU driver for XMC1 microcontroller family.
+ *
+ */
+
+/*********************************************************************************************************************
+ * HEADER FILES
+ *********************************************************************************************************************/
+#include "xmc_pau.h"
+
+#if defined(PAU)
+
+/**********************************************************************************************************************
+ * API IMPLEMENTATION
+ *********************************************************************************************************************/
+
+/*
+ * Enable peripheral access
+ */
+void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral)
+{
+  uint32_t reg_num;
+  
+  reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
+  XMC_PAU->PRIVDIS[reg_num] &= (uint32_t)~((uint32_t)peripheral & 0x0fffffffUL);
+}
+
+/*
+ * Disable peripheral access
+ */
+void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral)
+{
+  uint32_t reg_num;
+
+  reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
+  XMC_PAU->PRIVDIS[reg_num] |= (uint32_t)((uint32_t)peripheral & 0x0fffffffUL);
+}
+
+/*
+ * Check if peripheral access is enabled 
+ */
+bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral)
+{
+  uint32_t reg_num;
+
+  reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
+  return (bool)(XMC_PAU->PRIVDIS[reg_num] & ((uint32_t)peripheral & 0x0fffffffUL));
+}
+
+/*
+ * Check if peripheral is available
+ */
+bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral)
+{
+  uint32_t reg_num;
+
+  reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U;
+  return (bool)(XMC_PAU->AVAIL[reg_num] & ((uint32_t)peripheral & 0x0fffffffUL));
+}
+
+#endif /* defined(PAU) */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_posif.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_posif.c
- * @date 2015-10-27
+ * @date 2015-06-19
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without           

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_prng.c

@@ -0,0 +1,107 @@
+
+/**
+ * @file xmc_prng.c
+ * @date 2015-06-20
+ *
+ * @cond
+ *********************************************************************************************************************
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
+ *
+ * Copyright (c) 2015-2016, Infineon Technologies AG
+ * All rights reserved.                        
+ *                                             
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
+ * following conditions are met:   
+ *                                                                              
+ * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 
+ * disclaimer.                        
+ * 
+ * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 
+ * disclaimer in the documentation and/or other materials provided with the distribution.                       
+ * 
+ * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written permission.                                           
+ *                                                                              
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE  
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR  
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                                  
+ *                                                                              
+ * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 
+ * Infineon Technologies AG dave@infineon.com).                                                          
+ *********************************************************************************************************************
+ *
+ * Change History
+ * --------------
+ *
+ * 2015-02-20:
+ *     - Initial <br>
+ *     - Removed GetDriverVersion API <br>
+ *
+ * 2015-06-20
+ *     - Removed definition of GetDriverVersion API <br>
+ *
+ * @endcond
+ */
+ 
+#include "xmc_prng.h"
+
+#if defined (PRNG)
+
+/*********************************************************************************************************************
+ * API IMPLEMENTATION
+ *********************************************************************************************************************/
+ 
+/*
+ * Initializes the PRNG peripheral with the settings in the
+ * initialization structure XMC_PRNG_INIT_t
+ */
+XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng)
+{
+  volatile uint16_t read_warm_up;
+  uint16_t reg_val, iter;
+  XMC_PRNG_INIT_STATUS_t status = XMC_PRNG_INITIALIZED;
+  
+  XMC_ASSERT("XMC_PRNG_Init:Null Pointer", (prng != (XMC_PRNG_INIT_t *)NULL));
+
+  /* Configure block size for key loading mode */
+  XMC_PRNG_SetRandomDataBlockSize(XMC_PRNG_RDBS_WORD);
+
+  /* Enable key loading mode */
+  XMC_PRNG_EnableKeyLoadingMode();
+
+  /* Load key words (80 bits) and wait till RDV is set */
+  for (iter = (uint16_t)0UL; iter < (uint16_t)5UL; iter++)
+  {
+    XMC_PRNG_LoadKeyWords(prng->key_words[iter]);
+    while (PRNG_CHK_RDV_Msk != XMC_PRNG_CheckValidStatus());
+  }
+  
+  XMC_PRNG_EnableStreamingMode();
+
+  /* Warm up phase: Read and discard 64 bits */
+  read_warm_up = PRNG->WORD;
+  read_warm_up = PRNG->WORD;
+  read_warm_up = PRNG->WORD;
+  reg_val      = PRNG->WORD;
+  read_warm_up &= reg_val;
+
+  /* Configure block size either byte (8 bit) or word (16 bit) */
+  XMC_PRNG_SetRandomDataBlockSize(prng->block_size);
+
+  /*
+   * Checks for reset value for "random data block size". If reset,
+   * PRNG is not initialized
+   */
+  if ((uint16_t)XMC_PRNG_RDBS_RESET == (PRNG->CTRL & (uint16_t)PRNG_CTRL_RDBS_Msk))
+  {
+    status = XMC_PRNG_NOT_INITIALIZED;
+  }
+
+  return status;
+}
+
+#endif /* #if defined (PRNG) */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_rtc.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_rtc.c
- * @date 2015-10-27
+ * @date 2015-05-19
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -41,6 +41,10 @@
  *      
  * 2015-06-20:
  *     - Removed GetDriverVersion API
+ * 
+ * 2016-05-19:
+ *     - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
+ *
  * @endcond 
  *
  */
@@ -167,6 +171,25 @@ void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time)
   time->raw1 = RTC->TIM1;
 }
 
+/*
+ * Sets the RTC module time values in standard format
+ */
+void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime)
+{
+
+  XMC_RTC_TIME_t time;
+
+  time.seconds = stdtime->tm_sec;
+  time.minutes = stdtime->tm_min;
+  time.hours = stdtime->tm_hour;
+  time.days = stdtime->tm_mday - 1;
+  time.month = stdtime->tm_mon;
+  time.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
+  time.daysofweek = stdtime->tm_wday;
+
+  XMC_RTC_SetTime(&time);
+}
+
 /*
  * Gets the RTC module time values in standard format
  */
@@ -230,6 +253,24 @@ void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm)
 }
 
 
+/*
+ * Sets the RTC module alarm time value in standard format
+ */
+void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime)
+{
+  XMC_RTC_ALARM_t alarm;
+  
+
+  alarm.seconds = stdtime->tm_sec;
+  alarm.minutes = stdtime->tm_min;
+  alarm.hours = stdtime->tm_hour;
+  alarm.days = stdtime->tm_mday - 1;
+  alarm.month = stdtime->tm_mon;
+  alarm.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
+
+  XMC_RTC_SetAlarm(&alarm);
+}
+
 /*
  * Gets the RTC module alarm time value in standard format
  */

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_sdmmc.c

@@ -1,13 +1,13 @@
 
 /**
  * @file xmc_sdmmc.c
- * @date 2015-10-27
+ * @date 2016-07-11
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -44,6 +44,12 @@
  * 2015-06-20:
  *     - Removed definition of GetDriverVersion API <br>
  *
+ * 2016-03-14:
+ *     - Values are directly assigned to the int status registers <br>
+ *
+ * 2016-07-11:
+ *     - XMC_SDMMC_SetDataTransferMode() shall not invoke SetDateLineTimeout() <br>
+ *
  * @endcond
  */
  
@@ -257,8 +263,8 @@ void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event)
   XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
   XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid bit-field", !(event & XMC_SDMMC_TARGET_RESP_ERR));
 
-  sdmmc->INT_STATUS_NORM |= (uint16_t)event;
+  sdmmc->INT_STATUS_NORM = (uint16_t)event;
-  sdmmc->INT_STATUS_ERR |= (uint16_t)(event >> 16U);
+  sdmmc->INT_STATUS_ERR = (uint16_t)(event >> 16U);
 }
 
 /* Get the status of an SDMMC event */
@@ -309,9 +315,6 @@ void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_
   XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
   XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid transfer type", XMC_SDMMC_CHECK_TRANSFER_MODE(response->type));
   
-  /* Data line time-out */
-  XMC_SDMMC_SetDataLineTimeout(sdmmc, XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27);
-
   /* Block size */
   sdmmc->BLOCK_SIZE = (uint16_t)(response->block_size);
   
@@ -319,7 +322,8 @@ void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_
   sdmmc->BLOCK_COUNT = (uint16_t)(response->num_blocks);
 
   /* Type of data transfer: single, infinite, multiple or stop multiple */
-  sdmmc->TRANSFER_MODE |= (uint16_t)response->type;
+  sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk) |
+                                    ((uint16_t)response->type));
 
   /*
    * Clear block count enable bit; that's only valid for

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_spi.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_spi.c
- * @date 2015-10-27
+ * @date 2015-11-04
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -47,7 +47,10 @@
  *     - Removed GetDriverVersion API <br>
  *
  * 2015-09-01:
- *     - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration <br>
+ *     - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration <br>
+ *
+ * 2015-11-04: 
+ *     - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag <br>
  * @endcond 
  *
  */
@@ -158,7 +161,7 @@ void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons
   /* Check FIFO size */
   if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
   {
-    while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
+    while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
     {
     }
   

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_uart.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_uart.c
- * @date 2015-10-27
+ * @date 2016-07-22
  *
  * @cond
  *********************************************************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
@@ -48,6 +48,11 @@
  *
  * 2015-09-01:
  *     - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration <br>
+ * 
+ * 2016-07-22:
+ *     - Modified XMC_UART_CH_Init() to enable transfer status BUSY
+ *     - Modified XMC_UART_CH_Stop() to check for transfer status
+ *
  * @endcond 
  *
  */
@@ -90,10 +95,13 @@ void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const
    * Pulse length is set to 0 to have standard UART signaling, 
    * i.e. the 0 level is signaled during the complete bit time
    * Sampling point set equal to the half of the oversampling period
-   * Enable Sample Majority Decision */
+   * Enable Sample Majority Decision 
+   * Enable Transfer Status BUSY
+   */
   channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) |
-			             (((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) |
+                                    (((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) |
-			             USIC_CH_PCR_ASCMode_SMD_Msk);
+                                    USIC_CH_PCR_ASCMode_SMD_Msk |
+                                    USIC_CH_PCR_ASCMode_RSTEN_Msk | USIC_CH_PCR_ASCMode_TSTEN_Msk);
 
   /* Set passive data level, high
      Set word length. Data bits - 1
@@ -101,7 +109,7 @@ void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const
      Transmission Mode: The shift control signal is considered active if it
      is at 1-level. This is the setting to be programmed to allow data transfers */
   channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) |
-		              ((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk));
+                             ((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk));
 
   if (config->frame_length != 0U)
   {
@@ -181,14 +189,16 @@ uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
 XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel)
 {
   XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK;
-  if ((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
+
+  if (((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) ||
+      ((XMC_UART_CH_GetStatusFlag(channel) & XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY) != 0))
   {
-	status = XMC_UART_CH_STATUS_BUSY;
+    status = XMC_UART_CH_STATUS_BUSY;
   }
   else
   {
-	/* USIC channel in IDLE mode */
+    /* USIC channel in IDLE mode */
-	XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
+    XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
   }
   return status;
 }

Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/lib/xmclib/src/xmc_usbd.c

@@ -1,12 +1,12 @@
 /**
  * @file xmc_usbd.c
- * @date 2015-10-27
+ * @date 2015-06-20
  *
  * @cond
  **********************************************************************************
- * XMClib v2.1.2 - XMC Peripheral Driver Library 
+ * XMClib v2.1.8 - XMC Peripheral Driver Library 
  *
- * Copyright (c) 2015, Infineon Technologies AG
+ * Copyright (c) 2015-2016, Infineon Technologies AG
  * All rights reserved.                        
  *                                             
  * Redistribution and use in source and binary forms, with or without