x86: ns16550: Rework driver to allow for x86 I/O space
The current implementation fakes a memory-mapped I/O device at 0x3f8 and 0x2f8, then uses platform read/write functions to do the actual reading and writing. These platform functions only exist for the x86 platform; better to move the I/O routines into the driver and have the driver request I/O ports using request_ioport_region. Signed-off-by: Michel Stam <michel@reverze.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
940237285e
commit
9f556d4b6f
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@ -223,7 +223,8 @@ static int eukrea_cpuimx27_console_init(void)
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imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
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imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
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add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
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IORESOURCE_MEM_16BIT, &quad_uart_serial_plat);
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IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
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&quad_uart_serial_plat);
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#endif
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#endif
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return 0;
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return 0;
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}
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}
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@ -60,7 +60,8 @@ static int armada_370_xp_add_uart(void)
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uart_plat.clock = clk_get_rate(tclk);
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uart_plat.clock = clk_get_rate(tclk);
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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(unsigned int)CONSOLE_UART_BASE, 32,
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(unsigned int)CONSOLE_UART_BASE, 32,
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IORESOURCE_MEM_32BIT, &uart_plat))
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IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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&uart_plat))
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return -ENODEV;
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return -ENODEV;
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return 0;
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return 0;
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}
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}
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@ -58,7 +58,8 @@ static int kirkwood_add_uart(void)
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uart_plat.clock = clk_get_rate(tclk);
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uart_plat.clock = clk_get_rate(tclk);
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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(unsigned int)CONSOLE_UART_BASE, 32,
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(unsigned int)CONSOLE_UART_BASE, 32,
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IORESOURCE_MEM_32BIT, &uart_plat))
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IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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&uart_plat))
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return -ENODEV;
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return -ENODEV;
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return 0;
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return 0;
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}
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}
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@ -45,8 +45,8 @@ static void socfpga_uart_init(void)
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clks[uart] = clk_fixed("uart", 100000000);
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clks[uart] = clk_fixed("uart", 100000000);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
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add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM_8BIT,
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add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
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&uart_pdata);
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IORESOURCE_MEM_8BIT, &uart_pdata);
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}
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}
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static void socfpga_timer_init(void)
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static void socfpga_timer_init(void)
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@ -50,7 +50,7 @@ static int tegra20_add_debug_console(void)
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return -ENODEV;
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return -ENODEV;
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add_ns16550_device(DEVICE_ID_DYNAMIC, base, 8 << debug_uart.shift,
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add_ns16550_device(DEVICE_ID_DYNAMIC, base, 8 << debug_uart.shift,
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IORESOURCE_MEM_8BIT, &debug_uart);
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &debug_uart);
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return 0;
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return 0;
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}
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}
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@ -36,7 +36,7 @@ static int dir320_console_init(void)
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/* Register the serial port */
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/* Register the serial port */
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add_ns16550_device(DEVICE_ID_DYNAMIC, DEBUG_LL_UART_ADDR, 8,
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add_ns16550_device(DEVICE_ID_DYNAMIC, DEBUG_LL_UART_ADDR, 8,
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IORESOURCE_MEM_8BIT, &serial_plat);
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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return 0;
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}
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}
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@ -15,7 +15,7 @@ static int console_init(void)
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barebox_set_hostname("ls1b");
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barebox_set_hostname("ls1b");
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add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(LS1X_UART2_BASE),
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add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(LS1X_UART2_BASE),
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8, IORESOURCE_MEM_8BIT, &serial_plat);
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8, IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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return 0;
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}
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}
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@ -189,7 +189,9 @@ static int ar2312_console_init(void)
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/* Register the serial port */
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/* Register the serial port */
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serial_plat.clock = ar2312_sys_frequency();
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serial_plat.clock = ar2312_sys_frequency();
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add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(AR2312_UART0),
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add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(AR2312_UART0),
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8 << AR2312_UART_SHIFT, IORESOURCE_MEM_8BIT, &serial_plat);
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8 << AR2312_UART_SHIFT,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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&serial_plat);
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return 0;
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return 0;
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}
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}
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console_initcall(ar2312_console_init);
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console_initcall(ar2312_console_init);
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@ -15,7 +15,8 @@ static int openrisc_console_init(void)
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barebox_set_hostname("or1k");
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barebox_set_hostname("or1k");
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/* Register the serial port */
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/* Register the serial port */
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add_ns16550_device(DEVICE_ID_DYNAMIC, OPENRISC_SOPC_UART_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat);
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add_ns16550_device(DEVICE_ID_DYNAMIC, OPENRISC_SOPC_UART_BASE, 1024,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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#ifdef CONFIG_DRIVER_NET_ETHOC
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#ifdef CONFIG_DRIVER_NET_ETHOC
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add_generic_device("ethoc", DEVICE_ID_DYNAMIC, NULL,
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add_generic_device("ethoc", DEVICE_ID_DYNAMIC, NULL,
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@ -130,7 +130,7 @@ static int p1022ds_console_init(void)
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serial_plat.clock = fsl_get_bus_freq(0);
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(DEVICE_ID_DYNAMIC, CFG_IMMR + 0x4500, 16,
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add_ns16550_device(DEVICE_ID_DYNAMIC, CFG_IMMR + 0x4500, 16,
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IORESOURCE_MEM_8BIT, &serial_plat);
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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return 0;
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}
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}
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@ -112,7 +112,8 @@ static int p2020_console_init(void)
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serial_plat.clock = fsl_get_bus_freq(0);
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16, IORESOURCE_MEM_8BIT,
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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&serial_plat);
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&serial_plat);
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return 0;
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return 0;
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}
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}
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@ -115,7 +115,8 @@ static int da923rc_console_init(void)
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barebox_set_model("unknown");
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barebox_set_model("unknown");
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serial_plat.clock = fsl_get_bus_freq(0);
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(1, CFG_CCSRBAR + 0x4600, 16, IORESOURCE_MEM_8BIT,
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add_ns16550_device(1, CFG_CCSRBAR + 0x4600, 16,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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&serial_plat);
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&serial_plat);
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return 0;
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return 0;
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}
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}
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@ -30,8 +30,6 @@
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static struct NS16550_plat serial_plat = {
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static struct NS16550_plat serial_plat = {
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.clock = 1843200,
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.clock = 1843200,
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.reg_read = x86_uart_read,
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.reg_write = x86_uart_write,
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};
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};
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static int pc_console_init(void)
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static int pc_console_init(void)
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@ -40,7 +38,10 @@ static int pc_console_init(void)
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barebox_set_hostname("x86");
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barebox_set_hostname("x86");
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/* Register the serial port */
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/* Register the serial port */
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0x3f8, 8, 0, &serial_plat);
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0x3f8, 8, IORESOURCE_IO,
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&serial_plat);
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0x2f8, 8, IORESOURCE_IO,
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&serial_plat);
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return 0;
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return 0;
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}
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}
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@ -14,9 +14,6 @@
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*
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*
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*/
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*/
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extern unsigned int x86_uart_read(unsigned long, unsigned char);
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extern void x86_uart_write(unsigned int, unsigned long, unsigned char);
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#ifdef CONFIG_X86_BIOS_BRINGUP
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#ifdef CONFIG_X86_BIOS_BRINGUP
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extern int bios_disk_rw_int13_extensions(int, int, void*) __attribute__((regparm(3)));
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extern int bios_disk_rw_int13_extensions(int, int, void*) __attribute__((regparm(3)));
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@ -1,4 +1,3 @@
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obj-y += generic.o
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obj-y += reset.o
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obj-y += reset.o
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# reference clocksource
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# reference clocksource
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@ -1,34 +0,0 @@
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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/**
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* @file
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* @brief x86 Architecture Initialization routines
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*/
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#include <io.h>
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/** to work with the 8250 UART driver implementation we need this function */
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unsigned int x86_uart_read(unsigned long base, unsigned char reg_idx)
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{
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return inb(base + reg_idx);
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}
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/** to work with the 8250 UART driver implementation we need this function */
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void x86_uart_write(unsigned int val, unsigned long base, unsigned char reg_idx)
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{
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outb(val, base + reg_idx);
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}
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@ -47,6 +47,7 @@ struct ns16550_priv {
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struct console_device cdev;
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struct console_device cdev;
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struct NS16550_plat plat;
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struct NS16550_plat plat;
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int access_width;
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int access_width;
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int mmio;
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struct clk *clk;
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struct clk *clk;
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uint32_t fcrval;
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uint32_t fcrval;
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};
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};
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@ -61,6 +62,90 @@ struct ns16550_drvdata {
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const char *linux_console_name;
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const char *linux_console_name;
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};
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};
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/**
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* @brief read system i/o (byte)
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* @param[in] addr address to read
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline uint8_t ns16550_sys_readb(void __iomem *addr, int mmio)
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{
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if (mmio)
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return readb(addr);
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else
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return (uint8_t) inb((int) addr);
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}
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/**
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* @brief read system i/o (word)
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* @param[in] addr address to read
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline uint16_t ns16550_sys_readw(void __iomem *addr, int mmio)
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{
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if (mmio)
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return readw(addr);
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else
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return (uint16_t) inw((int) addr);
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}
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/**
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* @brief read system i/o (dword)
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* @param[in] addr address to read
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline uint32_t ns16550_sys_readl(void __iomem *addr, int mmio)
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{
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if (mmio)
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return readl(addr);
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else
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return (uint32_t) inl((int) addr);
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}
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/**
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* @brief write system i/o (byte)
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* @param[in] val data to write
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* @param[in] addr address to write to
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline void ns16550_sys_writeb(uint8_t val, void __iomem *addr,
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int mmio)
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{
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if (mmio)
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writeb(val, addr);
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else
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outb(val, (int) addr);
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}
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/**
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* @brief read system i/o (word)
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* @param[in] val data to write
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* @param[in] addr address to write to
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline void ns16550_sys_writew(uint16_t val, void __iomem *addr,
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int mmio)
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{
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if (mmio)
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writew(val, addr);
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else
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outw(val, (int) addr);
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}
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/**
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* @brief read system i/o (dword)
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* @param[in] val data to write
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* @param[in] addr address to write to
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* @param[in] mmio memory i/o space or i/o port space
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*/
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static inline void ns16550_sys_writel(uint32_t val, void __iomem *addr,
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int mmio)
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{
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if (mmio)
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writel(val, addr);
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else
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outl(val, (int) addr);
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}
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/**
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/**
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* @brief read register
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* @brief read register
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*
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*
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@ -78,16 +163,13 @@ static uint32_t ns16550_read(struct console_device *cdev, uint32_t off)
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off <<= plat->shift;
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off <<= plat->shift;
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if (plat->reg_read)
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return plat->reg_read((unsigned long)dev->priv, off);
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switch (width) {
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switch (width) {
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case IORESOURCE_MEM_8BIT:
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case IORESOURCE_MEM_8BIT:
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return readb(dev->priv + off);
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return ns16550_sys_readb(dev->priv + off, priv->mmio);
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case IORESOURCE_MEM_16BIT:
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case IORESOURCE_MEM_16BIT:
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return readw(dev->priv + off);
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return ns16550_sys_readw(dev->priv + off, priv->mmio);
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case IORESOURCE_MEM_32BIT:
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case IORESOURCE_MEM_32BIT:
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return readl(dev->priv + off);
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return ns16550_sys_readl(dev->priv + off, priv->mmio);
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}
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}
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return -1;
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return -1;
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}
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}
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@ -109,20 +191,15 @@ static void ns16550_write(struct console_device *cdev, uint32_t val,
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off <<= plat->shift;
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off <<= plat->shift;
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if (plat->reg_write) {
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||||||
plat->reg_write(val, (unsigned long)dev->priv, off);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (width) {
|
switch (width) {
|
||||||
case IORESOURCE_MEM_8BIT:
|
case IORESOURCE_MEM_8BIT:
|
||||||
writeb(val & 0xff, dev->priv + off);
|
ns16550_sys_writeb(val & 0xff, dev->priv + off, priv->mmio);
|
||||||
break;
|
break;
|
||||||
case IORESOURCE_MEM_16BIT:
|
case IORESOURCE_MEM_16BIT:
|
||||||
writew(val & 0xffff, dev->priv + off);
|
ns16550_sys_writew(val & 0xffff, dev->priv + off, priv->mmio);
|
||||||
break;
|
break;
|
||||||
case IORESOURCE_MEM_32BIT:
|
case IORESOURCE_MEM_32BIT:
|
||||||
writel(val, dev->priv + off);
|
ns16550_sys_writel(val, dev->priv + off, priv->mmio);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -293,16 +370,30 @@ static int ns16550_probe(struct device_d *dev)
|
||||||
struct console_device *cdev;
|
struct console_device *cdev;
|
||||||
struct NS16550_plat *plat = (struct NS16550_plat *)dev->platform_data;
|
struct NS16550_plat *plat = (struct NS16550_plat *)dev->platform_data;
|
||||||
struct ns16550_drvdata *devtype;
|
struct ns16550_drvdata *devtype;
|
||||||
|
struct resource *res;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
|
ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
|
||||||
if (ret)
|
if (ret)
|
||||||
devtype = &ns16550_drvdata;
|
devtype = &ns16550_drvdata;
|
||||||
|
|
||||||
dev->priv = dev_request_mem_region(dev, 0);
|
|
||||||
|
|
||||||
priv = xzalloc(sizeof(*priv));
|
priv = xzalloc(sizeof(*priv));
|
||||||
|
|
||||||
|
res = dev_get_resource(dev, IORESOURCE_MEM, 0);
|
||||||
|
priv->mmio = (res != NULL);
|
||||||
|
if (res) {
|
||||||
|
res = request_iomem_region(dev_name(dev), res->start, res->end);
|
||||||
|
} else {
|
||||||
|
res = dev_get_resource(dev, IORESOURCE_IO, 0);
|
||||||
|
if (res)
|
||||||
|
res = request_ioport_region(dev_name(dev), res->start,
|
||||||
|
res->end);
|
||||||
|
}
|
||||||
|
if (!res)
|
||||||
|
goto err;
|
||||||
|
dev->priv = (void __force __iomem *) res->start;
|
||||||
|
|
||||||
|
|
||||||
if (plat)
|
if (plat)
|
||||||
priv->plat = *plat;
|
priv->plat = *plat;
|
||||||
else
|
else
|
||||||
|
|
|
@ -278,7 +278,7 @@ static inline struct device_d *add_ns16550_device(int id, resource_size_t start,
|
||||||
resource_size_t size, int flags, struct NS16550_plat *pdata)
|
resource_size_t size, int flags, struct NS16550_plat *pdata)
|
||||||
{
|
{
|
||||||
return add_generic_device("ns16550_serial", id, NULL, start, size,
|
return add_generic_device("ns16550_serial", id, NULL, start, size,
|
||||||
IORESOURCE_MEM | flags, pdata);
|
flags, pdata);
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_DRIVER_NET_DM9K
|
#ifdef CONFIG_DRIVER_NET_DM9K
|
||||||
|
|
|
@ -33,18 +33,9 @@
|
||||||
struct NS16550_plat {
|
struct NS16550_plat {
|
||||||
/** Clock speed */
|
/** Clock speed */
|
||||||
unsigned int clock;
|
unsigned int clock;
|
||||||
/**
|
|
||||||
* register read access capability
|
|
||||||
*/
|
|
||||||
unsigned int (*reg_read) (unsigned long base, unsigned char reg_offset);
|
|
||||||
/**
|
|
||||||
* register write access capability
|
|
||||||
*/
|
|
||||||
void (*reg_write) (unsigned int val, unsigned long base,
|
|
||||||
unsigned char reg_offset);
|
|
||||||
|
|
||||||
int shift;
|
int shift;
|
||||||
unsigned int flags;
|
unsigned int flags;
|
||||||
|
int mmio;
|
||||||
#define NS16650_FLAG_DISABLE_FIFO 1
|
#define NS16650_FLAG_DISABLE_FIFO 1
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue