It is not the chip, but this controller which cannot do subpage writes.
So, make sure we add the flag at the proper place, so it doesn't get
overwritten by flash detection anymore.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EfikaSB has a bug requiring to write to an ULPI register after
powerup. It doesn't seem that this this bug is present on any other
hardware, so add a workaround directly into the driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Efika MX Smartbook is a i.MX51 based netbook. This patch adds
nearly full support for it including:
- USB
- SD card slots
- Internal SPI NOR flash
- Internal flash PATA drive
- LEDs
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When multiple MMC/SD cards are present in the system we often
have to have persistent names to identify them during runtime.
This patch allows to overwrite the devicename which is used.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make the register defines for ULPI more complete. Also, Add a proper
ULPI_* Namespace to the existing defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board variant found on the AT24 EEPROM holds the variant ID that we
can use to identify which expansion board we are running on and thus
which device tree to load and pass to the kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The AT24 found on the expansion boards store the variant of the board it
is soldered onto.
That means that we are that way able to determine what expansion board
is currently plugged in if any. If we can't communicate with the EEPROM,
we just assume that only the CFA-10036 is there.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This EEPROM is found on the expansion boards available for the 10036
module. Since we won't need to do anything fancy except reading/writing
from it, use bitbanging to communicate with it.
This EEPROM will hold mostly the board_id so that we can determine if
there is an expansion board plugged in and what expansion board it is.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Trivial pbl support has no cpu specific setup.
We will add cache setup routines in the future.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch is based on ARM pbl support and allows
creating a pre-bootloader binary for compressed image.
For different MIPS SoCs (or even for different boards based
on the same SoC) the operations carried on in start-pbl.S
can be very different. The additional constraints can be imposed
on the size of the boot code or the special magic labels in
the beginning of the boot code; In some cases it could be
necessary to show CPU is alive as early as possible
(transmit a char via UART or blink a LED).
So the demands for pbl start operation can be very different.
E.g. malta board store boot code at the NOR flash mapped
to the MIPS power-on address (0xbfc00000); it is the most
simple case: we need just copy pbl image from direct-mapped
flash to RAM and jump there.
The XBurst-powered boards store boot code in the beginning
of a NAND flash or in the beginning of SD/MMC card.
In this case we must use simple and short NAND or SD/MMC access
routines to copy pbl image to RAM.
To meet so different demands a simple technique is selected:
* MIPS pbl entry point located in file arch/mips/boot/start-pbl.S.
* MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled
board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h
header file. This file must contain definition of
the board_pbl_start macro. This macro is used as start of pbl image;
* the most popular asm routines (stack setup, relocation to link
address, NS16550 initialization (WIP) and so on) are containt
in the arch/mips/include/asm/pbl_macros.h header file.
So board pbl macro can use it if necessary.
It is possible to create similar headers with macros for each
specific SoC; so even if we have many different boards based
on the same SoC the board_pbl_start macro for every board
can be short and clear.
* after board-specific initialization the stack pointer
is initialized and pbl C code is started.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ULPI lines are normally input to the USB port. In order to configure
the ULPI transceiver properly the ongoing transfers must be stopped. This
can be done by configuring the the STP pin as gpio output and drinving
it high.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Register the USB misc devices and provide convenience wrappers to
register the USB ports for i.MX27.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For proper USB function the usbmisc registers have to be initialized.
This patch adds a driver which matches for the usbmisc registers. This
driver is called from a new driver which binds to the USB ports to
configure the misc registers. After that the driver registers the EHCI
driver and an ULPI transceiver if necessary. Currently only host mode
is supported, but device support can be added later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EHCI core often is part of a otg core. Allow it to be registered
separately from another driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The smsc911x has a bootstrap pin for detecting an external phy.
Unfortunately this is pulled into the wrong direction on the pcm037
board, so force internal phy with platform data.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When starting a network device wait until the link is up. Otherwise
autobooting does not work with little timeout and several attempts
have to be made until the network is finally up.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX27/31 have the second chip select enabled by reset default.
This can be considered as a hardware bug, because even boards which
need this settings cannot work out of reset because of the missing
initialization sequence. Detect this reset default setting and disable
this chipselect then to be able to properly detect the SDRAM size.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
dev_add_child is a very unsafe function. If called multiple times
it allows setting the same device to different parents thus corrupting
the siblings list. This happens regularly since:
| commit c2e568d19c
| Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| Date: Sat Nov 3 16:11:05 2012 +0100
|
| bus: add bus device
|
| automatically add it as parent of any bus device if none already specified
|
| we have now a nice output per bus
If for example a FATfs is mounted this nice output per bus often ends with:
> `---- fat0
> `---- 0
> `---- 0x86f0000087020031-0x86f000410df27124: /dev/<NULL>
> `---- sram00
> `---- 0x00000000-0xffffffffffffffff: /dev/<NULL>
> `---- 0x00000000-0xffffffffffffffff: /dev/<NULL>
> unable to handle NULL pointer dereference at address 0x0000000c
> pc : [<87f08a20>] lr : [<87f08a04>]
> sp : 86eff8c0 ip : 87f3fbde fp : ffffffff
> r10: ffffffff r9 : 00000000 r8 : 00000003
> r7 : 86f075b8 r6 : 00000002 r5 : ffffffec r4 : 86f07544
> r3 : 00000000 r2 : 43f900b4 r1 : 00000020 r0 : 00000005
> Flags: Nzcv IRQs off FIQs off Mode SVC_32
> [<87f08a20>] (do_devinfo_subtree+0x90/0x130) from [<87f08a90>] (do_devinfo_subtree+0x100/0x130)
>
> [<87f3e070>] (unwind_backtrace+0x0/0x90) from [<87f28514>] (panic+0x28/0x3c)
> [<87f28514>] (panic+0x28/0x3c) from [<87f3e4b8>] (do_exception+0x10/0x14)
> [<87f3e4b8>] (do_exception+0x10/0x14) from [<87f3e544>] (do_data_abort+0x2c/0x38)
> [<87f3e544>] (do_data_abort+0x2c/0x38) from [<87f3e268>] (data_abort+0x48/0x60)
This patch fixes this by adding a device to its parents children list in
register_device so that dev_add_child is no longer needed. This function
is removed from the tree. Now callers of register_device have to clearly
set the parent *before* registering a device.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reported-by: Jan Lübbe <jlu@pengutronix.de>
We call phy_update_status only once in 5 seconds. This makes
sure we do not have great overhead when using ethernet devices.
However, if phylib tells us the link is down anyway, there won't
be ethernet transfers, so it doesn't hurt to call phy_update_status
in this case. This makes sure we can use the ethernet device when
the link comes up and do not have an additional 5 second penalty
in this case.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some phys come up with this bit set, clear it so that these phys
can work. This has been observed with a ASIX compatible USB ethernet
adapter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
omap3 has a soc specific reset function, make sure it calls common_reset
so that the proper CPU flags are set.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We allow unaligned accesses on ARMv6 onwards, make sure the CR_A
flag is cleared so that unaligned accesses do not trap.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox not contain symbol MTD_NAND, so remove all references to it.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Wolfram Sang
Sascha Hauer
Maxime Ripard
Antony Pavlov
Alexander Shiyan