form linux 3.8
so you can have part by num or name
not by GUID as this is a non human reading name
`---- ffe08000.sata
`---- 0x00000000-0x3fffffff: /dev/ata0
`---- 0x00100000-0x063fffff: /dev/ata0.0
`---- 0x00100000-0x063fffff: /dev/ata0.boot
`---- 0x06400000-0x3fefffff: /dev/ata0.1
`---- 0x06400000-0x3fefffff: /dev/ata0.linux
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we can register partion with name as present in EFI GPT
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we can support multiple format
use filetpye to detect the parser to use
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
GPT need to be check before MBR
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
need it by upcoming EFI GPT support
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
Could you please review, or suggest better alternatives ?
Thanks,
--
Ivan
(this is a shorter and (hopefully) clearer repost of
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/144916.html)
The patch adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes:
arch/arm/boards/phycard-a-l1/lowlevel.c: In function 'pcaal1_sdrc_init':
arch/arm/boards/phycard-a-l1/lowlevel.c:105:2: warning: implicit declaration of function 'get_ram_size' [-Wimplicit-function-declaration]
arch/arm/boards/phycard-a-l1/lowlevel.c:113:3: warning: implicit declaration of function 'hang' [-Wimplicit-function-declaration]
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX21 has a imx1 gpio type. Change the name accordingly, otherwise
the gpio driver does not probe successfully.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX35 has a imx31 gpio type. Change the name accordingly, otherwise
the gpio driver does not probe successfully.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
__dev_printf is a define which uses a local variable 'ret'. This
means that whenever someone does a dev_*(dev, "ret: %d\n", ret);
ret will be 0.
Fix this by writing this without a local variable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The default setting for the imx28 watchdog is to do a power-off reset. If the
SoC is only powered via battery, then the watchdog powers the chip down, though.
According to the datasheet it should still be possible to execute a proper POR
with battery power, but testing showed otherwise.
When the watchdog power-off reset is disabled, a software reset is executed
instead. This works with and without battery power.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ArchosG9 the second stage low-level init was the fallback default.
Now that the low-level init is forcibly enabled it has to be skipped
when already executed from first stage.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Due to a hw bug do not enable teh Asym_Pause.
Otherwise if you ser the bit 11 in 4h you will have to unplug
and replug the cable to make the phy work.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
based on the kernel code
detect it via IP version
In the GEM we can use a full packet buffer for receive but the buffer size
need to be 64bit size aligned.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
the mininal tx ring size is 2 as if one we wrap on the same descriptor
and can cause IP lock on GEM (gigabit version) this is always the case
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as eth_device init is planning for remove and we need the init before register
the mdio bus
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
reset is confusing with the cpu reset and impossible to grep
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this will allow to pass more paraemeter to at91sam926x_lowlevel_init
and drop AT91_BASE_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this will make the code more readble
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here's the error message:
LD arch/mips/pbl/zbarebox
pbl/built-in-pbl.o: In function `decompress_unlzo':
/home/antony/barebox.git.rebased.isp/pbl/decomp.c:35: undefined reference to `free'
pbl/built-in-pbl.o: In function `pbl_barebox_uncompress':
(.text.pbl_barebox_uncompress+0x6d0): relocation truncated to fit: R_MIPS_26 against `free'
pbl/built-in-pbl.o: In function `pbl_barebox_uncompress':
(.text.pbl_barebox_uncompress+0x6e0): undefined reference to `free'
pbl/built-in-pbl.o: In function `pbl_barebox_uncompress':
(.text.pbl_barebox_uncompress+0x6e0): relocation truncated to fit: R_MIPS_26 against `free'
make[1]: *** [arch/mips/pbl/zbarebox] Error 1
make: *** [zbarebox.bin] Error 2
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
HAVE_CONFIGURABLE_MEMORY_LAYOUT was first meant as a feature, now it's a
feature to remove it. barebox on ARM now completely uses the memory passed
in from the lowlevel code and configures the malloc area and stack space
during runtime making it obsolete to hardcode these values.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Defining STACK_BASE and MALLOC_BASE only makes sense when
either CONFIG_MEMORY_LAYOUT_DEFAULT or CONFIG_MEMORY_LAYOUT_FIXED
is set, so use separate #ifdefs instead ot #if/#else
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This optionally enabled the MMU in the PBL or during early startup for
the non PBL case. The regular MMU init code will pickup the already enabled
MMU later. This might complicate debugging early code, so this has been
made optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move early mmu code to a separate file so that it can be
used from the pbl and the regular image. Disabling the mmu
can be dropped since the regular mmu code is now able to
pickup an enabled mmu.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Jean-Christophe PLAGNIOL-VILLARD
Ivan Djelic
Sascha Hauer
Steffen Trumtrar
Vicente Bergas
Alexander Shiyan
Antony Pavlov