This just starts the main image of the mvebu image assuming that the
header images just setup the RAM. The position of the internal register
window is provided in the header as introduced in the previous commit.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
A problem when using 2nd stage booting on mvebu is that the first bootloader
already switched the register window location from 0xd0000000 to
0xf1000000 by writing to 0xd0000080. When the second bootloader also
tries to do this switch it writes to the wrong location resulting in an
exception and so a boot failure.
For this reason the base address of the register window is passed in the
barebox header and picked up from there by early code. In a further
patch bootm is taught to put the actual position of the window there for
the second bootloader to finally make second stage booting work.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
binary.0 sets up all RAM but the address decoding isn't adapted accordingly
which makes barebox assume that there are only 512 MiB of RAM on a single
bank instead of two banks with 1 GiB each.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Similar to the two previous commits, this gets rid of a of-fixup which
is strange because the soc init stuff is rerun then when a new dt for
booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Similar to the previous commit, this gets rid of a of-fixup which is
strange because the soc init stuff is rerun then when a new dt for
booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This gets rid of a of-fixup which is strange because the soc init stuff
is rerun then when a new dt for booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit switches the RaspberryPi arch over to probe Barebox
from the builtin DT and enables multi-image builds.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To let the user select the right base, when building multi-image.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Makes more space available for the malloc area and will allow
to switch to multi-image later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This way we can print the correct model in the Barebox banner.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Raspberry PIs use different versions schemes for the older and newer
variants. The decoding arrays for these schemes were split up in rpi.c
and rpi2.c. This is not required, as the appropriate versioning scheme
can be determined programmatically.
Signed-off-by: Enrico Joerns <ejo@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This machine was a prototype and was never shipped to customers.
Since it has no dependencies to any image, it can be removed.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
prepare to drop the efi arch as efi boot up is not arch sepecific
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so other arch could include it too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as efi is not an arch but a boot mode from where barebox is started
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so it can be reused on any ARCH
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MACH_SABRELITE is only selectable if IMX_MULTI_BOARDS is enabled. The latter
already selects HAVE_PBL_MULTI_IMAGES.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Status quo is that initially a size of 64 MiB is assumed (which is also
used to determine the size of the malloc area) and then later the dtb
is fixed up with the actually available RAM which is then used.
Instead detect the real RAM size earlier and don't fixup the device tree.
The device tree is fixed up instead by generic code. This way the malloc
area is more appropriately sized and RAM detection is more similar to mach-imx
which is both nice.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This isn't needed since mvebu was converted to multi-pbl
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have a number of sama5d3 devices that sometimes hangs at the
barebox prompt during boot due to floating RX pins. This patch
fixes the problem for us (and probably others). It is similar in
nature to linux kernel commit 138c2b2f175b ("ARM: dts: at91: fixes
dbgu pinctrl, set pullup on rx, clear pullup on tx")
While at it, remove pointless waste of power that the pullup of
the TX pins causes and fix the signal comments for SAMA5D4.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IIM unit in defferent i.MX SoCs is always the same, but the
number of actually equipped fuses differs between the SoCs.
Reading nonexistent fuses oopses, so only register the fuses
we can actually read.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).
The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.
In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.
With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.
The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).
We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory
The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.
The PSCI and secure monitor code is based on the corresponding U-Boot
code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for ZII VF610 Dev based designs such as:
- VF610 Dev, revision B
- VF610 Dev, revision C
- CFU1, revision A
- SPU3, revision A
- SCU4 AIB, revision C
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Needed for compiling the i.MX7 warp board which already includes this
file.
This file is necessary because the upstream dtsi file currently assigns
MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful
clock rate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX7 has two pinmux controllers, the regular and the LPSR
controller. The LPSR pinmux controller doesn't have any sel_input
registers, instead they can be found in the regular pinmux controller.
This means whenever we want to apply the the sel_input setting for
the LPSR controller, we have to apply them to the regular controller
instead.
In barebox take the easy way out and just add the difference of the
two base addresses to the register offset. The same issue is present
in the Kernel aswell, but when the bootloader already configured
the pins correctly nobody notices when the Kernel sel_input setup
effectively is a no-op.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It's essential that we always pass the same size value to
arm_mem_barebox_image(), otherwise the result will be inconsistent.
Pass arm_barebox_size instead of barebox_image_size as the latter
does not contain the max bss segment size.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Most i.MX6SL infrastructure is already covered in barebox by general i.MX6
support. Missing infrastructure provided in separate commits are
* SoC type detection
* Clock infrastructure
Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc
and the remaining bits and pieces to provide barebox i.MX6SL SoC support.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX6 series SoC type is determined by barebox by examining the
USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located
at a common offset for all mx6 SoC - except for i.MX6SL where a different
offset is used. This creates a dilemma while distinguishing the mx6sl from
non-mx6sl SOC since the SoC type identification register location is type
specific itself.
Access to undocumented and probably invalid or unpredictable registers should
be avoided as possible. For the mx6sl detection an access to the general
USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This
register contained the value 0x00014009 for different mx6sl Rev. 1.2 based
e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This
implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller
than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s).
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision()
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Import the ARM IP bus base addresses from IMX7DRM 05/2016 AIPS Memory Map
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch is based on a patch from the U-Boot and fixes two errors with
the LCDC. Original commit message from Jyri Sarha [1]:
"Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock."
The register values are generated by testing, because there is no formula
to calculate them. Also from Jyri Sarha [1]:
"In practice the only rule to find an optimal value is to find as high as
possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO
underflows under worst case scenario. The worst case happens when the
highest pixel clock videomode with maximum bpp is used while memory
subsystem is stressed by endless stream of writes hitting the same
memory memory bank (can be the same address)."
It only contains the BeagleBone Black and the Phytec SoM, because I
don't have other boards.
[1] https://patchwork.ozlabs.org/patch/704013/
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Build of clk-imx7 depends on selection of COMMON_CLK_OF_PROVIDER
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
EFI applications should be unloaded to avoid leaking memory. However, boot
or runtime services continue in the background. So they must not be
unloaded.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is the same that U-Boot does. The registers are not documented.
Without this the architected timer on the i.MX7 does not work.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It is quite useless without a console and breaks the build.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for the QuadPlus variant of the board as a separate
Barebox binary.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Recent kernel versions should have appropriate driver code that sets up
interrupt rounting correctly, so there's no need for that to be done in
the bootloader.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add low-level pin configuration helper for early boot code, and convert
pinctrl driver to use that code as well.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Remove magic numbers in setup_uart and replace them with calls to
iomuxv3 helper functions.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add low-level pad configuration routine that can be used by early boot
code as well as leveraged by pinmux driver.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a basic low-level pad configuration function that can be used to
implement early boot pin configuration code as well as shared with
various iomuxv3 and vf610 drivers.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Mask ROM leaves the CPU running at 264Mhz, so configure the clock tree
such that CPU runs at maximum supported frequency. Maximum supported
frequncy is determined from speed grading burned into OCOTP fusebox by
the vendor.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add fusemap header for VF610 and move out fuse definitions that are
shared with i.MX6 familiy into a sperate file (ocotp-fusemap.h).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
According to the datasheet SJC_RESP_LOCK is one bit wide, adjust the
definition correspondingly.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add imx_ocotp_sense_enable() function to allow changing that aspect of
OCOTP driver behaviour before calling imx_ocotp_read_field()
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On Vybrid SoC OCOTP module contains speed grading information that is
needed to correctly adjust CPU clock to its maxumum rate, so we need to
have this information handy as early as possible.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
i.MX SoC variants like Vybrid have more than one built-in Ethernet
interface and as a consequence support storing more than one MAC address
in OCOTP module. Add code to create multiple 'mac_addr<n>' parameters as
well as 'mac_addr' as an "alias" to 'mac_addr0' for backwards
compatibility.
Acked-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move memory reversing, found in imx_ocotp_get_mac and
imx_ocotp_set_mac, into a subroutine to avoid code duplication.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Shadow memory does not have a true 1:1 mapping to fuse address
space. All i.MX6 devices, with exception of i.MX6SL have a 0x100 byte
gap between banks 5 and 6 (or addresses 0x2f and 0x30), so we need to
account for that when reading data from shadow memory.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Enable OCOTP driver on Vybrid as well as i.MX6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Give enet_osc explicit "enet_ext" name, since without it, Barebox
version of clk_set_parent fails when trying to re-parent "enet_sel".
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move clk code from 'mach-imx' to 'drivers' to keep the code tree
structure closer to that of analogous one from Linux kernel and,
arguably although subjective, to keep 'mach-imx' less cluttered.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Enabling the MMU (and so the caches) gives a nice performance boost, so
opt in for mvebu_defconfig.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If barebox binary image size exceeds the 4 MiB then
qemu exits with the 'Could not load MIPS bios' message.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The debug_ll_outhexw macro has no dependency on UART model
so we can remove it from UART-dependent header files (debug_ll_ns16550.h
and mach-ath79/.../debug_ll.h).
On the other hand the only debug_ll_outhexw user is MIPS nmon monitor
so we can move the debug_ll_outhexw macro to pbl_nmon.h.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Prolong global reset to the max. value of 0xff. Such a long reset
is required for some peripherals found on Baltos devices.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
PRM_RSTTIME register provides settings for global and power domain
reset durations.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The compatible vendor prefix for dialog pmic is dlg. We fix it in
the devicetrees using the wrong one.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The fpgamgr and sysmgr bindings are now in the upstream dtsi.
Remove them.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There is no fpga.c file.
Remove the entry.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It's no longer possible to assign a string to menu->display, instead
menu_add_title() must be called. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
nios2 links the board specific nios_sopc.h to include/. The relative
pathes used do not work with an out of tree build. Use absolute pathes
instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The file 'imx6qdl.dtsi' is already included by DualLite/Solo and
Dual/Quad specific files 'imx6dl.dtsi' and 'imx6q.dtsi'. So the include
is not needed here.
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the missing txc-skew-ps and rxc-skew-ps settings for the Micrel PHY.
I have seen problems with 1GBit ethernet on a phyCORE-i.MX6 Solo. Oddly
enough the missing skew values are no problems for all our other
modules.
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Refactor the common settings for device tree node 'fec' into the generic
phycore i.MX6 device tree file. This avoid redundant settings and makes
common fixes easier. Our kernel device tree files have the same layout.
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Uwe Kleine-König
Lucas Stach
Enrico Joerns
Daniel Schultz
Jean-Christophe PLAGNIOL-VILLARD
Alexander Kurz
Peter Rosin
Sascha Hauer
Wadim Egorov
Andrey Smirnov
Michael Olbrich
Juergen Borleis
Ulrich Ölmann
Antony Pavlov
Yegor Yefremov
Michael Grzeschik
Steffen Trumtrar
Christian Hemp
Stefan Lengfeld