Commit graph

932 commits

Author SHA1 Message Date
Tom Rini
dfe161032d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2012-11-26 14:53:33 -07:00
Scott Wood
c97cd1ba48 spl/85xx: new SPL support
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:25 -06:00
Scott Wood
4b919725b6 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
a179eb0a4b powerpc/mpc85xx: consistently use COBJS-y
A subsequent patch will conditionalize some of the files that are
currently unconditional.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
b9735cbaeb spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
59629c2897 spl/mpc85xx: move udelay to cpu code
It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:23 -06:00
Scott Wood
8bc50f0b6d powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
7f0a22ff25 powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
6ec63f411e powerpc: change .fixup test to a GCC version test
This was introduced by commit 2446151974, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing
2012-11-26 15:41:22 -06:00
Scott Wood
9a511bd6a3 powerpc/mpc85xx: add comma before "already enabled"
Now outputs like this:

L2:    512 KB already enabled, moving to 0xf8f80000

rather than this:

L2:    512 KB already enabledmoving to 0xf8f80000

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
2012-11-26 15:41:20 -06:00
Scott Wood
f545d300b0 powerpc/mpc85xx: move debug tlb entry after TLB is in known state
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
2012-11-26 15:41:20 -06:00
Ilya Yanok
c60795f41d usb: use linux/usb/ch9.h instead of usbdescriptors.h
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.

As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.

Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.

This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Kim Phillips
a2873bde4c powerpc/mpc83xx: sparse fixes
fdt.c:91:78: warning: Using plain integer as NULL pointer
fdt.c:103:78: warning: Using plain integer as NULL pointer
speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static?
speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static?
mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:37 -07:00
Kim Phillips
e56143e54f powerpc/mpc85xx: sparse fixes
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
2ed2e9121f arch/powerpc/cpu/mpc8xxx/: sparse fixes
ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static?
cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask'
cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores'
cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static?
cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static?
fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static?

and:

lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static?

making it static produces the following compiler warning:

lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function]

so we protect it with the preprocessor.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
20051f2ab2 arch/powerpc/lib/board.c, *traps.c: sparse fixes
traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static?
traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static?
board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static?
board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static?
board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static?
board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static?
board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static?
board.c:405:53: warning: Using plain integer as NULL pointer

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
fe44f452db arch/powerpc/lib/extable.c: sparse fix
extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static?

making it static can produce a new build warning on some boards:

extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable]

but ex_tab_message doesn't do much even when used, so just remove it.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
cdfdb8d7f3 arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefined
a fixup __iomem definition in arch code appears to be placed there as a cover
up from a code import from linux when u-boot didn't yet have a compiler.h,
introduced by commit 812711ce6b "Implement
__raw_{read,write}[bwl] on all architectures".

git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h
fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
eef1cf2d5c include/linux/byteorder: import latest endian definitions from linux
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
2012-11-04 11:00:34 -07:00
Wolfgang Denk
1b0757eced PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
2012-10-28 20:17:25 +01:00
Gerlando Falauto
a88731a6c2 mpc83xx: add support for mpc8309
This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:26 -05:00
Gerlando Falauto
8afad91f15 cleanup: introduce CONFIG_MPC830x
Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Gerlando Falauto
4b5282de99 cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Tom Rini
c7656bab41 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-10-22 16:54:38 -07:00
Andy Fleming
23028d69e9 85xx: Protect timeout_save variable with ifdefs
The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 17:28:18 -05:00
Liu Gang
19e4a00965 powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
990e1a8ce1 poweprc/85xx: add QMan frequency info and fdt fixup.
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
b0e8115741 mpc85xx/portals: Add qman and bman ip_cfg field into portal info
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
York Sun
98ffa19053 powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:33 -05:00
York Sun
ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
York Sun
3f0997b325 powerpc/mpc85xx: Remove R6 from spin table
R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
82968a7ab5 powerpc/mpc8xxx: Fix DDR SPD failed message
Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
89b7809568 powerpc/mpc8xxx: Add auto select bank interleaving mode
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:30 -05:00
York Sun
a1d558a20f powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:29 -05:00
York Sun
eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:28 -05:00
York Sun
f31cfd1925 powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:27 -05:00
York Sun
123922b1e5 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
York Sun
57495e4e5e powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
Roy Zang
111fd19e3b fm/mEMAC: add mEMAC frame work
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:25 -05:00
York Sun
d2404141f9 powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:24 -05:00
York Sun
9e75875849 powerpc/mpc85xx: Add T4240 SoC
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:23 -05:00
Andy Fleming
f311838ded powerpc/mpc85xx: Add T4 device definitions
The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:22 -05:00
York Sun
379c5145ef powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:20 -05:00
York Sun
d1001e3f0c powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
	The Common Public Radio Interface (CPRI) is publicly available
	specification that standardizes the protocol interface between the
	radio equipment control (REC) and the radio equipment (RE) in wireless
	basestations. This allows interoperability of equipment from different
	vendors,and preserves the software investment made by wireless service
	providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:19 -05:00
York Sun
fd3cebd020 powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
92230d49da powerpc/e6500: Move QCSP registers for QMan v3
The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
f8f85b049c powerpc/mpc85xx: expand SERDES reference clock select bit
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:17 -05:00
York Sun
9a653a9810 powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:16 -05:00
York Sun
2f1712b275 powerpc/mpc85xx: check number of cores
Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
f77329cfcf powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
69c7826759 powerpc/mpc85xx: Introduce new macros to add and delete TLB entries
These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
Kumar Gala
800c73c410 powerpc/85xx: Add determining and report IFC frequency
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
York Sun
553ae6f8f2 powerpc/DPAA: Fix compiling error
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Timur Tabi
4905443f1c powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
    Up to 2.4 GHz with 64-bit ISA support
    Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
    2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
        support Up to 1600MT/s
    Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
    Packet parsing, classification, and distribution (FMAN)
    Queue management for scheduling, packet sequencing and
    congestion management (QMAN)
    Hardware buffer management for buffer allocation and
    de-allocation (BMAN)
    Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
    20 lanes at up to 5 Gbps
    Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
    Two 10 Gbps Ethernet MACs
    Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
    Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
    Two serial ATA (SATA 2.0) controllers
    Two high-speed USB 2.0 controllers with integrated PHY
    Enhanced secure digital host controller (SD/MMC/eMMC)
    Enhanced serial peripheral interface (eSPI)
    Two I2C controllers
    Four UARTs
    Integrated flash controller supporting NAND and NOR flash
DMA
    Dual four channel
Support for hardware virtualization and partitioning enforcement
    Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
    Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
71cfcef649 powerpc/p5040ds: add per pci endpoint liodn offset list
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
    pci0: 193 256 259 262 265 268 271 274 277
    pci1: 194 257 260 263 266 269 272 275 278
    pci2: 195 258 261 264 267 270 273 276 279

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Timur Tabi
fd946040f1 powerpc/85xx: define SRIO LIODN functions only if SRIO is defined
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
e389a377ee powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself.  Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Timur Tabi
0c7e65f3d6 powerpc/mpc85xx: fix Unicode characters in release.S
Commit 709389b6 unintentionally used the Unicode version of the
apostrophy.  Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Liu Gang
d59c557049 powerpc/srio: Workaround for srio erratrm a004034
Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1.	One or more lanes fails to achieve lane synchronization.
	Depending on which lanes fail, this may result in downtraining
	from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2.	The link may fail to achieve lane alignment as a 4x, even
	though all 4 lanes achieve lane synchronization, and downtrain
	to a 1x. An SRIO port configured as a 1x port may fail to complete
	port initialization (PnESCSR[PU] never deasserts) because of
	scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
ramneek mehresh
9c889ece32 powerpc/mpc8xxx: Fix USB device-tree fixup
Fix usb device-tree fixup:
	- wrong modification of dr_mode and phy_type when
	  "usb1" is not mentioned inside hwconfig string;
	   now allows hwconfig strings like:
		"usb2:dr_mode=host,phy_type=ulpi"
	- add warning message for using usb_dr_mode
	  and usb_phy_type env variables (if either is used)

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Marek Vasut
8b493a5236 common: Discard the __u_boot_cmd section
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Marek Vasut
556751427b common: Add .u_boot_list into all linker files
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Zang Roy-R61911
4e0be34a85 P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Mark Marshall
320d53da60 powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.
We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:27 -05:00
Chris Packham
168e5bc409 mpc85xx: make gpio_direction_output respect value
Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:03:16 -05:00
Simon Glass
a7e5ee9ebb powerpc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Pavel Herrmann
8d1165e11a split mpc8xx hooks from cmd_ide.c
move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created
ide_init_postreset() (invoked after calling ide_reset after ide_preinit),
some cleanup to make checkpatch happy, enable IDE init hooks in configs of
affected boards.
confusingly, these hooks are used by more than just mpc8xx-based boards, and
therefore are placed in arch/ppc/lib/

note: checkpatch still emits warnings about using volatile

Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
2012-10-17 07:59:08 -07:00
Marek Vasut
ec3fd68952 serial: Use default_serial_puts() in drivers
Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication quite a bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
2012-10-17 07:55:50 -07:00
Stefan Roese
bfa5b71408 mpc82xx: Remove BMW board port
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: James F. Dougherty <jfd@broadcom.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-17 07:55:50 -07:00
Lucas Stach
c7e3b2b586 usb: lowlevel interface change to support multiple controllers
Carry an index in the lowlevel usb functions to make specify the
respective usb controller.

Also pass through an controller struct from lowlevel_init to the
creation of the root usb device of this controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15 11:54:00 -07:00
Stefan Roese
a821d08dca ppc4xx: Remove AP1000 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
dee9c534db ppc4xx: Remove ML2 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter De Schrijver <p2@mind.be>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
99bcad1809 ppc4xx: Remove IOP480 support
Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
036036d79c serial: Remove CONFIG_SERIAL_MULTI from remaining sources
Remove the parts depending either on disabled CONFIG_SERIAL_MULTI
or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI
is now enabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
a382725060 serial: Remove CONFIG_SERIAL_MULTI from serial drivers
Remove the support for not-CONFIG_SERIAL_MULTI part from serial
port drivers and some board files. Since CONFIG_SERIAL_MULTI is
now enabled by default, that part is a dead code. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:58 -07:00
Marek Vasut
fcc2074d57 serial: powerpc: Implement CONFIG_SERIAL_MULTI into iop480 serial driver
Implement support for CONFIG_SERIAL_MULTI into iop480 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the iop480 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
7a31154627 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc85xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc85xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc85xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
d68f4da2fa serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8260 serial drivers
Implement support for CONFIG_SERIAL_MULTI into both SCC and SMC mpc8260
serial drivers. These drivers were so far only usable directly, but this
patch also adds support for the multi method. This allows using more than
one serial driver alongside the mpc8260 drivers. Also, add a weak
implementation of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
2063a54e14 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8220 serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc8220 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc8220 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
b57c652802 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc5xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc5xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc5xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
918327c8f0 serial: mpc512x: Move serial registration from serial_initialize()
Move the registration of serialN_device ports from default
serial_initialize() into driver specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The newly implemented mpc512x_serial_initialize() function, which is
implemented inside of the mpc512x serial driver allows encapsulation
of serialN_device within the mpc512x serial driver itself.

Also, remove the exports of serialN_device from include/serial.h
as they are no longer needed. This is simply because the implementation of
default_serial_console() is wrapped into the mpx512x serial driver and
the default console is picked by CONFIG_SERIAL<N> macro in config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:50 -07:00
Marek Vasut
f0eb1f61b0 serial: mpc8xx: Move serial registration from serial_initialize()
Move the registration of serial_smc and serial_scc ports from
default serial_initialize() into CPU specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The exports of both serial_scc_device and serial_smc_device can
not yet be removed as they are still used in default_serial_console()
calls.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-15 11:53:49 -07:00
Marek Vasut
90bad891e1 serial: Properly spell out the structure member names of serial_driver
Properly spell out the whole structure member names when an initialized
varible is instantiated from the struct serial_driver. In case the
structure definition for struct serial_driver undergoes reordering,
there will be no impact on variables defined based on this structure.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: C Nauman <cnauman@diagraph.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
2012-10-15 11:53:48 -07:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Anatolij Gustschin
e5ab702a6c powerpc: re-add bi_ip_addr to bd_t struct
Since commit 50a47d0523
(net: punt bd->bi_ip_addr) booting old 2.4.x ppc kernels
is broken due to changed offsets of the fields in struct bd_t.
Offsets of the fields after removed bi_ip_addr are wrong,
causing wrong bus clocks and console baudrate configurations
and various other issues. Re-add the bi_ip_addr field to preserve
backward compatibility with older ppc kernels. Setting bi_ip_addr
in board.c is not really needed, grepping in the 2.4 linux tree
shows that bi_ip_addr is not accessed there. Adding bi_ip_addr
to struct bd_t for other arches isn't needed it seems. bd_t is
not used by other arches in the 2.4 linux tree.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-09-02 22:55:59 +02:00
Joakim Tjernlund
83f83d1935 ppc: Create a stack frame for wait_ticks()
wait_ticks() calls get_ticks() without building a back chain which
makes gdb unhappy when doing back trace. This can also cause
improper memory accesses.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2012-09-02 17:10:21 +02:00
Stefan Roese
0044c42e94 Consolidate bootcount code into drivers/bootcount
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-09-01 14:26:02 +02:00
Anatolij Gustschin
d7903ae159 mpc5xxx: add GPIO port configuration
Add posibility for board specifig GPIO configurations using
various CONFIG_SYS_ macros.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-09-01 14:19:52 +02:00
Andy Fleming
98ae9ac434 Revert "powerpc: Fix declaration type for I/O functions"
This reverts commit 20959471b5.
2012-08-23 12:16:57 -05:00
Scott Wood
3ea21536d7 powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:57 -05:00
York Sun
7ac3cc20e0 powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
1d083ff2c4 powerpc/mpc8xxx DDR: Fix interactive DDR debugging
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
62f739fe46 powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
7e4db27ffd powerpc/mpc8xxx DDR: Fix CAS latency calculation
Empty slot should be skipped when calculating CAS latency.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
45064adcae powerpc/mpc8xxx: Fix bug for extended DDR timing
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
a4c66509f1 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
fcea30688f powerpc/mpc8xxx: Add support for cas latency 12 and above
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
73b5396b25 powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
744713a6a3 powerpc/mpc85xx: Skip zero values for DDR debug registers
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.

Also add debug messages for workarounds and debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
709389b654 powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
ffdf8890ae Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
50d96e95b4 Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
5b6b85ae63 Add e6500 processor detection
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
123bd96d53 powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
1ca8690d27 powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
3854173aa8 powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC or corenet SoC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
e4879afba3 powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
33eee330cc powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
3e978f5dc8 powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
99abf7ded3 powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
York Sun
be7bebeac2 powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
b5f7c8732a powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Liu Gang
ff65f12699 powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
York Sun
57125f222e powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.

Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:

fsl_cpu_a011:disable

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:13 -05:00
Joakim Tjernlund
7de8a7169e powerpc: Stack Pointer not properly aligned
The code first aligns the SP to 16 then subtract 8, making it
8 bytes aligned. Furthermore the initial stack frame not
quite correct either.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Joakim Tjernlund
89f4289958 mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Prabhakar Kushwaha
20959471b5 powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.

Chage protoype declaration as static.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:24:31 +02:00
Prabhakar Kushwaha
a16a5cccfb powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32

Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:23:14 +02:00
Mike Frysinger
47fde91f0c global_data: unify global flag defines
All the global flag defines are the same across all arches.  So unify them
in one place, and add a simple way for arches to extend for their needs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-09 21:46:32 +02:00
Timur Tabi
5c5befda58 powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
York Sun
718f2b3187 powerpc/mpc85xx: Ignore E bit for BSC9130/1
Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
Timur Tabi
7ee411071f powerpc/85xx: improve definition of BR_PHYS_ADDR macro
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:15 -05:00
Shaohui Xie
98de369b1c powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
York Sun
535a159ab6 powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
Wolfgang Denk
b98b611502 Merge branch 'next' of git://git.denx.de/u-boot
* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-30 20:39:52 +02:00
Marek Vasut
15ae8a31ca MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Subject slightly changed.
Signed-off-by: Wolfgang Denk <wd@denx.de>

Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and
TQM860LDB0A3-T50.202 (MPC860T at 50MHz).

Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-07-30 09:58:02 +02:00
Stefano Babic
569fadcd74 MPC83xx, MPC85xx: compile stub cache function
An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture.  However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Andy Fleming <afleming@gmail.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Marek Vasut <marex@denx.de>
CC: Wolfgang Denk <wd@denx.de>

Added MPC83xx version.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-21 23:37:48 +02:00
Wolfgang Denk
8246ff864d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:16:14 +02:00
York Sun
feae34243f powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
5e23ab0a31 powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
1e9ea85f7d powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
7b6e80538b lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.

The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-06 17:30:32 -05:00
Prabhakar Kushwaha
e87dc41fc1 powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
ad75d44239 powerpc/mpc85xx:Add debugger support for e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Please refer doc/README.mpc85xx for more information

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
d16a37b864 powerpc/85xx:Fix NAND code base to support debugger
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
689f00fc7e powerpc/85xx:Make debug exception vector accessible
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.

1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.

2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
5344f7a258 powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
19a8dbdc45 powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:03:25 -05:00
Timur Tabi
a6cdaa0cd1 powerpc/mpc83xx: fix copyright string in serdes.c
The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-07-03 11:07:21 -05:00
Marek Vasut
25315683fd MPC8xxx: Define cache ops for USB
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:

$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1

--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
2012-06-07 23:29:19 +02:00
Joe Hershberger
cb487f5664 net: cosmetic: Un-typedef Ethernet_t
Separate the Ethernet header from the 802 header.
Base the size constants on the structs.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 17:46:14 -05:00
Joe Hershberger
1735188329 net: Encapsulate CDP packet identification
Checking for CDP packets should be encapsulated, not copied code.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:23 -05:00
Joe Hershberger
7a10692a9c arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warning
Fix this:
ether_scc.c: In function 'mpc82xx_scc_enet_initialize':
ether_scc.c:377:14: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 23:17:52 -05:00
Joe Hershberger
412411cb2e arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:453:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
888fc6158e arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:390:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
3573c327a6 arch/powerpc/cpu/mpc8220/fec.c: Fix compile warning
Fix this:
fec.c: In function 'mpc8220_fec_recv':
fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
fec.c: In function 'mpc8220_fec_initialize':
fec.c:839:12: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Wolfgang Denk
1b10d0717a MPC8xx: fix "Remove volatile from net API" aftermath
Commit db288a9 "net: Remove volatile from net API" caused a number of
build warnings:
fec.c: In function 'fec_initialize':
fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default]
fec.c: In function 'fec_recv':
fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default]
/home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
scc.c: In function 'scc_initialize':
scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default]

Fix these.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 10:18:14 -05:00
Wolfgang Denk
8fa3d2b816 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
  NAND: Remove ONFI detection message to from bootup log
  driver/mtd:IFC: Fix possible memory leak
  driver/mtd: IFC NAND: Add support of ONFI NAND flash
  mtd, nand: move some printfs to debug output.
  nand_util: correct YAFFS image write function
  powerpc/85xx: fix NAND boot linker scripts for -fpic
  nand: extend .raw accesses to work on multiple pages
2012-05-20 22:47:40 +02:00
Scott Wood
d2a97daf62 powerpc/85xx: fix NAND boot linker scripts for -fpic
GOT is now handled the way the main u-boot.lds does it.  Without this,
the boot hangs when built with newer GCC (since 4.6).  Older toolchains
hid the issue by converting -fpic to -fPIC.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-05-18 17:34:39 -05:00
Mike Frysinger
de30122bb5 net: move bootfile init into eth_initialize
All arches init this the same way, so move the logic into the core
net code to avoid duplicating it everywhere else.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:33 -05:00
Mike Frysinger
50a47d0523 net: punt bd->bi_ip_addr
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr").  After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:05 -05:00
Timur Tabi
822ad60f1c powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-04-24 23:58:34 -05:00
Liu Gang
5056c8e068 powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.

Master needs to:
	1. Set outbound SRIO windows in order to configure slave's registers
	   for the core's releasing.
	2. Check the SRIO port status when release slave core, if no errors,
	   will implement the process of the slave core's releasing.
Slave needs to:
	1. Set all the cores in holdoff by RCW.
	2. Be powered on before master's boot.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
0a85a9e705 powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by SRIO
	  interface, so it can not modify the ENV parameters stored in
	  master's NOR flash using "saveenv" or other commands.

Master needs to:
	1. Put the slave's ENV into it's own memory space.
	2. Set an inbound SRIO window covered slave's ENV stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
5ffa88eca7 powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:32 -05:00
Liu Gang
7d67ed58a2 powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2012-04-24 23:58:32 -05:00
Prabhakar Kushwaha
5113ee706d powerpc/85xx:Fix lds for nand boot debug info
Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.

The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.

So Fix u-boot-nand.lds to generate these debug information.

Signed-off-by: Anmol Paralkar <b07584@freescale.com>
Signed-off-by: John Russo <John.Russo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:31 -05:00
Prabhakar Kushwaha
119a55f9cf powerpc/85xx:Avoid vector table compilation for nand_spl
NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
64829baf04 powerpc/85xx:Fix IVORs addr after vector table relocation
After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.

As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00  hard-coded values.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
a4107f8617 powerpc/85xx:Avoid hardcoded vector address for IVORs
For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.

in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Mike Frysinger
5b84dd67cf usb: replace wait_ms() with mdelay()
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func.  This also fixes the build errors:

ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-03-19 00:08:16 +01:00
Simon Glass
770605e4f9 bootstage: Replace show_boot_progress/error() with bootstage_...()
These calls should not be made directly any more, since bootstage
will call the show_boot_...() functions as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:41:39 +01:00
Simon Glass
8ade950638 bootstage: Convert progress numbers 20-41 to enums
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:16:22 +01:00
Simon Glass
5ddb118da4 bootstage: Use show_boot_error() for -ve progress numbers
Rather than the caller negating our progress numbers to indicate an
error has occurred, which seems hacky, add a function to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:56:00 +01:00
Simon Glass
578ac1e9ba bootstage: Make use of BOOTSTAGE_ID_RUN_OS in show_boot_progress()
This changes the number 15 as used in boot_stage_progress() to use the
new name provided for it. This is a separate patch because it touches
so many files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:45:57 +01:00
Simon Glass
d01b17611b ppc: Change memsz variable to signed char
This seems to be unsigned char for no good reason. Tidy this up and
remove the casts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-03 16:56:51 +01:00
ramneek mehresh
79f49120ba powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
ramneek mehresh
5a52977f28 powerpc/8xxx: Cleanup USB device-tree fixup
Some code cleanup done for USB device-tree fixup:
	- handling error value returned from fdt_fixup_usb_mode_phy_type()
	- using ARRAY_SIZE macro
	- using snprintf instead of sprintf

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
Wolfgang Denk
670c24f6f3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks
2012-01-13 20:38:49 +01:00
Paul Gortmaker
3dc23c7c30 fsl_lbc: add printout of LCRR and LBCR to local bus regs
It can be handy to have these in the output when trying to
debug odd behaviour.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-13 12:56:06 -06:00
Joe Hershberger
4b56579388 mpc83xx: Add a GPIO driver for the MPC83XX family
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Jerry Huang
509adc8b77 powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
In the current u-boot code, the value of these fields are the reserved
value (0b100), through the signal integrity measurement on freescale's
board with these reserved setting, the signal eye is out of the recommended
spec for non-transition amplitude at 500mV nominal.
According to the errata for MPC8379E, we should make a change to the
recommended setting from essentially nothing at this time to 0b001 for SATA.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-12-12 18:33:39 -06:00
Kumar Gala
3b2001105f powerpc/bootm: Flush ramdisk and device tree image when booting on MP
We already flush the kernel image after we've loaded it to ensure
visiblity to the other cores.  We need to do the same thing for the
ramdisk and device tree images.  In AMP boot scenarios we might not be
HW cache coherent with the secondary core that we are loading and
setting the ramdisk and device tree up for.  Thus we need to ensure
we've flushed the regions of memory utilized by ramdisk and device tree
so the loadding and any modifications (from decompression or fdt updates)
are made visible to the secondary cores.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-12 08:17:52 +01:00
Kyle Moffett
01baa05643 powerpc: Minimal private libgcc to build on Debian
Standard Debian powerpc and powerpcspe systems only include hard-float
libgcc in their native compilers, which causes scary build warnings when
building U-Boot.

Debian and other PowerPC-supporting distributions used to provide libgcc
and other libraries in a "nof" (soft-float) form in the "multilib"
packages.  As they were completely unused by the distribution and
therefore tended to be very buggy it was decided to save some time on
the part of the maintainers and build-servers by removing them.

Admittedly, right now the linker warnings do not indicate any problems,
as the included routines do not use any floating point at all.

The concern is that if floating-point code were ever added it might
cause hard-float code to be unexpectedly included in U-Boot without
generating a hard error.  This would cause unexplained crashes or
indeterminate results at runtime.

The easiest way to resolve this is to borrow the routines that U-Boot
needs from the Linux kernel, which has the same issue.

Specifically, the routines are: _ashldi3(), _ashrdi3(), and _lshrdi3().
They were borrowed from arch/powerpc/kernel/misc_32.S as of v2.6.38-rc5,
commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, and are GPLv2+.

The Makefile framework was copied from the U-Boot ARM port.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Stefan Roese <sr@denx.de>
2011-12-07 23:04:32 +01:00
Wolfgang Denk
1086c5d6f8 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/83xx: fix sdram initialization for keymile boards
  powerpc/mpc83xx: cleanup makefile for mpc83xx
2011-12-07 23:01:26 +01:00
Stefan Roese
ce2acd371c ppc4xx: Remove usbdev.c
As this "driver" doesn't seem to be really used, let's remove
it completely.

Signed-off-by: Stefan Roese <sr@denx.de>
2011-12-07 20:00:40 +01:00
Wolfgang Denk
ad37ef1a85 arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning
Fix:
cpu.c: In function 'checkcpu':
cpu.c:51:7: warning: variable 'ver' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-02 00:16:46 +01:00
Ira W. Snyder
9839709ea3 mpc85xx: support for Freescale COM Express P2020
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 09:07:51 -06:00
Kumar Gala
411e150375 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
Fix:

interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
c18de0d7ae mpc85xx: support board-specific reset function
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
cc15df57b1 powerpc/85xx: verify the localbus device tree address before booting the OS
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR.  If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.

Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong.  This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
2f3a71f235 mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
f2717b47ea powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
fbc20aab11 powerpc/85xx: always implement the work-around for Erratum SATA_A001
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default.  So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
3e0529f742 powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
P1010 and P1014.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
York Sun
4108508a96 powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Jia Hongtao
33c875366e powerpc/85xx: fixup flexcan device tree clock-frequency
Make the fixup matchable with dts and kernel.  Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency".  We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.

We now keep the old interfaces to make previous kernel work. They should
be removed in the future.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Kumar Gala
43f082bb7f powerpc/85xx: Add workaround for erratum CPU-A003999
Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Kim Phillips
9da752e97f mpc83xx: spd_sdram - fix gcc 4.6 compiler warning
Configuring for sbc8349 board...
spd_sdram.c: In function 'spd_sdram':
spd_sdram.c:152:41: warning: variable 'trfc_high' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-16 21:40:26 +01:00
Stefan Roese
bddf144cb6 iop480_uart.c: Fix GCC 4.6 build warnings
Fix:
iop480_uart.c: In function 'serial_init':
iop480_uart.c:137:16: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:17:36 +01:00
Stefan Roese
4a1272662a 40x_spd_sdram.c: Fix GCC 4.6 build warnings
Fix:
40x_spd_sdram.c: In function 'spd_sdram':
40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:59 +01:00
Stefan Roese
deeecb7c7e 44x_spd_ddr2.c: Fix GCC 4.6 build warnings
44x_spd_ddr2.c: In function 'initdram':
44x_spd_ddr2.c:450:17: warning: variable 'dimm_spd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'program_copt1':
44x_spd_ddr2.c:1003:16: warning: variable 'ddrtype' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'DQS_calibration_process':
44x_spd_ddr2.c:2498:7: warning: variable 'window_found' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2497:16: warning: variable 'end_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2496:16: warning: variable 'end_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2495:16: warning: variable 'begin_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2494:16: warning: variable 'begin_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2493:7: warning: variable 'min_end' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:51 +01:00
Stefan Roese
6cd71d0f17 44x_spd_ddr.c: Fix GCC 4.6 build warnings
Fix:
44x_spd_ddr.c: In function 'program_cfg0':
44x_spd_ddr.c:384:16: warning: variable 'dimm_64bit' set but not used [-Wunused-but-set-variable]
44x_spd_ddr.c:383:16: warning: variable 'dimm_32bit' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:36 +01:00
Stefan Roese
a6370da13e cmd_ecctest.c: Fix GCC 4.6 build warnings
Fix:
cmd_ecctest.c: In function 'inject_ecc_error':
cmd_ecctest.c:116:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]
cmd_ecctest.c: In function 'rewrite_ecc_parity':
cmd_ecctest.c:154:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:20 +01:00
Stefan Roese
8f6db4b7ab 4xx_ibm_ddr2_autocalib.c: Fix GCC 4.6 build warnings
Fix:
4xx_ibm_ddr2_autocalib.c: In function 'get_membase':
4xx_ibm_ddr2_autocalib.c:157:8: warning: variable 'bxcf' set but not used [-Wunused-but-set-variable]
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:722:8: warning: variable 'rffd' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:07 +01:00
Stefan Roese
fe91a65707 4xx_pcie.c: Fix GCC 4.6 build warnings
Fix:
4xx_pcie.c: In function 'pcie_read_config':
4xx_pcie.c:230:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'pcie_write_config':
4xx_pcie.c:290:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'ppc4xx_setup_pcie_rootpoint':
4xx_pcie.c:1066:17: warning: variable 'rmbase' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:14:39 +01:00
Stefan Roese
af0af524ed usb_ohci.c: Fix GCC 4.6 build warnings
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:756:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:13:26 +01:00
Anatolij Gustschin
d14a94bf68 arch/powerpc/cpu/mpc512x/i2c.c: Fix GCC 4.6 warnings
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:81:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:12:48 +01:00
Anatolij Gustschin
c33b92ebcc arch/powerpc/cpu/mpc512x/pci.c: Fix GCC 4.6 warnings
Fix:
pci.c: In function 'pci_init_board':
pci.c:55:26: warning: variable 'pci_conf' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:12:29 +01:00
Wolfgang Denk
9dfa8da709 Merge branch 'master' of git://git.denx.de/u-boot-video
* 'master' of git://git.denx.de/u-boot-video:
  api: export LCD device to external apps
  font: split font data from video_font.h
  tools: logo: split bmp arrays from bmp_logo.h
  lcd: add clear and draw bitmap declaration
  VIDEO: mx3fb: GCC4.6 fix build warnings
  Powerpc/DIU: Fixed the 800x600 and 1024x768 resolution bug
2011-11-16 20:44:03 +01:00
Che-Liang Chiou
d3983ee853 font: split font data from video_font.h
While video_font.h is useful even without referencing the font data, it
is not possible to be included multiple times because it defines font
data array right in the header.

This patch splits the font data array into video_font_data.h and so now
video_font.h can be included multiple times.  This at least solves the
code duplication in board/mcc200/lcd.c.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-15 23:58:26 +01:00
York Sun
2d14e36a50 powerpc/mpc83xx: cleanup makefile for mpc83xx
Remove symbolic link generated by compiling. Fix makefile for out-of-tree
compiling error.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-11 16:40:51 -06:00
Kumar Gala
dea7f88726 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
Fix:

ctrl_regs.c: In function 'set_ddr_sdram_cfg_2':
ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable]
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds]
ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
c1ee16b8e0 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
Fix:

fsl_corenet_serdes.c: In function 'fsl_serdes_init':
fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable]
fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
667bc17e07 arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
Fix:

options.c: In function 'populate_memctl_options':
options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
e55d637a5f arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
Fix:

fsl_lbc.c: In function 'upmconfig':
fsl_lbc.c:110:9: warning: variable 'mdr' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Kumar Gala
3d6d9c3116 arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
Fix:

tlb.c: In function 'disable_tlb':
tlb.c:175:34: warning: variable '_mas7' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Kumar Gala
e4c9a35d21 arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
Fix:

cpu_init.c: In function 'cpu_init_r':
cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Poonam Aggrwal
cfee584eea fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
Wrong pointer was being used to copy code into L2SRAM.
Also removed the unreferenced variable l2srbar.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:37:25 -06:00
Kumar Gala
50cf3d17ce powerpc/85xx: Add support for Book-E MMU Arch v2.0
A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:51 -06:00
Ramneek Mehresh
4765fb7d73 powerpc/85xx: Fix warning for USB device-fixup
Fix USB device-fixup warning "node not found". This was occuring
because of static nature of start_offset variable

Static start_offset was storing offset of last node modified, and
was becoming issue if node fixup is carried multiple times,
resulting in "node not found" warning

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:02 -06:00
Timur Tabi
72243c0194 powerpc/85xx: resize the boot page TLB before relocating CCSR
On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code.  To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:09 -06:00
Timur Tabi
19e4384124 powerpc/85xx: verify the current address of CCSR before relocating it
Verify that CCSR is actually located where it is supposed to be before
we relocate it.  This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:06 -06:00
Timur Tabi
452ad61c3f powerpc/85xx: add some missing sync instructions in the CCSR relocation code
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:02 -06:00
Timur Tabi
c2efa0aa1e powerpc/85xx: fix some comments in the CCSR relocation code
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:59 -06:00
Timur Tabi
5c4a3d431e powerpc/85xx: fix definition of MAS register macros
Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.

Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter.  This hasn't caused any problems to date because the
parameter was always been 'tsize'.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:57 -06:00
chenhui zhao
aada81de70 powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.

Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:32 -06:00
Wolfgang Denk
5721385b18 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds
  powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
  mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code
  mpc83xx: Cleanup usage of LBC constants
  mpc83xx: Cleanup usage of DDR constants
  mpc83xx: Cleanup usage of BAT constants
  mpc83xx: cosmetic: vme8349.h checkpatch compliance
  mpc83xx: cosmetic: ve8313.h checkpatch compliance
  mpc83xx: cosmetic: sbc8349.h checkpatch compliance
  mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance
  mpc83xx: cosmetic: kmeter1.h checkpatch compliance
  mpc83xx: cosmetic: TQM834x.h checkpatch compliance
  mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance
  mpc83xx: cosmetic: MVBLM7.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance
  mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance
  mpc83xx: Fix ipic structure definition
  powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions
  cosmetic, powerpc, mpc83xx: checkpatch cleanup
  powerpc/83xx: move km 83xx specific i2c code to km83xx_i2c
  mpc83xx: fix global timer structure definition
2011-11-08 07:44:52 +01:00
Wolfgang Denk
69545df0e6 arch/powerpc/cpu/mpc8260/spi.c: Fix GCC 4.6 build warnings
Fix:
spi.c: In function 'spi_init_r':
spi.c:279:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]
spi.c: In function 'spi_xfer':
spi.c:361:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:47:44 +01:00
Wolfgang Denk
8a33201d0c arch/powerpc/lib/bat_rw.c: Fix GCC 4.6 build warning
Fix:
bat_rw.c: In function 'write_bat':
bat_rw.c:38:6: warning: variable 'batn' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Andy Fleming <afleming@gmail.com>
2011-11-07 22:16:55 +01:00
Wolfgang Denk
8b337be04e mpc8220/i2c.c: Fix GCC 4.6 build warning
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:109:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:52 +01:00
Wolfgang Denk
918e34674f mpc8260/i2c.c: replace PRINTD() by debug()
This also fixes some GCC 4.6 build warnings like:
i2c.c: In function 'i2c_init':
i2c.c:221:26: warning: variable 'txbd' set but not used
[-Wunused-but-set-variable]
i2c.c:221:19: warning: variable 'rxbd' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:46 +01:00
Wolfgang Denk
86ba925534 mpc8260/i2c.c: CodingStyle cleanup
Make (mostly) checkpatch clean (don't convert to use I/O accessors
yet, so there will be "Use of volatile is usually wrong" warnings
left.  Also accept some other harmless checkpatch warnings.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:43 +01:00
Wolfgang Denk
50f87ca556 mpc8220/fec.c: Fix GCC 4.6 build warning
Fix:
fec.c: In function 'mpc8220_fec_recv':
fec.c:733:8: warning: variable 'frame' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:16:39 +01:00
Wolfgang Denk
89a7b78c43 mpc8260/speed.c: Fix GCC 4.6 build warnings
Fix:
speed.c: In function 'get_clocks':
speed.c:113:30: warning: variable 'cpmdf' set but not used
[-Wunused-but-set-variable]
speed.c:113:23: warning: variable 'busdf' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:15:49 +01:00
Wolfgang Denk
4d4aebaa01 mpc8xx/spi.c: Fix GCC 4.6 build warnings
Fix:
spi.c: In function 'spi_init_f':
spi.c:144:21: warning: variable 'iop' set but not used
[-Wunused-but-set-variable]
spi.c:142:22: warning: variable 'cpi' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:14:32 +01:00
Wolfgang Denk
937943d3f0 mpc8xx/i2c.c: replace PRINTD() by debug()
This also fixes some GCC 4.6 build warnings like:
warning: variable 'txbd' set but not used [-Wunused-but-set-variable]
warning: variable 'rxbd' set but not used [-Wunused-but-set-variable]

Signed-off-by: WOlfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:14:10 +01:00
Wolfgang Denk
09e68ffadd mpc8xx/i2c.c: CodungStyle cleanup
Make (mostly) checkpatch-clean

We don't acctually change the code (like convert to use I/O
accessors), so there will be some remaining "Use of volatile"
warnings from checkpatch.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:14:06 +01:00
Wolfgang Denk
bae65019d7 mpc8xx/cpu.c: Fix GCC 4.6 build warnings
Fix:
cpu.c: In function 'check_CPU':
cpu.c:188:8: warning: variable 'mid' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:13:01 +01:00
Wolfgang Denk
90357f1493 mpc8xx/fec.c: Fix GCC 4.6 build warnings
Fix:
fec.c: In function 'fec_pin_init':
fec.c:381:18: warning: variable 'fecp' set but not used
[-Wunused-but-set-variable]
fec.c: In function 'fec8xx_miiphy_write':
fec.c:1013:8: warning: variable 'rdreg' set but not used
[-Wunused-but-set-variable]

Note: The code was slightly rearranged, but no functional changes
attempted, i. e. no conversion to use I/O accessors.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:11:42 +01:00
Wolfgang Denk
a442173048 arch/powerpc/cpu/mpc5xxx/usb_ohci.c: fix GCC 4.6 build warnings
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:751:8: warning: variable 'tdINFO' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:42 +01:00
Wolfgang Denk
1c2931d4ec arch/powerpc/lib/board.c: fix build warning
Fix:
board.c: In function 'board_init_r':
board.c:633:8: warning: unused variable 's' [-Wunused-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:35 +01:00
Wolfgang Denk
9b998b0c52 arch/powerpc/lib/board.c: make (mostly) checkpatch-clean
CodingStyle cleanup.

Accepted (in this cleanup) checkpatch messages:

- externs should be avoided
  (to be cleaned up later)
- no spaces at the start of a line
  (accepted in multi-line #if's)
- Macros with complex values
  (false reports)
- do not use assignment in if condition
  (accepted in one place, where avoiding it would have required an
  additional level of nesting, resulting in less readable code)

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:31 +01:00
Wolfgang Denk
9306749752 arch/powerpc/cpu/mpc5xxx/i2c.c: fix GC 4.6 build warnings
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:104:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:09:27 +01:00
Joe Hershberger
7d6a098219 mpc83xx: Cleanup usage of LBC constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:56 -05:00
Joe Hershberger
2fef402097 mpc83xx: Cleanup usage of DDR constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:55 -05:00
Joe Hershberger
4713db666c mpc83xx: Fix ipic structure definition
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

Added siprr_{b,c} and sepcr for completeness.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:52 -05:00
Kim Phillips
63063cc7ae mpc83xx: fix global timer structure definition
The byte address distance between GTCFR2 and GTMDR1 is 11, not 10.

Reported-by: Shawn Bai <programassem@hotmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:51 -05:00
Wolfgang Denk
cca4e4aec1 Reduce build times
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again.  On some architectures
(especially ARM) this results in a large number of calls to gcc.

This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.

Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
	-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
	-> grep execve /tmp/foo | wc -l

	Before: After:	Reduction:
==================================
P2020DS 20555	15205	-26%
qong	31692	14490	-54%

As a result, built times are significantly reduced, typically by
30...50%.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Tested-by: Sanjeev Premi <premi@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-03 20:44:58 +01:00
Wolfgang Denk
e5d5ed4b20 4xx_pci.c: add error checking, fix GCC 4.6 build warning
Fix:
4xx_pci.c: In function 'pci_init_board':
4xx_pci.c:855:6: warning: variable 'busno' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2011-11-03 20:40:38 +01:00
Wolfgang Denk
32bb34a768 4xx_uart.c: fix GCC 4.6 build warnings
Fix:
4xx_uart.c: In function 'get_serial_clock':
4xx_uart.c:204:6: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
2011-11-03 20:39:49 +01:00
Wolfgang Denk
a9f4fc3fe5 arch/powerpc/lib/board.c: fix build warning
Commit 1272592 "powerpc: Use getenv_ulong() in place of getenv(),
strtoul" instroduced a build warning for some PPC systems:

board.c: In function 'board_init_r':
board.c:626: warning: unused variable 's'

Fix it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2011-11-03 20:37:27 +01:00
Marek Vasut
7f2229b5c5 GCC4.6: Squash warnings in mpc86xx/interrupts.c
interrupts.c: In function 'interrupt_init_cpu':
interrupts.c:62: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
interrupts.c:69: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:72: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:75: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:79: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:83: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:01 +02:00
Marek Vasut
cd84b1fabf GCC4.6: Squash warnings in ddr[123]_dimm_params.c
ddr1_dimm_params.c: In function 'compute_ranksize':
ddr1_dimm_params.c:44: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'

ddr2_dimm_params.c: In function 'compute_ranksize':
ddr2_dimm_params.c:43: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'

ddr3_dimm_params.c: In function 'compute_ranksize':
ddr3_dimm_params.c:74: warning: format '%16lx' expects type 'long unsigned int',
but argument 2 has type 'long long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 23:54:00 +02:00