Help the boot loader and perform a bus clear. U-Boot will try to
read the MAC from the EEPROM and barebox has the complex boot
state stored in it.
In the past we have seen U-boot failing to read from the EEPROM
and let's have one place to initialize it.
Starting from revision F we can toggle a GPIO to control nWP of
the NAND chip. This means that during power-on or other mode of
operation no changes can be done to the flash.
Remove the nWP before we try to write to the flash in the UART
mode. Leave it enabled for further operations.
We want to know how many copies of UBL/APP have been written.
It is necessary to know that we have written multiple copies
to avoid two bitflips rendering the device unusable.
dvnixload debug1: Reading: [INFO: UBLs written: 0x5]
dvnixload debug1: Reading: [INFO: APPs written: 0x4]
I have not looked at the change in binary size but it seems to
be fine and still works on the device.
nandboot.c:61:3: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
magicNum = *((uint32_t *) nand_header);
nand.c:800:5: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
uart_send_hexnum(*((uint32_t *) &read_buf[k]), 8);
Do not block the boot process for five seconds or longer. When
adding the configurable timeout the other timeout code got broken.
Remove it and instead supply uart_recv_bytes with the timeout per
The NAND might have more bit flips than can be recovered. The way
to deal with it is to write multiple copies on multiple pages. The
probability of all pages failing depends on the specific NAND flash
used and was not calculated so far. The RBL is capable of trying to
load several copies and we should be more safe now.
This requires a new partioning inside the U-Boot or other bootloader.
I disabled the initialization of the vector interrupt tables in
davinci.c and then I can use u-boot commands like these
load and start ubl
dhcp; set serverip 192.168.0.88; tftp ubl_sysmobts_v2.elf; bootelf
manipulate bits. Flip a 1 to a 0:
nand read.raw 0x85000000 0x00080000 1
nand write.raw 0x85000000 0x00080000 1
Before doing the NAND boot the 'I_ME' message will be sent and the
ubl will wait up to a second for a response. This interruption mode
can be disabled, e.g. when deploying the system in a publically
accessible system. Right now the possibility of easy recovery is