Got this when compiling sandbox on a 64-bit system:
drivers/mtd/ubi/cdev.c: In function ‘ubi_volume_cdev_read’:
drivers/mtd/ubi/cdev.c:26:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t’ [-Wformat]
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch is from linux 3.7-rc1 and adapt to Barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we do not need to probe them and they have no driver or bus attached
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On i.MX we enable all necessary clocks during startup of the clock
controller driver, so we do not need the register hacking in the drivers
anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
toread is unitialized. We have to use count instead.
| commit 992c291e95
| Author: Sascha Hauer <s.hauer@pengutronix.de>
| Date: Sat Sep 15 16:54:47 2012 +0200
|
| mtd mtdraw: Fix partial page read
|
| When reading parts of a page we have to limit the maximum bytes copied
| to the remaining bytes of a page.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When reading parts of a page we have to limit the maximum bytes copied
to the remaining bytes of a page.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Some of the newer MLC devices have a 6-byte ID sequence in which
several field definitions differ from older chips in a manner that is
not backward compatible.
This method is already used in the Linux Kernel.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For the size_t type the format specifier %zu or %zx must be used.
See Documentation/printk-formats.txt in the kernel for details.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The mtdoob and mtdraw device don't clean up correctly.
Added a private data element to hold allocated memory.
Fix remove of mtdoob and mtdraw device.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With pbl support enabled most boards need a pbl-y for their lowlevel
stuff.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The existing nand_boot functions all do the same, so move it to
a common place. To be flexible enough for future boards the real
image size is used instead of hardcoded 256k.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Juergen Beisert <jbe@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This introduces a new NAND_BUSWIDTH_AUTO flag which can be used
to automatically detect the nand buswidth. The id is always read
in 8bit mode. An additional callback is needed to switch the nand
controller into 16bit mode.
This currently depends on a safe read_byte (always) and read_buf
(for onfi-only flashes) callback. It has been tested on OMAP, but
is not something that generally works. For this reason the existence
of the set_buswidth callback is used to determine whether we are
able to do autodetection or not.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use the prefetch engine to improve NAND performance. The howto
is derived from the Kernel. Unlike the kernel we do not make
the access mode configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- dev_ready is supposed to return whether the device is ready or
not, not to poll until the device is ready.
- dev_ready should return true for ready and false for not ready
- waitpin polarity is not needed (at least the kernel does not have it)
- wait_mon_mask must be 32bit.
The code was unused since no board specified a wait pin, so no breakage
included. This also removes the now unused timeout variable from
platformdata.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The 'off_t cur_ofs' variable was missed during the 64 bit conversion.
For the MEMGETBADBLOCK ioctl, a pointer to a loff_t is needed.
Also adjust the debug format strings.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since this commit we interpret the argument to the bad block ioctls
as a pointer to a 64bit number:
|commit e71c343668
|Author: Sascha Hauer <s.hauer@pengutronix.de>
|Date: Fri Oct 14 11:57:55 2011 +0200
|
| mtd: fix arguments to bad block ioctls
|
| In the Kernel the mtd ioctls expect a pointer to the offset, whereas
| barebox interprets the pointer itself as an offset. Since we want
| to add 64bit support for file sizes a pointer may not be sufficient,
| so align with the kernel and convert it to a pointer to the offset.
|
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This missed some places, fix them aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- add CMD_PARAM and read_param to get the ONFI structure
- fix OOB size for flash with 224 OOB on i.MX51/3
- add the same ecc layout as the one in the kernel for
4k page flashs
Tested on an i.MX53.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
the code is taken from linux & u-boot implementations
Validated on an i.MX53 which gives the following log :
ONFI flash detected ... ONFI param page 0 valid
NAND device: Manufacturer ID: 0x2c, Chip ID: 0x38 (Micron MT29F8G08ABABAWP), page size: 4096, OOB size: 224
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In the Kernel the mtd ioctls expect a pointer to the offset, whereas
barebox interprets the pointer itself as an offset. Since we want
to add 64bit support for file sizes a pointer may not be sufficient,
so align with the kernel and convert it to a pointer to the offset.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Based on the U-Boot version. Changed to kernel style register layout, added
MX23 support (WIP!), made MMU aware and adapted to barebox.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Backport 2 fixes back from Linux kernel (title verbatim from
Linux kernel log) :
- docg3 fix in-middle of blocks reads
- docg3 reduce read alignment burden
These 2 enable partial reads from the MTD (ie. read only the
111 first bytes), which enable linux kernel booting or UBIFS
from barebox.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When programming or erasing a page, don't wait
systematically for 3s, but finish the operation as soon as
the hardware has finished, and timeout if 3 seconds have
passed.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When unaligned writes are used, typically doing a cp file /dev/mtdraw0.foo,
the alignement correction code was incorrectly handling such cases, and
didn't return the expected number of written bytes.
This was tested on a 528 block size.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
commit 30de24d79fc6e659d0070f6e863ae0e53567ba0e param: add config to disable it
removes param support for xloader configurations. Set param eccmode calls
omap_gpmc_eccmode and so nand_scan_tail. So nand fails without param support
Call omap_gpmc_eccmode directly if CONFIG_PARAMETER is not enabled
to fix that.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Support added for ioctl of ECCGETSTATS and MEMGETREGIONINFO.
Fix default handling in core.c to return -EINVAL, if request
was unknown.
Signed-off-by: Alexander Aring <a.aring@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 88ce7ef769 has changed the API and commit
b29b8f43d5 has moved the S3C24xx NAND driver
file. With the move the API change in the S3C24xx NAND driver was lost.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 88ce7ef769 introduces an additional
parameter to the function add_mtd_device(). It seems one of the callers was
left.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To get rid of:
(MTD_OOB_DEVICE && MTD_RAW_DEVICE) selects NAND_READ_OOB which has unmet direct dependencies (MTD && NAND)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The aready existing NAND controller driver in Barebox is for the S3C24XX family
only. Change the name of the file to reflect this fact (and free the way to add
more recent Samsung NAND controllers)
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Start with renaming files to share them in the S3C CPU family,
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Bit errors in the ECC itself are not beeing taken into account.
In this cases the number of detected errors != number of corrected errors and
chien search returns an error.
This patch adds detection of bit errors in the ECC.
Signed-off-by: Steve Schefter <steve@scheftech.com>
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the MSystem disk-on-chip G3 support, taken from the
linux kernel with few amendments to bring it into barebox.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For PIO NAND access functions, we use the features of the SMC:
- no need to take into account the NAND bus width: SMC will deal with this
- use of an IO memcpy on the NAND chip-select space is able to generate
proper SMC behavior.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
introduced in commit f76ad819e4
drivers/mtd: cosmetic changes
it's supposed to the invert of the writesize - 1
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a device to read and write to MTD data and oob
(/dev/mtdraw<N>).
The device is constrained in a separate source file, so that
further improvement of commands (such as nandwrite) could
make it useless, and easy to remove.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Split /dev/mtd and /dev/mtdoob devices.
Remove from mtd structure the mtdoob character device.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If multiple MTD devices were registered, an exception
occured, as they all wanted id 0. Let the driver code choose
the device number dynamically.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Change NAND_WRITE into MTD_WRITE.
Change "page_shift" references in the core, which are purely
NAND, into mtd->writesize which is MTD generic.
Rename all "info" (struct mtd_info) into "mtd".
Also provide a parameter to add_mtd_device() so that legacy
nand devices still appear as nand<N>.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix whitespace, replace all debug() by dev_dbg(), and fix
line length to 80 characters.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The NAND_READ_OOB Kconfig option is used to
a) creating a cdev for reading OOB data
b) compiling in mtd->read_oob support
The former was intended and that's also what the Kconfig help
says. The latter though was implicit and wrong. mtd->read_oob
is also used by the bbt code which resulted in a NULL pointer
deref when compiled with BBT but without NAND_READ_OOB.
To fix this, split the option into two. The now invisible
option NAND_OOB_DEVICE is only responsible for b) and gets
selected when necessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- use KERN_ERR for messages when NAND-ID detection fails
- report the IDs also if not found
- print the errno if nand_scan failed
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OMAP4 romcode expects some unusual ecc layout which we could
write but not read. This patch adds a function which uses the
manual mode to read a page written with this ecc layout.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can't use the ECC_RESULTx_0 register set for manual mode which
we'll need in the next patch. So factor out an internal function
which makes the register set to use configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- add missing '\n' at line ends
- fix wrong argument type warnings
- remove too noisy debug in omap_hwcontrol
- add function names to debug printfs
- add 0x prefixes to hex values
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The driver used to print an error when bch decoing failed, but
did not actually throw an error. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move omap_calculate_ecc outside omap_correct_bch. When implementing
the romcode bch read page we have to call omap_calculate_ecc with
different arguments than in the standard case.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We need the bch correct algorithm in the next patches, so
factor out a seperate function for this and also safe an
indention level.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The nand controller on i.MX51/53 uses two base addresses. Instead
of hardcode the second address use the new shiny resources two specify
it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now a 'devinfo gpmc_nand0' shows the current used eccmode
instead of <NULL>.
The function omap_gpmc_eccmode is now called by dev_set_param.
Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The following patch came across the mtd mailing list today. I thinks its also
valid for barebox (it handles a special corner case, but maybe it can hit us,
too):
In nand_do_write_ops() code it is possible for a caller to provide
ops.oobbuf populated and ops.mode == MTD_OOB_AUTO, which currently
means that the chip->oob_poi buffer isn't initialised to all 0xFF.
The nand_fill_oob() method then carries out the task of copying
the provided OOB data to oob_poi, but with MTD_OOB_AUTO it skips
areas marked as unavailable by the layout struct, including the
bad block marker bytes.
An example of this causing issues is when the last OOB data read
was from the start of a bad block where the markers are not 0xFF,
and the caller wishes to write new OOB data at the beginning of
another block. In this scenario the caller would provide OOB data,
but nand_fill_oob() would skip the bad block marker bytes in
oob_poi before copying the OOB data provided by the caller.
This means that when the OOB data is written back to NAND,
the block is inadvertently marked as bad without the caller knowing.
This has been witnessed when using YAFFS2 where tags are stored
in the OOB.
This patch changes the code so that oob_poi is always initialised
to 0xFF to make sure no left over data is inadvertently written
back to OOB data.
The comment above is for the linux kernel, but the same is valid for barebox
and CPUs writing the OOB date controlled in software (like the Samsung
S3C2440 does).
Signed-off-by: Adam Thomson <adam.thomson@alcatel-lucent.com>
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
NAND_BUSWIDTH_16 should result in dev_width = 1 according to the kernel driver
omap_enable_hwecc: dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The old way happily removed cdev entries which were no bb dev
at all. Fix this by checking if the given device actually is
a bb device.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The cdev operations are available without the complete file API,
so they are more suitable for internal usage.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It's good to seperate the code which others can use from commands.
This way other users do not depend on the command being compiled in.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The information from the probe function is useful for developers
only, so turn them into dev_dbg to safe binary space.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The nand oob functions occupy quite some binary space. If not needed,
we can save this space by making this configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds BCH ecc support to the omap nand driver. The BCH
error correction allows for up to 8 bit error correction. It is
also needed for booting from nand on omap4.
This is based on code from Sukumar Ghorai <s-ghorai@ti.com>:
[PATCH] omap3: nand: bch ecc support added
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On omap we use different ecc modes for different purposes. The initial
boot code has to be written with hardware ecc whereas Linux usually uses
software ecc. To be able to write in both modes with a sinlge barebox
image introduce a eccmode device parameter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Give this omap specific entry an omap namespace. Also, remove
unnecessary dependency to omap2/3 in nand Kconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Do the same ECC handling and ECC size in barebox than the kernel does.
Currently its done for S3C2440 based systems only, as I have no idea how to
manage it on a S3C2410 based system.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.
This patch also extends the read routine to support more than four address
cycles on demand.
BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Something was to be done here. But I do not remember what. As it works also
without it, remove this dead code.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
After running the 'nand_boot_test' command, any usage of the NAND fails with
a IO error. This happens due to the load routine disables the NAND controller
after loading the image.
This patch re-enables the NAND controller again after running the test.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX Processors support two different boot modes, the internal
boot mode and the external boot mode. Traditionally the external
NAND boot mode is handled in drivers/mtd/nand and the internal
boot mode is handled in arch/arm/mach-imx. This patch consolidates
the handling of both boot modes in arch/arm/mach-imx so that
the user does not have to look in the mtd kconfig section for
booting from NAND. Also, selecting between internal and external
boot mode now is a clear choice.
The external NAND boot mode has been independent of the mtd nand
driver, but as the code was contained in the NAND driver it was
not possible to support booting from NAND without a mtd nand driver.
This is changed with this patch.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The S3C2440 provides 32 bit access to the NAND's data. Add specific read
routines to speed up data reading and writing.
These routines are stolen from the Linux kernel.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are a few but important differences in S3C2410 and S3C2440. This patch
fixes them for the S3C2440 CPU.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The default configuration of the current 2.6.37 kernel uses a flash based BBT.
So, barebox must also use one, to be in sync with the kernel about bad blocks
in the flash.
Due to the used OOB layout, the generic BBT description coming with the
framework can be used.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fixes warnings due to incompatible format strings
specified in the printf().
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This has two purposes. First we need to factor out initialization
to be able to do something different on v3 type controllers,
second with this patch we are independent of preinitialized register
values.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The v2 controller has a totally different mechanism to check
whether the data we read had ecc errors or not. Implement this.
The mechanism in the v2 controller happens to be identical to
the v3 controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This prepares the driver for v3 support. The v3 controller
has a completely different register layout, so add a V1_V2_
namespace to the register defines to avoid confusion with
the v3 regs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch prepares the driver to add v3 controller support
later. The v3 controller is basically the same controller as v1
and v2, but with a completely different register layout.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
NFC_SP_EN is cleared in probe and never set again, so we do not
need to clear it in other functions again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We save/restore the value in the buffer anyway, so it makes
no difference whether we use main_area0 or main_area1. So,
we can use main_area0 and remove main_area1 from the driver
which is otherwise unused. Also, clean up the comments in
get_dev_status.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the offset to the register base instead. This is done
in preparation for v3 controller support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This repairs a bug which came with patch "0cb00c1 omap nand: cleanup"
We first have to set ecc.layout before we can use it and should
do the nand_scan_tail after we set the ecc.mode.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Wolfram Sang
Jean-Christophe PLAGNIOL-VILLARD
Sascha Hauer
Alexander Aring
Marcus Folkesson
Jan Luebbe
Juergen Beisert
Eric Bénard
Alexey Galakhov
Antony Pavlov
Robert Jarzmik
Jan Weitzel
Alexander Aring
Steve Schefter
Juergen Kilb
Baruch Siach
Juergen Beisert
Juergen Beisert
Sanjeev Premi
Marek Belisko
Michael Grzeschik