The fec has a mdio bus. This adds support for a subnode
in which the phys on this bus can be specified.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We do not care about releasing the resources in the error
path, but at least check the return value of eth_register
and mdiobus_register.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX53 fec claims to be compatible to i.MX25 and i.MX53. In barebox
we do not have to make differences between i.MX25 and i.MX27 though, so
just fall back to i.MX27.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
While this makes sure that the phy fixups are applied even if
networking is not used on i.MX6, this patch due to latest phy
changes causes the startup of barebox delayed until we have a
link on the i.MX fec. Revert it for now and look for a better
solution later.
This reverts commit 3a17af33c0.
fec_init() initializes some bits important for phy access, so do
this before the mdiobus is registered. This fixes mdiobus support
on i.MX28 boards in RMII mode.
Reported-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Several i.MX boards (all i.MX6 boards) need to do some adjustments
to phy registers. If barebox itself does not use network, networking
won't work in the kernel if the kernel does not have the fixups. Connect
the phy at probe time so that these tweaks are done during probe so that
the kernel works without phy register tweaks. Also this has the effect
that the phy device is present and introspectable without doing fake
network transfers beforehand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On i.MX we enable all necessary clocks during startup of the clock
controller driver, so we do not need the register hacking in the drivers
anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds the device id mechanism to the i.MX fec driver and
uses it to determine the fec version. Also adds devicetree
probing support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adapt phylib from linux
switch all the driver to it
reimplement mii bus
This will allow to have
- phy drivers
- to only connect the phy at then opening of the device
- if the phy is not ready or not up fail on open
Same behaviour as in linux and will allow to share code and simplify porting.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently only 100Mb/s is tested. Freescale's U-Boot suggests that
there are some additional adjustments necessary for Gigabit support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Q: "the linux driver add these bits, why not we?"
A: Because nobody activated the bits?
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Introduce a variable which gets updated when needed and only written
once. Will make further additions easier.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
remove double include, remove unused (and double in case of RCNTRL)
defines, sort the includes at least somewhat.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The driver uses a static int once variable to alloc the
rx packets. remove this to make the driver multi instance
safe. While at it, remove the crappy selfmade alignment.
dma_alloc_coherent returns sufficiently aligned memory.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Rostislav Lisovy
Hubert Feurstein
Alexander Shiyan
Jean-Christophe PLAGNIOL-VILLARD
Wolfram Sang