NULL pointers should be treated as dummy clocks as done in the kernel.
Using a not fully filled in clk * array for of_clk_add_provider may result
in NULL clks. When these are passed into the clk framework we should not
crash.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.
Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.
Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds functions to bring up the new style
Tegra114+ PLL_E.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As the real value is 2^p a input value of 0 is
actually valid.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegra124 extended the mux by 1bit to allow for
more PLL sources.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some peripherals have a double wide divider in front
of them.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that we have a proper reset controller, it
isn't necessary anymore to keep the device reset
hack coupled to the clock.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The console devices are the only ones that can't
use the reset controller properly, as they get
registered from platform code. Reset those devices
from the clock controller.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows us to drop the hack in the clock controller
and implement proper reset at device level.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Clock gates having the CLK_GATE_HIWORD_MASK flag set use the upper 16
bits of the register as a "write enable" mask for the value in the
lower 16 bits.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To avoid code duplication and make easier to introduce new flags.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegra3 has some new clocks and resets. The new
registers don't form a linear range with the
old ones.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This most likely doesn't fix any real bugs, but it's the
right thing to do and reduces the noise level with static
checkers.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows to make relationship between DT and driver
more explicit and avoids duplication.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This updates the clk-divider to Kernel code, but without power-of-two
divider support which we do not need yet. This also adds table based
divider support to the divider.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>