Some MMC cards support boot partitions. These are special regions
on the MMC card intended to put a bootloader on.
This patch adds support for these partitions, they are accessible
as /dev/diskx.boot[0|1].
Additionally the partitions can be configured bootable using a
device parameter. This can be used to mark the user area or one
of the boot partitions as bootable.
Since this feature is mostly seen on eMMC cards it is made optional
to lower the size impact for boards which do not have eMMC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This updates the i.MX esdhc divider settings to FSLs U-Boot.
Current timings work fine for SD cards, but not for eMMC.
Although the calculation is fine according to the datasheet and reading from
eMMC works, writing is broken. Atleast on i.MX53/tqma53.
With this patch the result is the same, but uses different divider values to
achieve it.
While at it, replace the udelay with a busy-loop.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This gives the SDHCI specific registers a common name and moves
them to a separate file for use by other SDHCI like drivers.
The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses
these as 32bit registers. These register defines now are named after
the SDHCI registers they combine into one, for example:
SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL
is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL
and BLOCK_GAP_CONTROL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We recently gained helper functions for different types of
device parameters. One thing missing was a helper for an
enum type parameter. This patch adds this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some parameters may wish to provide some information about their
meaning or possible values. Provide an info callback for parameters.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some SoCs come up with invalid entries in the data cache. This can
lead to memory corruption when we enable them later, so invalidate
the caches early.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de>
At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.
That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()). Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There is no "settings-entries-edit" command. This results in a recursive call
to the settings menu. Use the missing "boot-entries-edit" command instead.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
From Kernel commit 418df63a ARM: 7670/1: fix the memset fix
| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value. However the memset itself became broken
| by that patch for misaligned pointers.
|
| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
|
| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
|
| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
|
| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The fdt reserve map needs address/size values, not address/end values
like accidently done for generating the reserve entry for the dt.
Reported-by: Jürgen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Although conclusions in 50d1b2de8e "ARM
v7: Fix register corruption in v7_mmu_cache_off" are correct, the
implemented fix is not complete because the following failure can
happen:
1. d-cache contains the cache line around 'sp'
2. v7_mmu_cache_off() disables cache
3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack
4. v7_mmu_cache_flush() flushes d-cache and can override stack written
by step 3.
5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which
might be random data now.
Patch avoids step 3 which is easy because 'lr' is never modified by the
function. By using the 'r12' scratch register instead of 'r10', the
whole initial 'push' can be avoided.
Patch moves also the 'DMB' operation so that it is executed after data
has been pushed on stack.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this fix the problems introduced when detecting non ONFI flashes in
commit 4c2bdc8728
"nand_base: detect more ONFI flash"
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the dhcp code discovered the tftp-server-name option it immediately
tries to resolve the name. This can't succeed since the we are somewhere
in the dhcp processing and the nameserver may not even be known.
Fix this by resolving the name when dhcp is completed. While at it, do
this in a way that net_set_serverip is only called when resolv() returns
something useful. Otherwise we may end up overwriting a previously
configured serverip which came from the bootp bp_siaddr field.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
See also:
commit eb84709192
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon Mar 25 15:18:38 2013 +0100
clk: remove unused __clk_[get|put]
This is some unused code resulting from copying stuff from
the kernel. Remove it.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The missing 'break' statement lets look an i.MX23 like an i.MX28.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Using the MXS MCI driver with an eight bit capable eMMC results into the
'devinfo' message the interface uses '0' bits for data transfer:
barebox:/ devinfo mxs_mci0
resources:
num : 0
start : 0x80034000
size : 0x00002000
driver: mxs_mci
bus: platform
Interface
Min. bus clock: 1476 Hz
Max. bus clock: 48000000 Hz
Current bus clock: 24000000 Hz
Bus width: 0 bit
The eight bit interface width is stored internally as value '2'. And a two bit
'2' ends up into 0xfffffffe when used as an array index. Using an unsigned
field instead fixes this issue:
barebox:/ devinfo mxs_mci0
resources:
num : 0
start : 0x80034000
size : 0x00002000
driver: mxs_mci
bus: platform
Interface
Min. bus clock: 1476 Hz
Max. bus clock: 48000000 Hz
Current bus clock: 24000000 Hz
Bus width: 8 bit
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This partly reverts:
commit 697e02b74f
Author: Alexander Shiyan <shc_work@mail.ru>
Date: Tue Jan 22 15:08:31 2013 +0400
ARM: ccmx51: Remove SDRAM size settings
This patch removes SDRAM memory size setting from board due
to auto detect last one by ESDCTL.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.
This patch brings back the old behaviour.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit ad09b59f8b "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
GPR[28] enable USBOTG loopback
GPR[17] override DSR_DCE1 with USBOTG_DATA4
GPR[0] select FIR DMA requests instead of UART2 DMA
Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The prefix/cleanup series
ad09b59f8ba8c63596674c53af062b
missed a few unprefixed IOMUXC_BASE define users. Fix these.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The checkpatch.pl script is also used to validate user-space code in
the scripts/ directory, so it should allow printf() lines to be longer
than 80 columns.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
